TW201405506A - Gate driver circuit with voltage pull down structure and display thereof - Google Patents

Abstract

A gate driver circuit with voltage pull down structure and display thereof is disclosed. The structure comprises a voltage pull down TFT having a first gate electrode, a first drain electrode, and a first source electrode; an enhanced voltage pull down TFT having a second gate electrode, a second drain electrode, and a second source electrode, wherein the second source electrode and the first gate electrode are electrically connected, the second gate electrode is electrically connected to an output P of a control circuit of the gate driver circuit, and the second drain is electrically connected to a time signal; and the control circuit of the gate driver circuit having a first time input terminal, a second time input terminal electrically connected to the second drain electrode, and a third time input terminal. Thereby, the enhanced voltage pull down TFT is electrically connected and the falling time of the output signal is shorter, and further the better driving ability is achieved.

Description

Voltage pull-down circuit structure of gate drive circuit and display device thereof

The present invention relates to a driving circuit, and more particularly to a voltage pull-down structure of a gate driving circuit and a display device therefor.

In a general liquid crystal display (LCD), a driving circuit (Driving Circuit) is an important driving component of a liquid crystal display. In the conventional panel technology, a driver IC (Driver IC) is often used as a driving circuit of the panel.

Please refer to FIG. 1 , which is a schematic diagram showing a display panel of a conventional display panel and GOA technology. Up to now, under the consideration of cost reduction, quality improvement and shortened production cycle, an A-Si Integrated Gate Driver (ASG) has been developed, which is referred to as ASG. Among them, ASG is applied to polycrystalline germanium (amorphous). In the silicon process, the gate driver circuit (Gate Driver) is integrated into the panel in the Array process. This technology is also collectively referred to as Gate Driver On Array (GOA) or Gate Driver On Panel (GOP).

Please refer to FIG. 2A and FIG. 2B simultaneously, wherein FIG. 2A is a voltage pull-down circuit diagram showing the GOA circuit structure of the display device of the conventional GOA technology, and FIG. 2B is a first-level output signal (Out1) and third in FIG. 2A. Waveform of the level output signal (Out3).

The circuit structure of GOA includes timing input (signal) (STV, CK1, CK3, CK5), control circuit, control circuit output (P1, Q1), thin film transistor (M1~M3), voltage ( VGL), first stage output signal Out1, third stage output signal Out3, and capacitance (Cc); In the GOA output circuit structure, the thin film transistor M3 is the main voltage pull-down component. Usually, the Gate Out is used as the pull-down signal by the next-stage output signal (Out), but the output signal (Out) is pre-charged (pre- Charge) action, so the rising time will be slower, causing the falling time of the output signal (Out) to slow down as well, as shown in Figure 3. If the falling time is too long If it is, the pixel will read the wrong data (Data), which will lead to a decrease in characteristics such as contrast and brightness.

At present, the structure of the voltage pull-down circuit is referred to the Republic of China Invention Patent No. 200951937 (shown in FIG. 4), which discloses a shift register and a shift register unit which can reduce the clock coupling effect, wherein each stage The shift register unit includes: at least one lift drive module, a lift module, at least a pull-down module, and at least a pull-down drive module, wherein the first clock signal waveform or the second time used by the lift module When the pulse waveform forms a rising edge, the pull-down driving module first turns on the pull-down module for a certain period of time according to the first period signal, and/or the first clock signal waveform or the second clock signal used by the lifting module When the waveform forms a falling edge, the pull-down driving module first turns off the conduction of the pull-down module for a certain period of time according to the second period signal, so that when the coupling effect of the clock signal appears, the pull-down module itself has sufficient The ability to resist, thereby improving the output waveform of the shift register unit.

The K-point signal disclosed is the function of stabilizing the ripple, and the help of the output level is limited. The exposed P-point signal is similar to the P_CK signal, which will cause the stress of the voltage pull-down film transistor ( Stress) is more serious, resulting in a decrease in the ability of the voltage pull-down film transistor; in addition, generating K The rising time of the point signal is slower, so there is limited help for voltage pull-down.

In addition, please refer to US Pat. No. 7,763,412 (shown in FIG. 5), which discloses a shift register circuit and an image display device having the same, in a shift register capable of bidirectionally shifting signals In order to prevent malfunction caused by leakage current of the thin film transistor; the bidirectional unit shift register has a thin film transistor (Q1) between the timing terminal (CK) and the output terminal (OUT); and an output terminal (OUT) a thin film transistor (Q2) for discharging; a film for supplying first and second voltage signals (Vn) and (Vr) complementary to each other with respect to a gate node (ie, a first node) of the thin film transistor (Q1) a transistor (Q3), (Q4); further comprising: a thin film transistor (Q5) for discharging the first node, the thin film transistor (Q5) having a gate node of the thin film transistor (Q2) (ie, a second The gate connected to the node).

Among them, the N2 point is a voltage pull-down signal, but it is similar to the DC signal and causes the stress of the voltage pull-down film transistor Q2 (Stress) to seriously affect the voltage drop of the voltage pull-down film transistor.

Based on the above problems, the inventors have proposed a voltage pull-down structure of a gate drive circuit and a display device thereof to overcome the drawbacks of the prior art.

The object of the present invention is to provide a voltage pull-down structure of a gate driving circuit that electrically connects a thin film transistor to generate a faster voltage pull-down signal, so that the output signal has a faster falling time, thereby achieving a better driving capability. Display device.

In order to achieve the above object, the present invention provides a gate drive circuit for electricity The pull-down structure comprises: a voltage pull-down film transistor having a first gate, a first drain and a first source; and a boosted voltage pull-down film transistor having a second gate and a a second drain and a second source, the second source is electrically connected to the first gate, and the second gate is connected to one of the control circuits of the other gate drive circuit The P-point output is electrically connected, and the second drain is electrically connected to a timing signal.

The first source is electrically connected to a VGL voltage.

The control circuit of the gate driving circuit has a first timing input terminal, a second timing input terminal and a third timing input terminal, and the second voltage of the boosted voltage pull-down film transistor The second timing input is electrically connected.

In order to achieve the above object, the present invention further provides a display device comprising: a display panel having a display area, a wiring area, and a bonding area, the bonding area being attached with a plurality of source driving integrated circuits; a circuit board structure; a gate driving circuit disposed in the wiring area of the display panel, the gate driving circuit at least comprising the voltage pull-down circuit structure; and a backlight module disposed under the display panel.

While the invention has been described in terms of several preferred embodiments, the preferred embodiments of the present invention It is not intended that the invention be limited to the following drawings and embodiments.

Please refer to FIG. 6A to FIG. 6C, wherein FIG. 6A is a circuit diagram showing the structure of the voltage pull-down circuit of the gate driving circuit of the present invention, and FIG. 6B is a table. The waveform diagrams of the first stage output signal (Out1) and the boost voltage pull down signal (Tfa) in FIG. 6A, and FIG. 6C show the waveform diagrams of the respective input and output terminals in FIG. 6A.

The gate driving circuit 1 of the present invention comprises a timing input terminal (signal) (STV, CK1, CK3, CK5), a control circuit, a control circuit output terminal (P1, Q1), and a thin film transistor (M1~M2). Voltage (VGL), first-stage output signal Out1, voltage pull-down circuit structure 2, and capacitance (Cc); waveform diagrams of respective input and output terminals are shown in FIG. 6C, wherein Gate1 represents the first-level gate signal Gate2 represents the second-level gate signal, Gate3 represents the third-level gate signal, and CK1~CK6 systems represent different timing inputs (signals).

The voltage pull-down structure 2 includes a voltage pull-down film transistor M3 and a boost voltage pull-down film transistor M4.

The voltage pull-down film transistor M3 has a first gate G1, a first drain D1 and a first source S1; and the boosted voltage pull-down film transistor M4 has a second gate G2 and a second drain D2 and a second source S2, wherein the second source S2 is electrically connected to the first gate G1, where a boost voltage pull-down signal Tfa is generated, and the second gate G2 is connected to the lower second gate. One of the control circuits of the pole drive circuit is electrically connected to the P point (if the gate drive circuit is the first pole, the P point output is P1, and the lower second P point output is P3), the second The drain D2 is electrically connected to a timing signal, and the first source S1 is electrically connected to the voltage (VGL).

Furthermore, the control circuit of the gate driving circuit 1 has a first timing input terminal (signal) CK1, a timing input terminal (signal) CK3, and a timing input terminal (signal) CK5. Second bungee D2 The second timing input terminal CK3 is electrically connected.

Therefore, comparing the waveforms of the first stage output signal (Out1) and the boost voltage pull down signal (Tfa) of the embodiment (as shown in FIG. 6B) and the conventional first stage output signal (Out1) and the third stage output signal ( The waveform of Out3) (as shown in Figure 2B), obviously, the rise time of the boost voltage pull-down signal (Tfa) is faster than the rise time of the original third-level output signal (Out3), so that the better drive can be achieved. The power of ability.

Please also refer to the following table 1 for the comparison of the characteristic of the voltage drop-down circuit structure and the falling time and rise time of the voltage pull-down circuit structure of the present embodiment, wherein the drop-down time of the conventional voltage pull-down circuit structure is 2.41μs, the falling time of the back period is 3.25μs. In contrast, the falling time of the voltage pull-down circuit structure of the present embodiment is 2.02μs, and the falling time of the back period is 2.53μs. It can be clearly seen that the voltage drop of this embodiment is The falling time of the front and back sections of the circuit structure is smaller than the falling time of the previous and subsequent sections of the conventional voltage pull-down circuit structure.

Please refer to FIG. 7 to FIG. 9 at the same time, wherein FIG. 7 is a comparative waveform diagram showing the falling time generated by the voltage pull-down circuit structure according to the present invention and a conventional voltage pull-down circuit structure, and FIG. 8 is a diagram showing the voltage pull-down according to the present invention. A comparative waveform diagram of the rise time of the circuit structure and the conventional voltage pull-down circuit structure, and FIG. 9 is a comparative bar graph showing the fall time of the voltage pull-down circuit structure according to the present invention and the conventional voltage pull-down circuit structure.

7 and FIG. 8, the falling time (2.53 μs) of the voltage pull-down circuit structure of this embodiment is smaller than the falling time of the conventional voltage pull-down circuit structure (3.25 μs), and the voltage pull-down circuit structure of this embodiment is The rise time (1.4μs) is less than the rise time (3μs) of the conventional voltage pull-down circuit structure. In contrast, as shown in FIG. 9, the fall time of the voltage pull-down circuit structure of this embodiment is faster than the conventional voltage pull-down. The fall time of the circuit structure is about 22%.

Therefore, by the above structure, a thin film transistor (ie, a boosted voltage pull-down film transistor M4) is electrically connected to generate a faster voltage pull-down signal, so that the output signal has a faster drop than the conventional structure. Time, and thus the ability to achieve better driving ability.

In addition, the gate driving circuit structure 1 of the present invention can be applied to a display device (not shown), including a display panel, a gate driving circuit structure, and a backlight module.

The display panel has a display area, a wiring area and a bonding area, the bonding area is attached with a plurality of source driving integrated circuits and a circuit board structure, wherein the circuit board structure can include at least one flexible circuit board Or, it includes a plurality of flexible circuit boards and at least one rigid circuit board.

The gate driving circuit structure 1 is the above structure of the present invention, and can be arranged In the wiring area of the display panel.

Therefore, by using the voltage pull-down circuit structure in the gate driving circuit structure of the present invention, a thin film transistor (ie, the enhanced voltage pull-down film transistor M4) is electrically connected to generate a faster voltage pull-down signal, so that the output signals are compared. In the conventional structure, there is a faster fall time, thereby achieving the effect of better driving ability.

Although the present invention has been explained in connection with the preferred embodiments, it is not intended to limit the invention. It should be noted that many other similar embodiments can be constructed in accordance with the teachings of the present invention, which are within the scope of the present invention.

1‧‧ ‧ gate drive circuit

STV‧‧‧ timing input (signal)

Cc‧‧‧ capacitor

CK1‧‧‧ timing input (signal)

CK2‧‧‧ timing input (signal)

CK3‧‧‧ timing input (signal)

CK4‧‧‧ timing input (signal)

CK5‧‧‧ timing input (signal)

CK6‧‧‧ timing input (signal)

D1‧‧‧First bungee

D2‧‧‧second bungee

G1‧‧‧ first gate

G2‧‧‧second gate

Gate1‧‧‧first level gate signal

Gate2‧‧‧Second level gate signal

Gate3‧‧‧third-level gate signal

M1, M2‧‧‧ film transistor

M3‧‧‧ voltage pull-down film transistor

M4‧‧‧Enhanced voltage pull-down film transistor

Out1‧‧‧first-level output signal

Out3‧‧‧ third-level output signal

P1‧‧‧ control circuit output (first stage)

P3‧‧‧ control circuit output (third level)

Q1‧‧‧Control circuit output

S1‧‧‧first source

S2‧‧‧Second source

Tfa‧‧‧Enhanced voltage pull-down signal

VGL‧‧‧ voltage

1 is a schematic view showing a display panel of a conventional display panel and GOA technology.

Fig. 2A is a voltage pull-down circuit diagram showing a GOA circuit structure of a display device of a conventional GOA technology.

2B is a waveform diagram showing the first stage output signal (Out1) and the third stage output signal (Out3) of FIG. 2A.

Figure 3 is a waveform diagram showing the data signal and the gate and output signals in Figure 2.

Fig. 4 is a circuit diagram showing the conventional Chinese Patent Publication No. 200951937.

Figure 5 is a schematic diagram of the circuit of the prior art U.S. Patent No. 7,763,412.

Fig. 6A is a circuit diagram showing the structure of a voltage pull-down circuit of the gate driving circuit of the present invention.

Fig. 6B is a waveform diagram showing the first stage output signal (Out1) and the boost voltage pull down signal (Tfa) in Fig. 6A.

Figure 6C is a waveform diagram showing the respective input and output terminals of Figure 6A.

Figure 7 is a graph showing a comparison of the falling times of the voltage pull-down circuit structure according to the present invention and the conventional voltage pull-down circuit structure.

Fig. 8 is a view showing a comparison waveform of the rise time generated by the voltage pull-down circuit structure according to the present invention and the conventional voltage pull-down circuit structure.

Figure 9 is a comparative bar graph showing the fall time of the voltage pull-down circuit structure in accordance with the present invention and the conventional voltage pull-down circuit structure.

1‧‧ ‧ gate drive circuit

STV‧‧‧ timing input (signal)

Cc‧‧‧ capacitor

CK1‧‧‧ timing input (signal)

CK3‧‧‧ timing input (signal)

CK5‧‧‧ timing input (signal)

D1‧‧‧First bungee

D2‧‧‧second bungee

G1‧‧‧ first gate

G2‧‧‧second gate

M1, M2‧‧‧ film transistor

M3‧‧‧ voltage pull-down film transistor

M4‧‧‧Enhanced voltage pull-down film transistor

Out1‧‧‧first-level output signal

P1‧‧‧ control circuit output (first stage)

Q1‧‧‧Control circuit output

S1‧‧‧first source

S2‧‧‧Second source

Tfa‧‧‧Enhanced voltage pull-down signal

VGL‧‧‧ voltage

Claims (8)

A voltage pull-down circuit structure of a gate driving circuit includes: a voltage pull-down film transistor having a first gate, a first drain and a first source; and a boosted voltage pull-down film transistor having a second gate, a second drain, and a second source, the second source is electrically connected to the first gate, and the second gate is driven by at least two other gates A P-point output of one of the control circuits of the circuit is electrically connected, and the second drain is electrically connected to a timing signal. The voltage pull-down circuit structure of the gate driving circuit of claim 1, wherein the first source is electrically connected to a VGL voltage. The voltage pull-down circuit structure of the gate driving circuit according to the first aspect of the invention, wherein the control circuit of the gate driving circuit has a first timing input terminal, a second timing input terminal, and a first a third timing input, and the second drain of the boosted voltage pull-down thin film transistor is electrically connected to the second timing input. The voltage pull-down circuit structure of the gate driving circuit of claim 1, wherein the second gate is electrically connected to the P point of the control circuit of the lower second gate driving circuit. . A display device includes: a display panel having a display area, a wiring area, and a bonding area, the bonding area is attached with a plurality of source driving integrated circuits and a circuit board structure; and a gate driving circuit Provided in the wiring area of the display panel, the gate driving circuit includes at least a voltage pull-down circuit structure, the electricity The voltage pull-down circuit structure comprises: a voltage pull-down film transistor having a first gate, a first drain and a first source; and a boosted voltage pull-down film transistor having a second gate and a first a second drain and a second source, the second source is electrically connected to the first gate, and the second gate is connected to one of the control circuits of the other gate drive circuit of the second The P-point output is electrically connected, the second drain is electrically connected to a timing signal, and a backlight module is disposed under the display panel. The display device of claim 5, wherein the first source is electrically connected to a VGL voltage. The display device of claim 5, wherein the control circuit of the gate driving circuit has a first timing input terminal, a second timing input terminal, and a third timing input terminal, and The second drain of the boosted voltage pull-down film transistor is electrically connected to the second timing input. The display device according to claim 5, wherein the second gate is electrically connected to the P point of the control circuit of the gate drive circuit of the lower stage.