TW201404253A - Wiring substrate, mounting structure, method of manufacturing wiring substrate and method of manufacturing mounting structure - Google Patents

Abstract

This invention provides a wiring substrate 4 comprising a core substrate 7, and a first build-up layer 8a provided on the core substrate 7 and having an electronic part 2 mounted on the upper surface thereof; the core substrate 7 has a substrate 9, and a plurality of power supply through-hole conductors 10P penetrating through the substrate 9 in a thickness direction; the first build-up layer 8a has an insulating layer 11 having a thickness smaller than the substrate 9, and a plurality of power supply pads 14P formed on the insulating layer 11 and electrically connected to power supply terminals 6P of the electronic part 2 and the power supply through-hole conductors 10P, and a plurality of power supply via conductors 13P penetrating through the insulating layer 11 in the thickness direction and electrically connecting the power supply through-hole conductors 10P and the power supply pads 14P; in one group of the power supply pads 14P and the power supply through-hole conductors 10P being electrically connected, the number of the power supply through-hole conductors 10P is larger than the number of the power supply pads 14P.

Description

Wiring board, mounting structure, method of manufacturing wiring board, and manufacturing method of mounting structure

The present invention relates to a wiring board, a mounting structure, a method of manufacturing a wiring board, and a method of manufacturing a mounting structure used in an electronic device, for example, various audio-visual equipment, home electric appliances, communication equipment, computer equipment, and peripheral equipment thereof.

Conventionally, in the case of an electronic device mounting structure, a person who mounts an electronic component on a wiring board is used.

Japanese Laid-Open Patent Publication No. 2004-134679 discloses a wiring board having a plurality of buildup layers on both sides of a core substrate, and a core substrate having a through hole portion. A portion of the signal line in the semiconductor package; and the plated through hole portion are part of the power supply line and the ground line in the semiconductor package.

Further, in recent years, power saving of electronic equipment is required, and power consumption of a semiconductor wafer is required to be lowered. This power consumption is proportional to the voltage of the power source of the semiconductor wafer. Therefore, in order to reduce the power consumption, it is necessary to lower the voltage of the power source.

However, when the voltage of the power supply of the semiconductor wafer is lowered, the influence of the impedance of the power supply line and the voltage fluctuation due to the inductance in the wiring substrate is increased, and the semiconductor wafer is liable to malfunction. Therefore, there has been a demand for highly reliable operation of semiconductor wafers.

The present invention provides a wiring board, a mounting structure, a method of manufacturing a wiring board, and a method of manufacturing the mounting structure, which are capable of operating a semiconductor wafer with high reliability.

The wiring board of the present invention includes a core substrate and a build-up layer on the core substrate and having electronic components mounted on the upper surface thereof; the core substrate has a substrate and a plurality of power sources penetrating the substrate in a thickness direction a through-hole conductor; a build-up layer having a thickness smaller than that of the base, a power supply terminal for the electronic component, and a power supply through-hole conductor, and a plurality of power supply pads formed on the insulating layer, and thickness a plurality of power supply via conductors that are electrically connected to the power supply through-hole conductor and the power supply pad; and the power supply pad and the power supply through hole that are electrically connected In the conductor, the number of the through-hole conductors for the power supply is larger than the number of the power supply pads.

According to the wiring board of the present invention, the number of power supply through-hole conductors is larger than the number of power supply pads in one set of power supply pads and power supply through-hole conductors that are electrically connected. Therefore, the path through which the current for supplying power in the core substrate can be increased in parallel, and the resistance of the through-hole conductor for the power source in the core substrate can be reduced. Resistance to inductance, and the electronic components can be activated with high reliability.

1‧‧‧Installation of structures

2‧‧‧Electronic parts

3‧‧‧Bumps

4‧‧‧Wiring substrate

5‧‧‧Semiconductor substrate

6‧‧‧ terminals

6G‧‧‧ grounding terminal

6P‧‧‧Power terminal

7‧‧‧ core substrate

8‧‧‧Additional

8a‧‧‧1st build-up

8b‧‧‧2nd layer

9‧‧‧ base

10‧‧‧through hole conductor

10G‧‧‧ Grounding through hole conductor

10P‧‧‧through hole conductor for power supply

11‧‧‧Insulation

11a‧‧‧1st insulation layer

11b‧‧‧2nd insulation layer

11c‧‧‧3rd insulation layer

12‧‧‧ Conductive layer

12G‧‧‧ Conductive layer for grounding

12P‧‧‧ Conductive layer for power supply

13‧‧‧Guide conductor

13G‧‧‧ Grounding via conductor

13P‧‧‧Power guide hole conductor

14‧‧‧ solder pads

14G‧‧‧ Grounding pad

14P‧‧‧Power pad

R1‧‧‧1st area

R2‧‧‧2nd area

The first (a) is a side view of the mounting structure according to the embodiment of the present invention, and the first (b) is a plan view of the mounting structure according to the embodiment of the present invention.

Fig. 2 is an enlarged view of a cross section taken along the line A-A in the thickness direction in the portion P1 of Fig. 1(b).

Fig. 3 is an enlarged view of a cross section taken along the line B-B in the thickness direction in the portion P1 of Fig. 1(b).

Fig. 4(a) is an enlarged view of a section cut along the CC line of Fig. 2 in the plane direction in the P1 portion of Fig. 1(b), and Fig. 4(b) is at the first (b) In the P1 portion of the figure, an enlarged view of the cross section cut along the DD line in Fig. 2 in the plane direction, and Fig. 4(c) is in the P1 portion of the first (b) diagram, along An enlarged view of the cross section of the EE line cut off in the plane direction in Fig. 2 .

Fig. 5 is a view showing the manufacturing steps of the mounting structure shown in Fig. 1(a), and corresponds to an enlarged view of the cross section of Fig. 2.

Fig. 6 is a view showing the manufacturing steps of the mounting structure shown in Fig. 1(a) and corresponding to the enlarged view of the cross section of Fig. 2.

Hereinafter, an attachment structure including a wiring board according to an embodiment of the present invention will be described in detail with reference to the drawings.

The mounting structure 1 shown in FIGS. 1(a) and 1(b) is, for example, a user of an electronic device such as various audio-visual equipment, home electric appliances, communication equipment, computer equipment, and peripheral equipment. The mounting structure 1 includes: a flat electronic component 2; In the flat wiring board 4, the electronic component 2 is flip-chip mounted via the bumps 3.

The electronic component 2 is, for example, a semiconductor element such as an IC (Integrated Circuit) or an LSI (Large Scale Integration), and includes a flat semiconductor substrate 5 as shown in FIGS. 2 and 3 . A plurality of terminals 6 formed in a disk shape on the lower surface of the semiconductor substrate 5. The semiconductor substrate 5 is formed of, for example, a semiconductor material such as tantalum, niobium, gallium arsenide, gallium arsenide, gallium nitride or tantalum nitride. The terminal 6 can be formed, for example, of a conductive material such as copper, gold, aluminum, nickel or chromium. Among these materials, copper is preferably used from the viewpoint of electrical conductivity.

As shown in FIGS. 2 and 3, the plurality of terminals 6 include a plurality of power supply terminals 6P for supplying power to the semiconductor substrate 5, and a plurality of ground terminals 6G for connecting the semiconductor substrate 5 to a ground potential; A plurality of signal terminals (not shown) are used for inputting and outputting signals to the semiconductor substrate 5.

Here, the lower surface of the electronic component 2 includes a first region R1 located at a central portion, and a second region R2 located near the outer periphery of the electronic component 2 and surrounding the first region R1. A plurality of power supply terminals 6P and a plurality of ground terminals 6G are disposed in the first region R1, and a plurality of signal terminals are disposed in the second region R2.

In the first region R1, the plurality of terminals 6 are arranged in a lattice shape, for example. The power supply terminal 6P and the grounding terminal 6G are alternately arranged, whereby a plurality of power supply terminals 6P are arranged in a staggered manner, and a plurality of grounding terminals 6G are also arranged in a staggered shape. At this time, in the first region R1, the pitch of the plurality of terminals 6 is set to, for example, 200 μm or more and 250 μm or less. Further, in the first region R1, the plurality of terminals 6 may not be arranged in a lattice shape. The pitch of the plurality of terminals 6 can be measured in the cross section cut in the thickness direction by measuring the center of each of the adjacent terminals 6 Obtained by the distance between them. Hereinafter, the pitch of each member can also be obtained in the same manner as the pitch of the terminal 6.

Further, in the second region R2, a plurality of signal terminals are arranged in a lattice shape, for example. The pitch of the plurality of terminals 6 in the second region R2 is set to be smaller than the pitch between the plurality of terminals 6 in the first region R1. The pitch of the plurality of terminals 6 in the second region R2 is set to, for example, 128 μm or more and 180 μm or less.

The bump 3 is made of a conductive material such as soft solder containing lead, tin, silver, gold, copper, zinc, bismuth, antimony, or aluminum.

The wiring board 4 is electrically connected to the mother board (not shown), the electronic parts 2 are attached to the upper surface, and the lower surface is attached to the mother board via the bump balls. The wiring board 4 includes a flat core substrate 7 and a pair of buildup layers 8 formed on both sides of the core substrate 7.

The core substrate 7 is intended to improve the strength of the wiring board 4 and to achieve a conduction between the pair of buildup layers 8. The core substrate 7 includes a flat substrate 9 in which a plurality of cylindrical through holes penetrating in the thickness direction are formed, and the through hole conductors 10 are filled in a plurality of through holes.

The base 9 is a resin that increases the rigidity of the core substrate and includes, for example, glass fibers and an epoxy resin coated with glass fibers. The resin is dispersed with a silica filler. The thickness of the base 9 is set, for example, to 0.4 mm or more and 1.2 mm or less. Further, the thickness of the base 9 is larger than the thickness of the insulator 11 to be described later, and is also larger than the thickness of one build-up layer 8.

The through-hole conductor 10 is formed by electrically connecting the build-up layers 8 above and below the core substrate 7 to each other, for example, a conductive material such as copper, aluminum or nickel. Among these materials, it is preferred to use copper of high conductivity. The plurality of through-hole conductors 10 are arranged in Grid-like. The pitch of the plurality of through-hole conductors 10 is smaller than the pitch of the plurality of terminals 6 in the first region R1. Further, the pitch of the plurality of through-hole conductors 10 is set to, for example, 100 μm or more and 180 μm or less.

The through-hole conductor 10 is electrically connected to the bump 3 and the terminal 6 via a via conductor 13 and a pad 14 which will be described later. The plurality of through-hole conductors 10 include a plurality of power supply through-hole conductors 10P electrically connected to the power supply terminal 6P, and a plurality of grounding through-hole conductors 10G electrically connected to the grounding terminal 6G; and a plurality of signals A through-hole conductor (not shown) is electrically connected to the signal terminal.

On the other hand, on both sides of the core substrate 7, a pair of buildup layers 8 are formed as described above. The buildup layer 8 functions as a multilayer wiring layer for increasing the wiring density and arranging wiring. The build-up layer 8 includes an insulating layer 11 laminated on the base 9 and formed with a via hole penetrating in a thickness direction; a conductive layer 12 formed on the substrate 9 and on the insulating layer 11; and a via conductor 13 The conductive pad 12 is electrically connected to the conductive layer 12 , and is electrically connected to the via conductor 13 and is connected with the bump 3 . In the present embodiment, one buildup layer 8 includes three insulating layers 11.

For the sake of convenience, among the pair of buildup layers 8, the buildup layer disposed on the side of the electronic component 2 is referred to as a first buildup layer 8a, and the buildup layer disposed on the side of the motherboard is referred to as a second buildup layer 8b.

The insulating layer 11 functions not only as a supporting member for supporting the conductive layer 12 but also as an insulating member that prevents the conductive layers 12 from being short-circuited with each other. The insulating layer 11 contains a resin such as an epoxy resin in which a cerium oxide filler or the like is dispersed. The thickness of the insulating layer 11 is set to be smaller than that of the substrate 9. As a result, not only the wiring can be increased in density in the buildup layer 8, but also the rigidity of the wiring substrate 4 can be improved by the substrate 9. Thickness of insulating layer 11 The degree is set to, for example, 20 μm or more and 40 μm or less.

For the sake of convenience, the three insulating layers 11 included in the first build-up layer 8a are sequentially referred to as the first insulating layer 11a, the second insulating layer 11b, and the third insulating layer 11c (uppermost layer) from the side of the substrate 9. .

The conductive layer 12 functions as a wiring, and can be formed, for example, of a metal material such as copper, silver, gold, aluminum, nickel, or chromium. Among these materials, copper is preferably used from the viewpoint of electrical conductivity. The thickness of the conductive layer 12 is set to, for example, 10 μm or more and 25 μm or less.

For the sake of convenience, the names of the respective layers provided with the conductive layer 12 are referred to as FC1, FC2, and FC3 from the upper surface of the base 9 toward the upper surface of the wiring substrate 4, from the lower surface of the base 9 toward the wiring substrate 4. The lower surfaces are called BC1, BC2, and BC3.

The conductive layer 12 includes: a plurality of power supply conductive layers 12P electrically connected to the power supply terminal 6P; a plurality of ground conductive layers 12G electrically connected to the ground terminal 6G; and a plurality of signal conductive layers (not The figure is electrically connected to the signal terminal. The power supply conductive layer 12P and the ground conductive layer 12G include a block surface layer formed in a block shape. The block surface layer of the power supply conductive layer 12P and the block surface layer of the ground conductive layer 12G are alternately arranged. As shown in FIG. 2, FIG. 4(a) and FIG. 4(b), in the first build-up layer 8a, a block surface layer (FC1) in which the ground conductive layer 12G is sequentially formed from the upper surface of the base 9 is formed. The bulk layer (FC2) of the conductive layer 12P for power supply and the bulk layer (FC3) of the conductive layer 12G for grounding. In the second build-up layer 8b, a bulk layer (BC1) for the power supply conductive layer 12P, a bulk layer (BC2) for the ground conductive layer 12G, and a power supply conductive layer 12P are sequentially formed from the lower surface of the substrate 9. Block layer (BC3).

The via hole conductors 13 are conductive layers that are spaced apart from each other in the thickness direction 12 are connected to each other, for example, a metal material such as copper, silver, gold, aluminum, nickel or chromium. Among them, from the viewpoint of electrical conductivity, copper is preferably used. The via-hole conductor 13 has a circular shape on the upper surface and the lower surface, and is formed in a tapered shape whose diameter is smaller toward the core substrate 7.

Further, the via-hole conductor 13 includes a plurality of power supply via conductors 13P electrically connected to the power supply terminal 6P, and a plurality of ground via conductors 13G electrically connected to the ground terminal 6G; and a signal guide A hole conductor (not shown) is electrically connected to the signal terminal.

The pad 14 functions as a terminal for electrically connecting to the electronic component 2, and is formed of, for example, a metal material such as copper, silver, gold, aluminum, nickel, or chromium. Among them, from the viewpoint of electrical conductivity, copper is preferably used. The thickness of the pad 14 is set to, for example, 10 μm or more and 25 μm or less.

The bonding pad 14 includes a plurality of power supply pads 14P electrically connected to the power supply terminal 6P, a plurality of grounding pads 14G electrically connected to the grounding terminal 6G, and a plurality of signal pads (not The figure is electrically connected to the signal terminal. These pads 14 are arranged in the same manner as the terminals 6 respectively.

In the wiring board 4 described above, a plurality of power supply through-hole conductors 10P, a plurality of power supply conductive layers 12P, a plurality of power supply via conductors 13P, and a plurality of power supply pads 14P are electrically connected to each other. One set of power supply wirings is formed, and only one set of power supply wirings is formed on the wiring board 4. In the power supply wiring, a plurality of power supply through-hole conductors 6P or a plurality of power supply via-conductors 13P are electrically connected to each other by a bulk layer of the power supply conductive layer 12P.

Similarly, a plurality of grounding through-hole conductors 10G, a plurality of grounding conductive layers 12G, a plurality of power supply via conductors 13G, and a plurality of power sources are used. The pads 14G are electrically connected to each other to constitute one set of grounding wirings, and only one set of grounding wirings is formed on the wiring substrate 4. In the grounding wiring, a plurality of grounding via conductors 6G and a plurality of grounding via conductors 13G are electrically connected to each other by a bulk layer of the grounding conductive layer 12G.

Further, the signal through-hole conductor, the signal conductive layer of each layer, the signal via-hole conductor of each layer, and the signal pad are electrically connected one by one to form one set of the wiring board 4 The signal wiring is used to form a wiring for the complex array signal on the wiring board 4.

Further, the thickness of the base 9 in the core substrate 7 is larger than the thickness of the insulating layer 11 of the buildup layer 8. Therefore, the impedance and inductance of the power supply through-hole conductor 10P that penetrates the base 9 in the thickness direction are likely to be larger than the impedance and inductance of the power supply via conductor 13P that penetrates the insulating layer 11 in the thickness direction.

As shown in Fig. 2, in the present embodiment, one set of power supply pads 14P and power supply through-hole conductors 10P (that is, one set of power supply wirings) are electrically connected, and the power supply through-hole conductor 10P is used. The number is larger than the number of power pads 14P. As a result, by increasing the number of power supply through-hole conductors 10P, the path through which the current for supplying power in the core substrate 7 can be increased in parallel, and the impedance of the power supply through-hole conductor 10P in the core substrate 7 can be reduced. inductance. Therefore, the power supply wiring can be stabilized, and the electronic component 2 can be operated with high reliability. In addition, the number of power supply through-hole conductors 10P is set to be, for example, twice or more and four times or less the number of power supply pads 14P.

In the power supply bonding pad 14P, the power supply via conductor 13P, and the power supply via conductor 10P (that is, in one set of power supply wiring), the number of power supply through hole conductors 10P is Passing through the third insulating layer 11c located at the uppermost layer The number of power supply via conductors 13P is large. As a result, the impedance and inductance of the power supply through-hole conductor 10p of the base 9 having a thickness larger than that of the third insulating layer 11c are reduced in the thickness direction, whereby the voltage of the power supply wiring can be effectively stabilized.

In the present embodiment, the number of power supply via conductors 13P penetrating through the third resin layer 11c is equal to the number of power supply pads 14P, and the power supply via conductors 13P penetrating through the third resin layer 11c are respectively connected to the power source. Connected by pad 14P.

In the present embodiment, the number of power supply via-conductors 13P that penetrate the first resin layer 11a is equal to the number of power supply through-hole conductors 10P, and the power supply via conductor 13P that penetrates the first resin layer 11a is used. Each is connected to the power supply through-hole conductor 10P. In the conductive layer 12 (FC2) on the first resin layer 11a, the power source via hole conductors 13P penetrating through the first resin layer 11a are electrically connected to each other in the block surface layer of the power source conductive layer 12P. A power supply via conductor 13P that penetrates the second resin layer 11b is connected to the bulk layer of the power supply conductive layer 12P. The number of the power source via-hole conductors 13P penetrating through the second resin layer 11b is smaller than the number of the power source via-hole conductors 13P penetrating through the first resin layer 11a, and the power source via-hole conductor penetrating the third resin layer 11c. The number of 13P is equal. The power supply via conductor 13P that penetrates the second resin layer 11b is connected to the power supply via conductor 13P that penetrates the third resin layer 11c. Further, the number of power source via conductors 13P in each layer can be appropriately changed.

Further, in the present embodiment, the power supply through-hole conductor 10P is filled in a through hole for a power supply that penetrates the base 9P in the thickness direction. As a result, the impedance and inductance of one power supply via-hole conductor 10P can be reduced.

In the present embodiment, in the group of the grounding pads 14G and the grounding via conductors 10G that are electrically connected (that is, in the grounding wiring), the number of the grounding through-hole conductors 10G is larger than that of the grounding pads 14G. The number is large. Result, with power supply In the same manner as the wiring, the voltage can be stabilized in the grounding wiring, and the electronic component 2 can be operated with high reliability.

In the group of the grounding pads 14G, the grounding via conductors 13G, and the grounding via conductors 10G (that is, one set of grounding wirings) that are electrically connected, the number of grounding through-hole conductors 10G is proportional to the through-position. The number of the grounding via conductors 13g in the third insulating layer 11c of the uppermost layer is large. As a result, the impedance and inductance of the grounding through-hole conductor 10G of the base 9 having a thickness larger than that of the third insulating layer 11c are reduced in the thickness direction, whereby the voltage of the grounding wiring can be effectively stabilized.

In the present embodiment, the number of the grounding via conductors 13G that penetrate the third resin layer 11c is equal to the number of the grounding pads 14G, and the grounding via conductors 13G that penetrate the third resin layer 11c are grounded and grounded. Pad 14G is connected.

In the present embodiment, the grounding through-hole conductor 10G is electrically connected to the block portion of the grounding conductive layer 12G in the conductive layer 12 (FC1) on the substrate 9. Further, the ground via conductor 13G penetrating the first resin layer 11a is connected to the block surface portion of the ground conductive layer 12G. The number of the grounding via-hole conductors 13G that penetrate the first resin layer 11a is smaller than the number of the grounding via-hole conductors 10G, and the number of the grounding via-hole conductors 13G that penetrate the second resin layer 11b is the third. The number of the grounding via conductors 13G of the resin layer 11c and the number of the grounding via pads 14G are equal. Further, the number of the grounding via conductors 13G in each layer can be appropriately changed.

On the other hand, in a group of signal pads and signal through-hole conductors that are electrically connected (that is, in one set of signal wires), the number of signal through-hole conductors is the number of signal pads. equal. As a result, it is possible to connect the signal pad and the signal through-hole conductor in a one-to-one manner, and it is possible to transmit well in the signal wiring. signal.

As described above, the above-described mounting structure 1 drives and controls the electronic component 2 in accordance with the power source and signal supplied through the wiring board 4, thereby exerting a desired function.

Next, a method of manufacturing the above-described mounting structure 1 will be described based on the drawings.

(1) As shown in Fig. 5, a core substrate is produced. Specifically, it is carried out as follows.

A copper-clad laminate formed of a base 9 obtained by curing an uncured resin sheet and a copper foil disposed on the upper and lower sides of the base 9 is provided. Next, a through hole is formed in the copper clad laminate 5x by sandblasting. Next, a through-hole conductor 10 is formed by filling a conductive material in a through hole by, for example, electroless plating, electrolytic plating, vapor deposition, CVD (Chemical Vapor Deposition) or sputtering. . Next, the copper foil on the substrate 9 is patterned by a conventionally known photolithography technique, etching, or the like to form the conductive layer 12. In the above manner, the core substrate 7 can be fabricated.

Here, a method of forming a through hole by sandblasting will be described in detail.

First, a resist having an opening at a portion where the through hole is formed is formed on both surfaces of the copper clad laminate. This resist can be formed, for example, by exposure and development of a photosensitive resin. Next, fine particles are ejected from the nozzle of the blasting apparatus toward one main surface of the copper clad laminate, whereby a part of the through hole (non-through) is formed through the opening of the resist. Next, fine particles are ejected toward the other main surface of the copper clad laminate, whereby a through hole penetrating the base 9 is formed. Further, the through hole penetrating through the base 9 can also be formed by spraying fine particles only on one main surface of the copper clad laminate. Next, the resist is removed with, for example, 1 to 3 wt% sodium hydroxide solution. Then, through The inner wall of the hole is subjected to high-pressure water washing, thereby removing residual fine particles or machining chips of the through hole. In the above manner, the through hole can be formed by sandblasting.

When the sand blasting method is used as described above, the through holes are formed by the ejection of the fine particles, so that the stress applied to the boundary between the glass fibers and the resin and the heat energy can be reduced as compared with the drilling process. Furthermore, the thermal energy applied to the boundary between the glass fiber and the resin can be reduced compared to the laser processing. Therefore, when the blasting method is used, the peeling of the glass fiber and the resin can be reduced as compared with the drilling process or the laser processing. Therefore, it is possible to reduce the short circuit between the adjacent through-hole conductors 10 and to reduce the interval, and it is possible to narrow the pitch of the through-hole conductors 10. As a result, as described above, the power supply through-hole conductor 10P can be narrowly pitched compared to the power supply pad 14P, and the number of power supply through-hole conductors 10P can be made larger than the number of power supply pads 14P. In addition, the number of the grounding through-hole conductors 10G can be made larger than the number of the grounding pads 14G in the same manner as the power supply through-hole conductors 10P.

Since the sandblasting process is performed after the resist is used, the plurality of through holes can be simultaneously processed by spraying the fine particles in a wide range, so that the through holes can be formed efficiently compared to the drilling process or the laser processing. Therefore, even if the number of through holes is increased, it is possible to suppress an increase in processing time and the like.

When sandblasting is used, when the content of the cerium oxide filler in the base 9 is increased, the drill is not worn as in the drilling process, and the through hole can be formed more easily than the laser processing.

In order to form a through hole by sandblasting as described above, the blasting can be performed using the following conditions.

First, the sandblasting process is performed by dry blasting. As a result, compared to wet blast, it can be less resistant to microparticles. It is possible to improve the machinability of the through hole, and to reduce the residual work debris during cutting, and to reduce the cutting hindrance caused by the machining debris.

As the fine particles sprayed in the blasting, fine particles (broken particles) containing an inorganic insulating material having a hardness higher than that of the glass can be used. As a result, the glass fiber which is exposed to the inner wall of the through hole can be efficiently cut by the sharp end portion of the crushed particle which is harder than the glass fiber, so that the stress applied between the glass fiber and the resin can be reduced, and the efficiency is improved. The through holes are formed well. As described above, for the inorganic insulating material having a higher hardness than the glass, for example, alumina, tantalum carbide, or zirconia can be used. Among these materials, alumina is preferably used. Further, in terms of hardness, Vickers hardness can be used.

The maximum diameter of the microparticle-based disrupted particles is set to be 3 μm or more and 40 μm or less. As a result, by setting the maximum diameter to 3 μm or more, the machinability by the crushed particles can be improved, and the through holes can be easily formed. Further, by setting the maximum diameter to 40 μm or less, it is possible to form a through hole without blocking the hole.

It is preferable to set the pressure of the injected fine particles to 0.15 MPa or more and 0.22 MPa or less. As a result, by setting the pressure to 0.15 MPa or more, the glass fiber in the through hole can be efficiently cut. Further, by setting the pressure to 0.22 MPa or less, it is possible to perform processing so that the crushed particles do not collide with each other and excessively cut the resin of the inner wall of the through hole.

The amount of ejection of the fine particles is preferably set to be 30 g/min or more and 200 g/min or less. As a result, by setting the injection amount to 30 g/min or more, the glass fiber located in the through hole can be efficiently cut. Further, by setting the injection amount to 200 g/min or less, it is possible to perform processing so that the crushed particles do not collide with each other and excessively cut the resin of the inner wall of the through hole.

When the thickness of the core substrate 7 is 40 μm or more and 200 μm or less, the number of times (the number of scans) of the fine particles to be ejected in one through hole is set to be 4 or more and 20 or less, for example.

The matrix 9 in which the fine particles are sprayed is set to have a content ratio of the cerium oxide filler of 40% by volume or more and 75% by volume or less. As a result, by setting the content ratio of the cerium oxide filler to 40% by volume or more, the machinability of the resin layer 15 by the blast processing can be improved. Further, by setting the content ratio of the cerium oxide filler to 75% by volume or less, the cerium oxide filler from the inner wall of the through-hole is formed during the formation of the through-hole, and the occurrence of bubbles remaining in the depression due to the granulation can be reduced. The case where the adhesion strength between the inner wall of the hole and the conductive layer 12 is lowered. Further, the content ratio of the cerium oxide filler can be obtained by calculating the ratio of the volume of the cerium oxide filler to the total volume of the resin and the cerium oxide filler in the region of the glass fiber not including the matrix 9.

Here, it is preferable that the inner wall of the through hole formed by sandblasting is not subjected to desmear treatment. When the through hole is formed by sandblasting, the heat applied to the inner wall of the through hole can be reduced to reduce the residue of the carbonized resin compared to the drilling or laser processing. Further, since the intermolecular bond is physically cut, the reactivity of the surface of the resin exposed on the inner wall of the through hole can be improved. As described above, by eliminating the desmear treatment, it is possible to reduce the possibility that only the resin is selectively etched to expose the side surface of the glass fiber, and the peeling of the resin and the glass fiber can be reduced.

(2) As shown in Fig. 6, a pair of buildup layers 8 are formed on both sides of the core substrate 7, whereby the wiring substrate 4 is produced. Specifically, it is performed as follows.

First, an uncured resin is placed on the conductive layer 12, the resin is heated and fluidly adhered, and further heated to harden the resin, whereby the insulating layer 11 is formed on the conductive layer 12. Next, a via hole is formed by laser processing, and the guide is guided At least a portion of the electrical layer 12 is exposed within the via. As described above, by forming the via holes by the laser processing, it is possible to reduce the damage of the conductive layer 12 exposed in the via holes compared to the sandblasting process. Next, the via conductor 13 is formed in the via hole by, for example, semi-additive, subtractive, or full-additive, and the conductive layer 12 is formed in The upper surface of the insulating layer 11. The buildup layer 8 can be formed by repeating the above steps. Further, the pad 14 can be formed on the upper surface of the uppermost insulating layer 11 in the same manner as the conductive layer 12.

In the above manner, the wiring board 4 can be produced. Further, by repeating this step, the insulating layer 11 and the conductive layer 12 can be further multilayered in the buildup layer 8.

(3) The bump 3 is formed on the upper surface of the pad 14, and the electronic component 2 is flip-chip mounted on the wiring substrate 4 via the bump 3.

In the above manner, the mounting structure 1 shown in Fig. 1(a) can be produced.

The present invention is not limited to the above-described embodiments, and various modifications, improvements, combinations, and the like can be made without departing from the scope of the invention.

For example, in the above embodiment, the configuration in which the buildup layer includes three insulating layers has been described as an example, but the buildup layer may include any number of insulating layers.

In the above-described embodiment, the configuration in which the through-hole conductor is filled in the through-hole is described as an example. However, the through-hole conductor may be disposed in the through-hole, and the inner wall of the through-hole may be covered in a tubular shape.

In the above embodiment, the configuration in which the via hole conductor is filled in the via hole has been described as an example. However, the via hole conductor may be disposed in the via hole, and the inner wall of the via hole may be covered in a tubular shape.

In the above embodiment, a plurality of via conductors are stacked. The stacked configuration, but can also be a stacked configuration, for example can be a spiral configuration.

In the above embodiment, the configuration in which the copper foil is used in the step (1) has been described as an example. However, a metal foil containing a metal material such as an iron-nickel alloy or an iron-nickel-cobalt alloy can be used.

3‧‧‧Bumps

4‧‧‧Wiring substrate

5‧‧‧Semiconductor substrate

6‧‧‧ terminals

6G‧‧‧ grounding terminal

6P‧‧‧Power terminal

7‧‧‧ core substrate

8‧‧‧Additional

8a‧‧‧1st build-up

8b‧‧‧2nd layer

9‧‧‧ base

10‧‧‧through hole conductor

10G‧‧‧ Grounding through hole conductor

10P‧‧‧through hole conductor for power supply

11‧‧‧Insulation

11a‧‧‧1st insulation layer

11b‧‧‧2nd insulation layer

11c‧‧‧3rd insulation layer

12‧‧‧ Conductive layer

12G‧‧‧ Conductive layer for grounding

12P‧‧‧ Conductive layer for power supply

13‧‧‧Guide conductor

13G‧‧‧ Grounding via conductor

13P‧‧‧Power guide hole conductor

14‧‧‧ solder pads

14G‧‧‧ Grounding pad

14P‧‧‧Power pad

Claims (9)

A wiring board comprising: a core substrate; and a buildup layer on the core substrate and having an electronic component mounted on the upper surface; the core substrate has a base body; and a plurality of power supply through holes penetrating the base body in a thickness direction a conductor; the build-up layer has an insulating layer having a thickness smaller than that of the base; and a plurality of power supply pads are electrically connected to the power supply terminal of the electronic component and the power supply through-hole conductor and formed on the insulating layer; a plurality of power supply via conductors penetrating the insulating layer in a thickness direction, and electrically connecting the power supply through-hole conductor and the power supply pad; and electrically connecting the group of the power supply pads and the power source In the through-hole conductor, the number of the through-hole conductors for the power supply is larger than the number of the power supply pads. The wiring board according to the first aspect of the invention, wherein the insulating layer has a multilayer structure, and is electrically connected to the power supply pad, the power supply via hole conductor, and the power supply through hole conductor. The number of the through-hole conductors for the power source is larger than the number of the power-conducting via conductors that penetrate the uppermost layer among the layers constituting the insulating layer. The wiring board according to the first aspect of the invention, wherein the power supply through-hole conductor is filled in a power supply through hole penetrating the base body in a thickness direction. The wiring board according to the first aspect of the invention, wherein the core substrate further includes a plurality of grounding through-hole conductors penetrating the substrate in a thickness direction; and the additional layer further includes: a plurality of grounding pads; The grounding terminal of the electronic component and the grounding through-hole conductor are electrically connected to each other and formed on the insulating layer; and a plurality of grounding via conductors penetrate the insulating layer in a thickness direction and the grounding through-hole conductor The grounding pads are electrically connected to each other, and the number of the grounding through-hole conductors is larger than the number of the grounding pads in the grounding bonding pads and the grounding through-hole conductors that are electrically connected. The wiring board according to the first aspect of the invention, wherein the core substrate further includes a plurality of signal through-hole conductors penetrating the substrate in a thickness direction, and the additional layer further includes: a plurality of signal pads; a signal terminal for the electronic component and the signal through-hole conductor are electrically connected to each other and formed on the insulating layer; and a plurality of signal via conductors penetrate the insulating layer in a thickness direction and use the through-hole conductor for the signal And the signal is electrically connected by a pad; wherein the number of the signal through-hole conductors and the signal pad are used in the group of the signal pads and the signal through-hole conductors that are electrically connected The number is equal. A mounting structure comprising the wiring board according to claim 1 and an electronic component mounted on the build-up layer of the wiring board and electrically connected to the power supply terminal and the power supply pad. A method of manufacturing a wiring substrate, comprising: a step of preparing a substrate; forming a core substrate by forming a plurality of power supply through-hole conductors penetrating the substrate in a thickness direction and forming a plurality of power supply through-hole conductors through the plurality of power supply through-holes; And forming an insulating layer having a smaller thickness than the base body on the core substrate, and forming a plurality of power supply pads electrically connected to the power supply terminal of the electronic component and the power supply through-hole conductor on the insulating layer. The step of forming a build-up layer of the electronic component on the core substrate; and the number of the power supply through-hole conductors in the power supply pad and the power supply through-hole conductor that are electrically connected; It is more than the number of pads for power supply mentioned above. The method for producing a wiring board according to claim 7, wherein the insulating layer has a multilayer structure, and in the step of forming the build-up layer on the core substrate, laser processing is used to form a thickness direction. a plurality of power supply via holes for the insulating layer, and a plurality of power supply via conductors are formed in the plurality of power supply vias, and the plurality of power supply via conductors are formed through the plurality of power supply via conductors a plurality of power supply pads electrically connected to the hole conductor; and one of the power supply pads, the power supply via conductors, and the power supply through-hole conductors that are electrically connected, the power supply through-hole conductor The number is larger than the number of the power source via conductors that pass through the uppermost layer among the layers constituting the insulating layer. A manufacturing method of the mounting structure, comprising the step of electrically connecting the power supply end of the electronic component to the power supply pad of the wiring board produced by the method of manufacturing the wiring board according to the seventh aspect of the invention. The electronic components are mounted on the build-up layer.