TW201346290A - IC reliability testing method - Google Patents

Abstract

An IC reliability testing method is provided. The method includes forming a plurality of integrated circuits on a wafer substrate; putting the wafer substrate into a tester and coupling the plurality of integrated circuits with the testing circuits of the tester; providing the tester a testing condition including a normal operating temperature, a stress temperature, a normal operating voltage, a stress voltage, an activation energy, and a tester parameter; simultaneously testing the plurality of integrated circuits by the tester with the testing condition for a period of testing time; providing a confidence parameter when the plurality of integrated circuits all remain functioning after the period of testing time; and obtaining an estimated IC life in accordance with the values included in the testing condition and the confidence parameter.

Description

Integrated circuit reliability test method

The invention relates to a method for testing the reliability of an integrated circuit.

As electronic devices become thinner and lighter, the speed and complexity of wafers are relatively higher, so the reliability of integrated circuits is becoming higher and higher. Therefore, in order to ensure that all the integrated circuits are functioning properly and meet customer requirements, some reliability tests are usually performed, such as High Temperature Operation Life (HTOL, Test) and High Temperature Storage Reliability Test (High Temperature Storage). Life, HTOL, Test), Solder Joint Reliability Test, Temperature Cyclic Test, Three Point Bending Test, Vibration Test, and the like. Among them, the results of the high-temperature action reliability test are used as an important reference for evaluating the service life of electronic products using this integrated circuit.

In the conventional high-temperature operation reliability test, the integrated circuit to be tested is first packaged one by one, and then placed on the machine for testing, and the test time may be several days to several weeks. If the test results are not as expected and need to be redesigned, the newly manufactured integrated circuit will be repackaged and then tested over a period of time. Therefore, the conventional high-temperature operation reliability test not only has a high cost in packaging, but also has a low efficiency due to a long time required for testing, and there is room for improvement.

The main object of the present invention is to provide a method for testing the reliability of an integrated circuit, which can shorten the test time.

Another object of the present invention is to provide a method for testing the reliability of an integrated circuit, which can improve the efficiency of the design work of the integrated circuit.

The method for testing the reliability of an integrated circuit of the present invention comprises the steps of: forming a plurality of integrated circuits on a wafer substrate; placing the wafer substrate into the test device to couple the plurality of integrated circuits with the test circuit of the test device; Providing test conditions to the test machine, the test conditions include normal operating temperature, pressure operating temperature, normal operating voltage, pressure operating voltage, activation energy, and machine parameters; using a test machine to simultaneously test a plurality of integrated circuits under test conditions Test, and continue testing time; when a plurality of integrated circuits are still operating correctly after the test time, the confidence parameter value is provided; and the estimated life of the integrated circuit is obtained according to the value of each condition included in the test condition and the value of the confidence parameter.

The step of estimating the life of the integrated circuit includes calculating the value of each condition included in the test condition, the test time, and the value of the confidence parameter into the following formula (1) to obtain the estimated life of the integrated circuit;

Among them, MTTF represents the estimated life of the integrated circuit, the unit is hour; Ea represents the activation energy, the unit is eV; k is 8.62×10 ^-5 , the unit is eV/K; T _use represents the normal operating temperature, the unit is K; _stress indicates stress operating temperature, in K; Y _v represents the machine parameters, in units of 1 / V; V _use represents a normal operating voltage, in V; V _stress represents a stress operating voltage, in V; TH represents a test time; SS represents the number of values of a plurality of integrated circuits in hours; and X ² (%CL, 2r+2) represents the value of the confidence parameter.

The test condition further includes an oxide layer thickness, and the integrated circuit estimation life obtaining step includes calculating the value of each condition included in the test condition, the test time, and the confidence parameter value into the following formula (2) to obtain an estimated life of the integrated circuit;

Among them, MTTF represents the estimated life of the integrated circuit, the unit is hour; Ea represents the activation energy, the unit is eV; k is 8.62×10 ^-5 , the unit is eV/K; T _use represents the normal operating temperature, the unit is K; _stress indicates stress operating temperature, in K; Y represents a machine parameter, in units of cm / MV; V _use represents a normal operating voltage, in V; V _stress represents a stress operating voltage, in V; TOX represents the oxide thickness, Unit is ;TH denotes the test time; SS denotes the number of the plurality of integrated circuits, the unit is hour; and X ² (%CL, 2r+2) denotes the confidence parameter value.

The confidence parameter value providing step includes determining the test confidence ratio; and obtaining a confidence parameter value corresponding to the test confidence ratio by the Chi-Square Distribution table. The number of integrated circuits formed by the plurality of integrated circuit forming steps is between 1,000 and 10,000. The step of placing the wafer substrate into the test device includes coupling the plurality of integrated circuits to the test circuit of the test device in parallel.

The integrated circuit reliability test method of the present invention comprises the following steps: providing an estimated life of an integrated circuit, a confidence parameter value, a number of integrated circuits, and a test condition, and the test conditions include a normal operating temperature, a pressure operating temperature, a normal operating voltage, Pressure operating voltage, activation energy and machine parameters, wherein the confidence parameter value is based on the test confidence ratio, and the confidence parameter value corresponding to the test confidence ratio is obtained from the confidence parameter table, and the number of integrated circuits is an integer of ≧2; Circuit life expectancy, confidence parameter value, number of integrated circuits and test conditions to obtain test time; integrated circuit for forming the number of integrated circuits on the wafer substrate; placing the wafer substrate into the test device to make a plurality of integrated circuits and The test circuit of the test device is coupled; the test machine is used to test a plurality of integrated circuits simultaneously under the test condition, and the test time is continued; and it is observed whether all of the integrated circuits are still operating correctly after the test time. The number of integrated circuits is preferably between 1000 and 10,000.

The test time obtaining step includes substituting the values of the integrated circuit estimated life, the confidence parameter value, the number of integrated circuits, and the conditions included in the test condition into the following formula (1) to obtain a test time;

Among them, MTTF represents the estimated life of the integrated circuit, the unit is hour; Ea represents the activation energy, the unit is eV; k is 8.62×10 ^-5 , the unit is eV/K; T _use represents the normal operating temperature, the unit is K; _stress indicates stress operating temperature, in K; Y _v represents the machine parameters, in units of 1 / V; V _use represents a normal operating voltage, in V; V _stress represents a stress operating voltage, in V; TH represents a test time; SS represents the number of values of a plurality of integrated circuits in hours; and X ² (%CL, 2r+2) represents the value of the confidence parameter.

The test condition further includes an oxide layer thickness, and the test time obtaining step includes substituting the values of the integrated circuit estimated life, the confidence parameter value, the number of integrated circuits, and the conditions included in the test condition into the following formula (2) to obtain an integrated body. Circuit life expectancy;

Among them, MTTF represents the estimated life of the integrated circuit, the unit is hour; Ea represents the activation energy, the unit is eV; k is 8.62×10 ^-5 , the unit is eV/K; T _use represents the normal operating temperature, the unit is K; _stress indicates stress operating temperature, in K; Y represents a machine parameter, in units of cm / MV; V _use represents a normal operating voltage, in V; V _stress represents a stress operating voltage, in V; TOX represents the oxide thickness, Unit is ;TH denotes the test time; SS denotes the number of the plurality of integrated circuits, the unit is hour; and X ² (%CL, 2r+2) denotes the confidence parameter value.

As shown in the flow chart of the preferred embodiment shown in FIG. 1, the method for testing the reliability of the integrated circuit of the present invention includes, for example, the following steps.

In step 1010, a plurality of integrated circuits are formed on the wafer substrate. Specifically, a plurality of integrated circuits are formed on the wafer substrate by repeatedly applying a semiconductor program such as thermal processing, deposition, lithography, or etching. The integrated circuit can be a logic circuit, a digital bit, an analog circuit, or the like. Among them, the number of integrated circuits formed is preferably between 1,000 and 10,000.

In step 1030, the wafer substrate is placed in the test device, and the plurality of integrated circuits are coupled to the test circuit of the test device. Specifically, the test device is a wafer substrate test device having a temperature increase function and an integrated circuit test program. After the wafer substrate is placed in the test device, the plurality of integrated circuits are preferably coupled to the test circuit of the test device in parallel or in series.

In step 1050, test conditions are provided to the test machine. The test conditions include a normal operating temperature, a pressure operating temperature, a normal operating voltage, a pressure operating voltage, an activation energy, and a machine parameter. Specifically, the above test conditions are input to the integrated circuit test program of the test machine.

In step 1070, the test machine is used to test a plurality of integrated circuits simultaneously under test conditions, and the test time is continued. Specifically, the test machine is controlled by the integrated circuit test program, so that the test machine simultaneously tests a plurality of integrated circuits in accordance with the test conditions and continues for a given test time.

In step 1090, when a plurality of integrated circuits are still operating correctly after the test time, a confidence parameter value is provided. Specifically, the test confidence ratio of the reliability test is determined first, and then the confidence parameter value corresponding to the test confidence ratio is obtained by the Chi-Square Distribution. For example, under the test confidence ratio of 60%, the confidence parameter value obtained by looking up the table is 1.83258; under the test confidence ratio of 90%, the confidence parameter value obtained by looking up the table is 4.60517.

In step 1110, the estimated life of the integrated circuit is obtained according to the values of the conditions included in the test condition and the value of the confidence parameter.

Specifically, in a preferred embodiment, step 1110 includes substituting the value of each condition included in the test condition, the test time, and the confidence parameter value into the following formula (1) to obtain an estimated life of the integrated circuit;

Among them, MTTF represents the estimated life of the integrated circuit, the unit is hour; Ea represents the activation energy, the unit is eV; k is 8.62×10 ^-5 , the unit is eV/K; T _use represents the normal operating temperature, the unit is K; _stress indicates stress operating temperature, in K; Y _v represents the machine parameters, in units of 1 / V; V _use represents a normal operating voltage, in V; V _stress represents a stress operating voltage, in V; TH represents a test time; SS represents the number of values of a plurality of integrated circuits in hours; and X ² (%CL, 2r+2) represents the value of the confidence parameter. The actual data is as follows:

[Example 1] Test Conditions:

The number of integrated circuits formed on the wafer substrate was 80, and the test time was 1000 hours. Under the test confidence ratio of 60%, the confidence parameter value obtained by looking up the table is 1.83258; under the test confidence ratio of 90%, the confidence parameter value obtained by looking up the table is 4.60517. From the above formula (1), it can be seen that the estimated life of the integrated circuit is 94,546,216 hours under the test confidence ratio of 60%; the estimated life of the integrated circuit is 3,766,668 hours under the test confidence ratio of 90%.

[Embodiment 2] Test Conditions:

The number of integrated circuits formed on the wafer substrate was 1000, and the test time was 80 hours. Under the test confidence ratio of 60%, the confidence parameter value obtained by looking up the table is 1.83258; under the test confidence ratio of 90%, the confidence parameter value obtained by looking up the table is 4.60517. From the above formula (1), it can be seen that the estimated life of the integrated circuit is also 9465416 hours under the test confidence ratio of 60%; at 90% of the test confidence ratio, the estimated life of the integrated circuit is also 3766668 hours.

Specifically, in the case where the same integrated circuit estimated life is obtained, increasing the number of integrated circuits formed on the wafer substrate can reduce the test time. In other words, the present invention can achieve the effect of shortening the test time by increasing the number of integrated circuits simultaneously measured. Since the test time is shortened, the estimated life of the integrated circuit can be known in a short time, and the present invention can improve the efficiency of the integrated circuit design work as a reference for evaluating the quality of the integrated circuit and whether it needs to be redesigned.

In various embodiments, the test conditions further comprise an oxide layer thickness. Wherein, the oxide layer comprises SiO ₂ , and the function of the oxide layer is to form an electron blocking layer in the transistor element. In formula (1), since the acceleration factor is constant in the conventional operation experience, that is, the thickness of different oxide layers is not considered, the machine parameter can be regarded as a simple voltage acceleration factor (Voltage Acceleration Factor), and the value and unit are 1V ^-1 . However, in equation (2), because of the electric field effect considering the thickness of different oxide layers, the machine parameters should be regarded as the Electric Field Acceleration Factor (β), with oxide thickness = 65.0. For example, the value and unit are 3.080 cm/MV. Step 1010 includes substituting the value of each condition included in the test condition, the test time, and the confidence parameter value into the following formula (2) to obtain an estimated life of the integrated circuit;

Among them, MTTF represents the estimated life of the integrated circuit, the unit is hour; Ea represents the activation energy, the unit is eV; k is 8.62×10 ^-5 , the unit is eV/K; T _use represents the normal operating temperature, the unit is K; _stress indicates stress operating temperature, in K; Y represents a machine parameter, in units of cm / MV; V _use represents a normal operating voltage, in V; V _stress represents a stress operating voltage, in V; TOX represents the oxide thickness, Unit is ;TH represents the test time in hours; SS represents the number of complex circuits; and X ² (%CL, 2r+2) represents the confidence parameter value. The actual data is as follows:

[Embodiment 3] Test Conditions:

The number of integrated circuits formed on the wafer substrate was 77, and the test time was 1000 hours. Under the test confidence ratio of 60%, the confidence parameter value obtained by looking up the table is 1.83258; under the test confidence ratio of 90%, the confidence parameter value obtained by looking up the table is 4.60517. From the above formula (1), it can be seen that the estimated life of the integrated circuit is 16896658 hours under the test confidence ratio of 60%; the estimated lifetime of the integrated circuit is 6723856 hours under the test confidence ratio of 90%.

[Embodiment 4] Test Conditions:

The number of integrated circuits formed on the wafer substrate was 1000, and the test time was 77 hours. Under the test confidence ratio of 60%, the confidence parameter value obtained by looking up the table is 1.83258; under the test confidence ratio of 90%, the confidence parameter value obtained by looking up the table is 4.60517. From the above formula (1), it can be seen that the estimated life of the integrated circuit is 16896658 hours under the test confidence ratio of 60%; the estimated lifetime of the integrated circuit is also 6723856 hours under the test confidence ratio of 90%.

Further, the difference between the integrated circuit reliability test method of the present invention and the prior art technical solution is that the number of integrated circuits measured simultaneously is increased, thereby achieving the technical effect of shortening the test time. Therefore, from a different perspective, the integrated circuit designer can also pre-define the estimated life of the integrated circuit, the confidence parameter value, the number of integrated circuits and the test conditions, in order to calculate the required test time, and then observe the multiple Whether the integrated circuit is still operating correctly after the test time can be known whether the design of the integrated circuit is good. As shown in FIG. 2, the integrated circuit reliability test method of the present invention includes, for example, the following steps.

Step 2010, providing an estimated life of the integrated circuit, a confidence parameter value, a number of integrated circuits, and a test condition, where the test conditions include a normal operating temperature, a pressure operating temperature, a normal operating voltage, a pressure operating voltage, an activation energy, and a machine parameter, wherein The confidence parameter value is based on the test confidence ratio, and the confidence parameter value corresponding to the test confidence ratio is obtained from the confidence parameter table, and the number of integrated circuits is an integer of ≧2. The number of integrated circuits is preferably between 1000 and 10,000.

In step 2030, the test time is obtained according to the estimated life of the integrated circuit, the confidence parameter value, the number of integrated circuits, and the test condition.

Step 2050, forming an integrated circuit of the number of integrated circuits on the wafer substrate. Specifically, a plurality of integrated circuits are formed on the wafer substrate by repeatedly applying a semiconductor program such as thermal processing, deposition, lithography, or etching.

In step 2070, the wafer substrate is placed in the test device, and the plurality of integrated circuits are coupled to the test circuit of the test device. Specifically, the test device is a wafer substrate test device having a temperature increase function and an integrated circuit test program. After the wafer substrate is placed in the test device, the plurality of integrated circuits are preferably coupled to the test circuit of the test device in parallel or in series.

In step 2090, a plurality of integrated circuits are simultaneously tested using the test machine under test conditions, and the test time is continued. Specifically, the test machine is controlled by the integrated circuit test program, so that the test machine simultaneously tests a plurality of integrated circuits in accordance with the test conditions and continues for a given test time.

In step 2110, it is observed whether all of the integrated circuits are still operating correctly after the test time.

Specifically, step 2030 includes substituting the values of the integrated circuit life expectancy, the confidence parameter value, the number of integrated circuits, and the conditions included in the test condition into the following formula (1) to obtain a test time;

Among them, MTTF represents the estimated life of the integrated circuit, the unit is hour; Ea represents the activation energy, the unit is eV; k is 8.62×10 ^-5 , the unit is eV/K; T _use represents the normal operating temperature, the unit is K; _stress indicates stress operating temperature, in K; Y _v represents the machine parameters, in units of 1 / V; V _use represents a normal operating voltage, in V; V _stress represents a stress operating voltage, in V; TH indicates the test time, The unit is hour; SS indicates the number of complex circuits; and X ² (%CL, 2r+2) indicates the confidence parameter value. The actual data is as follows:

[Embodiment 5] Test Conditions:

Under the test confidence ratio of 60% (the confidence parameter value obtained by looking up the table is 1.83258), the estimated life of the integrated circuit is set to 9465416 hours; or at the test confidence ratio of 90% (the confidence parameter value obtained by looking up the table is 4.60517). When the estimated lifetime of the integrated circuit is 3766668 hours and the number of integrated circuits formed on the wafer substrate is 1000, the test time is 80 hours by the above formula (1). In other words, if the integrated circuit keeps working well after 80 hours, it means passing the reliability test.

The test condition further includes an oxide layer thickness, and step 2030 includes substituting the values of the integrated circuit estimated life, the confidence parameter value, the number of integrated circuits, and the conditions included in the test condition into the following formula (2) to obtain an integrated circuit Estimate life expectancy;

Among them, MTTF represents the estimated life of the integrated circuit, the unit is hour; Ea represents the activation energy, the unit is eV; k is 8.62×10 ^-5 , the unit is eV/K; T _use represents the normal operating temperature, the unit is K; _stress indicates stress operating temperature, in K; Y represents a machine parameter, in units of cm / MV; V _use represents a normal operating voltage, in V; V _stress represents a stress operating voltage, in V; TOX represents the oxide thickness, Unit is ;TH represents the test time in hours; SS represents the number of complex circuits; and X ² (%CL, 2r+2) represents the confidence parameter value. The actual data is as follows:

[Embodiment 6] Test Conditions:

Under the test confidence ratio of 60% (the confidence parameter value obtained by looking up the table is 1.83258), the estimated life of the integrated circuit is set to 16896658 hours; or at the test confidence ratio of 90% (the confidence parameter value obtained by looking up the table is 4.60517). When the estimated lifetime of the integrated circuit is 6,723,856 hours and the number of integrated circuits formed on the wafer substrate is 1000, the test time is 77 hours by the above formula (1). In other words, if the integrated circuit remains in good operation after 77 hours, it means passing the reliability test.

While the foregoing description of the preferred embodiments of the invention, the embodiments of the invention The spirit and scope of the principles of the invention. Modifications of many forms, structures, arrangements, ratios, materials, components and components can be made by those skilled in the art to which the invention pertains. Therefore, the embodiments disclosed herein are to be considered as illustrative and not restrictive. The scope of the present invention is defined by the scope of the appended claims, and the legal equivalents thereof are not limited to the foregoing description.

1 is a flow chart of a preferred embodiment of a method for testing reliability of an integrated circuit of the present invention;

2 is a flow chart of different embodiments of a method for testing reliability of an integrated circuit of the present invention.

Claims (10)

An integrated circuit reliability test method includes the steps of: forming a plurality of integrated circuits on a wafer substrate; placing the wafer substrate into a test device, and the plurality of integrated circuits and the test circuit of the test device Coupling; providing a test condition to the test machine, the test condition includes a normal operating temperature, a pressure operating temperature, a normal operating voltage, a pressure operating voltage, an activation energy, and a machine parameter; using the testing machine The plurality of integrated circuits are simultaneously tested by the test condition for a test time; when the plurality of integrated circuits still operate correctly after the test time, a confidence parameter value is provided; and according to the test The value of each condition included in the condition and the value of the confidence parameter obtain an estimated lifetime of the integrated circuit. The integrated circuit reliability test method according to claim 1, wherein the integrated circuit estimated life obtaining step includes substituting the value of each condition included in the test condition, the test time, and the confidence parameter value into the following formula (1) Calculation to obtain the estimated life of the integrated circuit; Wherein, MTTF represents the estimated life of the integrated circuit, the unit is hour; Ea represents the activation energy, the unit is eV; k is 8.62×10 ^-5 , and the unit is eV/K; T _use represents the normal operating temperature, and the unit is K; T _stress represents the pressure operating temperature, the unit is K; Y _v represents the machine parameter, the unit is 1 / V; V _use represents the normal operating voltage, the unit is V; V _stress represents the pressure operating voltage, the unit is V; TH represents the test time, the unit is hour; SS represents the number of the plurality of integrated circuits; and X ² (%CL, 2r+2) represents the confidence parameter value. The integrated circuit reliability test method according to claim 1, wherein the test condition further comprises an oxide layer thickness, and the integrated circuit estimation life obtaining step includes a value of each condition included in the test condition, the test time And the confidence parameter value is substituted into the following formula (2) to obtain the estimated life of the integrated circuit; Wherein, MTTF represents the estimated life of the integrated circuit, the unit is hour; Ea represents the activation energy, the unit is eV; k is 8.62×10 ^-5 , and the unit is eV/K; T _use represents the normal operating temperature, and the unit is K; T _stress represents the pressure operating temperature, the unit is K; Y represents the machine parameter, the unit is cm / MV; V _use represents the normal operating voltage, the unit is V; V _stress represents the pressure operating voltage, the unit is V ;TOX indicates the thickness of the oxide layer in units of ;TH indicates the test time, the unit is hour; SS indicates the number of the plurality of integrated circuits; and X ² (%CL, 2r+2) indicates the confidence parameter value. The integrated circuit reliability test method according to claim 2 or 3, wherein the confidence parameter value providing step comprises: determining a test confidence ratio; and obtaining, by the confidence parameter table, the confidence parameter value corresponding to the test confidence ratio . The integrated circuit reliability test method according to claim 1, wherein the number of integrated circuits formed by the plurality of integrated circuit forming steps is between 1,000 and 10,000. The integrated circuit reliability test method of claim 1, wherein the step of placing the wafer substrate into the test device comprises coupling the plurality of integrated circuits to the test circuit of the test device in parallel. An integrated circuit reliability test method includes the following steps: providing an integrated circuit estimated life, a confidence parameter value, an integrated circuit number, and a test condition including a normal operating temperature and a pressure operating temperature a normal operating voltage, a pressure operating voltage, an activation energy, and a machine parameter, wherein the confidence parameter value is obtained according to a test confidence ratio, and the confidence parameter value corresponding to the test confidence ratio is obtained from the confidence parameter table, The number of the integrated circuits is an integer of ≧2; a test time is obtained according to the estimated life of the integrated circuit, the confidence parameter value, the number of integrated circuits, and the test condition; the number of integrated circuits formed on a wafer substrate The integrated circuit; the wafer substrate is placed in a test device, and the plurality of integrated circuits are coupled to the test circuit of the test device; and the plurality of integrated bodies are simultaneously simultaneously used in the test condition using the test machine The circuit is tested and continues for the test time; it is observed whether all of the complex circuits are still operating correctly after the test time. The integrated circuit reliability test method according to claim 7, wherein the test time obtaining step includes estimating the lifetime of the integrated circuit, the confidence parameter value, the number of the integrated circuit, and the conditions included in the test condition. The value is substituted into the following formula (1) to obtain the test time; Wherein, MTTF represents the estimated life of the integrated circuit, the unit is hour; Ea represents the activation energy, the unit is eV; k is 8.62×10 ^-5 , and the unit is eV/K; T _use represents the normal operating temperature, and the unit is K; T _stress represents the pressure operating temperature, the unit is K; Y _v represents the machine parameter, the unit is 1 / V; V _use represents the normal operating voltage, the unit is V; V _stress represents the pressure operating voltage, the unit is V; TH represents the test time, the unit is hour; SS represents the number of the plurality of integrated circuits; and X ² (%CL, 2r+2) represents the confidence parameter value. The integrated circuit reliability test method according to claim 7, wherein the test condition further includes an oxide layer thickness, the test time obtaining step includes estimating the lifetime of the integrated circuit, the confidence parameter value, and the integrated circuit The number and the values of the conditions included in the test condition are substituted into the following formula (2) to obtain the estimated life of the integrated circuit; Wherein, MTTF represents the estimated life of the integrated circuit, the unit is hour; Ea represents the activation energy, the unit is eV; k is 8.62×10 ^-5 , and the unit is eV/K; T _use represents the normal operating temperature, and the unit is K; T _stress represents the pressure operating temperature, the unit is K; Y represents the machine parameter, the unit is cm / MV; V _use represents the normal operating voltage, the unit is V; V _stress represents the pressure operating voltage, the unit is V ;TOX indicates the thickness of the oxide layer in units of ;TH indicates the test time, the unit is hour; SS indicates the number of the plurality of integrated circuits; and X ² (%CL, 2r+2) indicates the confidence parameter value. The integrated circuit reliability test method according to claim 7, wherein the number of the integrated circuits is between 1,000 and 10,000.