TW201344627A - Depth buffer compression for stochastic motion blur rasterization - Google Patents

Abstract

A depth buffer compression scheme uses bilinear patches as a predictor for depth. The scheme targets compression of scenes rendered with stochastic blur rasterization. A tile of fragments may be split into two or more regions and a higher-degree function may be fit to each region. The residuals are then stored as delta corrections.

Description

Depth buffer compression technique for random moving fuzzy rasterization

The present invention relates generally to depth buffer compression techniques.

Background of the invention

Previous depth buffer compression mechanisms compressed the depth obtained using rasterized static triangle techniques. This provides a large amount of bandwidth usage savings and is therefore very important to the graphics processor. However, random rasterization for both motion blur and depth of field is a real problem, even for instant graphics, and because of the location and depth irregularities provided, the previous depth buffer is compressed. The algorithm fails.

In accordance with an embodiment of the present invention, a method is specifically proposed comprising the steps of: generating a patch for a block of pixels (pixel block); estimating a position of a predictor; and encoding at the predictor location And the difference between the sampling depths.

Simple illustration

Some embodiments are illustrated with reference to the following figures: FIG. 1 is a three-step illustration of a depth buffer compression algorithm in accordance with an embodiment; FIG. 2 is a schematic diagram of a clustering technique in accordance with an embodiment; A schematic diagram of Mode 1 of an embodiment, wherein a pixel block and four points in the pixel block are shown on the left and the A, B, C, and D depth values are displayed in the middle of the right sub-pixel block; Figure 4 is a diagram of three prediction function graphs according to an embodiment and showing how they have similar data reduction steps, the left graph showing a set of irregular samples with gray scale samples indicating depth, and the middle graph showing the bounding boxes of the samples So that the box is split in half in the xy dimension and in each generated sub-region, a representative depth and position are generated from the average of the two depth values (the smallest and largest of the sub-pixel blocks), and are on the right In the square graph, a data prediction patch is shown; FIG. 5 is a flowchart for clustering according to an embodiment of the present invention; and FIG. 6 is a flowchart for a prediction function according to an embodiment; The drawings are a hardware description of an embodiment of the present invention; and FIG. 8 is a front elevational view of an embodiment of the present invention.

Detailed description

Our algorithm can be used to compress from no blur (ie, no motion blur, and depth of field), but also to the depth of the scene with blur (eg, motion blur) generated from the random rasterizer. value.

In an embodiment, our algorithm may not use information from the rasterizer, which is a great advantage in terms of complexity and therefore the input may be just a group (x_i, y_i, D_i), where (x_i, y_i) is the position of the screen space in the sample, and d_i is the sample depth. We compress a set of this sample so that it can be stored in a compressed form in the off-chip memory. Our algorithm computes a bilinear patch for a non-blurred scene, and a three-linear patch for a blurred scene, where time, t, is used as the third dimension. These patches are often referred to as prediction functions. We also A four-dimensional (x, y, z, t) plane can be used. In summary, the concept is to estimate the patch position and encode the difference from the patch. The patch essentially requires relatively few memories, and the differences are encoded using bits that are much less than the actual depth value. This typically causes the compressible sample block to fall to 25%, 50%, or 75% of its original memory (for example). This savings will only be in terms of memory bandwidth usage. However, it is noted that the gap between computing power and available memory bandwidth continues to increase, and for the foreseeable future, its structure will most likely be bandwidth limited.

A very simple general architecture illustrates the depth buffer compression mechanism. Let's start with some assumptions. A block of w x h pixels, sometimes referred to as a block of pixels, is processed independently, and we assume that each pixel has n samples. The ith sample is taken as S ⁱ =( , , , Is indicated, wherein the first two constituent elements are the x- and y-coordinates of the sample inside the pixel block, and the third constituent element, [0,1] is the time of sampling. It is also possible for the lens position to describe the depth of the field, for example, ( , ), adding more components. Current depth compression mechanisms do not explicitly handle motion blur and depth of field, and therefore have neither time components nor lens parameters. Note that for a particular sample, all ( , , ) is fixed, and since the rasterizer is only depth, = z / w . Thus, only the depth value, Can be compressed. However, if possible, the algorithm is dependent on the use of fixed components for better compression.

The depth buffer compression mechanism, shown in Figure 1, typically shares three common steps, and these steps are: 1. Cluster, 2. Predictive function generation, and 3. Differential coding.

It should be noted that, however, an algorithm may not have one or two of the above steps. The various steps are further explained below.

For example, a cluster is needed when a set of samples in a block of pixels belong to a background layer and the remaining samples in the block of pixels belong to the foreground layer. In these cases, it is very difficult to compress all depths in a block of pixels using the same prediction function. The clustering step therefore attempts to separate the pixel block samples into two or more layers, where the samples in each layer will typically share some characteristics (eg, close to the camera). The purpose of cutting the sample to make two or more layers is to compress all the samples compared to a single layer, and conceptually the layers will be simpler to compress. For a block of pixels with only foreground samples, the cluster may not be required, although or only if one triangle covers an entire block of pixels. In general, a one-dimensional mask or a number of bit masks are needed to indicate that a sample belongs to that layer.

In the next step, each layer produces its own prediction function. The purpose here is to use deep sampling and possibly their fixed (x, y, t) coordinates to produce a prediction function, d(x, y, t), whose task is to try to use inexpensive (in terms of storage, production, and The function is evaluated to predict the depth of each sample. For example, assume that for a pixel block, a rectangle with a small per pixel shift has been generated. This rectangular plane can be used due to the prediction function, as it would probably be a good guess for depth. This speculation will not be 100% correct, and so the next step will correct the result.

The differential code must confirm the exact depth, It can be rebuilt during pixel block decompression because the graphics application interface (API) is generally a depth buffer that requires lossless. The difference between the prediction function, d(x, y, t), and the sample depth is calculated as follows:

Given a good prediction function, the difference between the sampling depth and the prediction function, δ _i , will be small. Therefore, the difference will be encoded using very few bits. If there are a few layers, a good compression ratio can be achieved, so the prediction function is stored with very few bits, and thus the difference can also be encoded with very few bits. Another success factor of the compression mechanism is that the algorithm should actually be actuated on many pixel blocks during formation.

First, we make n segments for the depth interval of the pixel block partition between Z _min and Z _max , as shown in block 5 of FIG. For each segment, we store a single bit, and whether there is at least one sample in the recorded segment. The bits are initialized to zero. Each sample is then sorted into a segment based on the depth value of the sample, and the corresponding bit is set to one as indicated by block 24. In this step, the cleared samples can be ignored. When all samples have been processed, each 0 represents a gap of at least (Z _{max -} Z _min ) / n depth. A good approximation of the two depth layer separations is obtained by finding the maximum range of consecutive zeros as shown by block 26.

From the left to the right of Figure 2, the depth values are marked with a cross on the depth axis, and these depth values are then constrained by Z _min and Z _max . In this case, then after segmentation, 8 small segments are generated between Z _min and Z _max , and segments with at least one deep sample are labeled 1 and further they are marked as 0. . Finally, the maximum interval of zero is found, and this separates the depth into two layers. Each of the sample aggregations generated by this step is a layer that is individually processed using the prediction function generation step. In addition, the cluster processing inherently produces one or more bit masks indicating which samples belong to that layer. The bit mask will be part of the compressed block image. If desired, sampling can be simply aggregated into more layers by finding the longest range of consecutive zeros of the second and third (etc.). It is also possible to further outline this concept. Instead of having one bit per segment, we store a counter for each segment that records how many deep samples fall within that segment. The cluster is then completed by finding the deepest and longest "valley" in the graph, where y is the counter as a function of extent (x). This produces better results.

At this point, we have a one-bit mask generated from the previous step indicating which of the wxhxn samples of the current layer of pixel blocks should be compressed. It is noted that we may have only one layer, in which case all samples are included.

Most depth buffer compression mechanisms are based on the fact that the depth d=z/w in the screen space is linear, ie: d(x,y)=z(x,y)/w(x,y)=a+ Bx+cy. (2)

However, once the time scale is included then the motion blur is generated, this is no longer the case. We deal with the compression random buffer problem caused by motion blur by increasing the time, t, to the prediction term, but also increasing the predictor dimension. In general, we can use a prediction function, d(x, y, t), which is the sum of many items: d(x, y, t) = Σ _mno a _mno x ^m y ⁿ t ^o . (3)

We propose to predict a function array according to one of the equations, which has a cluster of different significant coefficients. When compressing, we can try all possible combinations. However, we may choose from these options that appear to apply to our data types. The selected mode is listed below:

For the three modes of ours, the prediction function has 4-8 unknown coefficients (a, b, etc.). Depending on the cost of the different computations in the target platform, we can derive the prediction function from one of the two proposed methods, ie using the least squares method, or using the data reduction method.

For the smallest sequence, since each pixel block contains many samples, it is possible to establish an over-constrained linear system when determining the prediction function coefficients. Often, this system is solved by calculating a pseudo-inverse method that includes many multiply and add operations and can use the Cramer's rule to complete the inverse of a smaller matrix. If the multiplication and addition operations are low cost on the target platform, then a least squares approach may be attractive in order to find the prediction function constants.

For data reduction, the following method is based on reducing the sampling in one layer to make it more manageable points. First, I find the bounding box for all samples in x and y (Figure 6, box 32). The bounding box is then divided into 2 x 2 uniform grid cells (Fig. 6, block 34). For each cell, we find two samples with minimum and maximum depth values (Fig. 6, box 36). The center point of these two samples (in xyz) is then calculated (Figure 6, box 38). This gives us four representation points, r ^ij , with i,j {0, 1}, where i and j are grid cell coordinates.

The order of Figures 5 and 6 can be implemented using software, hardware and/or firmware. In software and firmware embodiments, the sequences may be implemented in accordance with computer executed instructions stored in one or more non-transitory computer readable media (eg, magnetic, semiconductor, or optical memory).

Similarly, for the mode considering t, we can also calculate the limit in t and instead divide the bounding box into a 2 x 2 x 2 grid cell. This results in the representation of the point r ^ijk with 8 instead of 4, with i, j, k {0,1}. Next, we explain how we deal with each specific pattern from these reduced representative data points.

Mode 0 illustrates a four-dimensional plane such that d(x, y, t) = a + bx + cy + dt. This representation is available for static and can be used for moving geometry because it contains dt items. When calculating the plane equation, we first move the origin to one of the representation points. In this way we can't calculate the best a-coefficient. Instead, we later calculate this in a differential encoding step. Then we only need to solve the bx+cy+dt entry and the three remaining representation points. Any method suitable for solving a 3x3 linear system, such as Cramer's Law, can be used to calculate these.

Mode 1 is for static geometry, that is, the part used to generate the frame without moving blur. We use a bilinear patch, which is illustrated above using d(x, y) = a + bx + cy + dxy, which we call Mode 1 (Figure 6, Box 40). The motivation for this model is twice as large as using only the plane equation. First, a bilinear patch is more elastic because it is a second-order surface. And therefore there is a higher chance of being adapted to a smoother surface change. Second, it is quite straightforward to obtain a bilinear patch.

Give four depth values, A, B, C, and D, in a 2×2 grid of rules, which directly obtain a bilinear patch such as: d(x,y)=(1-x)(1 -y) A+x(1-y)B+(1-x)yC+xyD. However, for a particular layer, we calculate four representation points, as described above for reduction, and the next problem is that each of these points may be placed in (almost) arbitrary positions inside the pixel block, and I need to get a bilinear patch from these. We have solved this problem as shown in Figure 3, where we simply calculate a plane from three points and estimate the plane depth of the desired xy position.

For mode 1, we get four points, (x _i , y _i , z _i ), i {0,1,2,3}, and we need to calculate the depth in the middle of the sub-pixel block, A, B, C, and D, as shown on the right. For example, for the top-left sub-pixel block, the plane equation is calculated from (x ₀ , y ₀ , z ₀ ), (x ₁ , y ₁ , z ₁ ), and (x ₂ , y ₂ , z ₂ ). The plane equation is then estimated at the center of the top-left sub-pixel block, which produces A. Use A, B, C, and D, which are directly rewritten in the form of d(x, y) = a + bx + cy + dxy. It is noted that it is also possible to build a linear equation system and use, for example, Cramer's law to directly resolve b, c, and d.

Mode 2 linearly interpolates two bilinear patches (P ₀ and P ₁ ) placed in t=0 and t=1 to obtain one surface that moves with time. Therefore, we get the equation z(x, y, t) = P ₀ + t(P _{1 -} P ₀ ). To calculate this representation, we first perform a data reduction to produce a 2 x 2 x 2 representation point r ^ijk . Four representation points r ^ijk , i, j {0,1}, the same as used for mode 1 is used to calculate the two patches P _k ,k {0,1}. Each patch P _k then approximately represents time Pixel block data. We then have all eight coefficients needed for this mode. In the final step, the two patches are placed at time t0=0 and t1=1 via extrapolation.

All of our prediction functions have similar data reduction steps. Figure 4 shows the setting process for the xy-patch mode. On the left, we start a set of irregular sampling. The gray scales are sampled to indicate their depth. In the middle, the sampling bounding box is found. The box is split in half in the xy dimension. Among the generated sub-regions, an average representing the depth and position from the two samples having the minimum depth 10 and the maximum depth 12 is generated. On the right, we then have a data prediction patch. To make it easier to decompress, the approximate depth needs to be estimated at the four implied locations known to the decompressor.

Due to clustering and clear sampling, some of the grid cells in the data reduction step can end without any sampling, and therefore we cannot generate their representation points r ^ij(k) . To remedy this, we use neighboring grid cells to estimate new representation points. For the sake of simplicity, we only fill in the missing data of the xy neighbors, and not in t. Therefore, we only need to consider the case of 2×2 parts and perform it twice in time dependent mode.

If only one grid cell is a missing sample, we generate a plane from the other three points and estimate it at the center of the empty grid cell.

If there are only two representation points, for example, r ⁰⁰ and r ⁰¹ , and two empty grid cells, we generate a new point, r ¹⁰ as shown below:

The first two constituent elements of r ^{10 are} generated by rotating the difference vector in x and y, e, 90 degrees and increasing it to x and y of r ⁰⁰ . Other components are simply copied from r ⁰⁰ . This squeezes a plane from the vector from r ⁰⁰ to r ⁰¹ . When this third representation point has been generated, we proceed as if one representation point was missing. Finally, if only one representation point exists, it means that the point is generated in the middle of each empty grid cell. Their depth values are set to the depth values of the existing points.

In the final step, we calculate the corrections to encode how a particular sample can be regenerated from the prediction function. We need to store two values for each sample. The first is a layer indicator that joins a sample with a layer. Usually, we use between one layer and four layers, so we need up to two bits to store this indicator. If a block of pixels can be compressed using a single layer, then we do not need to store these metrics.

The second sample value to be stored is the correction term, δ _i . These are found by cycling through all the samples in the layer and calculating the difference between the predicted value, d(x, y, t), and the actual depth of the sample. During this phase, we track the number of bits needed to store the corrections and also calculate the a-constant used in our prediction function. The a-constant is set so we only get unsigned corrections (ie, all samples are placed on top of the prediction function).

For the k correction bit of each correction term, we retain the value 2 ^k -1 as a clear value, and therefore only corrections up to (and including) 2 ^k -2 can be used. However, in one embodiment, we have the benefit of being able to signal in a very inexpensive manner whether a particular sample is still being erased. Otherwise, this is usually done using one of the layer metrics.

FIG. 7 shows an embodiment of system 700. In an embodiment, system 700 can be a media system, although system 700 is not limited by the text. For example, system 700 can be included in a personal computer (PC), a laptop, an ultra-portable computer, a tablet, a touchpad, a portable computer, a handheld computer, a palmtop computer, a personal digital assistant (PDA), and a mobile device. Telephone, combined mobile phone/PDA, TV, smart device (for example, smart phone, smart tablet or smart TV), mobile internet device (MID), communication contact device, data communication device, etc.

In an embodiment, system 700 includes a platform 702 coupled to display 720. Platform 702 can receive content from a content device (eg, content service device 730 or content delivery device 740 or other similar content source). A navigation controller 750 that includes one or more navigation features can be used to interact with, for example, platform 702 and/or display 720. Each of these components will be explained in more detail below.

In an embodiment, platform 702 can include any combination of the following components, such as chipset 705, processor 710, memory 712, storage 714, graphics subsystem 715, software application 716, global positioning system (GPS) 721, camera 723 and/or radio 718. Wafer set 705 can provide intercommunication between processor 710, memory 712, storage 714, graphics subsystem 715, software application 716, and/or radio 718. For example, the chipset 705 can include a storage adapter (not shown) that can provide communication with the storage 714.

Additionally, platform 702 can include an operating system 770. The interface to processor 772 can interface with the operating system and processor 710.

Firmware 790 can be provided to implement functions, such as a startup sequence. From flat An update module that drives firmware update outside of station 702 can be provided. For example, the update module can include an instruction code to determine the decision to attempt to update the authorization and identify the most recent update of firmware 790 to facilitate when an update is needed.

In some embodiments, platform 702 can be powered using an external power supply. In some cases, platform 702 can also include an internal battery 780 that acts as a power source in embodiments that are not suitable for external power supply or in embodiments that allow any battery to supply power or externally supply power.

The order shown in Figures 5 and 6 can be implemented by software and firmware embodiments contained within the memory 714 of some of the examples mentioned or in memory within the processor 710 or graphics subsystem 715. In an embodiment, graphics subsystem 715 can include a graphics processing unit and processor 710 can be a central processing unit.

Processor 710 can be implemented as a Complex Instruction Set Computer (CISC) or Reduced Instruction Set Computer (RISC) processor, an x86 instruction set compatible processor, a multi-core or any other microprocessor or central processing unit (CPU). In an embodiment, processor 710 can include a dual core processor, a dual core mobile processor, and others.

The memory 712 can be implemented as an electrical memory device, such as, but not limited to, a random access memory (RAM), a dynamic random access memory (DRAM), or a static random access memory (SRAM). .

The storage 714 can be implemented as a non-electrical storage device, such as, but not limited to, a magnetic disk drive, a disk drive, a cassette drive, an internal storage device, an attached storage device, a flash memory, and a battery backup synchronization dynamic. Random access memory (synchronous DRAM) and/or network accessible storage devices. In an embodiment, the storage 714 can include a technique to increase the storage performance of the enhanced protection for valuable digital media, for example, when a plurality of hard disk drives are included.

Graphics subsystem 715 can perform image processing for display, such as display of still or video. Graphics subsystem 715 can be, for example, a graphics processing unit (GPU) or a visual processing unit (VPU). An analog or digital interface can be used to communicatively couple graphics subsystem 715 and display 720. For example, the interface can be any high definition multimedia interface, DisplayPort, wireless HDMI, and/or wireless HD compliance technology. Graphics subsystem 715 can be integrated into processor 710 or chipset 705. Graphics subsystem 715 can be a standalone card communicatively coupled to chipset 705.

The graphics and/or video processing techniques described herein can be implemented in a variety of hardware configurations. For example, graphics and/or video functions can be integrated into the chipset. Additionally, discrete graphics and/or video processors can be used. In another embodiment, graphics and/or video functions may be implemented using a general purpose processor including a multi-core processor. In further embodiments, the functions can be implemented in consumer electronic devices.

Radio 718 may include one or more radios that can transmit and receive signals using a variety of suitable wireless communication technologies. Such techniques may include communication across one or more wireless networks. Examples of wireless networks include (but are not limited to) wireless local area networks (WLANs), wireless personal area networks (WPANs), wireless metropolitan area networks (WMANs), mobile telephone networks, and satellite networks. . In the communication across these networks, the radio 718 can Operates according to one or more applicable standards of any version.

In an embodiment, display 720 can include any television type monitor or display. Display 720 can include, for example, a computer display screen, a touch screen display, a video monitor, a television similar device, and/or a television. Display 720 can be digital and/or analog. In an embodiment, display 720 can be a holographic camera. At the same time, display 720 can also be a transparent surface that can receive video projections. Such projections can convey various formed information, images, and/or objects. For example, such projections can be visual overlays for mobile augmented reality (MAR) applications. Platform 702 can display user interface 722 on display 720 under the control of one or more software applications 716.

In an embodiment, the content services device 730 can be hosted by any domestic, international, and/or independent service and, for example, the platform 702 can be accessed via the Internet. Content services device 730 can be coupled to platform 702 and/or display 720. Platform 702 and/or content services device 730 can be coupled to network 760 to communicate (e.g., transmit and/or receive) media information via network 760. Content delivery device 740 can also be coupled to platform 702 and/or display 720.

In an embodiment, the content service device 730 can include a cable television box, a personal computer, a network, a telephone, an internet-enabled device, or a component that can transmit digital information and/or content, and can be via the network 760 or directly Any other similar device that communicates content between the content provider and platform 702 and/or display 720 in one or two directions. It should be appreciated that content can be communicated to any of the components in system 700 and content providers via network 760 unidirectionally and/or bidirectionally. Content examples can include any media information, such as video, music, medical, and gaming information.

The content service device 730 receives, for example, cable television program content including media information, digital information, and/or other content. Examples of content providers can include any cable or satellite television or radio or internet content provider. The examples provided are not intended to limit the embodiments of the invention.

In an embodiment, platform 702 can receive control signals from navigation controller 750 having one or more navigation features. The navigation features of controller 750 can be used, for example, to interact with user interface 722. In an embodiment, the navigation controller 750 can be a pointing device that can be a computer hardware component (specifically, a human interface device) that allows a user to enter spatial (eg, continuous and multi-dimensional) material into the computer. Many systems, such as graphical user interfaces (GUIs), and televisions and monitors allow users to use physical gestures to control and provide data to a computer or television.

Movement of the navigation features of controller 750 can be echoed on the display (e.g., display 720) by movement of indicators, cursors, focus rings, or other visual indicators displayed on the display. For example, under the control of the software application 716, navigation features placed on the navigation controller 750 can be mapped, for example, to virtual navigation features displayed on the user interface 722. In an embodiment, controller 750 may not be a separate component, but may be integrated into platform 702 and/or display 720. However, the embodiments are not limited to the elements shown or described herein or herein.

In an embodiment, the driver (not shown) may include a technique, for example, when priming, similar to a television, the user can immediately turn the platform 702 on and off with a touch button after starting the power-on. Program logic can allow platform 702 to flood content to media converters or other content when the platform is "disconnected" Service device 730 or content delivery device 740. In addition, the chipset 705 can include hardware and/or software support, for example, for 5.1 surround sound audio and/or high-fidelity 7.1 surround sound audio. The drive can include a graphics driver for integrating the graphics platform. In an embodiment, the graphics driver can include a Peripheral Component Interconnect (PCI) advanced graphics display card.

In various embodiments, any one or more of the components shown in system 700 can be integrated. For example, platform 702 and content service device 730 can be integrated, or platform 702 and content delivery device 740 can be integrated, or for example, platform 702, content service device 730, and content delivery device 740 can be integrated. In various embodiments, platform 702 and display 720 can be integrated units. For example, display 720 and content service device 730 can be integrated, or display 720 and content delivery device 740 can be integrated. These examples are not intended to limit the invention.

In various embodiments, system 700 can be implemented as a wireless system, a wired system, or a combination of both. When implemented as a wireless system, system 700 can include components and interfaces suitable for communicating over a wireless shared medium, such as one or more antennas, transmitters, receivers, transceivers, amplifiers, filters, control logic And others. Examples of wireless shared media may include portions of the wireless spectrum, such as radio frequencies and others. When implemented as a wired system, system 700 can include components and interfaces suitable for communicating over a wired communication medium, such as input/output (I/O) converters, connected I/O converters, and corresponding wired communications. Physical connectors for media, network interface cards (NICs), disk controllers, video controllers, audio controllers, and others. Wired communication media examples can include metal wires, cable wires, metal wires, and printed Brush circuit board (PCB), backplane, switching fiber, semiconductor materials, twisted pair, coaxial cable, fiber, and more.

Platform 702 can establish a logical or physical channel of one or more communication messages. Information can include media information and control information. The media information can be any material associated with the content representing the user. Examples of content may include, for example, information from voice conversations, video conferencing, live video, email ("email") messages, voicemail messages, alphanumeric symbols, graphics, images, video, text, and the like. The information from the voice session can be, for example, voice information, silent periods, background noise, comfort noise, tones, and the like. Control information can be associated with any material that represents commands, instructions, or control words used to automate the system. For example, control information can be used to direct media information via the system, or to instruct the node to process media information in a predetermined manner. However, the embodiments are not limited to the elements shown or described in FIG. 8 or herein.

As described above, system 700 can be implemented with varying physical styles or pattern factors. FIG. 7 shows an embodiment of a miniature factor device 800 in which system 700 can be implemented. In an embodiment, for example, device 800 can be implemented as a mobile computer device with wireless capabilities. A mobile computer device can be associated with, for example, any device having a processing system and a mobile power source or supply (eg, one or more batteries).

As mentioned above, examples of mobile computer devices may include personal computers (PCs), laptops, laptops, ultra-thin portable computers, tablets, touch keyboards, portable computers, handheld computers, palmtop computers, personal digital assistants ( PDA), mobile phone, combination mobile phone/PDA, TV, smart device Equipment (for example, smart phones, smart tablets or smart TVs), mobile internet devices (MIDs), communication devices, data communication devices, and more.

Examples of mobile computer devices may also include computers that are configured for personnel to carry, such as wrist computers, finger computers, ring computers, eyeglass computers, caliper computers, armband computers, shoe computers, Clothing-type computers and other wearable computers. In an embodiment, for example, a mobile computer device can be implemented as a smart phone capable of executing a computer application, as well as voice communication and/or data communication. While some embodiments may be illustrated by way of example with a mobile computer device that is implemented as a smart phone, it should be appreciated that other embodiments may be implemented using other wireless mobile computer devices. The examples are not limited by the text.

As shown in FIG. 8, device 800 can include a housing 802, a display 804, an input/output (I/O) device 806, and an antenna 808. Device 800 can also include navigation features 812. Display 804 can include any suitable display unit for displaying information suitable for mobile computer devices. I/O device 806 can include any suitable I/O device for accessing information to the mobile computer device. Examples for the I/O device 806 can include an alphanumeric keypad, a digital keypad, a touch keyboard, input keys, buttons, switches, curved rocker switches, microphones, amplifiers, voice recognition devices, and software. Information can also be entered into device 800 by means of a microphone. This information can be digitized using a voice recognition device. Embodiments are not limited by this description.

Various embodiments may be implemented using hardware components, software components, or a combination of both. Examples of hardware components can include processors, microprocessors, circuits, circuit components (eg, transistors, resistors, capacitors, inductors, etc.), Integrated circuits, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), digital signal processors (DSPs), field programmable gate arrays (FPGAs), logic gates, scratchpads, semiconductor devices, wafers, Microchips, wafer sets, and the like. Software examples can include software components, programs, software applications, computer programs, applications, system programs, machine programs, computing system software, mediation software, firmware, software modules, program segments, sub-segments, functions, methods, programs. , software interface, application programming interface (API), instruction set, calculation code, computer code, code segment, computer code segment, block, value, symbol, or any combination thereof. Determining whether an embodiment is implemented using hardware components and/or software components can vary depending on any number of factors, such as required calculation rate, power level, heat capacity limit, processing cycle budget, input data Rate, output data rate, memory resources, data bus rate, and other design or performance limitations.

One or more aspects of at least one embodiment may be implemented by a representation instruction stored on a machine readable medium representing various logic within the processor, the instructions being caused by the machine being read Logic is formed to perform the techniques described herein. Such representations, known as "IP cores", can be stored on physical machine readable media and supplied to various customers or manufacturers for loading into manufacturing machines that actually constitute logic or processors.

Various embodiments may be implemented using hardware components, software components, or a combination of both. Examples of hardware components can include processors, microprocessors, circuits, circuit components (eg, transistors, resistors, capacitors, inductors, etc.), integrated circuits, application-specific integrated circuits (ASICs), programmable logic device (PLD), digital signal processor (DSP), field programmable gate array (FPGA), logic gate, scratchpad, semiconductor device, wafer, microchip, chipset, and the like. Software examples can include software components, programs, software applications, computer programs, applications, system programs, machine programs, computing system software, mediation software, firmware, software modules, program segments, sub-programs, functions, methods, programs. , software interface, application programming interface (API), instruction set, calculation code, computer code, code segment, computer code segment, block, value, symbol, or any combination thereof. Determining whether an embodiment is implemented using hardware components and/or software components can vary depending on any number of factors, such as required calculation rate, power level, heat capacity limit, processing cycle budget, input data Rate, output data rate, memory resources, data bus rate, and other design or performance limitations.

One or more aspects of at least one embodiment may be implemented by a representation instruction stored on a machine readable medium representing various logic within the processor, the instructions being caused by the machine being read Logic is formed to perform the techniques described herein. Such representations, known as "IP cores", can be stored on physical machine readable media and supplied to various customers or manufacturers for loading into manufacturing machines that actually constitute logic or processors.

The graphics processing techniques described herein can be implemented in a variety of hardware configurations. For example, graphics functionality can be integrated into a chip set. Alternatively, a discrete graphics processor can be used. As another example, graphics functionality may be implemented using a general purpose processor that includes a multi-core processor.

10‧‧‧Minimum depth

12‧‧‧Maximum depth

20‧‧‧Cluster flow chart

22-26‧‧‧Cluster Flowchart Steps

30‧‧‧Predictive function flow chart

32-40‧‧‧Predictive function flow chart steps

700‧‧‧ system

702‧‧‧ platform

705‧‧‧ Chipset

710‧‧‧ processor

712‧‧‧ memory

714‧‧‧Storage

715‧‧‧Graphics Subsystem

716‧‧‧Software applications

718‧‧‧ radio

720‧‧‧ display

721‧‧‧Global Positioning System (GPS)

722‧‧‧User interface

723‧‧‧ camera

730‧‧‧Content Service Equipment

740‧‧‧Content delivery equipment

750‧‧‧Navigation controller

760‧‧‧Network

770‧‧‧ operating system

772‧‧‧ to processor interface

780‧‧‧Battery

790‧‧‧ Firmware

792‧‧‧ Firmware update module

800‧‧‧ Equipment

802‧‧‧ Cover

804‧‧‧ display

806‧‧‧Input/Output (I/O) devices

808‧‧‧Antenna

810‧‧‧Display unit

812‧‧‧Navigation features

1 is a diagram showing three steps of a depth buffer compression algorithm according to an embodiment; FIG. 2 is a schematic diagram of a clustering technique according to an embodiment; and FIG. 3 is a schematic diagram of mode 1 according to an embodiment. , wherein one pixel block and four points in the pixel block are shown on the left and the A, B, C, and D depth values are displayed in the middle of the right sub-pixel block; FIG. 4 is three according to an embodiment. The predictive function chart composes and shows how they have similar data reduction steps, the left graph shows a set of irregular samples with grayscale samples indicating depth, and the middle graph shows the bounding box of the sample so that the box is half-paired in the xy dimension Dividing and in each generated sub-region, a representative depth and position are generated from an average of two depth values (minimum and maximum in the sub-pixel block), and in the right graph, a data prediction patch is displayed 5 is a flow chart for clustering according to an embodiment of the present invention; FIG. 6 is a flowchart for a prediction function according to an embodiment; and FIG. 7 is a hardware for an embodiment of the present invention; Drawing And 8 is a front elevational view of an embodiment of the present invention.

DEPTH‧‧ depth

Claims (28)

A method comprising the steps of: generating a patch for a block of pixels (pixel block); estimating a position of a predictor; and encoding a difference between the predictor position and the sample depth. The method of claim 1, wherein the method comprises generating a time dependent plane suitable for moving the blurred pixel block. The method of claim 1, wherein the method comprises generating a linear patch suitable for moving the blurred pixel block. The method of claim 2, wherein the method includes using a sampling position, a depth value, and a sampling time in the screen space to develop the plane/patch. The method of claim 1, wherein the method comprises generating a bilinear patch suitable for non-blurring pixel blocks. The method of claim 5, comprising the use of a sampling position and a depth value in the screen space to develop the patch. The method of claim 1, comprising compressing the depth values and storing the compressed representation in a memory. The method of claim 1, comprising dividing a depth interval into bins, marking the zones with at least one depth value, and finding a maximum spacing and depth between the seams. Clustered by value. The method of claim 1, wherein the method comprises: by finding a bounding box for all samples in a current layer, dividing the frame into a uniform A patch is developed and a patch is developed for each cell to find two samples with minimum and maximum depth values. A method of claim 9, comprising calculating a midpoint between the set minimum and maximum depth values. The method of claim 10, wherein the method comprises deriving a bilinear patch from the four midpoint values. At least one machine readable medium comprising a plurality of instructions and responsive to execution of the plurality of instructions on a computer device, causing the computer device to perform the method of any of claims 1-11. An apparatus comprising: a processor that develops a patch for a scene, estimates a location of the patch, and encodes a difference between the patch and a sample depth; and a coupling to the processor Memory. A device as claimed in claim 13, wherein the processor determines whether the scene is ambiguous or non-blurred. A device as claimed in claim 14, wherein the processor is for developing a bilinear patch for a non-blurred scene. The device of claim 15, wherein the processor uses the sampling position and the depth value in the screen space to develop the patch. The apparatus of claim 13 wherein the processor is operative to develop a trilinear patch for one of the blurred scenes. The apparatus of claim 17, wherein the processor uses the sampling position, depth value, and time in the screen space to develop the patch. A device as claimed in claim 13 wherein the processor uses only one location of the sample and screen space and the depth of the sample to compress the depth value. A device as claimed in claim 13, wherein the processor compresses the depth value without using information from a rasterizer. The device of claim 13, wherein the processor compresses the depth value and stores the value in the memory, wherein the memory is not combined with the processor. The device of claim 13, wherein the processor marks the zones by dividing a depth interval into zones, and marks the zones with at least one depth value, and finds the maximum spacing and depth values between the zones. Perform a cluster. The device of claim 13, wherein the processor becomes a uniform cell grid by finding a bounding box for all samples in a current layer, and finding the smallest cell grid for each cell A patch is developed with two samples of the maximum depth value. The apparatus of claim 13, wherein the processor calculates a midpoint between the set minimum and maximum depth values. The apparatus of claim 13, wherein the processor derives a bilinear patch from the four midpoint values. An apparatus as claimed in claim 13 which comprises an operating system. A device as claimed in claim 13 which comprises a battery. A device as claimed in claim 13 which comprises a firmware and a module for updating the firmware.