TW201338049A - Trench junction electric-field shielding power metal oxide semiconductor field effect transistor structure and manufacturing process method - Google Patents

Abstract

A trench junction electric-field shielding power metal oxide semiconductor field effect transistor structure and manufacturing process method are disclosed. Junction with an electric-field shield is provided for the structure of each trench of singlet unit cell so that the breakdown voltage can be increased and the leakage current can be reduced, wherein the manufacturing process method is to etch the gate trench and the source trench on the substrate and the epitaxial layer. Then an electric-field shielding junction is formed by implanting the different dopant. Oxide layer is filled into the gate trench and the source trench by totally or partially filled way. Pwell junction and Source junction are formed, and etching of the silicon and polycrystalline-silicon is carried out in Source contact while P-type heavy dope is implanted into the source contact area. The purposes of reducing the leakage current and enhancing the level of tolerance for the avalanche energy can be achieved by the structure and manufacturing process of this invention.

Description

Drainage well area electric field screen protection power gold oxygen half field effect transistor structure and process method

The invention relates to a crystal structure and a manufacturing method, in particular to a well-formed electric field screen protection power metal oxide half field effect transistor structure and a process method for forming an electric field screen well protection area in a power metal oxide half field effect electric crystal structure .

In the prior art, power MOSFETs have been widely used in many components and products, such as discrete components, optoelectronic components, power control components, DC-to-DC converters, and motor drives. Wait. However, these applications require special breakdown voltages, low on-resistance, high switching speeds, and a wide range of safe operating areas. In addition, in most applications, the power MOS field-effect transistor system needs to be able to be turned on and off when an inductive load occurs, and when the power MOS half-field transistor is switched from the on state to the off state. In the state, the inductive load induces an electromagnetic force between the source terminal and the 汲 terminal, and accelerates the increase rate of the avalanche breakdown current, so that when the parasitic bipolar transistor is turned on again, the semiconductor component is subjected to To the damage.

The current power transistor products are constantly pursuing low Rds-on, so the low on-resistance is achieved by continuously shortening the Pwell junction depth and the channel length.

However, while shortening the depth of the substrate and the length of the channel, there is a problem that the drain leakage current increases or the breakdown voltage of the transistor decreases.

Therefore, it is necessary to provide a new component structure in addition to the purpose of achieving a low on-resistance of a shallow junction, and simultaneously solving the problems of high collapse voltage and avalanche energy.

One of the objectives of the present invention is to provide a gold-oxygen half-field effect transistor structure for a well-drained field electric field screen protection power, which has a first screen well area and a second screen well area for increasing the breakdown voltage tolerance and reducing Loss of leakage current.

Another object of the present invention is to provide the above-described transistor structure, and form an insulating layer on a sidewall and a bottom of at least one of the gate trench and the source trench, and selectively fill the polysilicon layer on the insulating layer A gate electrode and a source electrode are formed.

Another object of the present invention is to provide the above-described transistor structure by adjusting the depth of a trench of a source trench or a gate trench for forming a shallow trench or a deep trench for embedding a source electrode, a gate electrode or a screen. Protection electrode.

It is still another object of the present invention to provide the above-described crystal structure having a plurality of polycrystalline germanium electrodes (e.g., gate electrodes and screen guard electrodes) separated from each other for the purpose of achieving high withstand voltage and reducing electric field.

Another object of the present invention is to provide the above-mentioned transistor structure, which is to provide a multi-step trench structure, for example, a second-order trench trench system further forms a multi-step wide and narrow structure trench having a wider width of the upper-order trench structure and a narrower structure of the lower-order trench structure. structure.

Another object of the present invention is to provide a method for manufacturing a gold-oxygen half-field effect transistor for a well-drained electric field screen, which transmits a first ion to an epitaxial layer to form a first screen well area, and a transmission value. The second ion is adjacent to the source trench of the epitaxial layer to form a second screen well region for enabling the power metal oxide half field effect transistor to have high breakdown voltage tolerance and low leakage current.

In order to achieve the above object or other objects, the present invention provides a trench-type well region electric field screen protection power metal oxide half field effect transistor structure, which comprises a substrate, an epitaxial layer, a first screen well protection area, and a second screen well protection area. , substrate junction, dielectric layer. The epitaxial layer is disposed on one side of the substrate, and the epitaxial layer has a gate trench and a source trench, and one of the sidewall and the bottom of the trench structure is filled with an insulating layer; the first screen protector a well area is implanted in the epitaxial layer, and the first screen well protection area covers the gate ditches and the source ditches; the second screen well protection area is laid in the epitaxial layer, And the second screen well protection area is adjacent to, partially covering or covering the source trench; the base connection surface is disposed on one side of the second screen well protection area, and the base connection surface is adjacent to the source a heavily doped region of the pole trench; the source junction is disposed on one side of the substrate junction, and the source junction has a source contact region corresponding to the source trench; the dielectric layer is tied to One side of the source junction is disposed, and the dielectric layer is disposed corresponding to the gate trench.

In order to achieve the above object or other objects, the present invention provides a method for manufacturing a gated well region electric field screen power MOS half field effect transistor structure, the method steps comprising: (a) providing a substrate, and stacking the substrate on the substrate a crystalline layer; (b) forming an oxide layer on one side of the epitaxial layer and passing through the patterned first photoresist layer, etching the oxide layer and at least a portion of the epitaxial layer to form a gate and a plurality of source trench structures, wherein the trenches respectively form at least one of a shallow trench or a deep trench; (c) fabricating the first ion to the epitaxial layer to form a first screen well region (shielding) (d) fabricating a second ion adjacent to the source trench of the epitaxial layer to form a second screen well region; (e) filling the insulating layer to the surface of the epitaxial layer and the trench structures a sidewall or a bottom; (f) depositing a polycrystalline germanium layer to at least one of the trench structures; (g) forming a substrate junction and a source junction on one side of the second screen well region; (h) depositing a dielectric layer and a patterned second photoresist layer for forming a source contact region; (i) doping And through the heavy ion source contact region to form a heavily doped region between these trench structures.

Compared with the prior art, the electric field screen protection power of the trench type well area of the present invention is achieved by shortening the depth of the base joint to achieve a shallow junction, in addition to being used to achieve a low junction. In addition to the on-resistance, high breakdown voltage and avalanche energy can also be achieved.

In order to fully understand the objects, features and advantages of the present invention, the present invention will be described in detail by the following specific embodiments and the accompanying drawings.

Referring to FIG. 1a, a schematic diagram of a structure of a gold-oxygen half-field effect transistor of an electric field screen protection power in a trench type well region according to an embodiment of the present invention. In the present embodiment, the electric field screen protection power of the trench type well region is composed of a plurality of unit cells 10, and the structure of any one of the unit cells 10 includes a substrate. 12. The epitaxial layer 14, the first screen well area 16, the second screen well area 18, the base junction 20 and the source junction 22. The material of the substrate 12 can be, for example, an N ⁺ -type red phosphorous substrate. The epitaxial layer 14 is disposed on one side of the substrate 12, and the epitaxial layer 14 has a gate trench 24 and a source trench 26, and sidewalls and/or bottoms of the gate trench 24 and the source trench 26 structure The insulating layer (SiO2) 32 is separately provided. For example, the material of the epitaxial layer 14 may be an N-type epitaxy layer.

The first screen shield junction 16 is disposed in the epitaxial layer 14 , and the first screen well region 16 covers the gate trench 24 and the source trench 26 . Here, the first screen well protection area 16 is illustrated by taking an N-type screen well protection area as an example.

The second screen well area 18 is disposed in the epitaxial layer 14 , and the second screen well area 18 covers the source trench 30 . Here, the second screen well protection area 18 is illustrated by taking a P-type screen well protection area as an example. In other embodiments, the second screen well area 18 may also partially or completely cover the source trench 26.

For example, the second screen well area 18 can be formed by multiple and deep multiples to form a multi-layered P-type screen well area 18', as shown in FIG. And the second screen well area 18 can be formed in the P-type screen well area 18" of the first screen well area 16 by local implantation and/or non-drive-in. a structure, as shown in FIG. 4; and the second screen well area 18 is formed by local implantation and not driven to form a P in the first screen well region 16 and the epitaxial layer 14 The structure of the type screen well area 18''' is as shown in Fig. 5.

The shallow body junction 20 is disposed on one side of the second screen well region 18, and the substrate junction 20 has a heavily doped region 30 adjacent to the source trench 26. Herein, the base interface 20 is exemplified by a P-substrate junction 20; and the heavily doped region 30 is exemplified by a P ⁺ heavily doped region.

The source source junction 22 is disposed on one side of the substrate junction 20, and the source junction 22 has a source contact region 32 corresponding to the source trench 26. Herein, the source junction 26 is described by taking an N ⁺ source junction as an example. The source doping region 32 is formed by at least a portion of the heavily doped region 30 and the source trench 22 and the source trench 26 .

The dielectric layer 34 is disposed on one side of the source contact surface 22, and the dielectric layer 34 is disposed corresponding to the gate trench 24. For example, the material of the dielectric layer 34 may be borophosphonate. In another embodiment, the dielectric layer 34 is planarized by etching or polishing to form a structure as shown in FIG.

In one embodiment, the metal layer can be further disposed on one side of the dielectric layer 34 such that the metal layer contacts the source contact region 32 to form a metal wire connection. For example, the material of the metal layer can be It is an aluminum metal; and a conductive metal layer is further plated on the other side of the substrate 12 as the crucible pole 40.

Furthermore, a polysilicon layer is selectively filled in the sidewall, the bottom or the insulating layer 28 of at least one of the gate trench 24 and the source trench 36 for separately forming the gate electrode 36 and the source electrode 38, For example, in Figure 1b, the gate electrode 36 of the gate trench 24 has a larger proportion of space than the gate electrode 36 of the gate trench 24 in Figure 1a. Furthermore, in FIG. 1c, the source trench 26 is filled only with the insulating layer 32, and may not be filled with any of the source electrodes 38.

Therefore, it can be clearly understood from the above embodiments that the gate trenches 24 and the source trenches 26 can be properly filled and dispensed. In addition, if the depth of the substrate junction 20 is shallower than the depth of the heavily doped region 30, it can be used to avoid leakage.

Referring to Figures 6a to 6i, a method for manufacturing a gold-oxygen half-field effect transistor structure of a trench-type well region electric field screen in the embodiment of the present invention. In this embodiment, the process steps first refer to FIGS. 6a-6c, provide a substrate 12, and stack the epitaxial layer 14 on the substrate 12, and form an oxide layer 42 on one side of the epitaxial layer 14 for As a mask layer, and through the patterned photoresist layer, the oxide layer 42 and at least a portion of the epitaxial layer 14 are etched to form a gate having a high aspect ratio. a plurality of trench structures of the trenches 24 and the source trenches 26, and after the trench structures are formed, the oxide layer 42 is subsequently removed, wherein the trenches 24, 26 can respectively form shallow trenches or deep trenches according to their needs. At least one of them; then referring to Figure 6d, the first ion 44 is applied to the epitaxial layer 14 to form a first screen well zone 16, and the first screen well zone 16 is comprehensive ( Blanket implantation) is formed by heat treatment of the sacrificial oxide layer (SAC oxide). Herein, the material of the substrate 12 is exemplified by an N ⁺ -type red phosphor substrate; the material of the oxide layer 42 is exemplified by cerium oxide; the material of the epitaxial layer 14 is N ^- type epitaxial The layer is taken as an example; the first ion 55 is described by taking an N-type material as an example.

Referring again to FIGS. 6e-6f, the second value 46 is adjacent to the source trench 26 of the epitaxial layer 14 to form a second screen well region 18, and the second screen well region 18 is The patterned photoresist layer 48 is formed with a junction implant, and after the second shield well region 18 is created, the photoresist layer 48 is removed. Here, the second ion 46 is described by taking a P-type material as an example.

Referring to FIG. 6g, the insulating layer 28 is filled on the surface of the epitaxial layer 14 and the sidewalls and/or the bottom of the trench structures 24, 26, and after the insulating layer 28 is filled, the polysilicon layer 48 is deposited. To the remaining space of at least one of the trench structures 24, 26. In another embodiment, depositing the polysilicon layer 48 may further comprise depositing all, a portion of the polysilicon layer 48 on at least one of the trench structures 24, 26, and then implanting it in a comprehensive manner. The base junction 20 and the source junction 22 are formed on one side of the second screen well region 16 in a manner of driving in. Wherein, the above method of directly utilizing comprehensive implantation can be used to reduce the mask lithography process and cost, but a mask can also be formed by using a mask. Here, the base contact surface 20 is described by taking a P ⁻ type material as an example; and the source contact surface 22 is described by taking an N ⁺ material as an example.

Referring next to FIG. 6h, a process of depositing a dielectric layer 34 is performed through a patterned second photoresist layer for forming a source contact region 32 and forming the source contact. After region 32, a heavy ion 50 is doped and passed through the source contact region 32 for forming a heavily doped region 30 between the trench structures 24, 26, which can be used to reduce leakage current. And enhance the tolerance of avalanche energy. In one embodiment, doping the heavy ions 50 causes the heavily doped region 304 to have a depth greater than the depth of the source junction. In another embodiment, after depositing the dielectric layer 34, the method further includes planarizing the dielectric layer 34 on a side of the corresponding substrate junction 20 and the source junction 22.

In addition, when the epitaxial layer 14 is etched, the height of the polysilicon 48 is etched due to the etching selectivity ratio, and the height difference may affect the implantation of the heavy ions 50, and the formation is very Good distribution control and improvement of avalanche energy, for example, the dielectric layer 34 may be borophosphonite glass; and the heavy ion 50 series may be P ⁺ type material.

It should be noted that the substrate in the above may be an N ⁺ type substrate, the epitaxial layer may be an N type epitaxial layer, and the first screen well protection zone may be an N type screen well protection area, and the The second screen well protection zone may be one of a P-type screen well protection zone, a ν-type screen well protection zone, or a π-type screen well protection zone.

Referring to FIGS. 7a to 7d together, FIG. 7 is a schematic diagram showing the structure of a gold-oxygen half-field effect transistor in a trench-type well region according to another embodiment of the present invention. In the figures 7a to 7d, the power MOS field-effect transistor structure 10' is divided by the substrate 12, the epitaxial layer 14, the first screen well area 16, the second screen well area 18, The substrate junction 20, the source junction 22, the gate trench 24, the source trench 26, the insulating layer 28, the gate electrode 36 and the source electrode 38, etc., may further comprise a screen guard electrode 52 is embedded in the insulating layer 28 and is separately disposed at the bottom of at least one of the gate electrode 36 and the source electrode 38, and the screen guard electrode 52 is disposed adjacent to the gate trench 24 and The bottom of the source trench 26 or the screen guard electrode 52 is disposed at the bottom of the gate electrode 36 and the source electrode 38. Furthermore, the gate electrode 36 of the gate trench 24 and the screen guard electrode 52 pass through the insulating layer 28 to form the gate terminal 54. Among them, the 7a to 7d drawings are illustrative of the embodiment.

Referring to Figures 8a to 8d together, a schematic diagram of a structure of a gold-oxygen half-field effect transistor for a well-drilled well area electric field screen protection power according to another embodiment of the present invention is shown. In the figures 8a to 8d, the power MOS field-effect transistor structure 10" is divided by the substrate 12, the epitaxial layer 14, the first screen well region 16, the second screen well region 18, The substrate junction 20, the source junction 22, the gate trench 24, the source trench 26, the insulating layer 28, the gate electrode 36 and the source electrode 38, etc., wherein the gate trench 24 The system further includes a first-order gate trench 24' and a second-order gate trench 24", and the source trench 26 further includes a first-order source trench 26' and a second-order source trench 26".

The gate electrode 36 is embedded in the first step gate trench 24' or the first step gate trench 24' and the second step gate trench 24", and the source electrode 38 is embedded in the system. Embedded in the first-order source trench 26' or the first-order source trench 26' and the second-order source trench 26". In addition, in this embodiment, the width of at least one of the second-order gate trench 24" and the second-order source trench 26" is narrower than or equal to the first-order gate trench 24', respectively. The width of at least one of the first-order source trenches 26".

The invention has been described above in terms of the preferred embodiments, and it should be understood by those skilled in the art that the present invention is not intended to limit the scope of the invention. It should be noted that variations and permutations equivalent to those of the embodiments are intended to be included within the scope of the present invention. Therefore, the scope of the invention is defined by the scope of the following claims.

10, 10', 10"... gold oxide half field effect crystal structure

12. . . Substrate

14. . . Epitaxial layer

16. . . First screen well area

18, 18', 18", 18'''... second screen well area

20. . . Substrate junction

twenty two. . . Source junction

twenty four. . . Gate ditches

twenty four'. . . First-order gate trench

24"...second-order gate ditches

26. . . Source ditch

26’. . . First-order source trench

26"...second-order source trench

28. . . Insulation

30. . . Heavily doped region

32. . . Source contact area

34. . . Dielectric layer

36. . . Gate electrode

38. . . Source electrode

40. . . Extreme

42. . . Oxide layer

44. . . First ion

46. . . Second ion

48. . . Polycrystalline germanium

50. . . Heavy ion

52. . . Screen guard electrode

54. . . Gate extreme

1a-1c is a schematic view showing the structure of a gold-oxygen half-field effect transistor in a trench-type well region of the present invention;

2 is a schematic view showing the structure of a gold-oxygen half-field effect transistor of an electric field screen protection power in a trench type well region according to another embodiment of the present invention;

Figure 3 is a schematic view showing the structure of a gold-oxygen half-field effect transistor of the electric field screen protection power of the trench type well region according to another embodiment of the present invention;

4 is a schematic view showing the structure of a gold-oxygen half-field effect transistor of an electric field screen protection power in a trench type well region according to another embodiment of the present invention;

Figure 5 is a schematic view showing the structure of a gold-oxygen half-field effect transistor of an electric field screen protection power in a trench type well region according to another embodiment of the present invention;

6a-6i is a schematic view showing the structure of a gold-oxygen half-field effect transistor of the electric field screen protection power of the trench-type well area according to the embodiment of the present invention;

7a-7d is a schematic view showing the structure of a gold-oxygen half-field effect transistor of the electric field screen protection power of the trench type well region according to the embodiment of the present invention;

8a to 8d are schematic diagrams showing the structure of a gold-oxygen half-field effect transistor in a trench-type well region according to still another embodiment of the present invention.

10. . . Gold oxide half field effect transistor structure

12. . . Substrate

14. . . Epitaxial layer

16. . . First screen well area

18. . . Second screen well area

20. . . Substrate junction

twenty two. . . Source junction

twenty four. . . Gate ditches

26. . . Source ditch

28. . . Insulation

30. . . Heavily doped region

32. . . Source contact area

34. . . Dielectric layer

36. . . Gate electrode

38. . . Source electrode

40. . . Extreme

Claims (21)

A method for manufacturing an electric field screen protection power metal oxide half field effect transistor structure (MOSFET) of a trench type well region, comprising: (a) providing a substrate, and stacking an epitaxial layer on the substrate; (b) forming an oxide layer thereon One side of the epitaxial layer, and through the patterned first photoresist layer, etching the oxide layer and at least a portion of the epitaxial layer to form a plurality of trenches having a gate and a source a structure, wherein the trenches respectively form at least one of a shallow trench or a deep trench; (c) fabricating a first ion to the epitaxial layer to form a first shielded junction; Having a second ion adjacent to the source trench of the epitaxial layer to form a second screen well region; (e) filling the insulating layer to a surface of the epitaxial layer and sidewalls and bottom portions of the trench structures One of (f) depositing a polycrystalline germanium layer to at least one of the trench structures; (g) forming a substrate junction and a source junction on one side of the second screen well region; (h) depositing a dielectric And a patterned second photoresist layer for forming a source contact region; and (i) doping heavy ions and passing through the source Region to form a trench structure between these heavily doped regions. The process of claim 1, wherein the step (f) further comprises depositing at least a portion of the polysilicon layer on at least one of the trench structures. The process method of claim 2, wherein the step is after the step (f), the polysilicon layer is embedded in the trench structures. The process of claim 1, wherein the step (h) further comprises planarizing the dielectric layer on the side of the substrate junction and the source junction of the corresponding gate. . The process of claim 1, wherein the step (i) further comprises doping the heavy ions such that the depth of the heavily doped region is greater than the depth of the source junction. The process of claim 1, wherein the first screen well zone is formed by a blanket implantation implant and a heat treatment of a sacrificial oxide layer (SAC oxide). The process of claim 1, wherein the second screen well region is formed by having a patterned photoresist layer and a junction implant. A trench-type well region electric field screen protection power metal oxide half field effect transistor (MOSFET) structure, which is composed of a plurality of unit cells, and the structure of any one of the unit cells includes: a substrate; an epitaxial layer is disposed on one side of the substrate, and the epitaxial layer has a gate trench and a source trench, and the gate trench and the sidewall and the bottom of the source trench are filled and insulated a first screen well protection area, the fabric value is in the epitaxial layer, and the first screen well protection area covers the gate ditches and the source ditches; the second screen protection area, the cloth value In the epitaxial layer, the second screen well area is adjacent to, partially covered or completely covered with the source trench; the base junction is disposed on one side of the second screen well area, and the substrate The junction has a heavily doped region adjacent to the source trench; the source junction is disposed on one side of the substrate junction, and the source junction has a source contact region corresponding to the source trench; The dielectric layer is on one side of the source junction, and the dielectric layer is disposed corresponding to the gate trench. The power metal oxide half field effect transistor structure according to claim 8 , wherein the first screen well protection zone is an N-type screen well protection zone and the second screen well protection zone is a P-type screen protection well Area. The power metal oxide half field effect transistor structure according to claim 8 , wherein the second screen well protection zone is formed by multiple and deep implants or partial implants to form Multi-level second screen well protection area. The power oxy-half field effect transistor structure of claim 8, wherein the second screen well protection zone is formed by local implantation and not driven to form in the first screen well protection zone. The power oxy-half field effect transistor structure according to claim 8 , wherein the second screen well protection zone is formed by local implantation and not driven to form the first screen well area and the Lei Crystal layer. The power oxy-half field effect transistor structure according to claim 8 , wherein the substrate junction is a P ^- substrate junction, the source junction is a N ⁺ source junction, and the heavily doped region is a P ⁺ heavily doped region, the substrate N ⁺ -type substrate, the epitaxial layer N-type epitaxial layer, the first screen well protection zone N -type screen well protection zone, and the second screen well protection zone One of the P-type screen well area, the ν-type screen well area, or the π-type screen well area. The power oxy-half field effect transistor structure of claim 8, wherein the insulating layer is filled with a polysilicon layer. The power oxy-half field effect transistor structure of claim 8, wherein the heavily doped region, at least a portion of the source junction and the source trench form the source contact region. The power metal oxide half field effect transistor structure according to claim 8 further includes a gate electrode and a source electrode, wherein the gate electrode is embedded in the gate trench and the source electrode system is embedded in the gate electrode The source ditch. The power metal oxide half field effect transistor structure according to claim 16, further comprising a screen protector electrode embedded in the insulating layer and separately disposed at least one of the gate electrode and the source electrode The screen electrode is disposed adjacent to the gate trench and the bottom of the source trench, or the screen electrode is disposed at the bottom of the gate electrode and the source electrode. The power oxy-half field effect transistor structure according to claim 17, wherein the gate electrode of the gate trench and the screen electrode pass through the insulating layer to form a gate terminal. The power oxy-half field effect transistor structure according to claim 16 , wherein the gate trench system further comprises a first-order gate trench and a second-order gate trench, and the source trench system further comprises First-order source trench and second-order source trench. The power metal oxide half field effect transistor structure according to claim 19, wherein the gate electrode is embedded in the first step gate trench or the first step gate trench and the second step gate The source electrode is embedded in the first-order source trench or the first-order source trench and the second-order source trench. The power oxy-half field effect transistor structure of claim 20, wherein a width of at least one of the second-order gate trench and the second-order source trench is narrower than or equal to the first a width of at least one of the first-order gate trench and the first-order source trench.