TW201330533A - Time de-interleaver method for digital audio broadcasting system - Google Patents
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本發明是有關於一種數位音訊廣播系統的解碼技術,且特別是有關於一種適用於數位音訊廣播系統之時域反交錯處理方法。The present invention relates to a decoding technique for a digital audio broadcasting system, and more particularly to a time domain de-interlacing processing method suitable for a digital audio broadcasting system.
數位音訊廣播(digital audio broadcasting,DAB)相較於傳統廣播,除了有抗干擾、抗雜訊和音質高之外,其頻譜利用率也更有效率。根據ETSI EN 300 401標準,每一個頻道最多可以有64個不同的子頻道,因此廣播業者可以在發送音訊節目的同時,利用其他子頻道傳送圖文資料,終端聽眾在收聽廣播節目時,可同時接收到附加資訊。當數位音訊廣播應用於手持式裝置時,低功率消耗成為一項不可或缺的條件。Compared with traditional broadcasting, digital audio broadcasting (DAB) is more efficient in spectrum utilization than anti-interference, anti-noise and high sound quality. According to the ETSI EN 300 401 standard, each channel can have up to 64 different subchannels. Therefore, the broadcaster can transmit the audio and video programs while using other subchannels to transmit the graphic materials. When the terminal listeners listen to the broadcast programs, they can simultaneously Received additional information. When digital audio broadcasting is applied to handheld devices, low power consumption becomes an indispensable condition.
依照ETSI EN 300 401標準,每一個通道在傳送前需經過時域交錯處理(time interleaver),將原始資料分散於各個共同交錯幀(common interleaved frame,CIF)中,以降低因叢發錯誤(burst error)所造成的影響。在時域交錯處理中以每16位元為基本單位,利用位元反轉(bit reverse)的方式將16位元分別分散在16個不同CIF中。請參見表1,其為摘自ETSI EN 300 401標準的內容,r’做為對每一ir模數16的可能數值的r函數。例如,第0個位元配置在第0個CIF,第1個位元配置在相對第0個CIF的前8個CIF位置(0001→1000),第2個位元配置在相對第0個CIF的前4個CIF位置(0011→1100),…,第14個位元配置在相對第0個CIF的前7個CIF位置(1110→0111),第15個位元配置在相對第0個CIF的前15個CIF位置。According to the ETSI EN 300 401 standard, each channel is subjected to time interleaver before transmission, and the original data is dispersed in common interleaved frames (CIF) to reduce burst errors (burst). The impact of error). In the time domain interleaving process, 16 bits are respectively dispersed in 16 different CIFs by bit reverse. See Table 1, which is taken from the ETSI EN 300 401 standard, and r' as an r function for the possible values for each i r modulus 16. For example, the 0th bit is placed at the 0th CIF, the 1st bit is placed at the first 8 CIF positions (0001→1000) relative to the 0th CIF, and the second bit is placed at the 0th CIF. The first 4 CIF positions (0011→1100),..., the 14th bit is placed in the first 7 CIF positions (1110→0111) relative to the 0th CIF, and the 15th bit is configured in the relative 0th CIF. The top 15 CIF locations.
請參閱上述的表2,其表示時域交錯處理中輸入和輸出之時間關係。從表2可以發現,基於時間延遲這樣的特性,接收端必須等待分散於16個CIF中的資料位元,完整接收後才能將資料重新還原,所以需要將接收到的前16個CIF資料位元先暫時儲存於記憶體中。若要支援最大容量單位(capacity unit,CU),1個CIF最大數為864個CU,並且以4個軟式決策位元(soft decision bits)表示的話,記憶體大小為864(cu)×64(bits/cu)×16(cif)×4(soft decision bit)=442368 byte,約為432 KB,其中1 KB等於1024 byte,因此需要相當大的儲存空間來進行時域反交錯處理(time de-interleaver)。See Table 2 above for the time relationship between input and output in time domain interleaving. From Table 2, it can be found that, based on the characteristics of time delay, the receiving end must wait for the data bits dispersed in the 16 CIFs, and the data can be restored again after complete reception, so the first 16 CIF data bits to be received are needed. Store temporarily in memory. To support the maximum capacity unit (CU), the maximum number of CIFs is 864 CUs, and the memory size is 864 (cu) × 64 (in terms of soft decision bits). Bits/cu) × 16 (cif) × 4 (soft decision bit) = 442368 byte, which is about 432 KB, of which 1 KB is equal to 1024 bytes, so considerable storage space is required for time domain de-interlacing (time de- Interleaver).
雖然時域交錯處理幫助了消除叢發錯誤和時域選擇性衰退(time selective fading)的問題,但卻換來了儲存空間增大的問題,一般設計經常為此而做出妥協,而無法完整支援ETSI EN 300 401標準所規範的864CU。Although time-domain interleaving helps eliminate clumping errors and time selective fading, it is in exchange for increased storage space. Generally, designs often compromise and do not complete. Supports the 864CU as specified in the ETSI EN 300 401 standard.
有鑑於此,本發明提出一種時域反交錯處理方法,藉以解決先前技術所述及的問題。In view of this, the present invention proposes a time domain de-interlacing processing method to solve the problems described in the prior art.
本發明提出一種時域反交錯處理方法,適用在數位音訊廣播系統。所提的方法包括:接收多個共同交錯幀(CIF)資料,其中每一CIF資料不同且每一CIF資料包括多個位元資料;根據這些CIF資料形成多個先進先出資料群組與直接輸出資料群組(注:資料組數目和軟式決策位元數相關),其中每一個先進先出資料群組包括多個位元資料,而此直接輸出資料群組包括單個位元資料;將這些先進先出資料群組儲存至隨機存取記憶體;讀取此隨機存取記憶體中的這些先進先出資料群組,將關聯於此直接輸出資料群組所表示同一幀的位元資料取出;以及所讀取出的多個位元資料與此直接輸出資料群組的單個位元資料依照幀資料的位元順序進行輸出,以解碼出完整幀資料。The invention provides a time domain de-interlacing processing method suitable for use in a digital audio broadcasting system. The method comprises: receiving a plurality of Common Interlaced Frame (CIF) data, wherein each CIF data is different and each CIF data comprises a plurality of bit data; forming a plurality of FIFO data groups according to the CIF data and directly Output data group (Note: the number of data sets is related to the number of soft decision bits), wherein each FIFO data group includes a plurality of bit data, and the direct output data group includes a single bit data; The first-in first-out data group is stored in the random access memory; the first-in-first-out data group in the random access memory is read, and the bit data associated with the same frame represented by the direct output data group is taken out And a plurality of read bit data and a single bit data of the direct output data group are output according to the bit sequence of the frame data to decode the complete frame data.
在本發明的一實施例中,當此方法係以M個軟式決策位元為基礎時,則儲存這些先進先出資料群組的隨機存取記憶體所需的空間總和X的計算式為:In an embodiment of the invention, when the method is based on M soft decision bits, the calculation formula of the space sum X required for storing the random access memory of the FIFO data groups is:
記憶體空間總和X=P×4(groups per cu)×120(group size)×M(soft decision bits),其中P為欲實施之容量單位(CU)的數量,M為軟式決策位元數(自然數)。The sum of memory spaces X = P × 4 (groups per cu) × 120 (group size) × M (soft decision bits), where P is the number of capacity units (CU) to be implemented, and M is the number of soft decision bits ( Natural number).
在本發明的一實施例中,在接收這些CIF資料的步驟後,更包括將這些CIF資料暫存至輸入緩衝器。此輸入緩衝器將De-QPSK解映像電路傳送過來之序列資料,分組平行送入記憶體。此輸入緩衝器具有128×M個位元的暫存空間。In an embodiment of the invention, after receiving the CIF data, the method further includes temporarily storing the CIF data to the input buffer. This input buffer sends the sequence data transmitted by the De-QPSK de-mapping circuit, and the packets are sent to the memory in parallel. This input buffer has a temporary storage space of 128 x M bits.
在本發明的一實施例中,將這些先進先出資料群組儲存至隨機存取記憶體的步驟包括以8個位元為一組重新排列,再儲存至隨機存取記憶體,而排列規則為依照如下資料順序來進行:X[1,17,33,49,65,81,97,113]、X[2,18,34,50,66,82,98,114]、X[3,19,35,51,67,83,99,115]、X[4,20,36,52,68,84,100,116]、X[5,21,37,53,69,85,101,117]、X[6,22,38,54,70,86,102,118]、X[7,23,39,55,71,87,103,119]、X[8,24,40,56,72,88,104,120]、X[9,25,41,57,73,89,105,121]、X[10,26,42,58,74,90,106,122]、X[11,27,43,59,75,91,107,123]、X[12,28,44,60,76,92,108,124]、X[13,29,45,61,77,93,109,125]、X[14,30,46,62,78,94,110,126]以及X[15,31,47,63,79,95,111,127],其中此處的X[]表示為以8個位元為一組的共同交錯幀資料,而每一個X[]中具有8筆數字係表示輸入資料的原始順序,而在將每一組的CIF資料排列至一輸出緩衝器時,亦依照此排列規則的順序,惟資料內容為已經過時域反交錯之內容。In an embodiment of the invention, the step of storing the FIFO data group into the random access memory comprises rearranging the data in groups of 8 bits, and storing the data in the random access memory, and arranging the rules. In order to proceed according to the following data order: X[1,17,33,49,65,81,97,113], X[2,18,34,50,66,82,98,114], X[3,19,35, 51,67,83,99,115], X[4,20,36,52,68,84,100,116], X[5,21,37,53,69,85,101,117], X[6,22,38,54,70 , 86, 102, 118], X [7, 23, 39, 55, 71, 87, 103, 119], X [8, 24, 40, 56, 72, 88, 104, 120], X [9, 25, 41, 57, 73, 89, 105, 121], X [10,26,42,58,74,90,106,122], X[11,27,43,59,75,91,107,123], X[12,28,44,60,76,92,108,124], X[13,29, 45, 61, 77, 93, 109, 125], X [14, 30, 46, 62, 78, 94, 110, 126] and X [15, 31, 47, 63, 79, 95, 111, 127], where X[] is represented as 8 The bits are a set of common interlaced frame data, and each X[] has 8 digits indicating the original order of the input data, and when arranging each group of CIF data into an output buffer, The order of this arrangement rule, but the content of the data is the content of the de-interlaced by the outdated domain.
在本發明的一實施例中,在解碼出該完整幀資料的步驟之前,更包括將所讀取出的多個位元資料與此直接輸出資料群組的單個位元資料依照幀資料的位元順序暫存至輸出緩衝器。此輸出緩衝器具有128×M個位元的暫存空間。In an embodiment of the present invention, before the step of decoding the complete frame data, the method further includes: reading the plurality of bit data and the single bit data of the direct output data group according to the bit of the frame data. The meta-order is temporarily stored in the output buffer. This output buffer has a temporary storage space of 128 x M bits.
在本發明的一實施例中,這些先進先出資料群組的數目為15組,且每一個先進先出資料群組具有不同的模數。其中,這些先進先出資料群組的模數依照順序分別為15、7、11、3、13、5、9、1、14、6、10、2、12、4以及8。In an embodiment of the invention, the number of these FIFO data groups is 15 groups, and each FIFO data group has a different modulus. The modulus of these FIFO data groups is 15, 7, 11, 3, 13, 5, 9, 1, 14, 6, 10, 2, 12, 4, and 8, respectively.
在本發明的一實施例中,當此方法係以多個軟式決策位元為基礎時,則儲存這些先進先出資料群組的隨機存取記憶體的空間分成對應這些軟式決策位元個數的獨立子記憶體空間。而在進行讀取隨機存取記憶體的步驟時,更根據所對應的軟式決策位元來致能對應的子記憶體空間,以讀取資料。In an embodiment of the present invention, when the method is based on a plurality of soft decision bits, the space of the random access memory storing the FIFO data groups is divided into the number of the soft decision bits. Independent sub-memory space. When the step of reading the random access memory is performed, the corresponding sub-memory space is further enabled according to the corresponding soft decision bit to read the data.
基於上述,本發明因有效管理隨機存取記憶體的配置空間,可在相對有限的RAM空間達成支援ETSI EN 300 401標準所訂之最大864 CU數。另一方面可以根據不同子通道設定不同的決策位元作彈性運用。本發明除了降低耗電量,同時又能大幅地降低硬體設計的複雜度。Based on the above, the present invention can achieve the maximum 864 CU number supported by the ETSI EN 300 401 standard in a relatively limited RAM space due to the effective management of the configuration space of the random access memory. On the other hand, different decision bits can be set for flexible use according to different sub-channels. The invention not only reduces the power consumption, but also greatly reduces the complexity of the hardware design.
為讓本發明的上述特徵和優點能更明顯易懂,下文特舉實施例,並配合所附圖式作詳細說明如下。The above described features and advantages of the invention will be apparent from the following description.
圖1為依照ETSI EN 300 401標準之數位音訊廣播(digital audio broadcasting,DAB)系統中的時域反交錯處理(time de-interleaver)電路和前後級的關係圖。請參閱圖1,數位音訊廣播系統100中包括反編碼正交相位鍵移調變(Demodulate Quadrature phase-shift keying,De-QPSK)解映像處理(de-mapper)電路110、時域反交錯處理電路120以及解剔除處理(de-puncture)電路130。時域反交錯處理電路120和前後級的資料匯流排為4位元,依據不同的軟式決策位元,有效的資料內容可為1、2、3、4位元。1 is a diagram of a time de-interleaver circuit and a front-to-back relationship in a digital audio broadcasting (DAB) system in accordance with the ETSI EN 300 401 standard. Referring to FIG. 1 , a digital audio broadcasting system 100 includes a Demodulate Quadrature Phase-Shift Keying (De-QPSK) de-mapper circuit 110 and a time domain de-interlacing processing circuit 120. And a de-puncture circuit 130. The time domain deinterlacing processing circuit 120 and the data bus of the front and rear stages are 4 bits. According to different soft decision bits, the effective data content can be 1, 2, 3, 4 bits.
圖2繪示為時域反交錯處理電路120接收一個軟式決策位元在儲存空間的示意圖。請參閱圖2。首先分析圖2中的r、r+1、r+2、…、r+15,分別表示為各個共同交錯幀(common interleaved frame,CIF)的接收順序,而data0、data1、data2、…、data15表示為以16位元為一個交錯處理(interleaver)群組。按照圖2中的儲存關係,16個圈圈中的資料就是在第15個CIF後,時域反交錯處理需輸出的還原資料。圖2中的資料全部相加為136個儲存位元,亦即真正所需要的記憶體空間只有136個位元,而可以省去用不到的部分。因此在接收完此136個位元後,便能輸出一組以16個位元為基礎的還原資料,例如以“Br,0、Br,1、Br,2、…、Br,14、Br,15”等16個CIF資料位元為一組還原資料,而“Br+1,0、Br+1,1、Br+1,2、…、Br+1,14、Br+1,15”等16個CIF資料位元為另一組還原資料,以此類推。由此可將此136個位元當成一個群組,並以支援4個軟式決策位元來表示的話,那麼可得所需要的記憶體空間為:864(cu)×4(group)×136(group size)×4(soft decision bits)=235008 byte。2 is a schematic diagram of the time domain de-interlacing processing circuit 120 receiving a soft decision bit in a storage space. Please refer to Figure 2. First, r, r+1, r+2, ..., r+15 in Fig. 2 are analyzed, which are respectively represented as the receiving order of each common interleaved frame (CIF), and data0, data1, data2, ..., data15 It is expressed as a 16-bit interleaver group. According to the storage relationship in Fig. 2, the data in the 16 circles is the restored data to be output in the time domain deinterlacing after the 15th CIF. The data in Figure 2 is all added to 136 storage bits, that is, the real required memory space is only 136 bits, and the unused portion can be omitted. Therefore, after receiving the 136 bits, a set of 16-bit based reduction data can be output, for example, "Br, 0, Br, 1, Br, 2, ..., Br, 14, Br, 16" and 16 CIF data bits are a set of restored data, and "Br+1, 0, Br+1, 1, Br+1, 2, ..., Br+1, 14, Br+1, 15", etc. 16 CIF data bits are another set of restored data, and so on. Thus, the 136 bits can be represented as a group and supported by four soft decision bits, so that the required memory space is: 864 (cu) × 4 (group) × 136 ( Group size) × 4 (soft decision bits) = 235008 byte.
圖3為依照本發明實施例之時域反交錯處理電路120接收一個軟式決策位元在記憶體空間的示意圖。請同時參閱圖2和圖3。經過圖2的分析可以發現,接收端在任何時刻只有原先之一半的資料被接收,所以記憶體空間只需上述記憶體大小之一半,然而這仍然佔據很大的記憶空間。另外,從圖2可進一步得知,data15在r+15時就需被取出,因此不需要額外的記憶體空間。於是。再進一步分析,並且改變儲存空間的讀寫機制,在第15個CIF之後,先將資料取出,再將原本要寫入r+15記憶體空間的資料,寫入已取出的記憶體空間。因此記憶體空間如圖3所示,其群組空間大小由136個位元減少為120個位元。以支援4個軟式決策位元來表示的話,便可將記憶體空間節省為:864(cu)×4(group numbers per cu)×120(group size)×4(soft decision bits)=207360 byte,約為202 KB。3 is a schematic diagram of a time domain de-interlacing processing circuit 120 receiving a soft decision bit in a memory space in accordance with an embodiment of the present invention. Please also refer to Figure 2 and Figure 3. It can be found from the analysis in Fig. 2 that only one half of the original data is received at any time, so the memory space only needs one and a half of the above memory size, but this still occupies a large memory space. In addition, as can be further seen from FIG. 2, data 15 needs to be taken out at r+15, so no additional memory space is required. then. Further analysis, and change the read and write mechanism of the storage space, after the 15th CIF, the data is first taken out, and the data originally written into the r+15 memory space is written into the extracted memory space. Therefore, the memory space is as shown in FIG. 3, and the group space size is reduced from 136 bits to 120 bits. By supporting four soft decision bits, the memory space can be saved as: 864 (cu) × 4 (group numbers per cu) × 120 (group size) × 4 (soft decision bits) = 207360 byte, It is about 202 KB.
根據上述實施例的揭示內容,傳統記憶體空間需要432 KB,而本發明實施例所需的記憶體空間為202 KB,可以有效降低記憶體所需的儲存空間。According to the disclosure of the foregoing embodiment, the conventional memory space requires 432 KB, and the memory space required by the embodiment of the present invention is 202 KB, which can effectively reduce the storage space required for the memory.
接下來請再參閱圖3。將圖3中的每一橫列視為一組先進先出(FIFO),共可分為15組FIFO,從De-QPSK解映像處理電路傳送過來的資料,依序進入各組FIFO,而實現此15組不同大小的FIFO,只需要15組模數計數器。在圖3中,第一組FIFO的模數(modulus)為15,所以計數範圍為0~14;第二組FIFO的模數為7,所以計數範圍為0~6;第三組FIFO的模數為11,所以計數範圍為0~10;其餘的第四組至第十五組的模數分別為3、13、5、9、1、14、6、10、2、12、4及8。每組計數器為依照CIF的模數作調整,根據各個不同模數的FIFO,那麼在第15個CIF的時刻後,各組FIFO就可以依序讀出正確之還原資料。Please refer to Figure 3 again. Each row in Figure 3 is regarded as a set of first-in-first-out (FIFO), which can be divided into 15 groups of FIFOs. The data transmitted from the De-QPSK solution processing circuit is sequentially entered into each group of FIFOs. These 15 sets of FIFOs of different sizes require only 15 sets of modulo counters. In Figure 3, the modulus of the first group of FIFOs is 15, so the counting range is 0~14; the modulus of the second group of FIFOs is 7, so the counting range is 0~6; the mode of the third group of FIFOs The number is 11, so the count range is 0~10; the remaining modules of the fourth to fifteenth groups are 3, 13, 5, 9, 1, 14, 6, 10, 2, 12, 4, and 8, respectively. . Each group of counters is adjusted according to the modulus of the CIF. According to the FIFO of each different modulus, after the 15th CIF time, each group of FIFOs can sequentially read the correct restored data.
圖4A為依照本發明實施例之時域反交錯處理電路的示意圖。圖4B與圖4C為依照圖4A之時域反交錯處理的示意圖。請同時參閱圖4A和圖4B。此時域反交錯處理電路120包括輸入緩衝器410、隨機存取記憶體(random access memory,RAM)420、輸出緩衝器430以及控制電路440。時域反交錯處理電路120的輸入端IN接收De-QPSK解映像處理電路傳送過的來的資料,並且資料經處理後由輸出端OUT輸出至解剔除處理電路。由於從De-QPSK解映像處理電路傳送過的來的資料是以位元為單位,也就是序列(series)傳送,如果收到每一個位元就做一次隨機存取記憶體的讀寫,則會增加RAM的耗電量,而且也使得控制電路440的設計更加複雜。因此,利用128個位元的輸入緩衝器410與128個位元的輸出緩衝器430作為RAM 420的前級與後級的緩衝處理,並且將資料做排列。將依序輸入的128個位元資料,以8個位元為一組重新排列,而並行(parallel)排列儲存至RAM 420,而排列規則為依照如下資料順序來進行:X[1,17,33,49,65,81,97,113]、X[2,18,34,50,66,82,98,114]、X[3,19,35,51,67,83,99,115]、X[4,20,36,52,68,84,100,116]、X[5,21,37,53,69,85,101,117]、X[6,22,38,54,70,86,102,118]、X[7,23,39,55,71,87,103,119]、X[8,24,40,56,72,88,104,120]、X[9,25,41,57,73,89,105,121]、X[10,26,42,58,74,90,106,122]、X[11,27,43,59,75,91,107,123]、X[12,28,44,60,76,92,108,124]、X[13,29,45,61,77,93,109,125]、X[14,30,46,62,78,94,110,126]以及X[15,31,47,63,79,95,111,127],其中,此處的X[]表示為在X軸方向上以8個位元為一組的CIF資料,而每一個X[ ]中具有8筆數字係表示輸入資料的原始順序,而在將每一組的CIF資料排列至輸出緩衝器430時,亦依照此排列規則的順序,惟資料內容為已經過時域反交錯之內容。亦即將交錯處理的16位元單位中相同的資料位元(data bit)分配在同一組,共為15組的8位元資料,而第16組為直接傳送至輸出緩衝器430,不需要進入到RAM 420。4A is a schematic diagram of a time domain de-interlacing processing circuit in accordance with an embodiment of the present invention. 4B and 4C are schematic diagrams of the time domain de-interlacing process in accordance with FIG. 4A. Please refer to FIG. 4A and FIG. 4B at the same time. The domain deinterlacing processing circuit 120 includes an input buffer 410, a random access memory (RAM) 420, an output buffer 430, and a control circuit 440. The input terminal IN of the time domain deinterlacing processing circuit 120 receives the data transmitted by the De-QPSK solution processing circuit, and the data is processed and outputted from the output terminal OUT to the de-cancellation processing circuit. Since the data transmitted from the De-QPSK solution processing circuit is transmitted in units of bits, that is, a sequence, if a random access memory is read and written once each bit is received, This will increase the power consumption of the RAM and also make the design of the control circuit 440 more complicated. Therefore, the 128-bit input buffer 410 and the 128-bit output buffer 430 are used as the buffer processing of the pre-stage and the post-stage of the RAM 420, and the data is arranged. The 128 bit data sequentially input is rearranged by a group of 8 bits, and the parallel arrangement is stored to the RAM 420, and the arrangement rule is performed according to the following data order: X[1, 17, 33,49,65,81,97,113], X[2,18,34,50,66,82,98,114], X[3,19,35,51,67,83,99,115], X[4,20 , 36, 52, 68, 84, 100, 116], X [5, 21, 37, 53, 69, 85, 101, 117], X [6, 22, 38, 54, 70, 86, 102, 118], X [7, 23, 39, 55, 71,87,103,119], X[8,24,40,56,72,88,104,120], X[9,25,41,57,73,89,105,121], X[10,26,42,58,74,90,106,122], X[11,27,43,59,75,91,107,123], X[12,28,44,60,76,92,108,124], X[13,29,45,61,77,93,109,125], X[14,30 , 46, 62, 78, 94, 110, 126] and X [15, 31, 47, 63, 79, 95, 111, 127], where X[] is represented as CIF in groups of 8 bits in the X-axis direction. Data, and each X[ ] has 8 digits indicating the original order of the input data, and when each set of CIF data is arranged to the output buffer 430, the order of the rules is also followed, but the content of the data is The content of the deinterlaced has been out of date. That is, the same data bit in the 16-bit unit that is interleaved is allocated in the same group, and a total of 15 groups of 8-bit data, and the 16th group is directly transmitted to the output buffer 430, and does not need to enter. Go to RAM 420.
請注意,RAM可以是動態隨機存取記憶體(dynamic random access memory,DRAM)或是靜態隨機存取記憶體(static random access memory,SRAM),本發明對於RAM的型態並不特別限制。Please note that the RAM may be a dynamic random access memory (DRAM) or a static random access memory (SRAM). The type of the RAM is not particularly limited.
在圖4B中繪示了Y[0~14,15~21,22~32,33~35,...],而Y[0~14,15~21,22~32,33~35,...]等同於Y[data_y0,data_y1,data_y2,data_y3,...,data_y14],用來表示位在記憶體空間Y軸方向的配置位址,例如data_y0為“0~14”,data_y0為儲存代表data0之Br~Br+14之CIF資料位址,Y[15~21]為儲存代表data1之Br~Br+6等CIF資料的位址,Y[22~32]為儲存代表data2之Br~Br+10等CIF資料的位址,Y[33~35]為儲存代表data3之Br~Br+2等CIF資料的位址,其餘的依此類推不再贅述。In Fig. 4B, Y[0~14, 15~21, 22~32, 33~35,...] are shown, and Y[0~14, 15~21, 22~32, 33~35,. ..] is equivalent to Y[data_y0, data_y1, data_y2, data_y3, ..., data_y14], which is used to indicate the configuration address of the bit in the Y-axis direction of the memory space, for example, data_y0 is "0~14", and data_y0 is stored. The CIF data address of Br~Br+14 representing data0, Y[15~21] is the address of CIF data such as Br~Br+6 representing data1, and Y[22~32] is the storage of Br~ representing data2. The address of CIF data such as Br+10, Y[33~35] is the address of CIF data such as Br~Br+2 representing data3, and the rest will not be repeated.
另外,在圖4B中繪示了MOD[15,7,11,3,13,5,9,1,14,6,10,2,12,4,8]用來表示data0至data14的模數分別為15、7、11、3、13、5、9、1、14、6、10、2、12、4以及8,而這些模數剛好與Y[]表示式之data_y0至data1_y14一對一對應。In addition, MOD[15,7,11,3,13,5,9,1,14,6,10,2,12,4,8] is used to represent the modulus of data0 to data14 in FIG. 4B. They are 15, 7, 11, 3, 13, 5, 9, 1, 14, 6, 10, 2, 12, 4, and 8, respectively, and these moduli are just one-to-one with data_y0 to data1_y14 of the Y[] expression. correspond.
另外,RAM 420的讀寫單位是以byte為單元,而不需以位元為單元,此一做法在一個軟式決策位元下,雖然增加了128個位元的緩衝區,卻可大大降低了RAM讀寫次數,使讀寫次數變成為原先的八分之一,因此可以降低RAM的耗電量。而且這樣排列的另一個好處是在同一位址的資料,為同一個CIF時刻的輸出資料,因此將128個位元寫入至前所述的各組FIFO,只需計算一次RAM位址,而存取在同一CIF中的其他群組資料,只需要加上一偏移位址。In addition, the reading and writing unit of the RAM 420 is in units of bytes, and does not need to be a unit of a bit. This method is greatly reduced in a soft decision bit, although a buffer of 128 bits is added. The number of RAM reads and writes makes the number of reads and writes become one-eighth of the original, thus reducing the power consumption of the RAM. And another advantage of this arrangement is that the data at the same address is the output data of the same CIF time, so 128 bits are written to each of the previously described FIFOs, and only one RAM address is calculated, and To access other group data in the same CIF, only one offset address needs to be added.
請再參閱圖4C,圖4C為從RAM 420讀出至輸出緩衝器430之示意圖。從RAM 420讀出資料時,同樣以8個位元為單位,其中8個位元等於1位元組(byte)。從RAM 420讀出資料,再將資料進行還原排列順序。例如第一個位元組是由前述CIF排序之X[1,17,33,49,65,81,97,113],此排序括號內的號碼即為要被放置於輸出緩衝器430的順序,資料做此排列的用意在於,並行處理8個交錯處理群組(8×16=128)。而此並行處理的優點為,只要一次的位址計算便可以完成8個群組,這也是用128個位元做為緩衝區的原因,另一個重要原因為128個位元剛好為2個容量單位(capacity unit,CU)的大小,其中一個CU等於64個位元。因此在硬體實現時只需要考慮奇數個CU的情形。若使用16個位元為一組,那麼緩衝區加大為256位元,同時需考慮CU數為n+1、n+2、n+3等另外三種情形,則將使硬體實現的複雜度提高,便減損了原先帶來的好處。Please refer to FIG. 4C again. FIG. 4C is a schematic diagram of reading from the RAM 420 to the output buffer 430. When data is read from the RAM 420, it is also in units of 8 bits, of which 8 bits are equal to 1 byte. The data is read from the RAM 420, and the data is restored and sorted. For example, the first byte is X[1,17,33,49,65,81,97,113] sorted by the aforementioned CIF, and the number in the parenthesis is the order to be placed in the output buffer 430. The purpose of this arrangement is to process 8 interleave processing groups in parallel (8 x 16 = 128). The advantage of this parallel processing is that as long as one address calculation can complete 8 groups, this is also the reason for using 128 bits as a buffer. Another important reason is that 128 bits are exactly 2 capacities. The size of a unit (CU), where one CU is equal to 64 bits. Therefore, only the case of an odd number of CUs needs to be considered in the hardware implementation. If 16 bits are used as a group, then the buffer is increased to 256 bits, and the other three cases, such as n+1, n+2, and n+3, need to be considered, which will make the hardware complex. The increase in degree will detract from the original benefits.
另一方面,當圖4B或圖4C的時域反交錯處理係以M個軟式決策位元為基礎時,則輸入緩衝器410或輸出緩衝器430為具有128×M個位元的暫存空間,而且儲存這些先進先出資料群組的隨機存取記憶體420的所需之記憶體空間總和X的計算式為:On the other hand, when the time domain de-interlacing processing of FIG. 4B or FIG. 4C is based on M soft decision bits, the input buffer 410 or the output buffer 430 is a temporary storage space having 128×M bits. And the sum of the required memory space X of the random access memory 420 storing these FIFO data groups is:
記憶體總和空間X=P×4(groups per cu)×120(group size)×M(soft decision bits),其中P為欲實施之CU的數量,M為軟式決策位元數(自然數)。The memory total space X = P × 4 (groups per cu) × 120 (group size) × M (soft decision bits), where P is the number of CUs to be implemented, and M is the number of soft decision bits (natural numbers).
圖5為依照本發明實施例之反交錯處理的決策位元的控制架構圖。請參閱圖5。圖5繪示不同軟式決策位元的做法,將所有需要的RAM空間切分為4塊,也就是4個獨立之子記憶體空間RAM1~RAM4,此4塊RAM為並行存取,且對應不同的決策位元。例如,最大有效位元(most significant bit,MSB)為RAM1,最小有效位元(least significant bit,LSB)為RAM4,當設定為一位元時,只需要一塊RAM動作,亦即只有四分之一的RAM空間為晶片選擇致能(CS enable)的狀態;若以傳統設計,不論幾位元,整塊RAM都在開啟的狀態,由此顯見傳統的方式較為耗電。再者,此決策位元的控制電路是採用並行架構,因此在不同的決策位元,並不需要額外的電路計算RAM的存取位址,如此可降低硬體實現的複雜度。請注意,子記憶體空間的數量不以此實施例為限。一切端視實際設計需求而論。FIG. 5 is a control architecture diagram of a decision bit of deinterlacing processing according to an embodiment of the present invention. Please refer to Figure 5. Figure 5 shows the different soft decision bits, dividing all required RAM space into 4 blocks, that is, 4 independent sub-memory spaces RAM1~RAM4, which are parallel accesses and corresponding to different Decision bit. For example, the most significant bit (MSB) is RAM1, and the least significant bit (LSB) is RAM4. When set to one bit, only one RAM action is required, that is, only four quarters. The RAM space of one is the state of the chip enable enable (CS enable); if the design is conventional, no matter how many bits, the entire RAM is turned on, thereby showing that the conventional method consumes more power. Moreover, the control circuit of the decision bit is a parallel architecture, so in different decision bits, no additional circuit is needed to calculate the access address of the RAM, which can reduce the complexity of the hardware implementation. Please note that the number of sub-memory spaces is not limited to this embodiment. Everything depends on the actual design needs.
另外,請將圖5以縱向來看,可示意為CIF之一段時間,假設有三個子通道SUBA、SUBB和SUBC需要被還原,且不同子通道各含不同性質之資料,例如子通道SUBA為音樂,子通道SUBB為投影片,子通道SUBC為電子節目導引(electronic program guide,EPG),所以本實施例可依照不同子通道之內容,設定不同之決策位元。例如,子通道SUBA為音樂,故期望有最好的收訊品質,所以設定為四個決策位元;而子通道SUBC為EPG,且EPG不需時常更新並且有重複發送的特性,所以可以只設定為一個決策位元,如此便可以達到省電的效果。In addition, please view Figure 5 in a vertical direction, which can be illustrated as a period of CIF, assuming that three sub-channels SUBA, SUBB and SUBC need to be restored, and different sub-channels each contain different properties, such as sub-channel SUBA for music, The sub-channel SUBB is a slide, and the sub-channel SUBC is an electronic program guide (EPG). Therefore, in this embodiment, different decision bits can be set according to the contents of different sub-channels. For example, the sub-channel SUBA is music, so it is expected to have the best reception quality, so it is set to four decision bits; the sub-channel SUBC is EPG, and the EPG does not need to be updated from time to time and has the characteristics of repeated transmission, so it can only Set as a decision bit, so you can achieve power saving effect.
值得一提的是,上述本發明各個實施例應用在數位音訊廣播中,可實現ETSI EN 300 401標準中的時域反交錯處理,並且在支援多個子通道情況下,還可有效降低所需儲存空間及消耗功率。It is worth mentioning that the above embodiments of the present invention are applied to digital audio broadcasting to implement time domain deinterlacing in the ETSI EN 300 401 standard, and can effectively reduce required storage when multiple subchannels are supported. Space and power consumption.
另一方面,圖5中繪示子通道SUBA接收第0個CU至第100個CU,子通道SUBB接收第150個CU至第200個CU,子通道SUBC接收第220個CU至第250個CU。若以子通道SUBA的起始位址ADDR_OFFSETA為基礎,則子通道SUBB的起始位址ADDR_OFFSETB等於ADDR_OFFSETA+150CU,而子通道SUBC的起始位址ADDR_OFFSETC等於ADDR_OFFSETA+220CU。請注意,本發明不以此實施例為限。On the other hand, in FIG. 5, the subchannel SUBA receives the 0th CU to the 100th CU, the subchannel SUBB receives the 150th CU to the 200th CU, and the subchannel SUBC receives the 220th CU to the 250th CU. . If based on the start address ADDR_OFFSETA of the sub-channel SUBA, the start address ADDR_OFFSETB of the sub-channel SUBB is equal to ADDR_OFFSETA+150CU, and the start address ADDR_OFFSETC of the sub-channel SUBC is equal to ADDR_OFFSETA+220CU. Please note that the present invention is not limited to this embodiment.
基於上述實施例所揭示的內容,可以彙整出一種通用的時域反交錯處理方法。更清楚來說,圖6繪示為本發明一實施例之時域反交錯處理方法的流程圖。請參閱圖6,本實施例之時域反交錯處理方法可以包括以下步驟:Based on the content disclosed in the above embodiments, a general time domain de-interlacing processing method can be summarized. More clearly, FIG. 6 is a flow chart of a time domain de-interlacing processing method according to an embodiment of the present invention. Referring to FIG. 6, the time domain de-interlacing processing method of this embodiment may include the following steps:
如步驟S601所示,接收從De-QPSK解映像處理電路傳送過來的多個共同交錯幀(CIF)資料,其中每一個CIF資料不同且每一個CIF資料包括多個位元資料。此外根據ETSI EN 300 401標準,每一個CIF資料為55296個位元資料。As shown in step S601, a plurality of Common Interlaced Frame (CIF) data transmitted from the De-QPSK de-image processing circuit are received, wherein each CIF data is different and each CIF data includes a plurality of bit data. In addition, according to the ETSI EN 300 401 standard, each CIF data is 55,296 bits of data.
接著,如步驟S603所示,根據這些CIF資料形成多個先進先出(FIFO)資料群組(如圖3繪示的每一橫列)與一個直接輸出資料群組(例如圖2繪示的data15之“Br,15”)。其中每一個FIFO資料群組包括多個位元資料,例如圖3中的data0的FIFO資料群組有15個位元資料,data1的FIFO資料群組有7個位元資料,其他則依圖3繪示內容類推,故不再贅述。而直接輸出資料群組包括單個位元資料,例如圖2繪示的data15之“Br,15”。另外,FIFO資料群組的數目為15組,且每一個FIFO資料群組具有不同的模數,而這些FIFO資料群組的模數,依照data0至data14的順序分別為15、7、11、3、13、5、9、1、14、6、10、2、12、4以及8,此部分請參考圖4B實施例。請注意,資料組數目和軟式決策位元數相關。Then, as shown in step S603, a plurality of first in first out (FIFO) data groups (such as each row shown in FIG. 3) and a direct output data group are formed according to the CIF data (for example, as shown in FIG. 2) Data15 "Br, 15"). Each of the FIFO data groups includes a plurality of bit data. For example, the FIFO data group of data0 in FIG. 3 has 15 bit data, the data FIFO data group has 7 bit data, and the other is according to FIG. The content is analogized, so I won't go into details. The direct output data group includes a single bit data, such as "Br, 15" of data15 shown in FIG. In addition, the number of FIFO data groups is 15 groups, and each FIFO data group has a different modulus, and the modulus of the FIFO data groups is 15, 7, 11, and 3 according to the order of data0 to data14, respectively. 13, 15, 9, 9, 14, 6, 10, 2, 12, 4, and 8, please refer to the embodiment of Figure 4B for this part. Note that the number of data sets is related to the number of soft decision bits.
接著,如步驟S605所示,將這些FIFO資料群組儲存至隨機存取記憶體(RAM)(此部分請參考圖4B實施例);接著,如步驟S607所示,讀取RAM中的這些FIFO資料群組,將關聯於直接輸出資料群組所表示同一幀的位元資料(例如將表示為第r個CIF的data0至data14)取出。Then, as shown in step S605, the FIFO data groups are stored in a random access memory (RAM) (refer to the embodiment of FIG. 4B for this part); then, as shown in step S607, the FIFOs in the RAM are read. The data group is extracted from the bit data of the same frame represented by the direct output data group (for example, data0 to data14 indicated as the rth CIF).
接著,如步驟S609所示,所讀取出的多個位元資料(data0至data14)與直接輸出資料群組的單個位元資料(data15)依照幀資料的位元順序進行輸出,如此一來可以解碼出一完整幀資料。Then, as shown in step S609, the read plurality of bit data (data0 to data14) and the single bit data (data15) of the direct output data group are output according to the bit order of the frame data, so that A complete frame of data can be decoded.
此外,當時域反交錯處理方法係以一個軟式決策位元為基礎時,則儲存這些先進先出資料群組的隨機存取記憶體的空間為120個位元。而當時域反交錯處理方法係以M個軟式決策位元為基礎時,則儲存這些先進先出資料群組的隨機存取記憶體的所需之記憶體空間總和X的計算式為:In addition, when the time domain de-interlacing method is based on a soft decision bit, the space for storing the random access memory of these FIFO data groups is 120 bits. When the domain de-interlacing method is based on M soft decision bits, the calculation formula of the total memory space X required for storing the random access memory of these FIFO data groups is:
記憶體總和空間X=P×4(groups per cu)×120(group size)×M(soft decision bits),其中P為欲實施之CU的數量,M為軟式決策位元數。The memory total space X = P × 4 (groups per cu) × 120 (group size) × M (soft decision bits), where P is the number of CUs to be implemented, and M is the number of soft decision bits.
在接收這些CIF資料的步驟S601後,更進一步包括將這些CIF資料暫存至輸入緩衝器(如圖4A至圖4B之輸入緩衝器410)。此輸入緩衝器可以具有128×M個位元的暫存空間。After receiving the CIF data step S601, it is further included to temporarily store the CIF data to the input buffer (such as the input buffer 410 of FIGS. 4A-4B). This input buffer can have a temporary storage space of 128 x M bits.
而在解碼出完整幀資料的步驟S609之前,更進一步包括將所讀取出的多個位元資料與直接輸出資料群組的單個位元資料依照幀資料的位元順序暫存至輸出緩衝器(如圖4A至圖4B之輸出緩衝器430)。此輸出緩衝器可以具有128×M個位元的暫存空間。Before the step S609 of decoding the complete frame data, the method further includes temporarily storing the read bit data and the single bit data of the direct output data group in the bit sequence of the frame data to the output buffer. (As shown in output buffer 430 of Figures 4A-4B). This output buffer can have a temporary storage space of 128 x M bits.
另一方面,當時域反交錯處理方法係以多個軟式決策位元為基礎時,則儲存這些FIFO資料群組的隨機存取記憶體的空間可分成對應這些軟式決策位元個數的獨立子記憶體空間。而在進行讀取隨機存取記憶體的步驟S607時,更進一步根據所對應的軟式決策位元來致能對應的子記憶體空間,以讀取相關資料。此部分請參照圖5實施例,在此不加以贅述。On the other hand, when the time domain de-interlacing method is based on multiple soft decision bits, the space of the random access memory storing these FIFO data groups can be divided into independent sub-numbers corresponding to the number of soft decision bits. Memory space. When the step S607 of reading the random access memory is performed, the corresponding sub-memory space is further enabled according to the corresponding soft decision bit to read the related data. Please refer to the embodiment of FIG. 5 for this part, and no further details are provided herein.
綜上所述,本發明實施例因有效管理隨機存取記憶體(RAM)的配置空間,可在相對有限的RAM(202 KB)空間達成支援ETSI EN 300 401標準所訂之最大864 CU數。另一方面可以根據不同子通道設定不同的決策位元作彈性運用。本發明實施例除了降低耗電量,同時又能大幅地降低硬體設計的複雜度,故本發明實施例為有效及優良之設計方案。In summary, the embodiment of the present invention can achieve the maximum 864 CU number supported by the ETSI EN 300 401 standard in a relatively limited RAM (202 KB) space due to effective management of the random access memory (RAM) configuration space. On the other hand, different decision bits can be set for flexible use according to different sub-channels. In the embodiment of the present invention, in addition to reducing the power consumption, and at the same time, the complexity of the hardware design is greatly reduced, the embodiment of the present invention is an effective and excellent design.
雖然本發明已以實施例揭露如上,然其並非用以限定本發明,任何所屬技術領域中具有通常知識者,在不脫離本發明的精神和範圍內,當可作些許更動與潤飾,故本發明的保護範圍當視後附的申請專利範圍所界定者為準。Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and those skilled in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.
100...數位音訊廣播系統100. . . Digital audio broadcasting system
110...De-QPSK解映像處理電路110. . . De-QPSK solution imaging processing circuit
120...時域反交錯處理電路120. . . Time domain deinterlacing processing circuit
130...解剔除處理電路130. . . Deblocking processing circuit
410...輸入緩衝器410. . . Input buffer
420...隨機存取記憶體420. . . Random access memory
430...輸出緩衝器430. . . Output buffer
440...控制電路440. . . Control circuit
ADDR_OFFSETA...子通道SUBA的起始位址ADDR_OFFSETA. . . Start address of subchannel SUBA
ADDR_OFFSETB...子通道SUBB的起始位址ADDR_OFFSETB. . . Start address of subchannel SUBB
ADDR_OFFSETC...子通道SUBC的起始位址ADDR_OFFSETC. . . Start address of subchannel SUBC
IN...輸入端IN. . . Input
OUT...輸出端OUT. . . Output
RAM1~RAM4...子記憶體空間RAM1~RAM4. . . Sub-memory space
S601~S609...本發明一實施例之時域反交錯處理方法的各步驟S601~S609. . . Each step of the time domain de-interlacing processing method according to an embodiment of the present invention
下面的所附圖式是本發明的說明書的一部分,繪示了本發明的示例實施例,所附圖式與說明書的描述一起說明本發明的原理。The following drawings are a part of the specification of the invention, and illustrate the embodiments of the invention
圖1為依照ETSI EN 300 401標準之數位音訊廣播系統中的時域反交錯處理電路和前後級的關係圖。1 is a diagram showing the relationship between a time domain de-interlacing processing circuit and a front-end stage in a digital audio broadcasting system in accordance with the ETSI EN 300 401 standard.
圖2繪示為時域反交錯處理電路120接收一個軟式決策位元在儲存空間的示意圖。2 is a schematic diagram of the time domain de-interlacing processing circuit 120 receiving a soft decision bit in a storage space.
圖3為依照本發明實施例之時域反交錯處理電路120接收一個軟式決策位元在記憶體空間的示意圖。3 is a schematic diagram of a time domain de-interlacing processing circuit 120 receiving a soft decision bit in a memory space in accordance with an embodiment of the present invention.
圖4A為依照本發明實施例之時域反交錯處理電路的示意圖。4A is a schematic diagram of a time domain de-interlacing processing circuit in accordance with an embodiment of the present invention.
圖4B與圖4C為依照圖4A之時域反交錯處理的示意圖。4B and 4C are schematic diagrams of the time domain de-interlacing process in accordance with FIG. 4A.
圖5為依照本發明實施例之反交錯處理的決策位元的控制架構圖。FIG. 5 is a control architecture diagram of a decision bit of deinterlacing processing according to an embodiment of the present invention.
圖6繪示為本發明一實施例之時域反交錯處理方法的流程圖。6 is a flow chart of a time domain de-interlacing processing method according to an embodiment of the present invention.
S601~S609...本發明一實施例之時域反交錯處理方法的各步驟S601~S609. . . Each step of the time domain de-interlacing processing method according to an embodiment of the present invention
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