TW201330533A - Time de-interleaver method for digital audio broadcasting system - Google Patents

Abstract

A de-interleaver method suitable for a digital audio broadcasting system is provided. The provided method includes: receiving a plurality of common interleaved frames (CIF) data, wherein each CIF data is different and each CIF data includes a plurality of bit data; forming a plurality of first in first out (FIFO) data groups and a direct output data group; storing these FIFO data groups into a RAM; reading these FIFO data groups from the RAM and outputting the bit data that is in accordance with the same frame of the direct output data group; and outputting a plurality of the readout bit data and the single bit data of the direct output data group in a frame bit sequence so as to decode a complete frame data.

Description

Time domain deinterlacing processing method for digital audio broadcasting system

The present invention relates to a decoding technique for a digital audio broadcasting system, and more particularly to a time domain de-interlacing processing method suitable for a digital audio broadcasting system.

Compared with traditional broadcasting, digital audio broadcasting (DAB) is more efficient in spectrum utilization than anti-interference, anti-noise and high sound quality. According to the ETSI EN 300 401 standard, each channel can have up to 64 different subchannels. Therefore, the broadcaster can transmit the audio and video programs while using other subchannels to transmit the graphic materials. When the terminal listeners listen to the broadcast programs, they can simultaneously Received additional information. When digital audio broadcasting is applied to handheld devices, low power consumption becomes an indispensable condition.

According to the ETSI EN 300 401 standard, each channel is subjected to time interleaver before transmission, and the original data is dispersed in common interleaved frames (CIF) to reduce burst errors (burst). The impact of error). In the time domain interleaving process, 16 bits are respectively dispersed in 16 different CIFs by bit reverse. See Table 1, which is taken from the ETSI EN 300 401 standard, and r' as an r function for the possible values for each i _r modulus 16. For example, the 0th bit is placed at the 0th CIF, the 1st bit is placed at the first 8 CIF positions (0001→1000) relative to the 0th CIF, and the second bit is placed at the 0th CIF. The first 4 CIF positions (0011→1100),..., the 14th bit is placed in the first 7 CIF positions (1110→0111) relative to the 0th CIF, and the 15th bit is configured in the relative 0th CIF. The top 15 CIF locations.

See Table 2 above for the time relationship between input and output in time domain interleaving. From Table 2, it can be found that, based on the characteristics of time delay, the receiving end must wait for the data bits dispersed in the 16 CIFs, and the data can be restored again after complete reception, so the first 16 CIF data bits to be received are needed. Store temporarily in memory. To support the maximum capacity unit (CU), the maximum number of CIFs is 864 CUs, and the memory size is 864 (cu) × 64 (in terms of soft decision bits). Bits/cu) × 16 (cif) × 4 (soft decision bit) = 442368 byte, which is about 432 KB, of which 1 KB is equal to 1024 bytes, so considerable storage space is required for time domain de-interlacing (time de- Interleaver).

Although time-domain interleaving helps eliminate clumping errors and time selective fading, it is in exchange for increased storage space. Generally, designs often compromise and do not complete. Supports the 864CU as specified in the ETSI EN 300 401 standard.

In view of this, the present invention proposes a time domain de-interlacing processing method to solve the problems described in the prior art.

The invention provides a time domain de-interlacing processing method suitable for use in a digital audio broadcasting system. The method comprises: receiving a plurality of Common Interlaced Frame (CIF) data, wherein each CIF data is different and each CIF data comprises a plurality of bit data; forming a plurality of FIFO data groups according to the CIF data and directly Output data group (Note: the number of data sets is related to the number of soft decision bits), wherein each FIFO data group includes a plurality of bit data, and the direct output data group includes a single bit data; The first-in first-out data group is stored in the random access memory; the first-in-first-out data group in the random access memory is read, and the bit data associated with the same frame represented by the direct output data group is taken out And a plurality of read bit data and a single bit data of the direct output data group are output according to the bit sequence of the frame data to decode the complete frame data.

In an embodiment of the invention, when the method is based on M soft decision bits, the calculation formula of the space sum X required for storing the random access memory of the FIFO data groups is:

The sum of memory spaces X = P × 4 (groups per cu) × 120 (group size) × M (soft decision bits), where P is the number of capacity units (CU) to be implemented, and M is the number of soft decision bits ( Natural number).

In an embodiment of the invention, after receiving the CIF data, the method further includes temporarily storing the CIF data to the input buffer. This input buffer sends the sequence data transmitted by the De-QPSK de-mapping circuit, and the packets are sent to the memory in parallel. This input buffer has a temporary storage space of 128 x M bits.

In an embodiment of the invention, the step of storing the FIFO data group into the random access memory comprises rearranging the data in groups of 8 bits, and storing the data in the random access memory, and arranging the rules. In order to proceed according to the following data order: X[1,17,33,49,65,81,97,113], X[2,18,34,50,66,82,98,114], X[3,19,35, 51,67,83,99,115], X[4,20,36,52,68,84,100,116], X[5,21,37,53,69,85,101,117], X[6,22,38,54,70 , 86, 102, 118], X [7, 23, 39, 55, 71, 87, 103, 119], X [8, 24, 40, 56, 72, 88, 104, 120], X [9, 25, 41, 57, 73, 89, 105, 121], X [10,26,42,58,74,90,106,122], X[11,27,43,59,75,91,107,123], X[12,28,44,60,76,92,108,124], X[13,29, 45, 61, 77, 93, 109, 125], X [14, 30, 46, 62, 78, 94, 110, 126] and X [15, 31, 47, 63, 79, 95, 111, 127], where X[] is represented as 8 The bits are a set of common interlaced frame data, and each X[] has 8 digits indicating the original order of the input data, and when arranging each group of CIF data into an output buffer, The order of this arrangement rule, but the content of the data is the content of the de-interlaced by the outdated domain.

In an embodiment of the present invention, before the step of decoding the complete frame data, the method further includes: reading the plurality of bit data and the single bit data of the direct output data group according to the bit of the frame data. The meta-order is temporarily stored in the output buffer. This output buffer has a temporary storage space of 128 x M bits.

In an embodiment of the invention, the number of these FIFO data groups is 15 groups, and each FIFO data group has a different modulus. The modulus of these FIFO data groups is 15, 7, 11, 3, 13, 5, 9, 1, 14, 6, 10, 2, 12, 4, and 8, respectively.

In an embodiment of the present invention, when the method is based on a plurality of soft decision bits, the space of the random access memory storing the FIFO data groups is divided into the number of the soft decision bits. Independent sub-memory space. When the step of reading the random access memory is performed, the corresponding sub-memory space is further enabled according to the corresponding soft decision bit to read the data.

Based on the above, the present invention can achieve the maximum 864 CU number supported by the ETSI EN 300 401 standard in a relatively limited RAM space due to the effective management of the configuration space of the random access memory. On the other hand, different decision bits can be set for flexible use according to different sub-channels. The invention not only reduces the power consumption, but also greatly reduces the complexity of the hardware design.

The above described features and advantages of the invention will be apparent from the following description.

1 is a diagram of a time de-interleaver circuit and a front-to-back relationship in a digital audio broadcasting (DAB) system in accordance with the ETSI EN 300 401 standard. Referring to FIG. 1 , a digital audio broadcasting system 100 includes a Demodulate Quadrature Phase-Shift Keying (De-QPSK) de-mapper circuit 110 and a time domain de-interlacing processing circuit 120. And a de-puncture circuit 130. The time domain deinterlacing processing circuit 120 and the data bus of the front and rear stages are 4 bits. According to different soft decision bits, the effective data content can be 1, 2, 3, 4 bits.

2 is a schematic diagram of the time domain de-interlacing processing circuit 120 receiving a soft decision bit in a storage space. Please refer to Figure 2. First, r, r+1, r+2, ..., r+15 in Fig. 2 are analyzed, which are respectively represented as the receiving order of each common interleaved frame (CIF), and data0, data1, data2, ..., data15 It is expressed as a 16-bit interleaver group. According to the storage relationship in Fig. 2, the data in the 16 circles is the restored data to be output in the time domain deinterlacing after the 15th CIF. The data in Figure 2 is all added to 136 storage bits, that is, the real required memory space is only 136 bits, and the unused portion can be omitted. Therefore, after receiving the 136 bits, a set of 16-bit based reduction data can be output, for example, "Br, 0, Br, 1, Br, 2, ..., Br, 14, Br, 16" and 16 CIF data bits are a set of restored data, and "Br+1, 0, Br+1, 1, Br+1, 2, ..., Br+1, 14, Br+1, 15", etc. 16 CIF data bits are another set of restored data, and so on. Thus, the 136 bits can be represented as a group and supported by four soft decision bits, so that the required memory space is: 864 (cu) × 4 (group) × 136 ( Group size) × 4 (soft decision bits) = 235008 byte.

3 is a schematic diagram of a time domain de-interlacing processing circuit 120 receiving a soft decision bit in a memory space in accordance with an embodiment of the present invention. Please also refer to Figure 2 and Figure 3. It can be found from the analysis in Fig. 2 that only one half of the original data is received at any time, so the memory space only needs one and a half of the above memory size, but this still occupies a large memory space. In addition, as can be further seen from FIG. 2, data 15 needs to be taken out at r+15, so no additional memory space is required. then. Further analysis, and change the read and write mechanism of the storage space, after the 15th CIF, the data is first taken out, and the data originally written into the r+15 memory space is written into the extracted memory space. Therefore, the memory space is as shown in FIG. 3, and the group space size is reduced from 136 bits to 120 bits. By supporting four soft decision bits, the memory space can be saved as: 864 (cu) × 4 (group numbers per cu) × 120 (group size) × 4 (soft decision bits) = 207360 byte, It is about 202 KB.

According to the disclosure of the foregoing embodiment, the conventional memory space requires 432 KB, and the memory space required by the embodiment of the present invention is 202 KB, which can effectively reduce the storage space required for the memory.

Please refer to Figure 3 again. Each row in Figure 3 is regarded as a set of first-in-first-out (FIFO), which can be divided into 15 groups of FIFOs. The data transmitted from the De-QPSK solution processing circuit is sequentially entered into each group of FIFOs. These 15 sets of FIFOs of different sizes require only 15 sets of modulo counters. In Figure 3, the modulus of the first group of FIFOs is 15, so the counting range is 0~14; the modulus of the second group of FIFOs is 7, so the counting range is 0~6; the mode of the third group of FIFOs The number is 11, so the count range is 0~10; the remaining modules of the fourth to fifteenth groups are 3, 13, 5, 9, 1, 14, 6, 10, 2, 12, 4, and 8, respectively. . Each group of counters is adjusted according to the modulus of the CIF. According to the FIFO of each different modulus, after the 15th CIF time, each group of FIFOs can sequentially read the correct restored data.

4A is a schematic diagram of a time domain de-interlacing processing circuit in accordance with an embodiment of the present invention. 4B and 4C are schematic diagrams of the time domain de-interlacing process in accordance with FIG. 4A. Please refer to FIG. 4A and FIG. 4B at the same time. The domain deinterlacing processing circuit 120 includes an input buffer 410, a random access memory (RAM) 420, an output buffer 430, and a control circuit 440. The input terminal IN of the time domain deinterlacing processing circuit 120 receives the data transmitted by the De-QPSK solution processing circuit, and the data is processed and outputted from the output terminal OUT to the de-cancellation processing circuit. Since the data transmitted from the De-QPSK solution processing circuit is transmitted in units of bits, that is, a sequence, if a random access memory is read and written once each bit is received, This will increase the power consumption of the RAM and also make the design of the control circuit 440 more complicated. Therefore, the 128-bit input buffer 410 and the 128-bit output buffer 430 are used as the buffer processing of the pre-stage and the post-stage of the RAM 420, and the data is arranged. The 128 bit data sequentially input is rearranged by a group of 8 bits, and the parallel arrangement is stored to the RAM 420, and the arrangement rule is performed according to the following data order: X[1, 17, 33,49,65,81,97,113], X[2,18,34,50,66,82,98,114], X[3,19,35,51,67,83,99,115], X[4,20 , 36, 52, 68, 84, 100, 116], X [5, 21, 37, 53, 69, 85, 101, 117], X [6, 22, 38, 54, 70, 86, 102, 118], X [7, 23, 39, 55, 71,87,103,119], X[8,24,40,56,72,88,104,120], X[9,25,41,57,73,89,105,121], X[10,26,42,58,74,90,106,122], X[11,27,43,59,75,91,107,123], X[12,28,44,60,76,92,108,124], X[13,29,45,61,77,93,109,125], X[14,30 , 46, 62, 78, 94, 110, 126] and X [15, 31, 47, 63, 79, 95, 111, 127], where X[] is represented as CIF in groups of 8 bits in the X-axis direction. Data, and each X[ ] has 8 digits indicating the original order of the input data, and when each set of CIF data is arranged to the output buffer 430, the order of the rules is also followed, but the content of the data is The content of the deinterlaced has been out of date. That is, the same data bit in the 16-bit unit that is interleaved is allocated in the same group, and a total of 15 groups of 8-bit data, and the 16th group is directly transmitted to the output buffer 430, and does not need to enter. Go to RAM 420.

Please note that the RAM may be a dynamic random access memory (DRAM) or a static random access memory (SRAM). The type of the RAM is not particularly limited.

In Fig. 4B, Y[0~14, 15~21, 22~32, 33~35,...] are shown, and Y[0~14, 15~21, 22~32, 33~35,. ..] is equivalent to Y[data_y0, data_y1, data_y2, data_y3, ..., data_y14], which is used to indicate the configuration address of the bit in the Y-axis direction of the memory space, for example, data_y0 is "0~14", and data_y0 is stored. The CIF data address of Br~Br+14 representing data0, Y[15~21] is the address of CIF data such as Br~Br+6 representing data1, and Y[22~32] is the storage of Br~ representing data2. The address of CIF data such as Br+10, Y[33~35] is the address of CIF data such as Br~Br+2 representing data3, and the rest will not be repeated.

In addition, MOD[15,7,11,3,13,5,9,1,14,6,10,2,12,4,8] is used to represent the modulus of data0 to data14 in FIG. 4B. They are 15, 7, 11, 3, 13, 5, 9, 1, 14, 6, 10, 2, 12, 4, and 8, respectively, and these moduli are just one-to-one with data_y0 to data1_y14 of the Y[] expression. correspond.

In addition, the reading and writing unit of the RAM 420 is in units of bytes, and does not need to be a unit of a bit. This method is greatly reduced in a soft decision bit, although a buffer of 128 bits is added. The number of RAM reads and writes makes the number of reads and writes become one-eighth of the original, thus reducing the power consumption of the RAM. And another advantage of this arrangement is that the data at the same address is the output data of the same CIF time, so 128 bits are written to each of the previously described FIFOs, and only one RAM address is calculated, and To access other group data in the same CIF, only one offset address needs to be added.

Please refer to FIG. 4C again. FIG. 4C is a schematic diagram of reading from the RAM 420 to the output buffer 430. When data is read from the RAM 420, it is also in units of 8 bits, of which 8 bits are equal to 1 byte. The data is read from the RAM 420, and the data is restored and sorted. For example, the first byte is X[1,17,33,49,65,81,97,113] sorted by the aforementioned CIF, and the number in the parenthesis is the order to be placed in the output buffer 430. The purpose of this arrangement is to process 8 interleave processing groups in parallel (8 x 16 = 128). The advantage of this parallel processing is that as long as one address calculation can complete 8 groups, this is also the reason for using 128 bits as a buffer. Another important reason is that 128 bits are exactly 2 capacities. The size of a unit (CU), where one CU is equal to 64 bits. Therefore, only the case of an odd number of CUs needs to be considered in the hardware implementation. If 16 bits are used as a group, then the buffer is increased to 256 bits, and the other three cases, such as n+1, n+2, and n+3, need to be considered, which will make the hardware complex. The increase in degree will detract from the original benefits.

On the other hand, when the time domain de-interlacing processing of FIG. 4B or FIG. 4C is based on M soft decision bits, the input buffer 410 or the output buffer 430 is a temporary storage space having 128×M bits. And the sum of the required memory space X of the random access memory 420 storing these FIFO data groups is:

The memory total space X = P × 4 (groups per cu) × 120 (group size) × M (soft decision bits), where P is the number of CUs to be implemented, and M is the number of soft decision bits (natural numbers).

FIG. 5 is a control architecture diagram of a decision bit of deinterlacing processing according to an embodiment of the present invention. Please refer to Figure 5. Figure 5 shows the different soft decision bits, dividing all required RAM space into 4 blocks, that is, 4 independent sub-memory spaces RAM1~RAM4, which are parallel accesses and corresponding to different Decision bit. For example, the most significant bit (MSB) is RAM1, and the least significant bit (LSB) is RAM4. When set to one bit, only one RAM action is required, that is, only four quarters. The RAM space of one is the state of the chip enable enable (CS enable); if the design is conventional, no matter how many bits, the entire RAM is turned on, thereby showing that the conventional method consumes more power. Moreover, the control circuit of the decision bit is a parallel architecture, so in different decision bits, no additional circuit is needed to calculate the access address of the RAM, which can reduce the complexity of the hardware implementation. Please note that the number of sub-memory spaces is not limited to this embodiment. Everything depends on the actual design needs.

In addition, please view Figure 5 in a vertical direction, which can be illustrated as a period of CIF, assuming that three sub-channels SUBA, SUBB and SUBC need to be restored, and different sub-channels each contain different properties, such as sub-channel SUBA for music, The sub-channel SUBB is a slide, and the sub-channel SUBC is an electronic program guide (EPG). Therefore, in this embodiment, different decision bits can be set according to the contents of different sub-channels. For example, the sub-channel SUBA is music, so it is expected to have the best reception quality, so it is set to four decision bits; the sub-channel SUBC is EPG, and the EPG does not need to be updated from time to time and has the characteristics of repeated transmission, so it can only Set as a decision bit, so you can achieve power saving effect.

It is worth mentioning that the above embodiments of the present invention are applied to digital audio broadcasting to implement time domain deinterlacing in the ETSI EN 300 401 standard, and can effectively reduce required storage when multiple subchannels are supported. Space and power consumption.

On the other hand, in FIG. 5, the subchannel SUBA receives the 0th CU to the 100th CU, the subchannel SUBB receives the 150th CU to the 200th CU, and the subchannel SUBC receives the 220th CU to the 250th CU. . If based on the start address ADDR_OFFSETA of the sub-channel SUBA, the start address ADDR_OFFSETB of the sub-channel SUBB is equal to ADDR_OFFSETA+150CU, and the start address ADDR_OFFSETC of the sub-channel SUBC is equal to ADDR_OFFSETA+220CU. Please note that the present invention is not limited to this embodiment.

Based on the content disclosed in the above embodiments, a general time domain de-interlacing processing method can be summarized. More clearly, FIG. 6 is a flow chart of a time domain de-interlacing processing method according to an embodiment of the present invention. Referring to FIG. 6, the time domain de-interlacing processing method of this embodiment may include the following steps:

As shown in step S601, a plurality of Common Interlaced Frame (CIF) data transmitted from the De-QPSK de-image processing circuit are received, wherein each CIF data is different and each CIF data includes a plurality of bit data. In addition, according to the ETSI EN 300 401 standard, each CIF data is 55,296 bits of data.

Then, as shown in step S603, a plurality of first in first out (FIFO) data groups (such as each row shown in FIG. 3) and a direct output data group are formed according to the CIF data (for example, as shown in FIG. 2) Data15 "Br, 15"). Each of the FIFO data groups includes a plurality of bit data. For example, the FIFO data group of data0 in FIG. 3 has 15 bit data, the data FIFO data group has 7 bit data, and the other is according to FIG. The content is analogized, so I won't go into details. The direct output data group includes a single bit data, such as "Br, 15" of data15 shown in FIG. In addition, the number of FIFO data groups is 15 groups, and each FIFO data group has a different modulus, and the modulus of the FIFO data groups is 15, 7, 11, and 3 according to the order of data0 to data14, respectively. 13, 15, 9, 9, 14, 6, 10, 2, 12, 4, and 8, please refer to the embodiment of Figure 4B for this part. Note that the number of data sets is related to the number of soft decision bits.

Then, as shown in step S605, the FIFO data groups are stored in a random access memory (RAM) (refer to the embodiment of FIG. 4B for this part); then, as shown in step S607, the FIFOs in the RAM are read. The data group is extracted from the bit data of the same frame represented by the direct output data group (for example, data0 to data14 indicated as the rth CIF).

Then, as shown in step S609, the read plurality of bit data (data0 to data14) and the single bit data (data15) of the direct output data group are output according to the bit order of the frame data, so that A complete frame of data can be decoded.

In addition, when the time domain de-interlacing method is based on a soft decision bit, the space for storing the random access memory of these FIFO data groups is 120 bits. When the domain de-interlacing method is based on M soft decision bits, the calculation formula of the total memory space X required for storing the random access memory of these FIFO data groups is:

The memory total space X = P × 4 (groups per cu) × 120 (group size) × M (soft decision bits), where P is the number of CUs to be implemented, and M is the number of soft decision bits.

After receiving the CIF data step S601, it is further included to temporarily store the CIF data to the input buffer (such as the input buffer 410 of FIGS. 4A-4B). This input buffer can have a temporary storage space of 128 x M bits.

Before the step S609 of decoding the complete frame data, the method further includes temporarily storing the read bit data and the single bit data of the direct output data group in the bit sequence of the frame data to the output buffer. (As shown in output buffer 430 of Figures 4A-4B). This output buffer can have a temporary storage space of 128 x M bits.

On the other hand, when the time domain de-interlacing method is based on multiple soft decision bits, the space of the random access memory storing these FIFO data groups can be divided into independent sub-numbers corresponding to the number of soft decision bits. Memory space. When the step S607 of reading the random access memory is performed, the corresponding sub-memory space is further enabled according to the corresponding soft decision bit to read the related data. Please refer to the embodiment of FIG. 5 for this part, and no further details are provided herein.

In summary, the embodiment of the present invention can achieve the maximum 864 CU number supported by the ETSI EN 300 401 standard in a relatively limited RAM (202 KB) space due to effective management of the random access memory (RAM) configuration space. On the other hand, different decision bits can be set for flexible use according to different sub-channels. In the embodiment of the present invention, in addition to reducing the power consumption, and at the same time, the complexity of the hardware design is greatly reduced, the embodiment of the present invention is an effective and excellent design.

Although the present invention has been disclosed in the above embodiments, it is not intended to limit the present invention, and those skilled in the art can make some changes and refinements without departing from the spirit and scope of the present invention. The scope of the invention is defined by the scope of the appended claims.

100. . . Digital audio broadcasting system

110. . . De-QPSK solution imaging processing circuit

120. . . Time domain deinterlacing processing circuit

130. . . Deblocking processing circuit

410. . . Input buffer

420. . . Random access memory

430. . . Output buffer

440. . . Control circuit

ADDR_OFFSETA. . . Start address of subchannel SUBA

ADDR_OFFSETB. . . Start address of subchannel SUBB

ADDR_OFFSETC. . . Start address of subchannel SUBC

IN. . . Input

OUT. . . Output

RAM1~RAM4. . . Sub-memory space

S601~S609. . . Each step of the time domain de-interlacing processing method according to an embodiment of the present invention

The following drawings are a part of the specification of the invention, and illustrate the embodiments of the invention

1 is a diagram showing the relationship between a time domain de-interlacing processing circuit and a front-end stage in a digital audio broadcasting system in accordance with the ETSI EN 300 401 standard.

2 is a schematic diagram of the time domain de-interlacing processing circuit 120 receiving a soft decision bit in a storage space.

3 is a schematic diagram of a time domain de-interlacing processing circuit 120 receiving a soft decision bit in a memory space in accordance with an embodiment of the present invention.

4A is a schematic diagram of a time domain de-interlacing processing circuit in accordance with an embodiment of the present invention.

4B and 4C are schematic diagrams of the time domain de-interlacing process in accordance with FIG. 4A.

FIG. 5 is a control architecture diagram of a decision bit of deinterlacing processing according to an embodiment of the present invention.

6 is a flow chart of a time domain de-interlacing processing method according to an embodiment of the present invention.

S601~S609. . . Each step of the time domain de-interlacing processing method according to an embodiment of the present invention

Claims (12)

A time domain de-interlacing processing method is applicable to a digital audio broadcasting system, the method comprising: receiving a plurality of common interlaced frame data, wherein each common interlaced frame data is different and each common interlaced frame data comprises a plurality of bit data; Forming, according to the common interlaced frame data, a plurality of FIFO data groups and a direct output data group, wherein each of the FIFO data groups includes a plurality of bit data, and the direct output data group includes a single bit data; storing the FIFO data groups in a random access memory; reading the FIFO data groups in the random access memory to be associated with the direct output data group The bit data of the same frame is taken out by the group; and the read bit data and the single bit data of the direct output data group are output according to the bit sequence of the frame data to decode a complete frame. data. The time domain deinterlacing processing method according to claim 1, wherein when the method is based on M soft decision bits, the random access memory of the FIFO data group is stored. The sum of the required spaces is P × 4 × 120 × M bits, where P is the number of capacity units to be implemented, and M is the number of soft decision bits. The time domain deinterlacing processing method of claim 1, wherein after the step of receiving the common interlaced frame data, the method further comprises: temporarily storing the common interlaced frame data to an input buffer. The time domain deinterlacing processing method according to claim 3, wherein the input buffer has a temporary storage space of 128×M bits, wherein M is a soft decision bit number. The time domain deinterlacing processing method of claim 1, wherein the step of storing the FIFO data groups in the random access memory comprises rearranging the groups of 8 bits, and then Stored in the random access memory, and the arrangement rule is performed according to the following data order: X[1,17,33,49,65,81,97,113], X[2,18,34,50,66,82 , 98, 114], X [3, 19, 35, 51, 67, 83, 99, 115], X [4, 20, 36, 52, 68, 84, 100, 116], X [5, 21, 37, 53, 69, 85, 101, 117] , X[6,22,38,54,70,86,102,118], X[7,23,39,55,71,87,103,119], X[8,24,40,56,72,88,104,120], X[9, 25,41,57,73,89,105,121], X[10,26,42,58,74,90,106,122], X[11,27,43,59,75,91,107,123], X[12,28,44,60 , 76, 92, 108, 124], X [13, 29, 45, 61, 77, 93, 109, 125], X [14, 30, 46, 62, 78, 94, 110, 126] and X [15, 31, 47, 63, 79, 95, 111, 127] Where X[] is represented as a common interlaced frame data in groups of 8 bits, and each X[] has 8 digits indicating the original order of the input data, but the data content is outdated domain Deinterlaced content. The time domain deinterlacing processing method according to claim 5, wherein if the common interlaced frame data of each group according to the arrangement rule is output to an output buffer, the order of the arrangement rules is also followed. arrangement. The time domain deinterlacing processing method of claim 1, wherein before the step of decoding the complete frame data, the method further comprises: reading the plurality of bit data and the direct output data group The single bit data is temporarily stored in an output buffer according to the bit order of the frame data. The time domain deinterlacing processing method according to claim 7, wherein the output buffer has a temporary storage space of 128×M bits, wherein M is a soft decision bit number. The time domain deinterlacing processing method of claim 1, wherein the number of the first in first out data groups is 15 groups, and each of the first in first out data groups has different modulus. The time domain deinterlacing processing method as described in claim 8, wherein the modulus of the FIFO data groups is 15, 7, 11, 3, 13, 5, 9, 1, and 14, respectively. , 6, 10, 2, 12, 4, and 8. The time domain deinterlacing processing method according to claim 1, wherein when the method is based on a plurality of soft decision bits, storing the random access memory of the FIFO data group The space is divided into independent sub-memory spaces corresponding to the number of soft decision bits. The time domain deinterlacing processing method according to claim 11, wherein when the step of reading the random access memory is performed, the corresponding sub-memory space is further enabled according to the corresponding soft decision bit. To read the data.