TW201327762A - Through silicon via and method of forming the same - Google Patents

Abstract

The present invention relates to a through silicon via (TSV). The TSV is disposed in a substrate including a via opening penetrating through a first surface and a second surface of the substrate. The TSV includes an insulation layer, a barrier layer, a buffer layer and a conductive electrode. The insulation layer is disposed on the surface of the via. The barrier layer is disposed on the surface of the insulation layer. The conductive electrode is disposed on the surface of the buffer layer and filled with the via. The buffer layer further covers on a surface of the conductive electrode at the side of the second surface. The present invention further discloses a method of forming the TSV.

Description

Tantalum through electrode and method of forming same

The present invention relates to a crucible through electrode and a method of fabricating the same, and more particularly to a crucible through electrode having a buffer layer and a method of fabricating the same.

In the modern information society, microprocessor systems consisting of integrated circuits (ICs) have long been used in all aspects of life, such as home appliances, mobile devices, personal computers, etc. There is a trace of the integrated circuit. With the increasing advancement of technology and the imagination of human society for electronic products, the integrated circuit has also developed in the direction of more yuan, more precision and smaller.

Generally, an integrated circuit is formed by a die produced in a conventional semiconductor process. The process of fabricating a die begins with the production of a wafer: first, a plurality of regions are distinguished on a wafer, and in each region, through various semiconductor processes such as deposition, lithography, etching, or flattening. The steps to form various required circuit paths, and then, the respective regions on the wafer are cut into individual chips, packaged into chips, and finally the wafer is electrically connected to a circuit board. Such as a printed circuit board (PCB), after the chip is electrically connected to the pins of the printed circuit board, a variety of stylized processing can be performed.

In order to improve the function and performance of the wafer and increase the degree of integration to accommodate more semiconductor components in a limited space, the related manufacturers have developed a number of semiconductor wafer stacking technologies, including flip chip technology (Flip-Chip) technology, multi-chip package ( Multi-chip Package (MCP) technology, package on package (PoP) technology, package in package (PiP) technology, etc., can be increased by stacking wafers or packages between each other. The degree of integration of semiconductor components per unit volume. Under the above various package architectures, a technique called a through silicon via (TSV) technology has been developed in recent years to facilitate internal interconnection of wafers in a package to improve stacking efficiency. Further advancement. However, since the tantalum penetration electrode generally uses copper as a main material, its coefficient of thermal expansion or response to stress and the substrate having defects are quite different, and many problems are easily caused.

The present invention thus proposes a crucible through electrode, particularly a crucible through electrode having a buffer layer, which provides a buffering function between the conductive electrode and the substrate.

According to an embodiment of the invention, the invention discloses a crucible through electrode. The cymbal through electrode is disposed in a substrate having a through hole penetrating through the first surface of the substrate and a second surface. The through electrode includes an insulating layer, a barrier layer, a buffer layer, and a conductive electrode. The insulating layer is disposed on the surface of the through hole. The barrier layer is disposed on the surface of the insulating layer. The buffer layer is disposed on the surface of the barrier layer. The conductive electrode is disposed on the surface of the buffer layer and fills the through hole, wherein the buffer layer also covers the surface of the conductive electrode on the side of the second surface.

According to an embodiment of the present invention, the present invention also provides a method of forming a ruthenium through electrode. A substrate is provided having a first surface and a second surface relative to one of the first surfaces. An opening is then formed on the first surface of the substrate, and an insulating layer is formed on the surface of the opening. A barrier layer is then formed on the surface of the insulating layer, and a buffer layer is formed on the surface of the barrier layer. A conductive electrode is then formed on the surface of the buffer layer, and the conductive electrode fills the opening. Finally, a planarization process is performed on the second surface of the substrate, and the buffer layer is used as a stop layer.

According to another embodiment of the present invention, the present invention also provides another method of forming a tantalum penetration electrode. A substrate is first provided having a first surface and a second surface relative to one of the first surfaces. A dielectric layer is then formed on the first surface of the substrate and an opening is formed in the dielectric layer and the substrate. Next, an insulating layer is formed on the surface of the opening, and a contact hole is formed in the insulating layer and the dielectric layer. A buffer layer is then formed on the substrate, the buffer layer fills the contact hole and is formed along the surface of the insulating layer in the opening, wherein the buffer layer in the contact hole forms a contact plug. A conductive electrode is then formed on the surface of the buffer layer, and the conductive electrode fills the opening. Finally, a planarization process is performed on the second surface of the substrate to expose the buffer layer.

Since the ruthenium-through electrode of the present invention provides a barrier layer-bonding buffer layer design, it can provide not only a good buffering effect between the conductive electrode and the ruthenium substrate, but also a high conductivity.

In order to make the present invention more familiar to those skilled in the art to which the present invention belongs, the following is a list of preferred embodiments of the present invention, and in conjunction with the drawings, the composition of the creation and the desired The effect.

Please refer to FIG. 1 to FIG. 9 , which are schematic diagrams showing a method for fabricating a tantalum penetration electrode according to the present invention. As shown in Fig. 1, a substrate 300 is first provided. Substrate 300 can be monocrystalline silicon, gallium arsenide (GaAs), or other materials well known in the art. The substrate 300 has a first surface 302 and a second surface 304 opposite to the first surface 302. In one embodiment of the invention, substrate 300 has a thickness of substantially 700 to 1000 micrometers. Next, an opening 306 is formed in the first surface 302 of the substrate 300, such as by dry etching. The opening 306 has a pore size of about 5 to 10 microns and a depth of about 50 to 100 microns, but the method of forming the opening 306 and the embodiment are not limited thereto, and the product may be adjusted differently.

As shown in FIG. 2, an insulating layer 308 is formed over the first surface 302 of the substrate 300 and covers at least the surface of the opening 306. The insulating layer 308 may comprise various insulating materials such as cerium oxide (SiO ₂ ). The thickness of the insulating layer 308 is generally between 0.5 and 1.5 microns, preferably 1 micron. Next, a barrier layer 310 is formed on the insulating layer 308. The barrier layer 310 is formed at least along the surface of the insulating layer 308 in the opening 306. The material of the barrier layer 310 is, for example, titanium/titanium nitride (Ti/TiN) or tantalum/tantalum nitride (Ta/TaN), but is not limited thereto. The barrier layer 310 has a thickness generally between 0.005 and 0.02 microns, preferably between 0.01 and 0.02 microns.

As shown in FIG. 3, a buffer layer 312 is formed on the barrier layer 310. The buffer layer 312 is formed at least along the surface of the barrier layer 310 in the opening 306. In a preferred embodiment of the invention, the buffer layer 312 is made of metallic tungsten and has a thickness generally between 0.05 and 0.2 microns, preferably 0.1 microns.

As shown in FIG. 4, a conductive electrode layer 314 is formed on the buffer layer 312. The formation is performed, for example, through an electroplating process. A conductive electrode layer 314 is formed on the first surface 302 of the substrate 300 and fills the opening 306. In a preferred embodiment of the invention, the conductive electrode layer 314 is, for example, a metal copper, and the conductive electrode layer 314 is located in the opening 306 to a thickness of substantially 10 microns.

As shown in FIG. 5, a planarization process is performed on the first surface 302 of the substrate 300. For example, the conductive electrode layer 314 of the first surface 302 may be removed by a chemical mechanical polish (CMP) process or an etch back process, and the buffer layer 312 is used as a stop layer, so that the conductive electrode layer 314 and the buffer layer Layer 312 is flush. As a result, the conductive electrode layer 314 located in the opening 306 forms a conductive electrode 316.

As shown in FIG. 6, another planarization process is performed on the first surface 302 of the substrate 300 to remove the buffer layer 312 and the barrier layer 310 outside the opening 306. Removing the buffer layer 312 and the barrier layer 310 may be performed in the same planarization step or two planarization steps, for example, removing the buffer layer 312 by a chemical mechanical polishing process, and then removing the barrier layer 310 by etch-back etching. . In a preferred embodiment of the invention, the insulating layer 308 may be retained, while in another embodiment, the insulating layer 308 may also be selectively removed.

As shown in FIG. 7, a redistribution layer (RDL) 318 and a bumper 320 are formed on the first surface 302 of the substrate 300. The redistribution layer 318 and the pad layer 320 are electrically connected. The conductive electrode 316 is used as a path for electrically connecting the conductive electrode 316 and other signals.

As shown in FIG. 8, a planarization process is performed on the second surface 304 of the substrate 300. One feature of the present invention is that the planarization process uses the buffer layer 312 as a stop layer, that is, the planarization process removes a portion of the substrate 300 and a portion of the insulating layer 308 from the second surface 304 of the substrate 300. And a portion of the barrier layer 310, but does not remove and expose the conductive electrode 316. In an embodiment of the present invention, another insulating layer 324, a redistribution layer 326, and a pad layer 328 may be formed on the second surface 304 of the substrate 300 to be electrically connected to the 矽 through electrode 322. The buffer layer 312 on the two surfaces 304 is as shown in FIG.

The above-described embodiment of the tantalum through electrode process is described by a frontside via-last technique, that is, a front-end-of-line (FEOL) and a back-end process (Back) in a conventional IC process. After the completion of the -End-of-Line, BEOL, the desired opening 306 is formed by laser or etching, and then the insulating layer 308, the barrier layer 310, the buffer layer 312, and the conductive electrode 316 are sequentially filled, and finally flattened. The redistribution layer 318 and the pad layer 320 electrically connected to the conductive electrode 316 are formed and formed. In addition, the present invention can also be applied to the implementation of the via middle method, that is, the tantalum through electrode 322 is introduced between the front-end process and the back-end process of the conventional IC process, eliminating the redistribution layer 318 and the pad. After the fabrication of the layer 320 is completed, a post-process (BEOL) of the semiconductor is performed, such as forming a metal interconnect or a contact pad, to connect the TSV with the wiring of the back-end process. To the component and signal source. Furthermore, the present invention can also be applied to a backside via-last technique without limitation.

Referring again to FIG. 8, the present invention provides a structure of a crucible through electrode 322. The through electrode 322 is disposed in the opening 306 of the substrate 300 (in this step, the opening 306 has penetrated the first surface 302 and the second surface 304 to form a via opening 307). The through electrode 322 includes an insulating layer 308, a barrier layer 310, a buffer layer 312, and a conductive electrode 316. The insulating layer 308 is disposed on the surface of the through hole 307. The barrier layer 310 is disposed on the surface of the insulating layer 312. The buffer layer 312 is disposed on the surface of the barrier layer 310. The conductive electrode 316 is disposed on the surface of the buffer layer 312 and fills the through hole 307. One feature of the present invention is that the buffer layer 312 overlies the surface of the conductive electrode 316 on the side of the second surface 304 and is flush with the second surface 304 such that the conductive electrode 316 is not exposed to the second surface 304.

The present invention provides a number of advantages due to the provision of a buffer layer 312 having metal tungsten between the conductive electrode 316 and the substrate 300. For example, the coefficient of thermal expansion (CTE) of tantalum is about 2.3 ppm/K, the coefficient of thermal expansion of tungsten is about 4.4 ppm/K, and the coefficient of thermal expansion of copper is about 17 ppm/K, so it has a buffer of tungsten. The layer 312 can avoid the problem that cracks occur between the conductive electrode 316 having copper and the substrate 300 having germanium due to excessive difference in thermal expansion coefficient. In addition, the Young's Modulus of tantalum is about 130 GPa, the Young's modulus of tungsten is about 400 GPa, and the Young's modulus of copper is about 110 GPa, so tungsten with a high Young's modulus can also protect the conductive electrode 316. . On the other hand, the buffer layer 312 is also disposed on the surface of the conductive electrode 316 on the side of the second surface 304, and the substrate 300 may be prevented from contaminating the conductive electrode 316 in a subsequent process. It should be noted that the materials of the foregoing conductive electrodes 316 and the buffer layer 312 are exemplified by copper and tungsten. However, those skilled in the art should understand that the buffer layer 312 may also be other materials matching the conductive electrodes 316 and the substrate 300. The material can be adjusted according to the material of the conductive electrode 316 or the substrate 300.

In another aspect, the present invention also provides a barrier layer 310 to increase the adhesion of the buffer layer 312 or the conductive electrode 316 to the insulating layer 308. However, since the material of the barrier layer 310 is titanium/titanium nitride, the Young's modulus is only about 115 GPa. Compared with the buffer layer 312, only the barrier layer 310 does not provide sufficient protection for the buffering function. The thick barrier layer 310 reduces the conductivity of the tantalum through electrode 322. Therefore, the through-electrode 322 of the present invention has a design of the barrier layer 310 and the buffer layer 312, and can provide not only a good buffering effect for the conductive electrode 316 but also a high conductivity. In a preferred embodiment of the present invention, the ratio of the thickness of the buffer layer 312 to the thickness of the conductive electrode 316 is substantially greater than 0.001, preferably between 0.01 and 1, and the thickness of the barrier layer 310 and the thickness of the conductive electrode 316. The ratio is substantially between 0.001 and 0.01.

In another embodiment of the present invention, the enthalpy through electrode of the present invention can also be combined with the prior art of a contact via process in the middle drilling process. Please refer to FIG. 10 to FIG. 15 , which are schematic diagrams showing the steps of a method for forming a ruthenium through electrode according to the present invention. As shown in Fig. 10, a substrate 400 is first provided. The substrate 400 can be a single crystal germanium, gallium arsenide or other materials well known in the art. The substrate 400 has a first surface 402 and a second surface 404 disposed opposite the first surface 402. In one embodiment of the invention, the substrate 400 has a thickness of substantially 700 to 1000 microns. A semiconductor component, such as a metal oxide semiconductor (MOS) 502, is then formed over the first surface 402 of the substrate 400. In one embodiment, the MOS 502 can include a gate 504, a gate oxide layer 506, a sidewall spacer 508, and a source/drain region 510, the structure of which is well known to those of ordinary skill in the art. I will not repeat them here. It should be noted, however, that the MOS 502 of the present embodiment may also include other components such as a metal salicide or an epitaxial layer. In addition, the semiconductor device of the present invention is not limited to a metal oxide semiconductor, and may be other kinds of semiconductor components, such as various planar transistors, non-planar transistors, capacitors, thin film transistors, or even photosensitive elements, optical transmission elements. Or it is a micro-electrical mechanical system (MEMS), etc., and is not limited to the above. Next, a dielectric layer 512 is formed on the substrate 400, and the dielectric layer 512 is overlaid on the MOS 502. Dielectric layer 512 can comprise germanium dioxide or other suitable insulating material. Thereafter, an opening 406 is formed in the dielectric layer 512 and the substrate 400. The opening 406 is further formed in the substrate 400 through the dielectric layer 512. In one embodiment, the opening 406 has a pore size of about 5 to 10 microns and a depth of about 50 to 100 microns. The manner in which the opening 406 is formed is, for example, a dry etching step. However, the method of forming the opening 406 and the embodiment are not limited thereto, and the product may be adjusted differently.

As shown in FIG. 11, an insulating layer 408 is entirely formed on the substrate 400. An insulating layer 408 is formed on the surface of the dielectric layer 512 and is conformally formed along the surface of the opening 406, but does not fill the opening 406. The insulating layer 408 may comprise various insulating materials such as cerium oxide (SiO ₂ ). The thickness of the insulating layer 408 is generally between 0.5 and 1.5 microns, preferably 1 micron.

As shown in FIG. 12, at least one contact hole 410 is then formed in the insulating layer 408 and the dielectric layer 512 to expose portions of the MOS 502, such as the gate 504 and the source/drain region 510. . Then, a buffer layer 412 is formed on the substrate 400. The buffer layer 412 is formed along the surface of the insulating layer 412 and fills the contact hole 410, and conformally forms along the surface of the insulating layer 408 in the opening 406. But will not fill the opening 406. In a preferred embodiment, the buffer layer 412 is made of metal tungsten and has a thickness of substantially 0.05 to 0.2 μm, preferably 0.1 μm. Since the buffer layer 412 is made of a metal tungsten material, the buffer layer 412 located in the contact hole 410 forms a contact via 411 in a subsequent step, and the buffer layer 412 in the opening 406 is used. A buffer material between the conductive electrode layer (for example, a copper electrode) and the insulating layer 408 in the through electrode.

As shown in FIG. 13, a conductive electrode layer 414 is formed on the buffer layer 412. The formation is performed, for example, through an electroplating process. A conductive electrode layer 414 is formed on the first surface 402 of the substrate 400 and fills the opening 406. In a preferred embodiment of the invention, the conductive electrode layer 414 is, for example, metallic copper, and the conductive electrode layer 414 is located in the opening 406 to a thickness of substantially 10 microns.

As shown in FIG. 14, a planarization process is performed on the first surface 402 of the substrate 400 to remove the buffer layer 412 and the conductive electrode layer 414 on the insulating layer 408. That is, this planarization step is performed with the insulating layer 408 as a stop layer. The removal of the conductive electrode layer 414 and the buffer layer 412 may be performed in the same planarization step or in the planarization step of two separate steps, for example, removing the conductive electrode layer 414 by a chemical mechanical polishing process, and then removing the buffer layer by etchback. 412. In the preferred embodiment of the present invention, the insulating layer 408 may be left. In another embodiment, the insulating layer 408 and the partial buffer layer 412 and the conductive electrode in the insulating layer 408 may be selectively removed. Layer 414.

As shown in FIG. 15, a metal interconnect system 516 is formed on the dielectric layer 512 of the substrate 400 to be electrically connected to the contact plug 411. Metal interconnect system 516 includes, for example, a plurality of layers of metal layers (not shown) and a plurality of layers of dielectric layers (not shown). Finally, a planarization process is performed on the second surface 404 of the substrate 400. In the present embodiment, the planarization process uses the buffer layer 412 as a stop layer, that is, the planarization process exposes the buffer layer 412. In another embodiment, the planarization process is performed by using the conductive electrode layer 414 as a stop layer, that is, the planarization process exposes the conductive electrode layer 414. In addition, in another embodiment, the step of forming the metal interconnecting system 516 may be intermodulated with the planarization process of the second surface 404. For example, after the planarization process of the second surface 404 is performed, a metal interconnect is formed. Line system 516. Through the above steps, the fabrication of the tantalum penetration electrode 422 in this embodiment is completed.

In the conventional flow, the contact plug and the tantalum through electrode are formed separately, and an additional planarization stop layer, an additional barrier layer (for example, a Ti/TiN layer) is required to form the tantalum through electrode. One of the features of this embodiment is that the buffer layer 412 of metal tungsten is used to simultaneously form the buffer material in the contact plug 411 and the 矽-through electrode, which can save manufacturing cost and time compared with the flow formed by the conventional two. . Moreover, the buffer layer 412 of the present embodiment can also have a barrier effect between the conductive electrode layer 414 and the insulating layer 408, so that the step of additionally forming a barrier layer can be omitted. On the other hand, when the first surface 402 of the substrate 400 is subjected to a planarization process, the insulating layer 408 is used as a stop layer, which can provide a good stop layer effect. It can be seen that the step of forming the contact plug and the 矽 through electrode separately from the conventional one is simpler and more efficient in productivity.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

300,400. . . Base

302,402. . . First surface

304,404. . . Second surface

306,406. . . Opening

307. . . Through hole

308,408. . . Insulation

310. . . Barrier layer

312,412. . . The buffer layer

314,414. . . Conductive electrode layer

316. . . Conductive electrode

318. . . Redistribution

320. . . Pad layer

322,422. . .矽through electrode

324. . . Insulation

326. . . Redistribution

328. . . Pad layer

410. . . Contact hole

411. . . Contact plug

502. . . Gold oxide semiconductor

504. . . Gate

506. . . Gate dielectric layer

508. . . Side wall

510. . . Source/bungee area

512. . . Dielectric layer

516. . . Metal interconnect system

1 to 9 are schematic views showing a method of fabricating a tantalum penetration electrode of the present invention.

10 to 15 are schematic views showing the steps of another method of forming a ruthenium-through electrode of the present invention.

300. . . Base

302. . . First surface

304. . . Second surface

306. . . Opening

307. . . Through hole

308. . . Insulation

310. . . Barrier layer

312. . . The buffer layer

316. . . Conductive electrode

318. . . Redistribution

320. . . Pad layer

322. . .矽through electrode

Claims (15)

A through silicon via (TSV) is disposed in a substrate having a via opening extending through a first surface of the substrate and a second surface, wherein the through electrode comprises: an insulation a layer is disposed on the surface of the through hole; a barrier layer is disposed on the surface of the insulating layer; a buffer layer is disposed on the surface of the barrier layer; and a conductive electrode is disposed on the surface of the buffer layer and fills the through hole Wherein the buffer layer is also overlaid on a surface of the conductive electrode on a side of the second surface. A crucible through electrode as described in claim 1, wherein the buffer layer comprises tungsten (W). A tantalum penetration electrode according to claim 1, wherein a ratio of a thickness of the buffer layer to a thickness of the conductive electrode is substantially between 0.01 and 1. A ruthenium-through electrode according to claim 1, wherein the barrier layer comprises titanium/titanium nitride (Ti/TiN) or tantalum/tantalum nitride (Ta/TaN). A tantalum penetration electrode according to claim 1, wherein a ratio of a thickness of the barrier layer to a thickness of the conductive electrode is substantially between 0.001 and 0.01. A method of forming a tantalum through electrode, comprising: providing a substrate having a first surface and a second surface opposite the first surface; forming an opening in the substrate from the first surface; Forming an insulating layer on the surface of the hole; forming a barrier layer on the surface of the insulating layer; forming a buffer layer on the surface of the barrier layer; forming a conductive electrode layer on the surface of the buffer layer, the conductive layer The electrode layer fills the opening; and the planarizing process is performed on the second surface of the substrate, and the buffer layer is used as a stopping layer. The method for forming a ruthenium-through electrode according to the first aspect of the invention, after the forming the conductive electrode layer, further comprising performing a first planarization process on the first surface of the substrate to remove the opening The conductive electrode layer. The method for forming a 矽-through electrode according to claim 8 , after performing the first planarization process, further comprising performing a second planarization process on the first surface of the substrate to remove the The buffer layer other than the opening. A method of forming a ruthenium through electrode as described in claim 1, wherein the buffer layer comprises tungsten. A ruthenium-through electrode according to claim 1, wherein the barrier layer comprises titanium/titanium nitride or tantalum/niobium nitride. A method of forming a tantalum through electrode, comprising: providing a substrate having a first surface and a second surface opposite to the first surface; forming a dielectric layer on the first surface of the substrate; Forming an opening in the dielectric layer and the substrate; forming an insulating layer on the surface of the opening; forming a contact hole in the insulating layer and the dielectric layer; forming a buffer layer on the substrate, the buffer The layer fills the contact hole and is formed along the surface of the insulating layer in the opening, wherein the buffer layer in the contact hole forms a contact plug; and a conductive electrode layer is formed on the surface of the buffer layer And the conductive electrode layer fills the opening; and the planarizing process is performed on the second surface of the substrate to expose the buffer layer. The method for forming a ruthenium-through electrode according to claim 11, wherein after forming the conductive electrode layer, further comprising performing a first planarization process on the first surface of the substrate. A method of forming a tantalum penetration electrode according to claim 12, wherein the first planarization process is such that the insulating layer is a stop layer. A method of forming a tantalum penetration electrode according to claim 11, wherein the buffer layer comprises tungsten. A method of forming a tantalum through electrode according to claim 11, further comprising forming a semiconductor component on the substrate, and the contact plug is electrically connected to a portion of the semiconductor component.