TW201325148A - Amplitude shift keying receiver - Google Patents

Abstract

An amplitude shift keying (ASK) receiver is proposed. The proposed receiver includes a coil, a rectifier and an ASK demodulator. The coil receives high frequency band (HF) signals, and respecitvley generates a first and a second time-varying signals from the HF signals at a first and a second output terminal thereof. The rectifier is connected to the coil, regulates the time-varying signals into the a direct-current (DC) power signal, and respectively generates a first time-varying control signal and a second time-varying control signal accroding to the time-varying signals and the DC power signal. Further, the ASK demodulator is connected to the rectifier, receives the DC power signal, the first and the second time-varying control signal, and uses the DC power signal as power source of the ASK demodulator. In addition, the ASK demodulator generates ASK demodulated data according to the first and the second time-varying control signal.

Description

Keyed shift receiver

The disclosure is directed to a keyed shifting (ASK) receiver.

At present, radio frequency identification (RFID) applied to implantable biomedical electronic devices, such as artificial heart, visual wafers and the like, can be basically divided into battery electronic devices and batteryless electronic devices. RFID technology without battery electronics requires external continuous supply of power, such as data signals sent via RFID readers to provide power to RFID implanted biomedical devices to maintain RFID implantable biomedical devices working normally. A prior art RFID receiver is a first processing path that extracts energy from a radio frequency signal transmitted by an RFID reader in parallel to a second processing path that performs keyed shift (ASK) demodulation using the same radio frequency signal.

Due to the limitation of the transmission field coupling characteristics of the induction coil of the RFID implanted biomedical electronic device (corresponding to the transmitting and receiving antenna of the RFID), the energy transmitted by the external transmitting end and the data carrier correspond to the distance between the transmitting end and the receiving end. Produces exponential decay. At the same time, the coupling factor (k) between the transmitting end and the receiving end of the implanted system is generally extremely low (<0.1), so it can be inferred that the energy consumption is very significant. The coupling factor (k) is affected by the size of the coil, the distance between the transmitting end and the receiving end, and the characteristics of the transmission medium. For example, if the electromagnetic signal received at the receiving end of the implanted body is depleted during the AC (AC)-DC (DC) conversion process, it will directly affect the current to be extracted on the power amplifier of the external transmitting end. Moreover, the current consumption level of the transmitting end generally varies from several hundred milliamperes to several amps, thereby causing a large attenuation of the energy efficiency of the overall RFID implanted biomedical electronic system.

Figure 1 is a schematic diagram showing the normalized transmit power value as a function of modulation depth. Referring to FIG. 1, the horizontal axis represents the modulation depth value m, and the vertical axis represents the normalized power of the corresponding transmitting end of the RFID implanted biomedical electronic device. It can be seen from FIG. 1 that the transmission power value of the transmitting end of the ASK (corresponding to the curve P _ASK ) decreases to a critical value as the modulation depth value m increases. Referring to the sub-picture of FIG. 1 , the digital signal is converted into ASK. As a result of the signal, the reference line ML is a case where the amplitude is 0, and the first amplitude value AL corresponding to the ASK signal corresponding to the logic signal “0” corresponds to a power sufficient for the RFID implanted biomedical electronic device to operate, and the logic signal” The second amplitude value BL corresponding to the corresponding ASK signal is to provide additional power consumption resulting from the difference of the first amplitude value AL.

2 is a schematic diagram of an amplitude modulation signal. The envelope waveform EN of the amplitude modulation signal has two kinds of amplitude values: an amplitude value A and an amplitude value B, and the modulation index value k is defined as the following equation (1).

Basically, when the value "1-m" approaches 0, the smaller the difference between the first amplitude value AL and the second amplitude value BL, the less the extra power consumption of the overall system, but the more difficult it is to restore the logic before modulation. signal. In other words, how to choose the low-modulation index value and the circuit complexity of the ASK demodulator is a problem to be solved in the field.

In addition, since the RFID implantable biomedical device is a human body and the radio frequency signal has poor penetration ability to the human body, most RFID implantable biomedical devices use a high frequency band (HF band) signal as a carrier signal for transmitting data. However, the carrier of the high-band signal requires a large capacitance value in the demodulation circuit of the receiving end to implement the filtering process. Generally, a large capacitance value requires a large circuit area, which in turn tends to result in high manufacturing cost, and is also disadvantageous for miniaturization of implanted biomedical electronic devices. Therefore, how to reduce the modulation index value of the ASK demodulator in the RFID implanted biomedical electronic device and reduce the overall circuit area of the ASK demodulator at the same time is indeed an important issue for the industry.

The demodulation circuit of the traditional ASK demodulator is designed separately from the power supply circuit, because the conventional ASK demodulation circuit cannot read the DC signal rectified and filtered by the power supply circuit, that is, the signal received by the induction coil needs to be separately transmitted to the power supply. The circuit generates power and transmits it to the demodulation circuit for demodulation processing, so the circuit of the conventional ASK demodulator is large and complicated.

The present disclosure proposes an exemplary embodiment of a keyed shift receiver. According to this exemplary embodiment, the proposed keyed shift receiver includes a coil, a rectifier, and a keyed shift demodulator. The coil receives the high frequency band signal and generates first and second time varying signals from the high frequency band signal to the first and second output ends of the coil, respectively. The rectifier is connected to the coil for rectifying the time-varying signals into power signals, and generates a first time-varying control signal and a second time-varying control signal according to the time-varying signals and the power signal respectively. In addition, a keyed shift demodulator is connected to the rectifier, receives the power signal and the first and second time varying control signals, and uses the power signal as the power supply of the keyed shift demodulator, and according to the first And the second time varying control signal generates keyed shifting demodulation variable data.

Several exemplary embodiments attached to the figures are described in detail below to describe the disclosure in further detail.

Some of the embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings. In fact, the various embodiments of the present disclosure can be embodied in many different forms and should not be construed as being limited to the embodiments set forth in the disclosure; rather, the embodiments are only provided so that the disclosure will be Legal requirements. The same reference numerals throughout the text represent the same elements.

The present disclosure proposes a keyed shifting (ASK) receiver that uses a rectifier to receive and rectify two relative sinusoidal signals (transmitted from a carrier signal transmitted from an RFID transmitting end) on an RFID receiving antenna coil to generate a rectified The power signal and the two time-varying signals, and then the ASK demodulator directly uses the power signal and the two time-varying signals to demodulate the data originally modulated in the RFID carrier signal, which can reduce the modulation index of the ASK demodulator. Value, and at the same time reduce the overall circuit area of the ASK receiver.

FIG. 3 is a functional block diagram of a keyed shift receiver according to an exemplary embodiment of the present disclosure. Referring to FIG. 3, the keyed shift receiver (hereinafter referred to as ASK receiver) 10 includes a coil 20, a rectifier 30 and an ASK demodulator 40.

The coil 20 is a receiving and transmitting antenna of the ASK receiver 10 and is used to receive a carrier signal transmitted by an RFID transmitting end (not shown). The coil 20 includes two output ends, which are a first output end 21 and a second output end 22, respectively. The coil 20 generates a first time-varying signal VCOILa from the first output by a carrier signal (or a HF band signal). The terminal 21 and the second time varying signal VCOILb are at the second output terminal 22. The rectifier 30 is connected to the coil 20 to receive the first time varying signal VCOILa and the second time varying signal VCOILb, respectively, and rectifies the first and second time varying signals to generate a power signal Vrecout, and simultaneously according to the first and second time varying signals. The first time varying control signal Vctrl1 and the second time varying control signal Vctrl2 are generated respectively with the power signal Vrecout. In addition, the power signal Vrecout is a DC power supply, and the power supply of the ASK demodulator 40 is provided.

The ASK demodulator 40 is connected to the rectifier 30, and the ASK demodulator 40 receives the power signal Vrecout of the rectifier 30 as its power supply, and simultaneously receives the first time varying control signal Vctrl1 and the second time varying control signal Vctrl2 output by the rectifier 30, And performing ASK demodulation processing on the first time varying control signal Vctrl1 and the second time varying control signal Vctrl2 according to the power signal Vrecout to generate the ASK demodulation variable data Demod. Since the ASK receiver 10 rectifies the two relative sinusoidal signals on the coil 20 by the rectifier 30, a power supply signal and a time-varying signal with ASK modulation are simultaneously generated and immediately subjected to ASK demodulation by the ASK demodulator 40. The ASK demodulation data Demod is changed, so that the conventional ASK demodulator directly draws the sine wave signal at both ends of the coil, does not require a large-area capacitor and reduces the high-pass or low-pass circuit, thereby reducing the ASK receiver or The overall circuit area of the ASK demodulator while reducing the circuit cost of the ASK receiver.

FIG. 4 is a functional block diagram of a rectifier according to an exemplary embodiment of the present disclosure. Referring to FIG. 4, in the circuit structure illustrated in FIG. 4, four active diodes include first, second, third, and fourth active diodes 31-34 and a capacitor CL, and The control signal judging circuit 35 constitutes a rectifier 30. This rectifier 30 is connected to the first output 21 and the second output 22 of the coil 20. The first end of the first active diode 31 is connected to the first output terminal 21, and the second end of the first active diode 31 is connected to the first end of the capacitor CL, and the second end of the capacitor CL is grounded. The control ends of the first active diode 31 and the second active diode 32 are simultaneously connected to the first time varying control signal Vctrl1, and the first end of the second active diode 32 is grounded, and the second active second The second end of the pole body 32 is coupled to the second output end 22.

Similarly, the first end of the third active diode 33 is connected to the second output terminal 22, and the second end of the third active diode 33 is connected to the first end of the capacitor CL. The control ends of the third active diode 33 and the fourth active diode 34 are simultaneously connected to the second time varying control signal Vctrl2, and the first end of the fourth active diode 34 is grounded, and the fourth active type II The second end of the pole body 34 is connected to the second output end 21.

The first to fourth active diodes 31 to 34 respectively rectify the two relative sinusoidal signals on the first output terminal 21 and the second output terminal 22 to generate a power signal Vrecout at the first end of the capacitor CL. The first and second active diodes 31, 32 receive the first time varying control signal Vctrl1, and the third and fourth active diodes 33, 34 receive the second time varying control signal Vctrl2. The rectifier 30 includes the control signal judging circuit 35, which is connected to the first output end 21 of the coil 20, the second output end 22, and the first end of the capacitor CL for receiving the signal on the first output end 21 (that is, a first time varying signal VCOILa), a signal on the second output terminal 22 (ie, the second time varying signal VCOILb), and a power supply signal Vrecout, and according to the first time varying signal VCOILa, the second time varying signal VCOILb, and the power signal Vrecout generates a first time varying control signal Vctrl1 or a second time varying control signal Vctrl2.

The manner in which the first time varying control signal Vctrl1 or the second time varying control signal Vctrl2 is generated is described below. When the control signal judging circuit 35 judges that the signal on the first output terminal 21 of the coil 20 (that is, the first time varying signal VCOILa) is greater than the power supply signal Vrecout, the control signal judging circuit 35 generates a set of first time varying control signals Vctrl1. Combination with the second time varying control signal Vctrl2 (this is a pulse signal for controlling the active diode that should be turned on), and outputs the first time varying control signal Vctrl1 to the first active diode 31 and the second The active diode 32 outputs a second time varying control signal Vctrl2 to the third active diode 33 and the fourth active diode 34. Meanwhile, the first time-varying control signal Vctrl1 turns on the first active diode 31 and the second active diode 32, and the second time-varying control signal Vctrl2 turns off the third active diode 33 and the fourth active The diode 34, the current flows from the first output terminal 21 of the coil 20 to the capacitor CL, the power supply signal Vrecout discharges the capacitor CL, and allows current to flow back to the coil 20 via the turned-on second active diode 32 via the ground plane. Second output terminal 22.

When the control signal judging circuit 35 judges that the signal on the second output terminal 22 of the coil 20 (that is, the second time varying signal VCOILb) is greater than the power source signal Vrecout, the control signal judging circuit 35 generates a set of second time varying control signals Vctrl2. Combination with the first time varying control signal Vctrl1 (this is a pulse signal for controlling the active diode that should be turned on), and outputs the second time varying control signal Vctrl2 to the third active diode 33 and the fourth The active diode 34 outputs a first time varying control signal Vctrl1 to the first active diode 31 and the second active diode 32. Meanwhile, the second time varying control signal Vctrl2 turns on the third active diode 33 and the fourth active diode 34, and the first time varying control signal Vctrl1 turns off the first active diode 31 and the second active The diode 32, the current flows from the second output terminal VCOILb of the coil 20 to the capacitor CL, the power signal Vrecout discharges the capacitor CL, and the current is returned to the first output via the turned-on fourth active diode 34 via the ground plane. End 21.

In addition, when the control signal determining circuit 35 determines that the first time varying signal VCOILa is smaller than the power signal Vrecout and the second time varying signal VCOILb is smaller than the power signal Vrecout, the control signal determining circuit 35 does not generate any pulse signal for turning on the charging path at the first time. The control signal Vctrl1 or the second time varying control signal Vctrl2 is changed, so that the power supply signal Vrecout charges the capacitor CL.

FIG. 5 is a functional block diagram of another rectifier according to an exemplary embodiment of the disclosure. Referring to the circuit structure illustrated in FIG. 5, circuit elements other than the coil 20 constitute a rectifier 30. The rectifier 30 includes a P-type transistor P1, a P-type transistor Paux1, a P-type transistor Paux2, a P-type transistor P2, a P-type transistor Paux3, a P-type transistor Paux4, a capacitor CL, a switching unit 51, and a switching unit 52.

The function of the constituent circuits of the P-type transistor P1, the P-type transistor Paux1, and the P-type transistor Paux2 is similar to that of the third active diode 33 shown in FIG. The function of the constituent circuits of the P-type transistor P2, the P-type transistor Paux3, and the P-type transistor Paux4 is similar to that of the first active diode 31 shown in FIG. The function of the switch unit 51 is similar to that of the fourth active diode 34 and the partial control signal judging circuit 35 shown in FIG. The function of the switch unit 52 is similar to that of the second active diode 32 and the partial control signal judging circuit 35 shown in FIG.

A control terminal (eg, a gate) of the P-type transistor P1 is coupled to the second output terminal 22 of the coil 20 to receive a second time-varying signal VCOILb, and a first end (eg, a source) of the P-type transistor P1 is coupled to The first output end 21 of the coil 20, the second end of the P-type transistor P1 (eg, the drain) is connected to the first end of the capacitor CL, and the third end of the P-type transistor P1 (eg, the substrate) A substrate connected to the P-type transistor Paux1 and the P-type transistor Paux2. The second end of the capacitor CL is grounded.

A control terminal (eg, a gate) of the P-type transistor Paux1 is coupled to a first end of the capacitor CL, and a first end (eg, a source) of the P-type transistor Paux1 is coupled to the first output terminal 21 of the coil 20 for reception The first time varying signal VCOILa, the second end (eg, the drain) of the P-type transistor Paux1 is coupled to the third end (eg, the substrate) of the P-type transistor Paux1.

A control terminal (eg, a gate) of the P-type transistor Paux2 is coupled to the first output terminal 21 of the coil 20, and a first end (eg, a drain) of the P-type transistor Paux2 is coupled to the first end of the capacitor CL, and A second end (eg, a source) of the P-type transistor Paux2 is coupled to a third end (eg, a substrate) of the P-type transistor Paux2.

A control terminal (eg, a gate) of the P-type transistor P2 is coupled to the first output terminal 21 of the coil 20 to receive a first time varying signal VCOILa, and a first end (eg, a source) of the P-type transistor P2 is coupled to The second output end 22 of the coil 20, the second end of the P-type transistor P2 (eg, the drain) is connected to the first end of the capacitor CL, and the third end (eg, the substrate) of the P-type transistor P2 is connected to A substrate of a P-type transistor Paux3 and a P-type transistor Paux4.

A control terminal (eg, a gate) of the P-type transistor Paux3 is coupled to a first end of the capacitor CL, and a first end (eg, a source) of the P-type transistor Paux3 is coupled to the second output terminal 22 of the coil 20 for reception The second time varying signal VCOILb, the second end (eg, the drain) of the P-type transistor Paux3 is connected to the third end (eg, the substrate) of the P-type transistor Paux3.

A control terminal (eg, a gate) of the P-type transistor Paux4 is coupled to the second output terminal 22 of the coil 20, and a first end (eg, a drain) of the P-type transistor Paux4 is coupled to the first end of the capacitor CL, and A second end (eg, a source) of the P-type transistor Paux4 is coupled to a third end (eg, a substrate) of the P-type transistor Paux4.

The switching unit 51 includes a comparator 53 and an N-type transistor N2. The second terminal of the P-type transistor P1 outputs a bias voltage to the control terminal of the P-type transistor Paux1 and the comparator 53, and the first input terminal (for example, an inverting input terminal) of the comparator 53 is connected. At a first end of the capacitor CL, a second input (eg, a non-inverting input terminal) of the comparator 53 is coupled to the second output 22 of the coil 20. A control terminal (eg, a gate) of the N-type transistor N2 is coupled to an output terminal of the comparator 53, and a first end (eg, a source) of the N-type transistor N2 is coupled to the first output terminal 21 of the coil 20, and The second end (eg, the drain) of the N-type transistor N2 is grounded at the same time as its third end (eg, the substrate).

The switching unit 52 includes a comparator 54 and an N-type transistor N1. The second terminal of the P-type transistor P2 outputs a bias voltage to the control terminal of the P-type transistor Paux4 and the comparator 54, and the first input terminal (for example, the inverting input terminal) of the comparator 54 is connected to the capacitor CL. At one end, a second input (eg, a forward input) of comparator 54 is coupled to first output 21 of coil 20. A control terminal (eg, a gate) of the N-type transistor N1 is coupled to an output of the comparator 54, and a first end (eg, a source) of the N-type transistor N1 is coupled to the second output terminal 22 of the coil 20, and The second end (eg, the drain) of the N-type transistor N1 is grounded at the same time as its third end (eg, the substrate).

When P-type transistor P1, P-type transistor Paux1, P-type transistor Paux2, P-type transistor P2, P-type transistor Paux3, P-type transistor Paux4, capacitor CL, switching unit 51 and switching unit 52 operate as a whole, Rectifying the first time varying signal VCOILa and the second time varying signal VCOILb produces a power signal Vrecout at a first end of the capacitor CL. The comparator 54 simultaneously generates the first time varying control signal Vctrl1 according to the power signal Vrecout and the first time varying signal VCOILa, and outputs the first time varying control signal Vctrl1 to the control terminal of the N type transistor N1, so that the N type transistor N1 is simultaneously The capacitor is charged or discharged according to the power supply signal Vrecout according to the first time-varying control signal Vctrl1 and the second time-varying signal VCOILb being turned on or off.

Similarly, the comparator 53 simultaneously generates the second time varying control signal Vctrl2 according to the power signal Vrecout and the second time varying signal VCOILb, and outputs the second time varying control signal Vctrl2 to the control end of the N type transistor N2, so that the N type The transistor N2 is simultaneously turned on or off according to the first time varying control signal Vctrl1 and the first time varying signal VCOILa, thereby affecting the charging or discharging of the capacitor CL by the power signal Vrecout.

FIG. 6 is a functional block diagram of a keyed shift demodulator according to an exemplary embodiment of the present disclosure. Referring to FIG. 3, FIG. 5 and FIG. 6, the ASK demodulator 40 receives the power signal Vrecout as the power supply of the ASK demodulator 40 by the rectifier 30, and simultaneously receives the first time-varying control signal Vctrl1 and the first by the rectifier 30. The second time varying control signal Vctrl2 has been subjected to ASK demodulation processing in accordance with the power supply signal Vrecout, the first time varying control signal Vctrl1, and the second time varying control signal Vctrl2 to generate ASK demodulated variable data Demod.

In the present example, the ASK demodulator 40 includes a digital mixer 60 and a demodulation signal decision circuit 70. A digital mixer 60 is connected to the rectifier 30 for receiving the power signal Vrecout, the first time varying control signal Vctrl1 and the second time varying control signal Vctrl2, the power signal Vrecout, the first time varying control signal Vctrl1 and The second time varying control signal Vctrl2 performs a mixing process to generate a transient output signal out, and outputs the transient output signal out to the demodulation signal decision circuit 70.

The demodulation signal decision circuit 70 is connected to the rectifier 30 and the digital mixer 60 for receiving the power signal Vrecout by the rectifier 30 and the transient output signal out by the digital mixer 60, and according to the power signal Vrecout and the transient. The output signal out performs a judgment process to generate ASK demodulation data Demod.

FIG. 7 is a functional block diagram of a digital mixer according to an exemplary embodiment of the present disclosure. Referring to FIG. 5 and FIG. 7 , the digital mixer 60 can basically include a current source unit 82 , a signal processing unit 84 , and a reference voltage generator 80 . The reference voltage generator 80 is coupled to the rectifier 30, receives the power supply signal Vrecout and produces a bias voltage bias. However, the reference voltage generator 80 can be embodied in a number of different forms, the input of which can also be derived from the output of a voltage regulator. The current source unit 82 is coupled to the rectifier 30 and the reference voltage generator 80. The power supply signal Vrecout is received by the rectifier 30 and the bias voltage bias is received by the reference voltage generator 80 for generating an output current i to the signal processing unit 84. The signal processing unit 84 is connected to the rectifier 30 and the current source unit 82, and receives the first time varying control signal Vctrl1 and the second time varying control signal Vctrl2 by the rectifier 30, and receives the output current i by the current source unit 82, and according to the first time The variable control signal Vctrl1 and the second time varying control signal Vctrl2 generate a transient output signal out.

More clearly, in the present embodiment, the current source unit 82 includes a P-type transistor MPT, an N-type transistor MN3, a P-type transistor MP4, and a P-type transistor MP5.

The control terminal (for example, the gate) of the P-type transistor MPT is connected to a correction voltage Tune provided by an external circuit, and the correction voltage Tune performs fine adjustment of the current or output voltage to the current source unit 82 to compensate the current source unit 82 in the semiconductor. Process error in the process, when the process error is within the acceptable range, the control terminal of the P-type transistor MPT does not need to receive the correction voltage Tune. In addition, a first end (eg, a source) of the P-type transistor MPT is coupled to the rectifier 30 for receiving a power signal Vrecout.

The control terminal (for example, the gate) of the N-type transistor MN3 and the control terminal (for example, the gate) of the P-type transistor MP4 are simultaneously connected to a control signal LSKctrl provided by an external circuit, and the control signal LSKctrl is designed to achieve The backscattering of the modulation of the RFID signal is used, and the control signal LSKctrl may or may not be designed in the embodiment of the present invention if no backhaul is required. A first end (eg, a drain) of the N-type transistor MN3 is coupled to the reference voltage generator 80 to receive a bias voltage bias. A second end (eg, a source) of the N-type transistor MN3 is coupled to the control terminal of the P-type transistor MP5.

A first end (eg, a source) of the P-type transistor MP4 is coupled to the first end of the P-type transistor MPT. A second end (eg, a drain) of the P-type transistor MP4 is coupled to the control terminal of the P-type transistor MP5. A second end (eg, a drain) of the P-type transistor MPT is coupled to a first end (eg, a source) of the MP5, and a second end (eg, a drain) of the P-type transistor MP5 is coupled to the signal processing Unit 84. The P-type transistor MPT and the P-type transistor MP5 provide an output current i to the signal processing unit 84 from the power supply signal Vrecout.

The signal processing unit 84 equivalently provides a function similar to a NOR gate. The signal processing unit 84 is coupled to the rectifier 30 for receiving the first time varying control signal Vctrl1 and the second time varying control signal Vctrl2, and The first time varying control signal Vctrl1 and the second time varying control signal Vctrl2 generate a transient output signal out. More clearly, the signal processing unit 84 performs inverse or gate logic processing of the first time varying control signal Vctrl1 and the second time varying control signal Vctrl2 to generate a transient output signal if the current source unit 82 provides sufficient current. Out.

More clearly, in the present embodiment, the signal processing unit 84 includes a P-type transistor MP0, a P-type transistor MP1, an N-type transistor MN0, and an N-type transistor MN1. The control terminal (for example, the gate) of the P-type transistor MP0 and the control terminal (for example, the gate) of the N-type transistor MN0 are simultaneously connected to the rectifier 30 for receiving the first time-varying control signal Vctrl1. Similarly, the control terminal (eg, the gate) of the P-type transistor MP1 and the control terminal (eg, the gate) of the N-type transistor MN1 are simultaneously connected to the rectifier 30 for receiving the second time varying control signal Vctrl2. A first end (eg, a source) of the P-type transistor MP0 is coupled to the current source unit 82, and a second end (eg, a drain) of the P-type transistor MP0 is coupled to the first end of the P-type transistor MP1 (eg, , source). The N-type transistor MN0 is connected in parallel with the N-type transistor MN1 between the second end (eg, the drain) of the P-type transistor MP1 and the ground plane.

The P-type transistor MP0, the P-type transistor MP1, the N-type transistor MN0 and the N-type transistor MN1, according to the first time-varying control signal Vctrl1 and the second time-varying control signal Vctrl2, the first time-varying control signal Vctrl1 and the first The second time varying control signal Vctrl2 performs inverse or gate logic processing and generates a transient output signal out at the second end of the P-type transistor MP1.

However, the embodiments of the present disclosure are not limited to the embodiment of FIG. 7. In other embodiments of the present disclosure, the digital mixer 60 may further include a plurality of current source units connected in parallel between the power signal Vrecout and the signal processing unit 84. Used to provide a larger and adjustable output current to the signal processing unit 84 to increase the transient response of the logic "high" signal of the transient output signal out generated by the signal processing unit 84. When a plurality of current source units are connected in parallel between the power signal Vrecout and the signal processing unit 84, the transistor width and length of the P-type transistor MPT and the P-type transistor MP5 of each stage of the current source unit must be Before the parallel configuration, the transistor width-to-length ratio of the corresponding transistor of the primary current source unit is multiplied, and the output current is multiplied by the output current value of the primary current source unit before the parallel configuration.

FIG. 8 is a functional block diagram of a determination circuit according to an exemplary embodiment of the present disclosure. Referring to FIG. 3 and FIG. 5 to FIG. 8 simultaneously, the demodulation signal decision circuit 70 provides a function similar to a Schmitt trigger or a hysteresis comparator, and the demodulation signal decision circuit 70 is connected to the rectifier 30 and the signal processing unit. 84, for receiving the transient output signal out and the power signal Vrecout, the demodulation variable signal decision circuit 70 uses the power signal Vrecout as the power supply, and compares the transient output signal out with a preset threshold value, when the transient output When the signal out is less than the preset threshold, the logic "high" potential is output; when the transient output signal out is greater than the preset threshold, a logic "low" potential is output. In this way, the ASK demodulation variable data Demod is generated based on the transient output signal out and the power supply signal Vrecout.

More specifically, the demodulation signal decision circuit 70 includes a P-type transistor P80, a P-type transistor P81, an N-type transistor N80, an N-type transistor N81, a P-type transistor P82, and a P-type transistor C1, N. Type transistor N82, N type transistor D1.

A control terminal (for example, a gate) of the P-type transistor P80, the P-type transistor P81, the N-type transistor N80, and the N-type transistor N81 is connected to the signal processing unit 84 for receiving the transient output signal out. A first end (eg, a source) of the P-type transistor P80 is coupled to the rectifier 30 for receiving a power signal Vrecout, and a second end (eg, a drain) of the P-type transistor P80 is coupled to the P-type transistor P81. a first end (eg, a source); a second end (eg, a drain) of the P-type transistor P81 is coupled to the first end of the N-type transistor N81 (eg, a drain); the first of the N-type transistor N81 A second end (eg, a source) is coupled to a first end (eg, a drain) of the N-type transistor N80, and a second end (eg, a source) of the N-type transistor N80 is coupled to ground.

The P-type transistor P82 and the P-type transistor C1 are connected in parallel to the second end of the P-type transistor P80 and the ground plane. The control terminal (eg, the gate) of the P-type transistor C1 receives a control voltage DP1 provided by an external circuit for switching or adjusting the amount of current and directly affecting the aforementioned preset threshold. A first end (eg, a source) of the P-type transistor C1 is coupled to a second end of the P-type transistor P80, and a second end (eg, a drain) of the P-type transistor C1 is coupled to ground. A first end (eg, a source) of the P-type transistor P82 is connected to a second end of the P-type transistor P80, and a second end (eg, a drain) of the P-type transistor P82 is grounded, and the P-type transistor P82 The control terminal (eg, the gate) is connected to the second end of the P-type transistor P81.

The N-type transistor N82 and the N-type transistor D1 are connected in parallel to the second end of the N-type transistor N81 and the first end of the P-type transistor P0. The control terminal (eg, the gate) of the N-type transistor D1 receives a control voltage DN1 provided by an external circuit for switching or adjusting the amount of current and directly affecting the aforementioned preset threshold. A first end (eg, a drain) of the N-type transistor D1 is coupled to the second end of the N-type transistor N81, and a second end (eg, a drain) of the N-type transistor D1 is coupled to the rectifier 30 for Receive power signal Vrecout. A first end (eg, a drain) of the N-type transistor N82 is coupled to a second end of the N-type transistor N81, and a second end (eg, a source) of the N-type transistor N82 is coupled to the rectifier 30 for receiving The power signal Vrecout, and the control terminal (eg, the gate) of the N-type transistor N82 is connected to the second end of the P-type transistor P81.

The demodulation change signal decision circuit 70 generates the ASK demodulation variable data Demod at the second end of the P-type transistor P81 based on the control voltage DP1, the control voltage DN1, and the transient output signal out.

FIG. 9 is a timing diagram showing the operation of a keyed shift receiver according to an exemplary embodiment of the present disclosure. Referring to FIG. 3, FIG. 5, FIG. 6, and FIG. 9, the horizontal axis of the operation timing chart is time, and the unit of the vertical axis of each sub-picture is a voltage standard. From the top down, the sine wave signal Vab is the high frequency band signal actually received by the coil 20, and the sine wave signal Vab is the difference between the first time varying signal VCOILa and the second time varying signal VCOILb. From another point of view, the first time varying signal VCOILa is a time varying signal having an amplitude of the sine wave signal Vab greater than a reference potential (eg, 0 V), and the second time varying signal VCOILb is an amplitude of the sine wave signal Vab being greater than a reference potential The inverted signal of the time-varying signal.

The rectifier 30 rectifies the first time varying signal VCOILa and the second time varying signal VCOILb, respectively, to generate the power signal Vrecout to the ASK demodulator 40 (which includes the digital mixer 60 and the demodulation signal decision circuit 70) as an ASK tone The power supply of the converter 40 is simultaneously used as an input signal for the demodulation processing of the ASK modulator 40. The rectifier 30 also determines the condition that when the first time varying signal VCOILa > the power signal Vrecout, the rectifier 30 generates a first time varying control signal Vctrl1 (which is a pulse signal). Similarly, when the second time varying signal VCOILb > the power signal Vrecout, the rectifier 30 generates a second time varying control signal Vctrl2 (which is a pulse signal).

The digital mixer 60 receives the power signal Vrecout, the first time varying control signal Vctrl1 and the second time varying control signal Vctrl2, and uses the power signal Vrecout as the power supply, and the first time varying control signal Vctrl1 and the second time varying control signal. Vctrl2 performs inverse or gate logic processing to generate a transient output signal out. The ideal output value of the transient output signal out is a pulse signal, but since the transient response of the power supply is slow, it may appear as the waveform of FIG.

The demodulation signal modification circuit 70 functions as a hysteresis comparator, receives the power signal Vrecout and the transient output signal out, uses the power signal Vrecout as the power supply, and compares the transient output signal out with the preset threshold T. Threshold T. When the transient output signal out is less than the preset threshold T, the demodulation signal decision circuit 70 outputs the ASK demodulation variable Demod to a logic "high" potential; when the transient output signal out is greater than the preset threshold T, the solution The modulation signal decision circuit 70 outputs the ASK demodulation variable data Demod to a logic "low" potential.

FIG. 10 is a signal simulation diagram of a keyed shift receiver according to an exemplary embodiment of the present disclosure. Referring to FIG. 3, FIG. 5, FIG. 6, and FIG. 10, the vertical axis of FIG. 10 is voltage (V), and the horizontal axis is time (50 ns/div). 10 illustrates that the rectifier 30 rectifies the power signal Vrecout generated by the first time varying signal VCOILa and the second time varying signal VCOILb, respectively, and generates the first according to the power signal Vrecout, the first time varying signal VCOILa, and the second time varying signal VCOILb. A time varying control signal Vctrl1 and a second time varying control signal Vctrl2. The ASK demodulator 40 of the keyed shift receiver 10 of the present disclosure directly utilizes the first time varying control signal Vctrl1 and the second time varying control signal Vctrl2 generated by the rectifier 30 (as shown in FIG. 10) to be larger than the power signal. Part of the signal of Vrecout is used for ASK demodulation, so as to generate ASK demodulation data Demod. Since the first time varying control signal Vctrl1 and the second time varying control signal Vctrl2 are relatively larger than the power signal Vrecout, the partial signal of the low frequency modulation index value can be achieved.

In summary, according to various exemplary embodiments of the present disclosure, a keyed shift receiver and a demodulation method thereof are proposed. The keyed shift receiver proposed by the disclosure utilizes a rectifier as a processing circuit for extracting energy, and the rectifier directly outputs the extracted energy as an input signal of the keyed shift demodulator and the power supply, and is simultaneously subjected to a keyed shift solution. The modulator performs keyed shift and demodulation processing on the extracted energy to generate demodulated data. The demodulation circuit of the keyed shift receiver proposed in the present disclosure directly reads the rectified signal of the power supply, and can directly perform signal demodulation processing, and largely omits large capacitance or high pass or low pass in the conventional ASK demodulation circuit. The circuit reduces the overall area of the circuit, does not require additional parallel circuits for waveform envelope detection, and can achieve the effect of low-modulation index value and low overall circuit cost.

The present invention has been disclosed in the above embodiments, and is not intended to limit the present invention. Any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the disclosure. The scope of protection is subject to the definition of the scope of the patent application.

10. . . Keyed shift receiver

20. . . Coil

twenty one. . . First output

twenty two. . . Second output

30. . . Rectifier

31~34. . . Active diode

35. . . Control signal judgment circuit

40. . . Keyed shift demodulator

51, 52. . . Switch unit

53, 54, . . Comparators

60. . . Digital mixer

70. . . Demodulation signal decision circuit

80. . . Reference voltage generator

82. . . Power flow unit

84. . . Signal processing unit

A, B. . . Amplitude value

ASK. . . Keyed shift

AL. . . First amplitude value

BL. . . Second amplitude value

Bias. . . Bias voltage

C1, MPT, MP4, MP5, MP0, MP1, P1, P2, Paux1, Paux2, Paux3, Paux4, P80, P81, P82. . . P-type transistor

CL. . . Capacitor

D1, MN0, MN1, N1, N2, MN3, N80, N81, N82. . . N type transistor

Demod. . . Keyed shift demodulation variable data

DN1, DP1, LSKctrl. . . control signal

EN. . . Wave seal waveform

i . . . Current

k. . . Modulation index value

ML. . . Baseline

m. . . Modulation depth value

Out. . . Transient output signal

P _ASK . . . curve

T. . . Preset threshold

Tune. . . Correction voltage

VCOILa. . . First time-varying signal

VCOILb. . . Second time-varying signal

Vctrl1. . . First time varying control signal

Vctrl2. . . Second time varying control signal

Vrecout. . . Power signal

FIG. 1 is a schematic diagram showing a normalized transmission power value as a function of a modulation index value.

2 is a schematic diagram of an amplitude modulation signal.

FIG. 3 is a functional block diagram of a keyed shift receiver according to an exemplary embodiment of the present disclosure.

FIG. 4 is a functional block diagram of a coil and a rectifier of a keyed shift receiver according to an exemplary embodiment of the present disclosure.

FIG. 5 is a functional block diagram of another rectifier according to an exemplary embodiment of the disclosure.

FIG. 6 is a functional block diagram of a keyed shift demodulator according to an exemplary embodiment of the present disclosure.

FIG. 7 is a functional block diagram of a digital mixer according to an exemplary embodiment of the present disclosure.

FIG. 8 is a functional block diagram of a determination circuit according to an exemplary embodiment of the present disclosure.

FIG. 9 is a timing diagram showing the operation of a keyed shift receiver according to an exemplary embodiment of the present disclosure.

FIG. 10 is a signal simulation diagram of a keyed shift receiver according to an exemplary embodiment of the present disclosure.

10. . . Keyed shift receiver

20. . . Coil

30. . . Rectifier

40. . . Keyed shift demodulator

Demod. . . Keyed shift demodulation variable data

VCOILa. . . First time-varying signal

VCOILb. . . Second time-varying signal

Vctrl1. . . First time varying control signal

Vctrl2. . . Second time varying control signal

Vrecout. . . Power signal

Claims (11)

A keyed shift receiver includes: a coil for receiving a high frequency band signal, and a first time varying signal and a second time varying signal respectively generating a first output of the coil from the high frequency band signal And a second output end; a rectifier connected to the coil for rectifying the first and second time-varying signals into a power signal, and generating the signal according to the first and second time-varying signals and the power signal respectively a first time varying control signal and a second time varying control signal; and a keyed shift demodulator coupled to the rectifier, receiving the power signal and the first and second time varying control signals, utilizing the power source The signal is used as a power supply for the keyed shift demodulator, and generates a keyed shift demodulation variable data according to the first time varying control signal and the second time varying control signal. The keyed shift receiver according to claim 1, wherein the keyed shift demodulator comprises: a digital mixer connected to the rectifier to receive the power signal, the first time varying a control signal and a second time varying control signal, using the power signal as a power supply of the digital mixer, and generating a transient output signal according to the first time varying control signal and the second time varying control signal; and determining a circuit, connected to the rectifier and the digital mixer, receiving the power signal and the transient output signal, using the power signal as a power supply of the determining circuit, and generating the keyed shifting solution according to the transient output signal Modulate data. The keyed shift receiver of claim 1, wherein the rectifier comprises: a first P-type transistor, the first end of which is connected to the first output end of the coil, and the control end is connected The second end of the coil is connected to the first end of a capacitor, wherein the second end of the capacitor is grounded; a second P-type transistor has a control terminal connected to the capacitor The first end is connected to the first output end of the coil, and the second end is connected to the substrate of the first P-type transistor simultaneously with the substrate, and generates a first bias voltage; a third P The first end of the transistor is connected to the first end of the capacitor, and the second end is connected to the substrate of the first P-type transistor simultaneously with the substrate; a fourth P-type transistor is connected to the control terminal The first output end of the coil has a first end connected to the second output end of the coil, a second end connected to the first end of the capacitor, and a fifth P-type transistor connected to the control end a first end of the capacitor, the first end of which is coupled to the second output of the coil, The second end and the substrate are simultaneously connected to the substrate of the fourth P-type transistor, and generate a second bias voltage; a sixth P-type transistor, the first end of which is connected to the first end of the capacitor, and the second The end and the substrate are simultaneously connected to the substrate of the fourth P-type transistor, wherein the first, second, third, fourth, fifth, and sixth P-type transistors rectify the first and second time-varying signals to Generating the power signal to the first end of the capacitor; a first comparator having a first input coupled to the first end of the capacitor and a second input coupled to the second output of the coil and receiving The first bias voltage generates a second time varying control signal according to the second time varying signal and the power signal; a first N-type transistor whose control end is connected to the output of the first comparator for receiving The second time-varying control signal has a first end connected to the control end of the third P-type transistor, a second end of which is grounded to the substrate, and a second comparator whose first input is connected to the capacitor One end, the second input end of which is connected to the first output end of the coil, and receives The second bias voltage generates the first time varying control signal according to the first time varying signal and the power signal; and a second N-type transistor whose control end is connected to the output end of the first comparator Receiving the second time varying control signal, the first end thereof is connected to the control end of the sixth P-type transistor, and the second end thereof is grounded to the substrate. The keyed shift receiver of claim 1, wherein the rectifier is connected to a first output end and a second output end of the coil, the rectifier comprises: a capacitor; a first active type a diode, the control end of which is coupled to the first time varying control signal, the first end of which is coupled to the first output end of the coil, the second end of which is coupled to the first end of the capacitor, and the second end of the capacitor The second active diode is connected to the first time-varying control signal, and the first end is grounded, and the second end is connected to the second output end of the coil; An active diode is connected to the second time-varying control signal, the first end of which is connected to the second output end of the coil, and the second end of which is connected to the first end of the capacitor; The active diode has a control terminal connected to the second time varying control signal, the first end of which is grounded, the second end of which is connected to the second output end of the coil, and a control signal determining circuit connected to The first output of the coil and the second output The first end of the capacitor is configured to receive the first time varying signal, the second time varying signal, and the power signal, and generate the first according to the first time varying signal, the second time varying signal, and the power signal A time varying control signal or the second time varying control signal. The keyed shift receiver according to claim 4, wherein the control signal determining circuit determines that the first time varying signal is greater than the power signal, generating a set of the first time varying control signal and the second a combination of time varying control signals, and outputting the first time varying control signal to the first and second active diodes, and outputting the second time varying control signal to the third and fourth active diodes The first time varying control signal turns on the first and second active diodes, and the second time varying control signal turns off the third and the fourth active diodes, and the power signal will The capacitor discharges and causes a current to flow back through the grounded surface to the second output of the coil via the turned-on second active diode. The keyed shift receiver according to claim 4, wherein the control signal determining circuit determines that the second time varying signal is greater than the power signal, generating a set of the second time varying control signal and the first Combining a time varying control signal, and outputting the second time varying control signal to the third and fourth active diodes, outputting the first time varying control signal to the first and second active diodes a body, wherein the second time varying control signal turns on the third and fourth active diodes, and the first time varying control signal turns off the first and second active diodes, the power signal will The capacitor discharges and causes a current to flow back through the ground plane to the first output of the coil via the turned-on fourth active diode. The keyed shift receiver according to claim 4, wherein the control signal determining circuit determines that the first time varying signal and the second time varying signal are both smaller than the power signal, and the first time is not generated. The control signal or the second time varying control signal is changed, and the power signal charges the capacitor. The keyed shift receiver according to claim 2, wherein the digital mixer comprises: a reference voltage generator connected to the rectifier, receiving the power signal, and generating a bias voltage; a current source unit connected to the rectifier and the reference voltage generator, receiving the power signal and the bias voltage, generating an output current from the power signal according to the bias voltage; and a signal processing unit coupled to the rectifier The current source unit receives the output current, the first time varying control signal and the second time varying control signal, and generates the transient output signal according to the first time varying control signal and the second time varying control signal. The keyed shift receiver according to claim 2, wherein the determining circuit is a demodulation signal determining circuit, comprising: a first P-type transistor, the control end of which is connected to the digital mixing The wave device receives the transient output signal, and the first end is connected to the rectifier to receive the power signal; the second P-type transistor is connected to the digital mixer to receive the transient output signal, The first end is connected to the second end of the first P-type transistor; a first N-type transistor has a control end connected to the digital mixer to receive the transient output signal, the first end of which is connected to a second end of the second P-type transistor; a second N-type transistor having a control end connected to the digital mixer for receiving the transient output signal, the first end of which is coupled to the first N-type a second end of the crystal, the second end of which is grounded; a third P-type transistor, the control end receives a first control voltage, and the first end thereof is connected to the second end of the first P-type transistor, the first Two-terminal grounding; a fourth P-type transistor, the control end of which is connected to the second of the second P-type transistor a first end connected to the second end of the first P-type transistor, the second end of which is grounded; a third N-type transistor whose control end is connected to the second end of the second P-type transistor, The first end is connected to the second end of the first N-type transistor, the second end is connected to the digital mixer to receive the transient output signal, and the fourth N-type transistor is received by the control end a second control voltage, the first end of which is connected to the second end of the first N-type transistor, and the second end of which is connected to the digital mixer to receive the transient output signal, wherein the determining circuit generates the The keyed shift demodulation variable data is at the second end of the second P-type transistor. The keyed shift receiver of claim 8, wherein the current source unit comprises: a first P-type transistor, the control end is connected to a correction voltage, and the first end is connected to the rectifier Receiving the power signal; a second P-type transistor, the control end of which is connected to a control signal, the first end of which is connected to the first end of the first P-type transistor; and a third P-type transistor, The control end is connected to the second end of the second P-type transistor, the first end is connected to the second end of the first P-type transistor, and the second end is connected to the signal processing unit; an N-type transistor The control terminal receives the control signal, the first end thereof is connected to the reference voltage generator to receive the bias voltage, and the second end is connected to the control end of the third P-type transistor; and wherein the first The P-type transistor and the third P-type transistor generate the output current from the power signal and provide the output current to the signal processing unit. The keyed shift receiver of claim 8, wherein the signal processing unit comprises: a first P-type transistor, the control end of which is connected to the rectifier to receive the first time-varying control signal, The first end receives the current source unit; a second P-type transistor whose control end is connected to the rectifier to receive the second time varying control signal, the first end of which is connected to the first P-type transistor a second N-type transistor having a control terminal connected to the rectifier for receiving the first time-varying control signal, the first end of which is connected to the second end of the second P-type transistor, and the second end thereof Grounding; and a second N-type transistor having a control terminal connected to the rectifier for receiving the second time varying control signal, the first end of which is coupled to the second end of the second P-type transistor, and the second end thereof Grounding, wherein the signal processing unit generates the transient output signal at the second end of the second P-type transistor.