TW201325047A - DC-DC converter providing output voltage overshoot prevention - Google Patents

Abstract

A DC-DC converter for preventing output voltage overshoot is provided. The converter receives an input voltage to generate a regulated output voltage. In one embodiment of the present invention, the converter comprises an error amplifier, a compensation network, and a selection circuit. The error amplifier has a positive input terminal receiving a reference voltage, a negative input terminal receiving a feedback voltage correlated to the output voltage, and an output terminal supply an error voltage. The compensation network compensates the stability of the error amplifier, and the selection circuit connects the compensation network to the output terminal of the error amplifier selectively according to the voltage level of the error voltage. When the voltage level of the feedback voltage is less than that of the reference voltage, the compensation network disconnects to the output terminal of the error amplifier. When the voltage level of the feedback voltage is substantially equal to that of the reference voltage, the compensation network connects to the output terminal of the error amplifier.

Description

Voltage converter that suppresses output voltage overshoot

The present invention relates to a voltage converter that suppresses an output voltage overshoot condition.

A DC to DC voltage converter can be used to regulate an input voltage to a stable output voltage to supply the current required by the load. In general, the DC to DC voltage converter is divided into a boost converter, a buck converter, and a buck-boost voltage converter according to the input voltage and the output voltage value. Buck-boost converter). FIG. 1 is a schematic diagram showing the architecture of a typical boost voltage converter 10. Referring to FIG. 1 , the boost voltage converter 10 includes an input capacitor C _IN , an inductor L , two switches SW ₁ and SW ₂ , an output capacitor C _{OUT ,} and a control circuit 12 . The control circuit 12 is for providing two driving signals D ₁ and D ₂ for controlling the two switches SW ₁ and SW ₂ so that the switches SW ₁ and SW ₂ can be alternately turned on and off.

Referring to FIG. 1, the control circuit 12 includes an error amplifier 122, a compensation network 124, a comparator 126, and a Pulse Width Modulation (PWM) circuit 128. The boost voltage converter 10 further includes a voltage dividing circuit 14 for detecting a change in the output voltage V _OUT . The voltage dividing circuit 14 divides the output voltage V _OUT by two series resistors R ₁ and R ₂ to generate a corresponding feedback voltage V _FB . Then, based on the voltage difference between the reference voltage V _REF and the feedback voltage V _FB , the error amplifier 122 generates a corresponding output voltage V _E . The comparator 126 generates a pulse wave signal after comparing the output voltage V _E from the error amplifier 10 with a sawtooth wave signal V _SAW . The pulse signal is transmitted to the PWM circuit 128 to generate corresponding drive signals D ₁ and D ₂ . With the drive signals D ₁ and D ₂ are turned on or off switches SW ₂ and SW and the output voltage on the inductor L is charged or discharged, the voltage boost converter 10 can generate a stable load current and required _1.

To compensate for the stability of the error amplifier 122, the output of the error amplifier 122 is coupled to the compensation network 124 to compensate for the output voltage V _E . However, at the beginning of system startup, limited by the response time of the compensation network 124, the boost voltage converter 10 produces an output voltage overshoot condition. FIG. 2 is a waveform diagram of the boost voltage converter 10 when it is turned on. Referring to FIG. 2, at the initial stage of system startup (t<t _START ), since the output voltage V _E cannot reach a stable voltage level quickly, a considerable inductor current I _L is generated at the time of power-on, and the output voltage V _OUT There will be an overshoot. This overshoot voltage can cause damage to the load components.

Therefore, it is necessary to propose a voltage converter that can suppress the overshoot of the output voltage to solve the potential problem when the system is turned on.

It is an object of the present invention to provide a voltage converter that suppresses an output voltage overshoot condition for receiving an input voltage to regulate the generation of an output voltage.

To achieve the above objects, an embodiment of the voltage converter of the present invention includes an error amplifier, a compensation network, and a selection circuit. The error amplifier has a non-inverting input that receives a reference voltage, an inverting input that receives a feedback voltage associated with the output voltage, and an output that provides an error voltage. The compensation network is used to compensate for the stability of the error amplifier. The selection circuit is configured to selectively connect the compensation network to the output of the error amplifier based on a voltage level of the error voltage. In operation, when the voltage level of the feedback voltage is less than the voltage level of the reference voltage, the compensation network is not connected to the output terminal of the error amplifier, and when the voltage level of the feedback voltage is substantially equal to the The compensation circuit is coupled to the output of the error amplifier when the voltage level of the reference voltage is applied.

The direction discussed herein is a voltage converter for suppressing output voltage overshoot conditions. In order to fully understand the present invention, detailed steps and structures are set forth in the following description. Obviously, the implementation of the present invention is not limited to the specific details familiar to those skilled in the relevant art. On the other hand, well-known structures or steps are not described in detail to avoid unnecessarily limiting the invention. The preferred embodiments of the present invention are described in detail below, but the present invention may be widely practiced in other embodiments, and the scope of the present invention is not limited by the scope of the following patents. .

3 shows a block diagram of a voltage converter 30 that suppresses an output voltage overshoot condition in conjunction with an embodiment of the present invention. The voltage converter 30 is configured to receive an input voltage V _IN to adjust to generate an output voltage V _OUT . Referring to FIG. 3, the voltage converter 30 includes an input capacitor C ₁ , an inductor L ₁ , two switches SW _A and SW _B , an output capacitor C _{2 ,} and a control circuit 32 . The control circuit 32 is operative to provide two drive signals D _A and D _B that control the switches SW _A and SW ₂ such that the switches SW _A and SW _B can be alternately turned on and off.

Referring to FIG. 3, the control circuit 32 includes an error amplifier 322, a selection circuit 324, a comparator 326, and a PWM circuit 328. The error amplifier 322 has a non-inverting input that receives a reference voltage V _REF , an inverting input that receives an feedback voltage V _FB associated with the output voltage V _OUT , and an output that provides an error voltage V _EA . To compensate for the loop stability of the error amplifier 322, a compensation network 325 is coupled to the output of the error amplifier 322 by the selection circuit 324 to compensate for the error voltage V _EA . 4 shows a detailed circuit diagram of a selection circuit 324 incorporating an embodiment of the present invention. Referring to FIG. 4, the selection circuit 324 includes a signal conversion circuit 3242 and a switch 3244. The signal conversion circuit 3242 is configured to generate a logic signal S ₁ according to the voltage level of the error voltage V _EA , and the switch 3244 selectively connects the compensation network 325 to the error amplifier 322 according to the logic signal S _{1 .} The output.

Referring to FIG. 3, the comparator 326 has a positive phase input receiving a sawtooth signal V _SAW , an inverting input receiving the error voltage V _EA , and an output providing a pulse signal V _PUL . After receiving the pulse signal V _PUL , the PWM circuit 328 generates two drive signals D _A and D _B to control the two switches SW _A and SW _B , so that the switches SW _A and SW _B can be alternately turned on and off.

The operation of the voltage converter 30 will now be described with reference to Figures 3 and 4. When the voltage converter 30 operates in the normal mode, a stable voltage V _OUT is output and its voltage level is greater than the voltage level of the input voltage V _IN . The voltage converter 30 further includes a voltage dividing circuit 34 for detecting a change in the output voltage V _OUT . The voltage dividing circuit 34 divides the output voltage V _OUT by two series resistors R _A and R _B to generate a corresponding feedback voltage V _FB . Then, based on the voltage difference between the reference voltage V _REF and the feedback voltage V _FB , the error amplifier 322 generates a corresponding output voltage V _EA . To compensate for the output voltage V _EA , the compensation network 36 is coupled to the output of the error amplifier 322 by conduction of the switch 3244. In the present embodiment, the compensation network 325 is composed of a resistor R _C and a capacitor C _C connected in series. However, the invention should not be limited thereto. The compensation network 325 can be formed by any single series or parallel combination of a single capacitor or other compensating element coupled between the output of the error amplifier 322 and the ground.

After generating the output voltage V _EA , the comparator 326 compares the output voltage V _EA with the sawtooth signal V _SAW to generate the pulse signal V _PUL . The pulse signal V _{PUL is} transmitted to the PWM circuit 328 to generate corresponding drive signals D _A and D _B to control the switches SW _A and SW _B . The inductor L ₁ is charged or discharged by turning the switches SW _A and SW _B on or off so that the output voltage V _OUT can have a stable voltage level.

When the voltage converter 30 operates in the normal mode, the voltage level of the feedback voltage V _FB will be close to the voltage level of the reference voltage V _REF , and the output voltage V _{EA of} the error amplifier 322 will be maintained according to the magnitude of the load current. At a fixed value of V _{EA, stable} . However, at the initial stage of the voltage converter 30, the output voltage V _OUT generated is still at a relatively low voltage level, so the feedback voltage V _FB has a value close to zero. At this time, the compensation network 325 will not be connected to the output of the error amplifier 322 by the opening of the switch 3244 in FIG. Therefore, the error amplifier 322 can be equivalent to a comparator, and its output voltage V _EA will quickly reach a quasi-maximum value, so that the output voltage V _OUT can be rapidly increased.

As the output voltage V _OUT increases, the feedback voltage V _FB also gradually rises by the voltage dividing circuit 34. When the voltage level of the feedback voltage V _FB rises to a voltage level close to the reference voltage V _REF , the signal conversion circuit 3242 outputs a transition logic signal S ₁ such that the switch 3244 is turned on. At this time, the compensation network 325 will be connected to the output of the error amplifier 322 to compensate for the error voltage V _EA .

In another embodiment of the invention, the compensation network 325 is coupled to a current source or a voltage clamping circuit at the beginning of system startup to clamp the voltage across the compensation network 325. Figure 5 shows a detailed circuit diagram of a selection circuit 324' incorporating another embodiment of the present invention. Referring to Figure 5, the selection circuit 324' includes a signal conversion circuit 3242' and switches 3246 and 3248. The signal conversion circuit 3242' has the same or similar circuit configuration as the signal conversion circuit 3242 in FIG. In addition, the switch 3246 selectively connects the compensation network 325 to the output of the error amplifier 322 according to the output signal S _{2 of} the selection circuit 3242', and the switch 3248 is based on another output signal S of the selection circuit 3242'. ₃ selectively connecting the compensation network 325 to a certain current source I _CONST . Figure 6 shows a detailed circuit diagram of a selection circuit 324" in accordance with yet another embodiment of the present invention. Referring to Figure 6, the selection circuit 324" includes a signal conversion circuit 3242" and switches 3250 and 3252. The signal conversion circuit 3242" has and The signal conversion circuit 3242 of 4 has the same or similar circuit configuration. In addition, the switch 3250 selectively connects the compensation network 325 to the output of the error amplifier 322 according to the output signal S _{4 of} the selection circuit 3242", and the switch 3252 is based on another output signal S of the selection circuit 3242". ₅ selectively connects the compensation network 325 to a voltage clamping circuit 3254. In the present embodiment, the voltage clamping circuit 3254 is composed of a certain current source I ₂ and a transistor M ₂ short-circuited by a gate-source stage. However, the invention should not be limited thereto.

Referring to FIG. 5, in operation, at the initial stage of the voltage converter 30, the voltage level of the feedback voltage V _FB is less than the voltage level of the reference voltage V _REF , so the switch 3246 in FIG. 5 is turned off and the switch 3248 Will be turned on such that the output of the error amplifier 322 is not connected to the compensation network 325. At this time, the compensation network 325 is connected to the constant current source I _CONST . The constant current source I _CONST charges the compensation network 325 such that the voltage V _C on the compensation network 325 rises to a predetermined value when the logic signal S ₂ transitions. The predetermined value is preferably less than or equal to the aforementioned fixed value V _EA,stable . Therefore, after the compensation network 325 is switched to the output of the error amplifier 322, since the voltage V _C on the compensation network 325 is already a fixed value V _{EA, stable} , the voltage converter 30 can enter the stable state relatively quickly. state. Similarly, the constant current source I _{2 of} FIG. 6 can be adjusted such that the gate voltage of the transistor M ₂ is maintained at a fixed value V _{EA, stable} .

In the above embodiments, the embodiment of the present invention and its effects are described by taking a step-up voltage converter as an example, but the present invention should not be limited thereto. For example, the buck voltage converter and the buck-boost voltage converter have the same or approximately configured control circuit, so the present invention can also be applied thereto.

The technical and technical features of the present invention have been disclosed as above, and those skilled in the art can still make various substitutions and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention should be construed as not limited by the scope of the invention, and the invention is intended to be

10. . . Step-up voltage converter

12. . . Control circuit

122. . . Error amplifier

124. . . Compensation network

126. . . Comparators

128. . . PWM circuit

14. . . Voltage dividing circuit

30. . . Voltage converter

32. . . Control circuit

322. . . Error amplifier

324. . . Selection circuit

3242. . . Signal conversion circuit

3244~3252. . . switch

3254. . . Voltage clamp circuit

325. . . Compensation network

326. . . Comparators

328. . . PWM circuit

34. . . Voltage dividing circuit

C _IN , C _OUT , C ₁ , C ₂ , C _C . . . capacitance

I ₁ , I ₂ , I _CONST . . . Battery

L, L ₁ . . . inductance

M ₁ , M ₂ . . . Transistor

R ₁ , R ₂ , R _A , R _B , R _C . . . resistance

SW ₁ , SW ₂ , SW _A , SW _B . . . switch

X ₁ ~X ₂ . . . inverter

1 is a schematic structural diagram of a typical boost voltage converter;

2 is a waveform diagram of the boost voltage converter when it is turned on;

3 is a block diagram showing the structure of a voltage converter for suppressing an output voltage overshoot condition in accordance with an embodiment of the present invention;

4 shows a detailed circuit diagram of a selection circuit incorporating an embodiment of the present invention;

Figure 5 shows a detailed circuit diagram of a selection circuit incorporating another embodiment of the present invention;

Figure 6 shows a detailed circuit diagram of a selection circuit incorporating yet another embodiment of the present invention.

30. . . Voltage converter

32. . . Control circuit

322. . . Error amplifier

324. . . Selection circuit

324. . . Compensation network

326. . . Comparators

328. . . PWM circuit

34. . . Voltage dividing circuit

C ₁ , C ₂ , C _C . . . capacitance

L ₁ . . . inductance

R _A , R _B , R _C . . . resistance

SW _A , SW _B . . . switch

Claims (6)

A voltage converter for suppressing an output voltage overshoot condition for receiving an input voltage to adjust an output voltage, the voltage converter comprising: an error amplifier having a positive phase input receiving a reference voltage, and receiving associated with One of the feedback voltages of the output voltage is an inverting input terminal and an output terminal providing an error voltage; a compensation network for compensating for the stability of the error amplifier; and a selection circuit for determining the error voltage according to the error voltage a voltage level to selectively connect the compensation network to the output of the error amplifier; wherein the compensation network is not connected to the error amplifier when a voltage level of the feedback voltage is less than a voltage level of the reference voltage The output terminal is coupled to the output of the error amplifier when the voltage level of the feedback voltage is substantially equal to the voltage level of the reference voltage. A voltage converter according to claim 1, wherein the compensation network comprises a capacitor. The voltage converter of claim 1, wherein the selection circuit comprises: a signal conversion circuit for generating a logic signal according to a voltage level of the error voltage; and a first switch for selectively connecting according to the logic signal The compensation network is to the output of the error amplifier. The voltage converter of claim 3, wherein the selection circuit further comprises: a second switch for selectively connecting a certain current source to the compensation network according to the logic signal; wherein the voltage level of the feedback voltage When the voltage level is less than the voltage level of the reference voltage, the constant current source charges the compensation network, so that the voltage level on the compensation network rises when the voltage level of the feedback voltage is substantially equal to the voltage level of the reference voltage. To a predetermined value. The voltage converter of claim 3, wherein the selection circuit further comprises: a third switch for selectively connecting a voltage clamping circuit to the compensation network according to the logic signal; wherein the voltage clamping circuit is used to When the voltage level of the feedback voltage is less than the voltage level of the reference voltage, the voltage level on the compensation network is maintained to a predetermined value. A voltage converter according to claim 1, wherein the voltage converter is a boost voltage converter.