TW201314787A - Power MOSFET with low RDSON and fabrication method thereof - Google Patents

Abstract

This invention is aims to providing a Power MOSFET with low RDSON structure and relative assembly method. A universal concave matrix array on back side of wafer is used reducing substrate contribution on RDSON of the power MOSFET. And a matching convex matrix array on the lead frame is used for die attaching and package. The matrix concave array on back side of wafer can be independent of die size. In this invention, no photo alignment with wafer front side is required for making this universal concave matrix array.

Description

Power MOS transistor device with low on-resistance and preparation method thereof

The present invention generally relates to a power semiconductor device and a method of fabricating the same, and more particularly to a method for thinning a germanium substrate to reduce the on-resistance of a power MOS transistor and a power MOS transistor device prepared by the method .

For power transistors, the large on-resistance RDSON will result in a relatively large power dissipation, and we expect to reduce the on-resistance as much as possible to reduce device losses. In some transistors whose on-resistance can be simulated, for example, in a 0.8 μm cell-spaced trench gate MOS transistor, the total on-resistance in a square millimeter at 10 V is 4.1 milliohms, while the 矽 substrate The on-resistance occupies 2 milliohms, and the on-resistance of the substrate is almost 49% of the total on-resistance; if the total on-resistance is 5.7 milliohms in the square millimeter of 4.5V, the on-resistance of the germanium substrate is approximately 2 In milliohms, the on-resistance of the substrate is almost 35% of the total on-resistance. It can be seen that eliminating the germanium substrate can achieve an ideal low on-resistance in a power device.
The etching of the germanium substrate can usually be done by some etching methods used in standard processes. In addition, the electro-chemical etching method can also etch the germanium substrate. The main principle is that the PN junction generated at the junction of the N-type semiconductor substrate and the P-type semiconductor substrate is reverse-biased and needs to be etched. The semiconductor substrate is subjected to electrochemical etching. For example, FIG. 1 shows that the N-type semiconductor substrate and the P-type semiconductor substrate combined together are immersed in an etching liquid, and a P-type semiconductor substrate to be etched is exposed in the etching liquid, and then on the N-type semiconductor substrate. The anode is connected to the anode, and the cathode is placed in the etching liquid, and the reference electrode can also be placed in the etching liquid as a reference. During the etching process, the etching stops when the wet etching reaches the PN junction, and the etching condition can pass. The current ICE is measured to monitor.
U.S. Patent No. 6,111, 280, issued to U.S. Pat. A pressure sensor that forms an opening in the bottom is primarily intended to increase the pressure sensitivity of the pressure sensor; in addition, U.S. Patent No. 6,927,102 B2 discloses a MOSFET device that forms an opening in a ruthenium substrate, primarily In order to laterally reduce the parasitic capacitance of the power MOSFET, this method does not reduce the resistance.

In view of the above problems, the present invention provides a method of fabricating a low-on-resistance power MOS transistor device in which a vertical MOS transistor unit is formed in an epitaxial layer supported by a substrate, and a bottom surface of the epitaxial layer constitutes a vertical MOS transistor unit. a bottom electrode, and an etch stop layer is disposed between the substrate and the epitaxial layer, the method mainly comprises the steps of: depositing a bottom passivation layer overlying the bottom surface of the substrate; forming in the bottom passivation layer One or more openings, etching the substrate with an opening on the bottom passivation layer, etching stops on the etch barrier layer, and forming one or more recesses in the substrate by the etching process; further Etching the region of the barrier layer exposed in the recess for etching, the etching stops on the epitaxial layer, forming one or more bottom recesses sequentially penetrating the substrate and the etch stop layer; the epitaxial layer is exposed at the bottom Doping a dopant of the same type as the epitaxial layer doping in the region of the top of the recess to form a heavily doped bottom electrode contact region in the epitaxial layer above the top of the bottom trench; a metal layer covering the bottom surface of the substrate, the metal layer also covering the sidewalls and the top of the bottom recess; wherein the metal layer is located at the top of the bottom recess and the bottom electrode contact area remains Contact, and the metal layer is used to form a first metal electrode of the power MOS transistor device.
In the above method, etching the substrate is performed by wet etching or deep reactive dopant etching. In the above method, the etching solution used for wet etching the substrate is tetramethylammonium hydroxide solution (TMAH) or potassium hydroxide solution (KOH) or ethylenediamine catechol solution (EDP). In the above method, the etch barrier layer is a layer of buried ruthenium dioxide layer. In the above method, the etching solution used for wet etching the etching stopper layer is a buffered hydrofluoric acid solution. In the above method, the substrate is a lightly doped N-type substrate, the epitaxial layer is a lightly doped N-type epitaxial layer, and the vertical MOS transistor unit is an N-type channel trench MOS transistor. In the above method, the substrate is a lightly doped P-type substrate, the epitaxial layer is a lightly doped P-type epitaxial layer, and the vertical MOS transistor unit is a P-type trenched MOS transistor.
The above method further includes the steps of: preparing a plurality of metal bumps protruding from a top surface of the pedestal on a top surface of the susceptor, the number of the metal bumps being consistent with the number of the bottom recesses, and The topography of the metal bump is adapted to the groove structure of the bottom groove; and the power MOS transistor device is pasted on the top surface of the base by a conductive adhesive material, wherein any one of the metal bumps corresponds to Embedded in a bottom groove, and the conductive adhesive material is located between the metal layer and the base, and the conductive adhesive material is also filled between the top of the bottom groove and the metal bump and the sidewall of the bottom groove and the metal bump between.
The above method, forming a vertical MOS transistor unit in the epitaxial layer supported by the substrate, comprising the steps of: etching in the epitaxial layer to form a plurality of first type trenches and at least one second type trench; 1. The sidewalls and the bottom of the second type of trench are covered with an oxide layer and filled with polysilicon in the first and second types of trenches; the first conductivity type is implanted in the region of the epitaxial layer around the sidewall of the first type of trench a dopant extending from a top surface of the epitaxial layer to a body region in the epitaxial layer; and implanting a second conductivity type in a region of the body region around the sidewall of the upper portion of the first type of trench The dopant is formed to extend from a top surface of the body region to a top electrode doped region in the body region such that any one of the first type of trenches sequentially penetrates the top electrode doped region and the body region and extends Up to an epitaxial layer below the body region; depositing an insulating dielectric layer overlying the epitaxial layer, and simultaneously covering the body region, the top electrode doped region, and the first type of trench and the second type of trench Filled in the slot Was etched in the insulating dielectric layer, the top electrode doped region, and the body region to form a plurality of first type of via holes that sequentially penetrate the edge dielectric layer, the top electrode doped region, and extend into the body region. And forming a second type of via hole forming at least one through-edge dielectric layer and contacting the polysilicon filled in the second type of trench; implanting a heavily doped first conductivity type in the body region around the bottom of the first type of via a foreign matter forming a contact region surrounding a bottom portion of the first type of via hole; depositing a layer of barrier material overlying the insulating dielectric layer, the barrier material layer simultaneously covering the bottom of the first and second types of via holes and On the sidewall; filling the conductive material in the first and second types of via holes, and depositing a metal layer over the barrier material layer above the insulating dielectric layer, the metal layer also covering the first and second types of vias And electrically contacting the conductive material filled in the hole; etching the metal layer and the barrier material layer above the insulating dielectric layer to divide the metal layer into a conductive material filled in the first type of via hole Electrically connected second gold The electrode, the metal layer is further divided into a third metal electrode electrically connected to the conductive material filled in the second type of via hole, and the remaining portion of the barrier material layer overlying the insulating dielectric layer is left in the 2. Below the third metal electrode.
The above method, forming a vertical MOS transistor unit in the epitaxial layer supported by the substrate, comprising the steps of: etching in the epitaxial layer to form a plurality of first type trenches and at least one second type trench; 1. The sidewalls and the bottom of the second type of trench are covered with an oxide layer and filled with polysilicon in the first and second types of trenches; the first conductivity type is implanted in the region of the epitaxial layer around the sidewall of the first type of trench a dopant extending from a top surface of the epitaxial layer to a body region in the epitaxial layer; and implanting a second conductive region in a region of the body region around a sidewall of the upper portion of each of the first type of trenches a type of dopant forming a plurality of top electrode doped regions in the body region, and any one of the top electrode doped regions surrounding the sidewall of the upper portion of a first type of trench, such that any one The first type of trenches sequentially penetrate through a top electrode doped region and the body region and extend into an epitaxial layer located below the body region; an insulating dielectric layer is deposited over the epitaxial layer, and the insulating dielectric layer is also covered at the same time. Place a body region, a plurality of top electrode doped regions, and a polysilicon layer filled in the first type of trenches and the second type of trenches; etching in the insulating dielectric layer to form a plurality of first through dielectric layers a via-like hole, and a second type of via hole forming at least one through-edge dielectric layer and contacting the polysilicon filled in the second type of trench; implanting a heavily doped region in a region of the body region exposed to the bottom of the first type of via hole a dopant of a first conductivity type forming a contact region at a bottom of the first type of via hole; depositing a layer of barrier material overlying the dielectric dielectric layer, the barrier material layer simultaneously covering the first and the a second type of via hole is filled with a conductive material, and a second type of via hole is filled with a conductive material, and a metal layer is deposited over the barrier material layer above the insulating dielectric layer and a portion of the metal layer is further filled in the first In the via-like hole, the metal layer also covers and is in electrical contact with the conductive material filled in the second type of via hole; etching the metal layer and the barrier material layer above the insulating dielectric layer, Metal layer is divided into a second metal electrode electrically connected to a portion of the metal layer filled in the via hole, the metal layer is further divided into a third metal electrode electrically connected to the conductive material filled in the second type of via hole, covering The remaining portion of the barrier material layer over the insulating dielectric layer remains under the second and third metal electrodes.
In the above method, while depositing a bottom passivation layer overlying the bottom surface of the substrate, a top passivation layer is deposited over the insulating dielectric layer, and the top passivation layer simultaneously covers the second and third metal electrodes; A portion of the top passivation layer covering the second and third metal electrodes is removed to expose the second and third metal electrodes in the top passivation layer. In the above method, the implanted first conductivity type dopant is used to form the body region, and a guard ring doping region surrounding the body region is formed in the epitaxial layer, and the guard ring doped region and the body region are formed. The doping types are the same and are spaced apart from the body regions. In the above method, while the implanted second conductivity type dopant is used to form the top electrode doped region, a channel blocking doping region surrounding the doped region of the guard ring is formed in the epitaxial layer, and the channel is blocked. The doping region has the same doping type as the top electrode doping region and is spaced apart from the guard ring doping region.
The present invention also provides a method of fabricating a low on-resistance power MOS transistor device in which a vertical MOS transistor unit is formed in an epitaxial layer supported by a substrate, wherein a bottom surface of the epitaxial layer constitutes a bottom of a vertical MOS transistor unit An electrode, and the substrate is opposite to the doping type of the epitaxial layer, the method mainly comprising the steps of: depositing a bottom passivation layer overlying the bottom surface of the substrate; forming one or more openings in the bottom passivation layer, and lining The PN junction generated at the interface between the bottom and the epitaxial layer is etched by the opening on the bottom passivation layer under the condition of reverse bias, and the etching stops on the epitaxial layer and is formed by the etching process. One or more bottom recesses in the substrate; implanting dopants of the same type as the epitaxial layer doping in a region of the epitaxial layer exposed at the top of the bottom trench to form a top of the bottom trench in the epitaxial layer a heavily doped bottom electrode contact region above; a metal layer is deposited over the bottom surface of the substrate, the metal layer also overlying the sidewall and top of the bottom trench Wherein the metal layer is located in a region of the bottom electrode contact region held in contact with the top of the bottom of the recess, and the metal layer is composed of a first metal electrode of the power MOS transistor devices.
In the above method, etching the substrate is performed by electrochemical etching. In the above method, the etching solution used for the electrochemical etching of the substrate is tetramethylammonium hydroxide solution (TMAH) or potassium hydroxide solution (KOH) or ethylenediamine catechol solution (EDP). . In the above method, the substrate is a lightly doped P-type substrate, the epitaxial layer is a lightly doped N-type epitaxial layer, and the vertical MOS transistor unit is an N-type trenched MOS transistor. In the above method, the substrate is a lightly doped N-type substrate, the epitaxial layer is a lightly doped P-type epitaxial layer, and the vertical MOS transistor unit is a P-type trenched MOS transistor.
The above method further includes the steps of: preparing a plurality of metal bumps protruding from a top surface of the pedestal on a top surface of the susceptor, the number of the metal bumps being consistent with the number of the bottom recesses, and The topography of the metal bump is adapted to the groove structure of the bottom groove; and the power MOS transistor device is pasted on the top surface of the base by a conductive adhesive material, wherein any one of the metal bumps corresponds to Embedded in a bottom groove, and the conductive adhesive material is located between the metal layer and the base, and the conductive adhesive material is also filled between the top of the bottom groove and the metal bump and the sidewall of the bottom groove and the metal bump between.
The above method, forming a vertical MOS transistor unit in the epitaxial layer supported by the substrate, comprising the steps of: etching in the epitaxial layer to form a plurality of first type trenches and at least one second type trench; 1. The sidewalls and the bottom of the second type of trench are covered with an oxide layer and filled with polysilicon in the first and second types of trenches; the first conductivity type is implanted in the region of the epitaxial layer around the sidewall of the first type of trench a dopant extending from a top surface of the epitaxial layer to a body region in the epitaxial layer; and implanting a second conductivity type in a region of the body region around the sidewall of the upper portion of the first type of trench The dopant is formed to extend from a top surface of the body region to a top electrode doped region in the body region such that any one of the first type of trenches sequentially penetrates the top electrode doped region and the body region and extends Up to an epitaxial layer below the body region; depositing an insulating dielectric layer overlying the epitaxial layer, and simultaneously covering the body region, the top electrode doped region, and the first type of trench and the second type of trench Filled in the slot Was etched in the insulating dielectric layer, the top electrode doped region, and the body region to form a plurality of first type of via holes that sequentially penetrate the edge dielectric layer, the top electrode doped region, and extend into the body region. And forming a second type of via hole forming at least one through-edge dielectric layer and contacting the polysilicon filled in the second type of trench; implanting a heavily doped first conductivity type in the body region around the bottom of the first type of via a foreign matter forming a contact region surrounding a bottom portion of the first type of via hole; depositing a layer of barrier material overlying the insulating dielectric layer, the barrier material layer simultaneously covering the bottom of the first and second types of via holes and On the sidewall; filling the conductive material in the first and second types of via holes, and depositing a metal layer over the barrier material layer above the insulating dielectric layer, the metal layer also covering the first and second types of vias And electrically contacting the conductive material filled in the hole; etching the metal layer and the barrier material layer above the insulating dielectric layer to divide the metal layer into a conductive material filled in the first type of via hole Electrically connected second gold The electrode, the metal layer is further divided into a third metal electrode electrically connected to the conductive material filled in the second type of via hole, and the remaining portion of the barrier material layer overlying the insulating dielectric layer is left in the 2. Below the third metal electrode.
The above method, forming a vertical MOS transistor unit in the epitaxial layer supported by the substrate, comprising the steps of: etching in the epitaxial layer to form a plurality of first type trenches and at least one second type trench; 1. The sidewalls and the bottom of the second type of trench are covered with an oxide layer and filled with polysilicon in the first and second types of trenches; the first conductivity type is implanted in the region of the epitaxial layer around the sidewall of the first type of trench a dopant extending from a top surface of the epitaxial layer to a body region in the epitaxial layer; and implanting a second conductive region in a region of the body region around a sidewall of the upper portion of each of the first type of trenches a type of dopant forming a plurality of top electrode doped regions in the body region, and any one of the top electrode doped regions surrounding the sidewall of the upper portion of a first type of trench, such that any one The first type of trenches sequentially penetrate through a top electrode doped region and the body region and extend into an epitaxial layer located below the body region; an insulating dielectric layer is deposited over the epitaxial layer, and the insulating dielectric layer is also covered at the same time. Place a body region, a plurality of top electrode doped regions, and a polysilicon layer filled in the first type of trenches and the second type of trenches; etching in the insulating dielectric layer to form a plurality of first through dielectric layers a via-like hole, and a second type of via hole forming at least one through-edge dielectric layer and contacting the polysilicon filled in the second type of trench; implanting a heavily doped region in a region of the body region exposed to the bottom of the first type of via hole a dopant of a first conductivity type forming a contact region at a bottom of the first type of via hole; depositing a layer of barrier material overlying the dielectric dielectric layer, the barrier material layer simultaneously covering the first and the a second type of via hole is filled with a conductive material, and a second type of via hole is filled with a conductive material, and a metal layer is deposited over the barrier material layer above the insulating dielectric layer and a portion of the metal layer is further filled in the first In the via-like hole, the metal layer also covers and is in electrical contact with the conductive material filled in the second type of via hole; etching the metal layer and the barrier material layer above the insulating dielectric layer, Metal layer is divided into a second metal electrode electrically connected to a portion of the metal layer filled in the via hole, the metal layer is further divided into a third metal electrode electrically connected to the conductive material filled in the second type of via hole, covering The remaining portion of the barrier material layer over the insulating dielectric layer remains under the second and third metal electrodes.
In the above method, while depositing a bottom passivation layer overlying the bottom surface of the substrate, a top passivation layer is deposited over the insulating dielectric layer, and the top passivation layer simultaneously covers the second and third metal electrodes; A portion of the top passivation layer covering the second and third metal electrodes is removed to expose the second and third metal electrodes in the top passivation layer. In the above method, the implanted first conductivity type dopant is used to form the body region, and a guard ring doping region surrounding the body region is formed in the epitaxial layer, and the guard ring doped region and the body region are formed. The doping types are the same and are spaced apart from the body regions. In the above method, the implanted second conductivity type dopant is used to form the top electrode doped region, and a channel blocking doping region around the doped region of the guard ring is formed in the epitaxial layer. The doped region and the top electrode doped region have the same doping type and are spaced apart from the guard ring doped region.
The invention provides a method for preparing a low-on-resistance power MOS transistor device, wherein a vertical MOS transistor unit is formed in an epitaxial layer supported by a substrate, and a bottom surface of the substrate constitutes a bottom electrode of a vertical MOS transistor unit, An etch stop layer composed of a buried heavily doped layer is further disposed between the substrate and the epitaxial layer, and the method mainly comprises the steps of: depositing a bottom passivation layer overlying the bottom surface of the substrate; at the bottom Forming one or more openings in the passivation layer, etching the substrate by using an opening on the bottom passivation layer, stopping on the etch stop layer formed by the buried heavily doped layer, and forming through the etching process One or more bottom grooves in the substrate; a metal layer is deposited over the bottom surface of the substrate, the metal layer also covering the sidewalls and the top of the bottom groove; wherein the metal layer is at the bottom A region at the top of the recess remains in contact with the buried heavily doped layer and the metal layer is used to form a first metal electrode of the power MOS transistor device.
In the above method, etching the substrate is performed by wet etching or deep reactive dopant etching. In the above method, the etching solution used for wet etching the substrate is tetramethylammonium hydroxide solution (TMAH) or potassium hydroxide solution (KOH) or ethylenediamine catechol solution (EDP). In the above method, the substrate is a lightly doped P-type substrate, the epitaxial layer is a lightly doped P-type epitaxial layer, and the vertical MOS transistor unit is a P-type trenched MOS transistor. In the above method, the buried heavily doped layer is a P-type heavily doped layer, and the P-type heavily doped layer has a doping concentration exceeding 1e19/cm3.
The above method further includes the steps of: preparing a plurality of metal bumps protruding from a top surface of the pedestal on a top surface of the susceptor, the number of the metal bumps being consistent with the number of the bottom recesses, and The topography of the metal bump is adapted to the groove structure of the bottom groove; and the power MOS transistor device is pasted on the top surface of the base by a conductive adhesive material, wherein any one of the metal bumps corresponds to Embedded in a bottom groove, and the conductive adhesive material is located between the metal layer and the base, and the conductive adhesive material is also filled between the top of the bottom groove and the metal bump and the sidewall of the bottom groove and the metal bump between.
The above method, forming a vertical MOS transistor unit in the epitaxial layer supported by the substrate, comprising the steps of: etching in the epitaxial layer to form a plurality of first type trenches and at least one second type trench; 1. The sidewalls and the bottom of the second type of trench are covered with an oxide layer and filled with polysilicon in the first and second types of trenches; the first conductivity type is implanted in the region of the epitaxial layer around the sidewall of the first type of trench a dopant extending from a top surface of the epitaxial layer to a body region in the epitaxial layer; and implanting a second conductivity type in a region of the body region around the sidewall of the upper portion of the first type of trench The dopant is formed to extend from a top surface of the body region to a top electrode doped region in the body region such that any one of the first type of trenches sequentially penetrates the top electrode doped region and the body region and extends Up to an epitaxial layer below the body region; depositing an insulating dielectric layer overlying the epitaxial layer, and simultaneously covering the body region, the top electrode doped region, and the first type of trench and the second type of trench Filled in the slot Was etched in the insulating dielectric layer, the top electrode doped region, and the body region to form a plurality of first type of via holes that sequentially penetrate the edge dielectric layer, the top electrode doped region, and extend into the body region. And forming a second type of via hole forming at least one through-edge dielectric layer and contacting the polysilicon filled in the second type of trench; implanting a heavily doped first conductivity type in the body region around the bottom of the first type of via a foreign matter forming a contact region surrounding a bottom portion of the first type of via hole; depositing a layer of barrier material overlying the insulating dielectric layer, the barrier material layer simultaneously covering the bottom of the first and second types of via holes and On the sidewall; filling the conductive material in the first and second types of via holes, and depositing a metal layer over the barrier material layer above the insulating dielectric layer, the metal layer also covering the first and second types of vias And electrically contacting the conductive material filled in the hole; etching the metal layer and the barrier material layer above the insulating dielectric layer to divide the metal layer into a conductive material filled in the first type of via hole Electrically connected second gold The electrode, the metal layer is further divided into a third metal electrode electrically connected to the conductive material filled in the second type of via hole, and the remaining portion of the barrier material layer overlying the insulating dielectric layer is left in the 2. Below the third metal electrode.
The above method, forming a vertical MOS transistor unit in the epitaxial layer supported by the substrate, comprising the steps of: etching in the epitaxial layer to form a plurality of first type trenches and at least one second type trench; 1. The sidewalls and the bottom of the second type of trench are covered with an oxide layer and filled with polysilicon in the first and second types of trenches; the first conductivity type is implanted in the region of the epitaxial layer around the sidewall of the first type of trench a dopant extending from a top surface of the epitaxial layer to a body region in the epitaxial layer; and implanting a second conductive region in a region of the body region around a sidewall of the upper portion of each of the first type of trenches a type of dopant forming a plurality of top electrode doped regions in the body region, and any one of the top electrode doped regions surrounding the sidewall of the upper portion of a first type of trench, such that any one The first type of trenches sequentially penetrate through a top electrode doped region and the body region and extend into an epitaxial layer located below the body region; an insulating dielectric layer is deposited over the epitaxial layer, and the insulating dielectric layer is also covered at the same time. Place a body region, a plurality of top electrode doped regions, and a polysilicon layer filled in the first type of trenches and the second type of trenches; etching in the insulating dielectric layer to form a plurality of first through dielectric layers a via-like hole, and a second type of via hole forming at least one through-edge dielectric layer and contacting the polysilicon filled in the second type of trench; implanting a heavily doped region in a region of the body region exposed to the bottom of the first type of via hole a dopant of a first conductivity type forming a contact region at a bottom of the first type of via hole; depositing a layer of barrier material overlying the dielectric dielectric layer, the barrier material layer simultaneously covering the first and the a second type of via hole is filled with a conductive material, and a second type of via hole is filled with a conductive material, and a metal layer is deposited over the barrier material layer above the insulating dielectric layer and a portion of the metal layer is further filled in the first In the via-like hole, the metal layer also covers and is in electrical contact with the conductive material filled in the second type of via hole; etching the metal layer and the barrier material layer above the insulating dielectric layer, Metal layer is divided into a second metal electrode electrically connected to a portion of the metal layer filled in the via hole, the metal layer is further divided into a third metal electrode electrically connected to the conductive material filled in the second type of via hole, covering The remaining portion of the barrier material layer over the insulating dielectric layer remains under the second and third metal electrodes.
In the above method, while depositing a bottom passivation layer overlying the bottom surface of the substrate, a top passivation layer is deposited over the insulating dielectric layer, and the top passivation layer simultaneously covers the second and third metal electrodes; A portion of the top passivation layer covering the second and third metal electrodes is removed to expose the second and third metal electrodes in the top passivation layer. In the above method, the implanted first conductivity type dopant is used to form the body region, and a guard ring doping region surrounding the body region is formed in the epitaxial layer, and the guard ring doped region and the body region are formed. The doping types are the same and are spaced apart from the body regions. In the above method, the implanted second conductivity type dopant is used to form the top electrode doped region, and a channel blocking doping region around the doped region of the guard ring is formed in the epitaxial layer. The doped region and the top electrode doped region have the same doping type and are spaced apart from the guard ring doped region.
The invention provides a method for preparing a low-on-resistance power MOS transistor device, wherein a vertical MOS transistor unit is formed in an epitaxial layer supported by a substrate, and a bottom surface of the substrate constitutes a bottom electrode of a vertical MOS transistor unit, The method mainly comprises the steps of: depositing a bottom passivation layer overlying the bottom surface of the substrate; forming one or more openings in the bottom passivation layer, etching the substrate by using an opening on the bottom passivation layer, and etching stops Forming, in the substrate, one or more bottom grooves in the substrate by the etching process; depositing a metal layer overlying the bottom surface of the substrate, the metal layer also covering the bottom groove simultaneously And a top layer; wherein the metal layer is used to form a first metal electrode of the power MOS transistor device.
In the above method, etching the substrate is performed by wet etching or deep reactive dopant etching. In the above method, the etching solution used for wet etching the substrate is tetramethylammonium hydroxide solution (TMAH) or potassium hydroxide solution (KOH) or ethylenediamine catechol solution (EDP). In the above method, the substrate is a heavily doped P-type substrate, the epitaxial layer is a lightly doped P-type epitaxial layer, and the vertical MOS transistor unit is a P-type trenched MOS transistor. In the above method, the substrate is a heavily doped N-type substrate, the epitaxial layer is a lightly doped N-type epitaxial layer, and the vertical MOS transistor unit is an N-type channel trench MOS transistor. In the above method, the distance between the top of the formed bottom groove and the top surface of the epitaxial layer is maintained between 10 um and 20 um during the etching of the substrate.
The above method further includes the steps of: preparing a plurality of metal bumps protruding from a top surface of the pedestal on a top surface of the susceptor, the number of the metal bumps being consistent with the number of the bottom recesses, and The topography of the metal bump is adapted to the groove structure of the bottom groove; and the power MOS transistor device is pasted on the top surface of the base by a conductive adhesive material, wherein any one of the metal bumps corresponds to Embedded in a bottom groove, and the conductive adhesive material is located between the metal layer and the base, and the conductive adhesive material is also filled between the top of the bottom groove and the metal bump and the sidewall of the bottom groove and the metal bump between.
The above method, forming a vertical MOS transistor unit in the epitaxial layer supported by the substrate, comprising the steps of: etching in the epitaxial layer to form a plurality of first type trenches and at least one second type trench; 1. The sidewalls and the bottom of the second type of trench are covered with an oxide layer and filled with polysilicon in the first and second types of trenches; the first conductivity type is implanted in the region of the epitaxial layer around the sidewall of the first type of trench a dopant extending from a top surface of the epitaxial layer to a body region in the epitaxial layer; and implanting a second conductivity type in a region of the body region around the sidewall of the upper portion of the first type of trench The dopant is formed to extend from a top surface of the body region to a top electrode doped region in the body region such that any one of the first type of trenches sequentially penetrates the top electrode doped region and the body region and extends Up to an epitaxial layer below the body region; depositing an insulating dielectric layer overlying the epitaxial layer, and simultaneously covering the body region, the top electrode doped region, and the first type of trench and the second type of trench Filled in the slot Was etched in the insulating dielectric layer, the top electrode doped region, and the body region to form a plurality of first type of via holes that sequentially penetrate the edge dielectric layer, the top electrode doped region, and extend into the body region. And forming a second type of via hole forming at least one through-edge dielectric layer and contacting the polysilicon filled in the second type of trench; implanting a heavily doped first conductivity type in the body region around the bottom of the first type of via a foreign matter forming a contact region surrounding a bottom portion of the first type of via hole; depositing a layer of barrier material overlying the insulating dielectric layer, the barrier material layer simultaneously covering the bottom of the first and second types of via holes and On the sidewall; filling the conductive material in the first and second types of via holes, and depositing a metal layer over the barrier material layer above the insulating dielectric layer, the metal layer also covering the first and second types of vias And electrically contacting the conductive material filled in the hole; etching the metal layer and the barrier material layer above the insulating dielectric layer to divide the metal layer into a conductive material filled in the first type of via hole Electrically connected second gold The electrode, the metal layer is further divided into a third metal electrode electrically connected to the conductive material filled in the second type of via hole, and the remaining portion of the barrier material layer overlying the insulating dielectric layer is left in the 2. Below the third metal electrode.
The above method, forming a vertical MOS transistor unit in the epitaxial layer supported by the substrate, comprising the steps of: etching in the epitaxial layer to form a plurality of first type trenches and at least one second type trench; 1. The sidewalls and the bottom of the second type of trench are covered with an oxide layer and filled with polysilicon in the first and second types of trenches; the first conductivity type is implanted in the region of the epitaxial layer around the sidewall of the first type of trench a dopant extending from a top surface of the epitaxial layer to a body region in the epitaxial layer; and implanting a second conductive region in a region of the body region around a sidewall of the upper portion of each of the first type of trenches a type of dopant forming a plurality of top electrode doped regions in the body region, and any one of the top electrode doped regions surrounding the sidewall of the upper portion of a first type of trench, such that any one The first type of trenches sequentially penetrate through a top electrode doped region and the body region and extend into an epitaxial layer located below the body region; an insulating dielectric layer is deposited over the epitaxial layer, and the insulating dielectric layer is also covered at the same time. Place a body region, a plurality of top electrode doped regions, and a polysilicon layer filled in the first type of trenches and the second type of trenches; etching in the insulating dielectric layer to form a plurality of first through dielectric layers a via-like hole, and a second type of via hole forming at least one through-edge dielectric layer and contacting the polysilicon filled in the second type of trench; implanting a heavily doped region in a region of the body region exposed to the bottom of the first type of via hole a dopant of a first conductivity type forming a contact region at a bottom of the first type of via hole; depositing a layer of barrier material overlying the dielectric dielectric layer, the barrier material layer simultaneously covering the first and the a second type of via hole is filled with a conductive material, and a second type of via hole is filled with a conductive material, and a metal layer is deposited over the barrier material layer above the insulating dielectric layer and a portion of the metal layer is further filled in the first In the via-like hole, the metal layer also covers and is in electrical contact with the conductive material filled in the second type of via hole; etching the metal layer and the barrier material layer above the insulating dielectric layer, Metal layer is divided into a second metal electrode electrically connected to a portion of the metal layer filled in the via hole, the metal layer is further divided into a third metal electrode electrically connected to the conductive material filled in the second type of via hole, covering The remaining portion of the barrier material layer over the insulating dielectric layer remains under the second and third metal electrodes.
The above method is characterized in that, while depositing a bottom passivation layer overlying the bottom surface of the substrate, a top passivation layer is deposited over the insulating dielectric layer, and the top passivation layer simultaneously applies the second and third metal electrodes Covering; then removing a portion of the top passivation layer overlying the second and third metal electrodes to expose the second and third metal electrodes in the top passivation layer. In the above method, the implanted first conductivity type dopant is used to form the body region, and a guard ring doping region surrounding the body region is formed in the epitaxial layer, and the guard ring doped region and the body region are formed. The doping types are the same and are spaced apart from the body regions. In the above method, the implanted second conductivity type dopant is used to form the top electrode doped region, and a channel blocking doping region around the doped region of the guard ring is formed in the epitaxial layer. The doped region and the top electrode doped region have the same doping type and are spaced apart from the guard ring doped region.
The invention provides a method for preparing a low-on-resistance power MOS transistor device, wherein a vertical MOS transistor unit is formed in an epitaxial layer supported by a substrate, and a bottom surface of the substrate constitutes a bottom electrode of a vertical MOS transistor unit, The method mainly comprises the steps of: depositing a bottom passivation layer overlying the bottom surface of the substrate; forming one or more openings in the bottom passivation layer, etching the substrate by using an opening on the bottom passivation layer, and etching stops Forming one or more bottom vias in the substrate by the etching process in the substrate; depositing a layer of barrier material on the sidewalls and top of the bottom via and filling the via vias a conductive material; a second metal layer overlying the bottom surface of the substrate, the metal layer also simultaneously in electrical contact with the conductive material filled in the bottom via; wherein the metal layer is used to form power A first metal electrode of a MOS transistor device.
In the above method, etching the substrate is performed by dry etching or laser etching. In the above method, the substrate is a heavily doped P-type substrate, the epitaxial layer is a lightly doped P-type epitaxial layer, and the vertical MOS transistor unit is a P-type trenched MOS transistor. In the above method, the substrate is a heavily doped N-type substrate, the epitaxial layer is a lightly doped N-type epitaxial layer, and the vertical MOS transistor unit is an N-type channel trench MOS transistor. In the above method, the distance between the top of the formed bottom via and the top surface of the epitaxial layer is maintained between 5 um and 20 um during the etching of the substrate.
The above method, forming a vertical MOS transistor unit in the epitaxial layer supported by the substrate, comprising the steps of: etching in the epitaxial layer to form a plurality of first type trenches and at least one second type trench; 1. The sidewalls and the bottom of the second type of trench are covered with an oxide layer and filled with polysilicon in the first and second types of trenches; the first conductivity type is implanted in the region of the epitaxial layer around the sidewall of the first type of trench a dopant extending from a top surface of the epitaxial layer to a body region in the epitaxial layer; and implanting a second conductivity type in a region of the body region around the sidewall of the upper portion of the first type of trench The dopant is formed to extend from a top surface of the body region to a top electrode doped region in the body region such that any one of the first type of trenches sequentially penetrates the top electrode doped region and the body region and extends Up to an epitaxial layer below the body region; depositing an insulating dielectric layer overlying the epitaxial layer, and simultaneously covering the body region, the top electrode doped region, and the first type of trench and the second type of trench Filled in the slot Was etched in the insulating dielectric layer, the top electrode doped region, and the body region to form a plurality of first type of via holes that sequentially penetrate the edge dielectric layer, the top electrode doped region, and extend into the body region. And forming a second type of via hole forming at least one through-edge dielectric layer and contacting the polysilicon filled in the second type of trench; implanting a heavily doped first conductivity type in the body region around the bottom of the first type of via a foreign matter forming a contact region surrounding a bottom portion of the first type of via hole; depositing a layer of barrier material overlying the insulating dielectric layer, the barrier material layer simultaneously covering the bottom of the first and second types of via holes and On the sidewall; filling the conductive material in the first and second types of via holes, and depositing a metal layer over the barrier material layer above the insulating dielectric layer, the metal layer also covering the first and second types of vias And electrically contacting the conductive material filled in the hole; etching the metal layer and the barrier material layer above the insulating dielectric layer to divide the metal layer into a conductive material filled in the first type of via hole Electrically connected second gold The electrode, the metal layer is further divided into a third metal electrode electrically connected to the conductive material filled in the second type of via hole, and the remaining portion of the barrier material layer overlying the insulating dielectric layer is left in the 2. Below the third metal electrode.
The above method, forming a vertical MOS transistor unit in the epitaxial layer supported by the substrate, comprising the steps of: etching in the epitaxial layer to form a plurality of first type trenches and at least one second type trench; 1. The sidewalls and the bottom of the second type of trench are covered with an oxide layer and filled with polysilicon in the first and second types of trenches; the first conductivity type is implanted in the region of the epitaxial layer around the sidewall of the first type of trench a dopant extending from a top surface of the epitaxial layer to a body region in the epitaxial layer; and implanting a second conductive region in a region of the body region around a sidewall of the upper portion of each of the first type of trenches a type of dopant forming a plurality of top electrode doped regions in the body region, and any one of the top electrode doped regions surrounding the sidewall of the upper portion of a first type of trench, such that any one The first type of trenches sequentially penetrate through a top electrode doped region and the body region and extend into an epitaxial layer located below the body region; an insulating dielectric layer is deposited over the epitaxial layer, and the insulating dielectric layer is also covered at the same time. Place a body region, a plurality of top electrode doped regions, and a polysilicon layer filled in the first type of trenches and the second type of trenches; etching in the insulating dielectric layer to form a plurality of first through dielectric layers a via-like hole, and a second type of via hole forming at least one through-edge dielectric layer and contacting the polysilicon filled in the second type of trench; implanting a heavily doped region in a region of the body region exposed to the bottom of the first type of via hole a dopant of a first conductivity type forming a contact region at a bottom of the first type of via hole; depositing a layer of barrier material overlying the dielectric dielectric layer, the barrier material layer simultaneously covering the first and the a second type of via hole is filled with a conductive material, and a second type of via hole is filled with a conductive material, and a metal layer is deposited over the barrier material layer above the insulating dielectric layer and a portion of the metal layer is further filled in the first In the via-like hole, the metal layer also covers and is in electrical contact with the conductive material filled in the second type of via hole; etching the metal layer and the barrier material layer above the insulating dielectric layer, Metal layer is divided into a second metal electrode electrically connected to a portion of the metal layer filled in the via hole, the metal layer is further divided into a third metal electrode electrically connected to the conductive material filled in the second type of via hole, covering The remaining portion of the barrier material layer over the insulating dielectric layer remains under the second and third metal electrodes.
In the above method, while depositing a bottom passivation layer overlying the bottom surface of the substrate, a top passivation layer is deposited over the insulating dielectric layer, and the top passivation layer simultaneously covers the second and third metal electrodes; A portion of the top passivation layer covering the second and third metal electrodes is removed to expose the second and third metal electrodes in the top passivation layer. In the above method, the implanted first conductivity type dopant is used to form the body region, and a guard ring doping region surrounding the body region is formed in the epitaxial layer, and the guard ring doped region and the body region are formed. The doping types are the same and are spaced apart from the body regions. In the above method, the implanted second conductivity type dopant is used to form the top electrode doped region, and a channel blocking doping region around the doped region of the guard ring is formed in the epitaxial layer. The doped region and the top electrode doped region have the same doping type and are spaced apart from the guard ring doped region. A low on-resistance power MOS transistor device provided by the present invention is prepared by the above method.
These and other advantages of the present invention will no doubt become apparent to those skilled in the <RTIgt;

Embodiment 1:
Referring to FIG. 2A, in the wafer 100, an etch stop layer 120 is disposed between the substrate 125 and the epitaxial layer 101. Such a wafer is commonly referred to as a silicon on insulator (SOI) wafer. In the wafer 100' shown in FIG. 2B, the epitaxial layer 101 is grown directly on the substrate 125. In addition, in the wafer 100" shown in the second C-1 to 2C-2, a layer of heavily doped layer 120" is implanted on the top surface of the substrate 125 to form a buried heavily doped layer 120". An epitaxial layer 101 is grown on the substrate 125, for example, by implanting a heavily doped P+ type buried heavily doped layer 120" from the top surface of the lightly doped P-type substrate 125, and then growing lightly on the substrate 125. The doped P-type epitaxial layer 101 is such that there is a heavily doped buried heavily doped layer 120" between the substrate 125 and the epitaxial layer 101.
The case is described by taking SOI wafer as an example. In FIG. 3A, an oxide layer 102 (such as LTO low temperature oxide) is overlaid on the epitaxial layer 101, and a photoresist 115 is coated on the oxide layer 102, which is formed in the photoresist 115 by a photolithography process. The plurality of openings 115' etch the oxide layer 102 to form a plurality of openings 102' in the oxide layer 102, and etch the epitaxial layer 101 using the oxide layer 102 as a hard mask to form the epitaxial layer 101. The plurality of first type trenches 101' and the at least one second type of trenches 101" are generally wetted by anisotropic etching to obtain a small portion of the trenches in order to obtain a relatively smooth trench bottom. Etching, then removing the oxide layer 102, as shown in Figure 3B-2, Figure C. In Figure 3C, the physical damage to the trench walls is caused by the dry etching process that forms the trench process and Some other forms of surface defects require a layer of defective germanium to be removed from the surface of the trench wall. Typically, a sacrificial oxidation process is performed using a relatively fast and low thermal budget wet oxygen to form a sacrificial oxide layer 103 overlying the epitaxial layer 101. Top surface while sacrificing oxide layer 103 The sidewalls and the bottom of the first type of trench 101' and the second type of trench 101" are also covered, and then the sacrificial oxide layer 103 is etched. As shown in FIG. 3D, a gate oxide layer 104 is then grown by a gate oxide process, typically under high temperature dry oxygen conditions, with the gate oxide layer 104 overlying the first type of trench 101' and the second type of trench 101". The sidewalls and the bottom portion also cover the top surface of the epitaxial layer 101. As shown in Figures 3E-3F, the LPCVD deposition polysilicon layer 105 is first overlaid on the gate oxide layer 104, in which the bottom and sidewalls are gated. The first type of trench 101' and the second type of trench 101" of the oxide layer 104 are filled with a polysilicon layer 105, and the polysilicon layer 105 can be selectively doped or deposited after being doped, and then polycrystalline germanium layer. 105 is etched back, leaving only the gate polysilicon 105' in the first type of trench 101' and the gate runner polysilicon 105" (or gate channel polysilicon) in the second type of trench 101", In fact, the first type of trench 101' and the second type of trench 101" are in communication, so the gate polysilicon 105' and the gate runner polysilicon 105" are also electrically conductive. As shown in FIG. 3G, the gate oxide layer 104 overlying the top surface of the epitaxial layer 101 is etched after masking, and a mask oxide layer 106 is formed overlying the top surface of the epitaxial layer 101 and overlying the gate polysilicon 105. 'and the gate runner polysilicon 105". As shown in FIG. 3H, a dopant of the first conductivity type is implanted in the region of the epitaxial layer 101 around the sidewall of the trench of the first type of trench 101' with annealing diffusion Forming a body region 107 extending from the top surface of the epitaxial layer 101 down to the epitaxial layer 101 (the junction depth is typically between 0.6 and 0.7 microns) and using the same ion implantation mask while also utilizing the first conductivity type The dopant forms a guard ring doping region 107a around the body region 107 in the epitaxial layer 101. The guard ring doping region 107a has the same doping type as the body region 107 and is spaced apart from the body region 107. As shown in FIG. 3I, a second conductivity type (opposite to the doping type of the first conductivity type) is implanted in a region of the body region 107 around the sidewall of the upper portion of the first type of trench 101'. The dopant is diffused with annealing to form a slave region The top surface of the 107 extends downward to a top electrode doped region 108 in the body region 107 (the junction depth is typically about 0.25 microns) such that any one of the first type of trenches 101' sequentially penetrates the top electrode doped region 108 and the body. The region 107 extends to a region below the body region 107 where the epitaxial layer 101 is formed, wherein the same ion implantation mask is used, and a dopant of the second conductivity type is also utilized in the epitaxial layer 107. Forming a channel blocking doping region 108a around the guard ring doping region 107a, the doping type of the channel blocking doping region 108a and the top electrode doping region 108 are the same and the guard ring doping region 107a are spaced apart from each other.
As shown in FIG. 3J, after the mask oxide layer 106 is stripped, an insulating dielectric layer 109 is deposited over the epitaxial layer, which is typically a double passivation layer of a low temperature oxide/boric acid-containing bismuth glass (LTO/BPSG). And the insulating dielectric layer 109 also covers the gate polysilicon 105' filled in the body region 107, the guard ring doping region 107a, the top electrode doping region 108, the channel blocking doping region 108a, and the first type of trench 101'. And the second type of trench 101" is filled in the gate runner polysilicon 105". Then, as shown in FIG. 3K, etching is performed in the insulating dielectric layer 109, the top electrode doping region 108, and the body region 107 by using a plurality of openings 116' in the mask 116 to form a through-insertion dielectric layer 109 and a top portion in sequence. The electrode doped region 108 extends to the plurality of first type vias 110 in the body region 107, and forms at least one through-edge dielectric layer 109 and contacts the gate runner polysilicon 105 filled in the second type of trench 101" The second type of vias 110', and the first type of vias 110 are typically between 0.25 and 0.4 microns deep from the top surface of the top electrode doped region 108. As shown in FIG. 3L, a heavily doped first conductivity type dopant is implanted in a region of the body region 107 around the bottom of the first type of via 110 to form a bottom surrounding the first type of via 110. Contact area 110a. As shown in FIG. 3M, a barrier material layer 112 (eg, Ti/TiN) having a good electrical conductivity is deposited over the insulating dielectric layer 109, and the barrier material layer 112 also covers the first via 110. The second type of through holes 110' are respectively on the bottom and the side walls; then the first type of through holes 110 and the second type of through holes 110' with the barrier material layer 112 attached to the bottom and the side walls are filled with a conductive material (for example, tungsten W And a metal layer 113 is deposited over the region of the barrier material layer 112 above the insulating dielectric layer 109, and the metal layer 113 is also covered in the first type of via hole 110 and the second type of via hole, respectively. The conductive material 111 in 110' is in electrical contact with the conductive material 111. As shown in FIG. 3N, the regions of the metal layer 113 and the barrier material layer 112 above the insulating dielectric layer 109 are simultaneously etched to divide the metal layer 113 into conductive materials filled in the first type of vias 110. 111 electrically connected second metal electrode 113A, in this process, the metal layer 113 is further divided into a third metal electrode 113B electrically connected to the conductive material 111 filled in the second type of via hole 110', the barrier material layer The remaining portions 112'a and 112'b which are etched in the region overlying the insulating dielectric layer 109 are left under the second metal electrode 113A and the third metal electrode 113B, respectively. As shown in FIG. 3O, PECVD deposits a bottom passivation layer 114b overlying the bottom surface of the substrate 125, and deposits a top passivation layer 114a overlying the dielectric dielectric layer 109. The top passivation layer 114a simultaneously exposes the second metal electrode 113A and The third metal electrode 113B is covered, and the passivation layer is usually hafnium oxide or tantalum nitride. As shown in FIG. 3P, an opening 114'b or a plurality of openings, not shown, are formed in the bottom passivation layer 114b, thereby using the bottom passivation layer 114b as a mask and utilizing the opening 114'b on the bottom passivation layer 114b. The substrate 125 is etched, and a recess 115 or a plurality of recesses not shown in the substrate 125 are formed by the etching process, and etching is stopped on the etch barrier layer 120. The etching of the substrate 125 may be wet etching or deep reactive dopant etching, and the etching solution used for wet etching is usually tetramethylammonium hydroxide solution (TMAH) or potassium hydroxide. Solution (KOH) or ethylenediamine catechol solution (EDP), due to TMAH compatible CMOS wet etching and no alkali metal ions, and EDP has corrosive and potential carcinogenic disadvantages, in addition, K in KOH etching solution ⁺ It is a mobile ionic charge source that has a negative impact on the electrical characteristics of the device (e.g., turn-on voltage), so TMAH is preferred as an etchant in the present invention.
As shown in FIG. 3Q, the region of the etch barrier layer 120, which is typically cerium oxide, exposed in the recess 115 (eg, the region 120' enclosed by the dashed line) is further etched, and the etch can be buffered with hydrogen fluoride. The acid solution is etched and the etch stops on the epitaxial layer 101, thereby forming one or more bottom recesses 115' that extend through the substrate 125 and the etch stop layer 120 in sequence. As shown in FIG. 3R, a dopant of the same type as that of the epitaxial layer 101 is implanted in a region of the epitaxial layer 101 exposed at the top of the bottom recess 115' to form the bottom recess 115' of the epitaxial layer 101. The heavily doped bottom electrode contact region 116 at the top of the top, and then the bottom passivation layer 114b is removed, after which the partial top passivation layer 114a covering the second metal electrode 113A and the third metal electrode 113B is removed, at a suitable timing The region (eg, 114a-1) that covers the top passivation layer 114a over the second metal electrode 113A is removed, and the top passivation layer 114a is removed over the region (eg, 114a-2) on the third metal electrode 113B. The second metal electrode 113A and the third metal electrode 113B are exposed in the top passivation layer 114a. As shown in FIG. 3S, a metal layer (bottom metal layer) 117 is deposited over the bottom surface of the bottom of the liner 125. The metal layer 117 also covers the sidewalls and top of the bottom recess 115', wherein the metal layer 117 The region at the top of the bottom recess 115' maintains good ohmic contact with the heavily doped bottom electrode contact region 116, and the metal layer 117 is used to form the first metal electrode of the power MOS transistor device 100A. As shown in FIG. 3S, in the MOS transistor device 100A, the vertical MOS transistor unit is a trench MOS transistor, and the gate polysilicon 105' filled in the first type of trench 101' constitutes a vertical MOS transistor unit. The gate, the channel is formed in the body region 107, and the current controlled by the gate polysilicon 105' flows from the top electrode doping region 108 to the bottom surface (or vice versa) of the epitaxial layer 101 via the body region 107, so that the bottom surface of the epitaxial layer 101 is formed. The bottom electrode (e.g., the drain) of the vertical MOS transistor unit, and the corresponding top electrode doped region 108 generally constitutes the top electrode (e.g., source) of the vertical MOS transistor unit. Wherein, the conductive material 111 filled in the first type of via hole 110 provides electrical contact between the top electrode doped region 108 and the second metal electrode 113A, and also provides electrical contact between the source region and the body region, so the second The metal electrode 113A constitutes the source electrode of the MOS transistor device 100A; the conductive material 111 filled in the second type of via hole 110' provides electrical contact between the gate runner polysilicon 105" and the third metal electrode 113B, due to the third The metal electrode 113B and any one of the gate polysilicon 105' are electrically conductive, so that the third metal electrode 113B constitutes the gate electrode of the power MOS transistor device 100A, and the first metal electrode composed of the metal layer 117 is power. The drain electrode of the MOS transistor device 100A. For example, if the substrate 125 is a lightly doped N-type substrate, the epitaxial layer 101 is a lightly doped N-type epitaxial layer, and the aforementioned first conductivity type dopant may be a P-type The ion, the dopant of the second conductivity type may be an N-type ion, and the vertical MOS transistor unit is an N-channel trench MOS transistor; if the substrate 125 is a lightly doped P-type substrate, The epitaxial layer is a lightly doped P-type epitaxial layer, and the first conductive layer The type of dopant may be an N-type ion, the second conductivity type dopant may be a P-type ion, and the vertical MOS transistor unit is a P-channel trench MOS transistor.
Embodiment 2:
Referring to FIGS. 2B and 4A-4D, in the wafer 100', the epitaxial layer 101 is directly grown on the substrate 125. If the foregoing fabrication of the vertical MOS transistor unit is performed in the wafer 100', Then, the preparation of the vertical MOS transistor unit in the epitaxial layer 101 is not different from the flow in the first embodiment, so that the same vertical MOS transistor unit is formed in the epitaxial layer 101 supported by the substrate 125. However, the doping type of the substrate 125 and the epitaxial layer 101 are required to be opposite at this time. The main reason is that the PN junction generated by the interface between the substrate 125 and the epitaxial layer 101 is used as an etch barrier when the substrate 125 is etched. Floor. As shown in FIG. 4A, a bottom passivation layer 114b is deposited over the bottom surface of the substrate 125, and an opening 114'b or a plurality of openings (not shown) are formed in the bottom passivation layer 114b (for the sake of brevity, only An opening is indicated). As shown in FIG. 4B, the PN junction generated by the interface between the substrate 125 and the epitaxial layer 101 is etched by the opening 114'b on the bottom passivation layer 114b under reverse bias conditions. Mainly electrochemical corrosion, the wet etching solution used in the electrochemical etching method is mainly tetramethylammonium hydroxide solution (TMAH) or potassium hydroxide solution (KOH), and the etching reaction stops when the etching reaches the PN junction. At this time, the etching precision is adjusted to be considered to substantially stop on the epitaxial layer 101, thereby forming a bottom recess 115' or a plurality of unillustrated bottom recesses in the substrate 125 by the etching process. As shown in FIG. 4C, a dopant of the same type as that of the epitaxial layer 101 is implanted in a region of the epitaxial layer 101 exposed at the top of the bottom recess 115'. This doping process is a heavily doped process to form A bottom electrode contact region 116 in the epitaxial layer 101 above the top of the bottom recess 115'. As shown in Fig. 4D, a metal layer (bottom metal layer) 117 is deposited overlying the bottom surface of the substrate 125, which also covers the sidewalls and top of the bottom recess 115'. Wherein, the region of the metal layer 117 located at the top of the bottom recess 115' maintains good ohmic contact with the bottom electrode contact region 116, and the first metal electrode composed of the metal layer 117 is the drain of the power MOS transistor device 100'A. The electrode electrode, the second metal electrode 113A constitutes the source electrode of the power MOS transistor device 100'A, and the third metal electrode 113B constitutes the gate electrode of the power MOS transistor device 100'A. Wherein, if the substrate 125 is a lightly doped P-type substrate, the epitaxial layer 101 is a lightly doped N-type epitaxial layer, the dopant of the first conductivity type may be a P-type ion, and the second conductivity type is doped. The object may be an N-type ion, and the vertical MOS transistor unit is an N-channel trench MOS transistor. If the substrate 125 is a lightly doped N-type substrate, the epitaxial layer 101 is a lightly doped P-type epitaxial layer, the aforementioned first conductivity type dopant may be an N-type ion, and the second conductivity type dopant may be In the case of a P-type ion, the vertical MOS transistor unit is a P-channel trench MOS transistor.
Embodiment 3:
Referring to FIGS. 2C-1 to 2C-2 and 5A-5D, in the wafer 100", the epitaxial layer 101 is grown on the substrate 125, but previously implanted on the top surface of the substrate 125. A layer of heavily doped material is formed to bury the heavily doped layer 120", so that a layer of buried heavily doped layer 120" is considered to be interposed between the epitaxial layer 101 and the substrate 125. If the foregoing preparation of the vertical MOS transistor unit is in the crystal In the case of the circle 100", the preparation of the vertical MOS transistor unit in the epitaxial layer 101 shown in FIG. A5 is not different from the flow in the first embodiment. At this time, the heavily doped layer 120" is mainly used as an etch barrier when etching the substrate 125. Alternatively, a heavily doped layer is implanted from the top surface of the lightly doped P-type substrate 125. The P+ type buried heavily doped layer 120", such as a heavily doped boron doped layer, has a doping concentration in excess of 1e19/cm3. A lightly doped P-type epitaxial layer 101 is then grown on the substrate 125. It should be noted that since the doping type of the epitaxial layer 101, the buried heavily doped layer 120" and the substrate 125 are the same, the current controlled by the gate polysilicon 105' can flow from the top electrode doping region 108 to the epitaxial region 107. The bottom surface of layer 101 continues to flow to the bottom surface of the substrate (or vice versa), so that the bottom surface of substrate 125 is said to form the bottom electrode (e.g., the drain) of the vertical MOS transistor unit. As shown in Figure 5B, a bottom passivation layer is deposited. 114b overlies the bottom surface of the substrate 125, forming an opening 114'b or a plurality of openings, not shown, in the bottom passivation layer 114b, etching the substrate 125 using the opening 114'b on the bottom passivation layer 114b, Etching is stopped on the etch stop layer formed by the buried heavily doped layer 120", and a bottom recess 115' or a plurality of bottom recesses not shown in the substrate 125 are formed by the etching process. As shown in Figure 5C. Further, as shown in FIG. 5D, a metal layer (bottom metal layer) 117 is deposited over the bottom surface of the substrate 125, and the metal layer 117 also covers the sidewalls and the top of the bottom recess 115', wherein the metal layer 117 is located at the top of the bottom recess 115' and maintains good ohmic contact with the buried heavily doped layer 120", and the first metal electrode composed of the metal layer 117 is the drain electrode of the power MOS transistor device 100"A The second metal electrode 113A constitutes the source electrode of the power MOS transistor device 100"A, and the third metal electrode 113B constitutes the gate electrode of the power MOS transistor device 100"A. The dopant of the first conductivity type may be an N-type ion, and the dopant of the second conductivity type may be a P-type ion, and then the vertical MOS transistor unit is a P-type channel trench MOS Crystal.
Embodiment 4:
Referring to FIGS. 2B and 6 , in the wafer 100 ′, the epitaxial layer 101 is directly grown on the substrate 125 . If the foregoing prepared vertical MOS transistor unit is implemented in the wafer 100 ′, then The vertical MOS transistor unit prepared in the epitaxial layer 101 is not different from the flow in the first embodiment, so that the same vertical MOS transistor unit is formed in the epitaxial layer 101 supported by the substrate 125. At this time, the doping type of the substrate 125 and the epitaxial layer 101 are the same, but the substrate 125 is heavily doped and the epitaxial layer 101 is lightly doped. Since the doping type of the epitaxial layer 101 and the substrate 125 are the same, the current controlled by the gate polysilicon 105' can flow from the top electrode doping region 108 through the body region 107 to the bottom surface of the epitaxial layer 101 and continue to flow to the bottom surface of the substrate (or Conversely, it is considered that the bottom surface of the substrate 125 constitutes the bottom electrode (e.g., the drain) of the vertical MOS transistor unit. A bottom passivation layer (not shown) may be deposited over the bottom surface of the substrate 125, and one or more openings may be formed in the bottom passivation layer, and the substrate 125 may be etched and etched using an opening in the bottom passivation layer. Stopping in the substrate 125 and forming one or more bottom vias 118 in the substrate 125 by the etching process. At this time, the bottom vias 118 can be formed by etching such as dry etching or laser etching. And it must be ensured that the top of the bottom via 118 is still some distance away from the epitaxial layer 101, usually during the etching of the substrate, or by the etching factor, so that the top of the bottom via 118 is formed. Distance X from the top surface of the epitaxial layer 101 ₁ Keep between 5um and 20um. After depositing a layer of barrier material (such as Ti/TiN, not shown) on the sidewalls and top of the bottom via 118, chemical vapor deposition is performed in the sidewall vias 118 of the sidewall and top pad with barrier material layers. A conductive material (such as tungsten) 119 is filled, and a metal layer (bottom metal layer) 117 is deposited on the bottom surface of the substrate 125. The metal layer 117 is also electrically insulated from the conductive material 119 filled in the bottom via 118. Sexual contact, wherein the first metal electrode composed of the metal layer 117 is the drain electrode of the power MOS transistor device 100'B, and the second metal electrode 113A constitutes the source electrode of the power MOS transistor device 100'B, The trimetal electrode 113B constitutes the gate electrode of the power MOS transistor device 100'B. At this time, if the substrate 125 is a heavily doped N-type substrate, the epitaxial layer 101 is a lightly doped N-type epitaxial layer, and the dopant of the first conductivity type may be a P-type ion, and the second conductivity type dopant The N-type ion may be an N-channel trench MOS transistor. If the substrate 125 is a heavily doped P-type substrate, the epitaxial layer 101 is a lightly doped P-type epitaxial layer, the aforementioned first conductivity type dopant may be an N-type ion, and the second conductivity type dopant may be For the P-type ions, the vertical MOS transistor unit is a P-channel trench MOS transistor.
Embodiment 5:
This embodiment is the same as the fourth embodiment in that it is a preparation method for the wafer 100' shown in FIG. 2B, in which a vertical MOS transistor is formed in the epitaxial layer 101 supported by the substrate 125. The cell, and the doping type of the substrate 125 and the epitaxial layer 101 are the same, but the substrate 125 is heavily doped and the epitaxial layer 101 is lightly doped. In this embodiment, a bottom passivation layer (not shown) is first deposited over the bottom surface of the substrate 125, and one or more openings (not shown) are formed in the bottom passivation layer, and the bottom passivation layer is utilized. The opening is wet etched on the substrate 125, the etching is stopped in the substrate 125, and a bottom recess 115' or a plurality of bottom recesses 115' in the substrate 125 are formed by the etching process. The etching time or other etching factor can be adjusted such that the distance between the top of the bottom recess 115' and the top surface of the epitaxial layer 101 ₂ Keep between 10um and 20um. A metal layer (bottom metal layer) 117 is then deposited over the bottom surface of the substrate 125, which also covers the sidewalls and top of the bottom recess 115', wherein the first layer of metal layer 117 is formed. The metal electrode is the drain electrode of the power MOS transistor device 100"B, the second metal electrode 113A constitutes the source electrode of the power MOS transistor device 100"B, and the third metal electrode 113B constitutes the power MOS transistor device 100"B a gate electrode. If the substrate 125 is a heavily doped N-type substrate, the epitaxial layer 101 is a lightly doped N-type epitaxial layer, and the dopant of the first conductivity type may be a P-type ion, and the second conductivity type The dopant may be an N-type ion, and the vertical MOS transistor unit is an N-channel trench MOS transistor. If the substrate 125 is a heavily doped P-type substrate, the epitaxial layer 101 is lightly doped P The epitaxial layer, the dopant of the first conductivity type may be an N-type ion, the dopant of the second conductivity type may be a P-type ion, and the vertical MOS transistor unit is a P-type trench MOS transistor.
Each of the above embodiments injects dopants into the region of the body region 107 around the sidewall of the upper portion of the first type of trench 101', forming a region extending downward from the top surface of the body region 107 into the body region 107. A top electrode doped region 108, generally the structural mode of such a vertical MOS transistor unit can be referred to as a TC-MOS (Trench touch MOSFET) device. In order to further clarify the broader scope of the present invention, the SOI wafer 100 is still described as an example. 8A-8E shows a vertical MOS transistor as a method for reducing the on-resistance of a conventional Trench DMOS device, which is substantially identical to the preparation method of the 3A-3S diagram, and the difference is that it is located only in the body region 107. A dopant of a second conductivity type is implanted into a region around a sidewall of the upper portion of each of the first type of trenches 101' to form a plurality of top electrode doped regions 108' in the body region 107, and any one of the top electrodes The doped region 108' surrounds the sidewall of the upper portion of the first type of trench 101' so that any one of the first trenches 101' sequentially penetrates through the top electrode doped region 108' and the body. The region 107 extends to an area in which the epitaxial layer 101 is located below the body region 107, as shown in Fig. 8A. Then, as shown in FIG. 8B, an insulating dielectric layer 109 is deposited over the epitaxial layer 101. The insulating dielectric layer 109 also covers the body region 107, the plurality of top electrode doped regions 108', and the first type of trenches. The gate polysilicon 105' filled in the trench 101' and the gate runner polysilicon 105" filled in the trench 101" of the second type. Then, as shown in FIG. 8C, etching is performed in the insulating dielectric layer 109 to form a plurality of first-type via holes 110-1 penetrating the edge dielectric layer 109, and at least one through-edge dielectric layer 109 is formed and in contact with the second type. The second type of via hole 110'-1 of the polysilicon (ie, the gate runner polysilicon 105" filled in the trench 101" is in the region of the body region 107 exposed at the bottom of the first type via 110-1 A heavily doped dopant of the first conductivity type is implanted to form a contact region 110a-1 at the bottom of the first type of via 110-1, as shown in FIG. 8D. A layer of barrier material (not shown) 112 is deposited over the insulating dielectric layer 109. The barrier material layer 112 also covers the first via 110-1 and the second via 110'-1. On the bottom and on the side walls. Further, a conductive material (such as tungsten) 111 is filled in the second type of via hole 110'-1, and a metal layer (not shown) 113 is deposited over the region of the barrier material layer 112 above the insulating dielectric layer 109, and A portion 113A-2 of the metal layer 113 is also filled in the first type of via hole 110-1, and the metal layer 113 also covers the conductive material 111 filled in the second type of via hole 110'-1 and is Electrical contact is formed. The metal layer 113 and the region of the barrier material layer 112 above the insulating dielectric layer 109 are etched, and the metal layer 113 is divided to form the second metal electrode 113A-1 and the third metal electrode 113B-1, and the second metal electrode 113A-1 is electrically connected to the portion 113A-2 of the metal layer 113 filled in the first type of via hole 110-1, and the conductive portion filled in the third metal electrode 113B-1 and the second type via hole 110'-1 The material 111 is electrically connected, and the remaining portions 112'a, 112'b of the region of the barrier material layer 112 overlying the insulating dielectric layer 109 are respectively left at the second metal electrode 113A-1 and the third metal electrode 113B. Below the -1. The portion 113A-2 of the metal layer 113 filled in the first type of via hole 110-1 constitutes an interconnection joint, and the top electrode doping region 108' is shorted to the body region 107, and the heavily doped contact region 110a-1 is The doping type of the body region 107 is the same, and promotes the ohmic contact of the portion 113A-2 of the metal layer 113 filled in the first type of via hole 110-1 with the body region 107. The preparation process of the bottom groove 115' in Fig. 8E is not different from the method of Figs. 3O to 3S or other methods previously provided. The method of preparing the vertical MOS transistor unit and the bottom recess, in addition to the wafer 100 shown in FIG. 2A, the wafers 100', 100" shown in FIGS. 2B and 2C-2 are also applicable. Moreover, the manner of preparing the bottom groove can also be adaptively corrected. Since the foregoing has fully revealed that the method of preparing the bottom groove can be adjusted to cope with different wafers (that is, to deal with different etch barrier layers), Therefore, in this case, the preparation method of the bottom groove is not repeated for the Trench DMOS.
The power MOS transistor device 200, as shown in FIG. 9A, at this time, a plurality of power MOS transistor devices 200 originally cast together and co-located on one wafer are cut and separated from the wafer to form a separate wafer. After one or more bottom recesses 115' are formed in its substrate 125 (not shown), as an alternative, all of the bottom recesses 115' of the plurality of bottom recesses 115' are combined to form a common a matrix. The bottom recess 115' is located on one side of the bottom surface 202 of the power MOS transistor device 200. It is noted that the metal layer 117 is not illustrated in FIG. 9A. The first metal electrode composed of the metal layer 117 is the drain electrode of the power MOS transistor device 200, the second metal electrode constitutes the source electrode of the MOS transistor device 200, and the third metal electrode constitutes the power MOS transistor device. The gate electrode of 200, the second metal electrode, and the third metal electrode are all located on one side of the top surface 201 of the power MOS transistor device 200. In order to reduce the on-resistance of the MOS, a plurality of metal bumps 315 protruding from the top surface 301 of the susceptor 300 may be prepared on the top surface 301 of the susceptor 300 as shown in FIG. 9B, the metal bumps 315 The number is consistent with the number of bottom recesses 115' and the topography of the metal bumps 315 is adapted to the slot structure of the bottom recess 115'. For example, assuming that the metal bump 315 is a quadrangular prism, the groove structure of the bottom groove 115' is a quadrangular cavity and the cavity volume thereof is preferably embedded in the metal bump 315; the metal bump 315 is preferably The topography may also be other types such as a cube, a cuboid, a cylinder, a truncated cone, etc., in which case the groove structure (cavity topography) of the bottom groove 115' is required to vary. Next, the power MOS transistor device 200 is pasted on the top surface 301 of the susceptor 300 by using a conductive bonding material 320 (such as a conductive silver paste or solder paste, etc.), wherein any one of the metal bumps 315 is correspondingly embedded in a bottom portion. In the recess 115', and the conductive adhesive material 320 is located between the metal layer 117 and the susceptor 301, the conductive adhesive material 320 is also filled between the top of the bottom recess 115' and the metal bump 315, and conductive bonding The material 320 is filled between the sidewall of the bottom recess 115' and the metal bump 315, as shown in the cross-sectional view of the power MOS transistor device 200 and the susceptor 300 as shown in FIG. The source lead pedestal 302 disposed near the susceptor 300 in FIG. 9B may be electrically connected to the second metal electrode through an additional metal wire or a metal piece/band or the like, thereby serving as the power MOS transistor device 200. The source lead; the gate lead pedestal 303 disposed near the susceptor 300 can be electrically connected to the third metal electrode through an additional metal wire or a metal piece/band or the like, thereby serving as the power MOS transistor device 200. The gate pin; the wider pedestal 300 can be directly used as the drain pin and the heat sink of the power MOS transistor device 200. It has to be mentioned that in order to enhance the adhesion between the power MOS transistor device 200 and the susceptor 300, voids and the like in the conductive bonding material 320 between the two are reduced to avoid the power MOS transistor device 200 from The susceptor 300 is detached, and the power MOS transistor device 200 can be attached to the top surface 301 of the susceptor 300 in a vacuum-extracting environment. In another embodiment, as shown in FIG. 11, even the power MOS transistor device 200 can be directly pasted on the top surface 401 of the susceptor 400, noting that it is not present on the top surface 401 of the susceptor 400. Any protrusions such as metal bumps are disposed, but the conductive bonding material 320 is coated on the top surface 401 of the susceptor 400, and the power MOS transistor device 200 is directly pasted on the susceptor 400, and is electrically conductive. The adhesive material 320 is not only located between the metal layer 117 (not shown) and the susceptor 301, and a portion of the conductive adhesive material 320 is also filled in the bottom recess 115', as well as to reduce air bubbles in the bottom recess 115'. (Void) amount, this pasting process can also be carried out under vacuum. It can be seen that the pedestal 300, 400 or similar lead frame that fits the bottom recess 115' provides a better low resistance package model.
The above content is described by taking a vertical gate MOS transistor device as an example. In fact, a vertical gate MOS transistor device is also applicable, such as a vertical double diffused MOSFET (VDMOS) device. Referring to FIG. 12, a vertical MOS transistor unit is formed in the epitaxial layer 101 supported by the substrate 125, except that the gate of the vertical MOS transistor unit is planar rather than trench type, specifically, epitaxial A body region 607 of the VDMOS is formed in the layer 101 and near the top surface of the epitaxial layer 101, and a top electrode doped region (ie, a source) extending from the top surface of the body region 607 to the body region 607 is also formed in the epitaxial layer 101. The polar region 608, and the body region 607 is surrounded by the top electrode doping region 608. A gate oxide layer 604 is disposed under the polysilicon gate 605, a region 607a of the body region 607 under the gate oxide layer 604 and the polysilicon gate 605, and the region 607a is located between the top electrode doping region 608 and the epitaxial layer 101, thereby The region 607a constitutes a current path of the VDMOS device, and the current flows laterally from the top electrode doping region 608 through the body region 607 and then vertically to the bottom surface of the epitaxial layer 101. Therefore, it can be considered that the bottom surface of the epitaxial layer 101 constitutes the bottom electrode of the vertical MOS transistor unit. (drain). Barrier material layer 612 and metal layer 613A provide a short between top electrode doped region 608 and body region 607. The etch stop layer 120 is disposed between the epitaxial layer 101 and the substrate 125 to form a bottom recess 115' or a plurality of unillustrated bottom recesses that sequentially penetrate the substrate 125 and the etch stop layer 120. A dopant of the same type as that of the epitaxial layer 101 is implanted in a region of the epitaxial layer 101 exposed at the top of the bottom recess 115' to form a heavily doped layer in the epitaxial layer 101 above the top of the bottom recess 115'. The bottom electrode contact region 116, the metal layer (bottom metal layer) 117 covers the bottom surface of the substrate 125, the metal layer 117 also covers the sidewall and the top of the bottom recess 115', and the metal layer 117 is located at the bottom recess 115. The top region remains in contact with the bottom electrode contact region 116, and the metal layer 117 is used to form the first metal electrode (drain) of the VDMOS device, at which time the metal layer 613A is the second metal electrode (source electrode), and The metal layer illustrated and connected to the polysilicon gate 605 constitutes a third metal electrode (gate electrode). Since the foregoing has sufficiently revealed that the method of preparing the bottom groove can be adjusted to cope with different wafers (that is, to deal with different etch barrier layers), the method of preparing the bottom groove is not repeated for the VDMOS in this case.
Although the present application does not separately describe the above various device structures in detail, the structural mode of the semiconductor device prepared by the above listed method is already clear, and the device structure is fully embodied in the method. In this regard, the device structure will not be described again in this application. However, it must be clarified that the low on-resistance power MOS transistor device to be protected by the present invention is prepared by the above methods.
Exemplary embodiments of a specific structure of a specific embodiment are given by way of illustration and the accompanying drawings. For example, the present invention is illustrated by a vertical MOS transistor with a top-source drain, and the wafer can be used for other types of conversions based on the spirit of the present invention. For example, a vertical MOS transistor in which a vertical MOS transistor is replaced with a top-drain bottom source is also feasible. Therefore, although the above invention proposes a prior preferred embodiment, these are not intended to be limiting.
Various changes and modifications will no doubt become apparent to those skilled in the <RTIgt; Accordingly, the appended claims are to cover all such modifications and modifications The scope and content of any and all equivalents are intended to be within the scope and spirit of the invention.

100, 100’. . . Wafer

100A, 100"A...MOS transistor device

101. . . Epitaxial layer

101', 101"...groove

102, 102’. . . Oxide layer

103. . . Sacrificial oxide layer

104, 604. . . Gate oxide layer

105', 105"...gate polysilicon

106. . . Mask oxide

107, 107a, 607, 607a. . . Body area

108, 108a, 108'a, 608. . . Top electrode doped region

109. . . Insulating dielectric layer

110, 110', 110a, 110-1, 110a-1. . . Through hole

111. . . Conductive material

112, 612. . . Barrier material layer

112’a, 112’b. . . The remaining part

113A, 113A-1. . . Second metal electrode

113B, 113B-1. . . Third metal electrode

114a, 114’a. . . Top passivation layer

114b, 114’b. . . Bottom passivation layer

115, 115’. . . Bottom groove

116. . . Electrode contact zone

117. . . Metal layer (bottom metal layer)

120, 120’. . . Etch barrier

125. . . Substrate

200. . . Power MOS transistor device

300, 400. . . Pedestal

201, 301, 401. . . Top surface

202. . . Bottom

302. . . Source lead pedestal

303. . . Gate lead pedestal

315. . . Metal bump

320. . . Conductive bonding material

605. . . Polycrystalline germanium gate

613A. . . Metal layer

Embodiments of the present invention are described more fully with reference to the accompanying drawings. However, the attached drawings are for illustration and illustration only and are not intended to limit the scope of the invention.
Fig. 1 is a schematic view of a ruthenium substrate etched by electro-chemical etching in the background art.
Figure 2A is a schematic illustration of an etch stop layer disposed between the substrate and the epitaxial layer.
Figure 2B is a schematic illustration of the formation of an epitaxial layer directly on a substrate.
2C is a schematic diagram of forming a buried layer by heavily doping with a dopant between the substrate and the epitaxial layer, and using the buried layer as an etch barrier.
3A-3S is a flow chart of a method of forming a power device in an epitaxial layer and forming a bottom recess in the substrate.
4A-4D is a schematic diagram of utilizing a PN junction formed between a substrate and an epitaxial layer as an etch barrier.
5A-5D is a schematic illustration of the use of a heavily doped buried layer between the substrate and the epitaxial layer as an etch stop.
Figure 6 is a schematic illustration of forming a bottom via directly in the substrate and filling the bottom via with a metal material.
Figure 7 is a schematic illustration of the formation of a bottom recess directly in the substrate without the use of any etch stop.
8A-8E is a flow chart of a method of forming another trench vertical power device in an epitaxial layer.
Figure 9A is a schematic view showing the structure of forming a plurality of bottom grooves in the substrate.
Figure 9B is a schematic view of the structure of the lead frame/base adapted to the bottom recess in the substrate.
Figure 10 is a schematic cross-sectional view of a power MOS transistor attached to a pedestal with metal bumps.
Figure 11 is a schematic cross-sectional view of a power MOS transistor adhered to a pedestal without metal bumps.
Figure 12 is a schematic view showing the structure of forming a bottom groove in a substrate of a VDMOS.

100A. . . MOS transistor device

101. . . Epitaxial layer

101’. . . Groove

105’. . . Gate polysilicon

107. . . Body area

108. . . Top electrode doped region

110, 110’. . . Through hole

111. . . Conductive material

112. . . Barrier material layer

113A. . . Second metal electrode

113B. . . Third metal electrode

115’. . . Bottom groove

116. . . Electrode contact zone

117. . . Metal layer (bottom metal layer)

125. . . Substrate

Claims (24)

A method for preparing a low-on-resistance vertical power MOS transistor device, wherein a vertical MOS transistor unit is formed in an epitaxial layer supported by a substrate, and a bottom surface of the epitaxial layer constitutes a bottom electrode of the vertical MOS transistor unit, wherein The method mainly includes the following steps:
Depositing a bottom passivation layer overlying the bottom surface of the substrate;
Forming one or more openings in the bottom passivation layer, etching the substrate with an opening on the bottom passivation layer, and forming one or more bottom recesses through the substrate by the etching process to expose the epitaxy a bottom surface of the layer;
Doping a dopant of the same type as that of the epitaxial layer from a bottom surface of the substrate to form a heavily doped region corresponding to the recess at the bottom of the epitaxial layer;
Depositing a metal layer overlying the bottom surface of the substrate, the metal layer also covering the sidewalls and top of the bottom recess simultaneously;
Wherein the metal layer is used to form a bottom metal electrode of the vertical power MOS transistor device. The method of claim 1, wherein the substrate and the epitaxial layer are both lightly doped. The method of claim 2, wherein etching the substrate is performed by wet etching or deep reactive dopant etching. The method of claim 3, wherein the etching solution used for wet etching the substrate is tetramethylammonium hydroxide solution (TMAH) or potassium hydroxide solution (KOH) or ethylene. Amine catechol solution (EDP). The method of claim 1, wherein the distance between the top of the formed bottom groove and the top surface of the epitaxial layer is maintained between 10 um and 20 um during etching of the substrate. . The method of claim 1, wherein the method further comprises the following steps:
Preparing a plurality of metal bumps protruding from a top surface of the pedestal on a top surface of a pedestal, the number of metal bumps is consistent with the number of the bottom recesses, and the topography of the metal bumps is The groove structure of the bottom groove is adapted; and the power transistor device is pasted on the top surface of the base by using a conductive adhesive material, wherein any one of the metal bumps is correspondingly embedded in a bottom groove, and is electrically conductive The bonding material is between the metal layer and the pedestal, and the conductive bonding material is also filled between the top of the bottom groove and the metal bump and between the sidewall of the bottom groove and the metal bump. The method of claim 1, wherein a top passivation layer is deposited over the bottom surface of the substrate while a top passivation layer is deposited to cover the top metal electrode;
A portion of the top passivation layer overlying the top metal electrode is then removed to expose the top metal electrode in the top passivation layer. The method of claim 2, wherein the substrate is opposite to the doping type of the epitaxial layer, one or more openings are formed in the bottom passivation layer, and an interface between the substrate and the epitaxial layer is generated. The PN junction is etched by electrochemical etching using an opening on the bottom passivation layer under reverse bias conditions, etching is stopped on the epitaxial layer, and one of the substrates is formed by the etching process. Or multiple bottom grooves. The method of claim 1, wherein an etching barrier layer is further disposed between the substrate and the epitaxial layer, and the substrate is etched by using an opening on the bottom passivation layer, and the etching is stopped. Etching the barrier layer and forming one or more recesses in the substrate by the etching process;
Further etching the region of the etch barrier that is exposed in the recess, the etch stops on the epitaxial layer, forming one or more bottom recesses that sequentially penetrate the substrate and the etch stop. The method of claim 9, wherein the etch barrier layer is a layer of buried ruthenium dioxide. The method of claim 10, wherein the etching solution used for wet etching the etch barrier layer is a buffered hydrofluoric acid solution. The method of claim 10, wherein the substrate and the epitaxial layer are of the same doping type. A method of fabricating a low-on-resistance vertical power transistor device, wherein a vertical transistor unit is formed in an epitaxial layer supported by a substrate, wherein the method mainly comprises the following steps:
Forming a lightly doped epitaxial layer on a lightly doped substrate;
Forming a vertical transistor unit in the epitaxial layer;
Depositing a bottom passivation layer overlying the bottom surface of the substrate;
Forming one or more openings in the bottom passivation layer, etching the substrate with an opening on the bottom passivation layer, and forming one or more bottom recesses through the substrate by the etching process to expose the epitaxy a bottom surface of the layer;
Depositing a metal layer overlying the bottom surface of the substrate, the metal layer also covering the sidewalls and top of the bottom recess simultaneously;
Wherein the metal layer is used to form a bottom metal electrode of the vertical power transistor device. The method of claim 13, wherein the substrate is opposite to the doping type of the epitaxial layer, one or more openings are formed in the bottom passivation layer, and an interface between the substrate and the epitaxial layer is generated. The PN junction is etched by electrochemical etching using an opening on the bottom passivation layer under reverse bias conditions, etching is stopped on the epitaxial layer, and one of the substrates is formed by the etching process. Or a plurality of bottom recesses; implanting dopants of the same type as the epitaxial layer doping from the bottom surface of the substrate to form heavily doped regions corresponding to the recesses at the bottom of the epitaxial layer. The method of claim 13, wherein the substrate and the epitaxial layer have the same doping type, and an etch barrier layer is disposed between the substrate and the epitaxial layer, and the bottom passivation layer is used. The opening etches the substrate, the etching stops on the etch barrier layer, and one or more recesses in the substrate are formed by the etching process;
Further etching an area of the etch stop layer exposed in the recess, the etch stops on the epitaxial layer, forming one or more bottom recesses sequentially passing through the substrate and the etch stop layer; from the substrate The bottom surface is implanted with a dopant of the same type as the epitaxial layer doping to form a heavily doped region at the bottom of the epitaxial layer corresponding to the recess. The method of claim 13, wherein an etching barrier layer composed of a buried heavily doped layer is further disposed between the substrate and the epitaxial layer. The method of claim 16, wherein the epitaxial layer is a lightly doped P-type epitaxial layer, and the vertical MOS transistor unit is a P-type trenched MOS transistor. The method of claim 16, wherein the buried heavily doped layer is a P-type heavily doped layer, and the P-type heavily doped layer has a doping concentration of more than 1e19/cm3. A package of a low on-resistance vertical power transistor device comprising a semiconductor wafer mounted on a susceptor, wherein the semiconductor wafer comprises:
Forming a vertical transistor unit in a first conductivity type epitaxial layer supported by a substrate, the substrate including one or more bottom recesses penetrating the substrate from the bottom surface, exposing one of the epitaxial layers Bottom surface
a metal layer covering the bottom surface of the substrate, the metal layer also covering the sidewall of the bottom recess and the bottom surface of the exposed epitaxial layer;
Wherein the metal layer is used to form a bottom metal electrode of the vertical power transistor device. The package of a low-on-resistance vertical power transistor device according to claim 19, wherein the substrate is opposite to the doping type of the epitaxial layer at an interface between the substrate and the epitaxial layer A PN junction is formed. A package of a low on-resistance vertical power transistor device according to claim 20, wherein the substrate is lightly doped. The package of a low-on-resistance vertical power transistor device according to claim 19, wherein a buried ruthenium dioxide etch barrier layer is disposed between the substrate and the epitaxial layer, and the bottom concave portion is further disposed between the substrate and the epitaxial layer. The trench penetrates the buried cerium oxide etch barrier layer. The package of a low-on-resistance vertical power transistor device according to claim 19, wherein the top surface of the pedestal comprises a plurality of metal bumps protruding from a top surface of the pedestal, metal The number of bumps is consistent with the number of the bottom recesses, and the topography of the metal bumps is adapted to the slot structure of the bottom recess; and the power transistor device is bonded to the base using a conductive bonding material a top surface of the seat, wherein any one of the metal bumps is correspondingly embedded in a bottom recess, and the conductive adhesive material is located between the metal layer and the base, and the conductive adhesive material is also filled on the top of the bottom recess and Between the metal bumps and between the sidewalls of the bottom recess and the metal bumps. The package of a low on-resistance vertical power transistor device according to claim 19, wherein the pedestal comprises a flat top surface, and the power transistor device is pasted on the pedestal by using a conductive adhesive material. The top surface, wherein the bottom groove further fills a conductive material of a different material than the base.