TW201314771A - Method for processing high-k dielectric layer - Google Patents

Abstract

A method for processing a high-k dielectric layer includes the following steps. A semiconductor substrate is provided, and a high-k dielectric layer is formed thereon. The high-k dielectric layer has a crystalline temperature. Subsequently, a first annealing process is performed, and a process temperature of the first annealing process is substantially smaller than the crystalline temperature. A second annealing process is performed, and a process temperature of the second annealing process is substantially larger than the crystalline temperature.

Description

High-k dielectric layer manufacturing method

The present invention relates to a method of fabricating a high-k dielectric layer, and more particularly to an annealing process for a high-k gate dielectric layer.

As the size of metal-oxide-semiconductor (MOS) transistor components continues to shrink, the thickness of the gate dielectric layer also shrinks with line width. However, if the thickness of the gate dielectric layer is insufficient to support the gate Extreme voltages can cause severe leakage currents. In addition, polysilicon gates are also susceptible to reduced device performance due to boron penetration effects. Therefore, the semiconductor industry has attempted to use a metal gate and a high dielectric constant (High-K) material to replace the conventional polysilicon gate and oxide gate dielectric layer as a new gate combination.

In addition, the quality of the gate dielectric layer formed by an atomic layer deposition (ALD) process or other processes can be further improved by an annealing process. Since the oxide gate dielectric layer and the high dielectric constant gate dielectric layer are different in material, the annealing process suitable for the oxide gate dielectric layer is implemented in the high dielectric constant gate dielectric layer, and each machine The temperature curve of the temperature controller may be in a disperse state due to the original convergence state, that is, the consistency of the temperature control effect is lost, which is not conducive to the stability of the process, or even the occurrence of fragmentation. Therefore, how to design an annealing process suitable for improving the quality and reliability of a high dielectric constant gate dielectric layer is a subject of the related art.

One of the objects of the present invention is to provide a method of fabricating a high-k dielectric layer to obtain a high-quality dielectric layer of better quality.

A preferred embodiment of the present invention provides a method of fabricating a high-k dielectric layer, the steps of which are as follows. A semiconductor substrate is provided and a high-k dielectric layer is formed over the semiconductor substrate, wherein the high-k dielectric layer has a crystallization temperature. Thereafter, a first annealing process is performed in which one of the first annealing processes has a process temperature substantially less than the crystallization temperature of the high-k dielectric layer. Next, a second annealing process is performed, wherein one of the process temperatures of the second annealing process is substantially greater than the crystallization temperature of the high-k dielectric layer.

The present invention provides a two-stage annealing process for a high-k dielectric layer, including a first annealing process and a second annealing process, wherein the second annealing process and the first annealing process are preferably performed separately in different reaction chambers. . The first annealing process can be used to repair the defects of the high-k dielectric layer, and the second annealing process can be used to adjust the crystallization region of the high-k dielectric layer and the non-adjacent high-k dielectric layer to the semiconductor substrate. interface. This two-stage annealing process improves the structural integrity and electrical performance of the high-k dielectric layer.

The present invention will be further understood by those of ordinary skill in the art to which the present invention pertains. .

Please refer to Figures 1 to 5. 1 to 5 are schematic views showing a method of fabricating a high-k dielectric layer according to a preferred embodiment of the present invention. As shown in FIG. 1, a semiconductor substrate 10 is first provided, such as a substrate composed of a gallium arsenide, a blanket insulating (SOI) layer, an epitaxial layer, a germanium layer, or other semiconductor substrate material. Next, a high-k dielectric layer 12 is formed on the semiconductor substrate 10. The material of the high-k dielectric layer 12 is selected from the group consisting of hafnium oxide (HfO ₂ ), hafnium silicon oxide (HfSiO ₄ ), and hafnium silicon oxynitride (HfSiON). , aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), tantalum oxide (Ta ₂ O ₅ ), yttrium oxide (Y ₂ O ₃ ), oxidation Zirconium oxide (ZrO ₂ ), strontium titanate oxide (SrTiO ₃ ), zirconium silicon oxide (ZrSiO ₄ ), hafnium zirconium oxide (HfZrO ₄ ), yttrium Oxide (strontium bismuth tantalate, SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _1-x O ₃ , PZT), barium strontium titanate, Ba _x Sr _a group consisting of _1-x TiO ₃ , BST), or a combination thereof. The method of forming the high-k dielectric layer 12 includes an atomic layer deposition (ALD) process or a metal-organic chemical vapor deposition (MOCVD), but is not limited thereto. For example, a high-k dielectric layer 12 composed of hafnium oxide (HfO ₂ ) is formed by an atomic layer deposition process, and a precursor is preferably hafnium chloride (HfCl ₄ ) and an oxidant source. For water vapor. If an organometallic chemical vapor deposition method is used, for example, an organic metal can be used as a precursor. At this time, the high-k dielectric layer 12 is a loose amorphous film and has an oxygen vacancy 14 located at/near its surface.

In order to obtain a higher quality dielectric constant dielectric layer, the present invention provides a two-stage annealing process for implementation in a high-k dielectric layer. The present invention can perform the associated annealing process in any suitable process chamber, including any process capable of performing a rapid thermal process (RTP) process such as a spike rapid thermal process or an immersion A combination of a soak rapid thermal process, a laser spike annealing process, a flash annealing, a dynamic surface annealing process, or a combination of the above processes.

Next, as shown in FIG. 2, a first annealing process is performed in a first chamber. The first annealing process can be an immersion rapid heat treatment process, but is not limited thereto. One of the first annealing processes has a process temperature that is substantially less than the crystallization temperature of the high-k dielectric layer 12, such as substantially less than 500 °C. In addition, when performing the first annealing process, it also includes simultaneously introducing a first process gas. In this embodiment, the process temperature of the first annealing process is preferably between 300 ° C and 400 ° C, and the first process gas includes a plurality of radical ions to repair the high dielectric constant. The oxygen defect 14 of the dielectric layer 12 is as shown in FIG. The radical ions of the first process gas include oxygen radical ions or nitrogen radical ions. The oxygen radical ion (O radical) can be obtained by dissolving oxygen vapor (O ₂ ) or ozone vapor (O ₃ ) by heating, ultraviolet irradiation or plasma application, and the nitrogen radical ion (N radical) ) can be obtained by dissociation of ammonia (NH ₃ ). For example, in the first process gas containing radical ions, the first annealing process is performed on the high-k dielectric layer 12 by providing heat energy by the heater, wherein the temperature-time relationship diagram is a horizontal line, that is, the first The initial temperature of the chamber is substantially the same as the predetermined process temperature, and the predetermined process temperature value is required to be less than the crystallization temperature of the high-k dielectric layer 12. In this embodiment, the predetermined process temperature of the first annealing process is any value substantially between 300 ° C and 400 ° C. In addition, the process time can be defined as 50 seconds after the high-k dielectric layer 12 enters the first chamber and 80 seconds before leaving the first chamber. In this embodiment, the processing time of the first annealing process is preferably substantially between 20 seconds and 120 seconds. It should be noted that the implementation of the first annealing process with radical ions is advantageous for reducing the oxygen defect 14 of the high-k dielectric layer 12 and avoiding the leakage current of the high-k dielectric layer 12 subsequently integrated into the semiconductor device. occur.

Next, as shown in FIG. 4, a second annealing process is performed in a second chamber. The second annealing process is preferably a laser spike annealing process, but is not limited thereto. One of the second annealing processes has a process temperature that is substantially greater than the crystallization temperature of the high-k dielectric layer 12, such as substantially greater than 500 °C. In addition, when performing the second annealing process, it may also include simultaneously introducing a second process gas, and the second process gas includes nitrogen (N ₂ ) or a reactive low inert gas. For example, in a nitrogen atmosphere, a laser beam is applied to the surface of the high-k dielectric layer 12 for thermal annealing, wherein the temperature-time relationship diagram is a prominent peak shape, that is, in the second annealing process, from the initial The temperature, substantially equal to room temperature, raises the temperature to a predetermined process temperature, that is, the peak temperature, that is, is greater than the crystallization temperature of the high-k dielectric layer 12, and then returns to room temperature. In this embodiment, the predetermined process temperature of the second annealing process is preferably substantially between 800 ° C and 900 ° C. In addition, the process time can be defined as the time required for the temperature to rise from a predetermined process temperature of 400 ° C to a predetermined process temperature and then to a temperature below the predetermined process temperature of 400 ° C. In this embodiment, the processing time of the second annealing process is preferably substantially between 10 seconds and 20 seconds. It should be noted that the implementation of the second annealing process having a process temperature greater than the crystallization temperature of the high-k dielectric layer 12 facilitates the conversion of the loose amorphous amorphous high-k dielectric layer 12, resulting in a denser structure. The high-k dielectric layer 12 of a crystalline region 16 is as shown in FIG. In addition, the short processing time of the second annealing process can avoid the comprehensive crystallization of the high-k dielectric layer 12, and the adjustment of the crystallization region 16 is not adjacent to the interface between the high-k dielectric layer 12 and the semiconductor substrate 10. The regional crystallization effect helps to improve the electrical performance of the high-k dielectric layer 12 subsequently integrated into the semiconductor device.

Since the first annealing process and the second annealing process have different operating conditions including a predetermined process temperature and a process gas type. In order to simultaneously achieve better temperature control effects in different temperature ranges and avoid mutual interference of process gases, for example, the first process gas containing radical ions may form an unintended oxide layer in the high dielectric constant dielectric layer in the second annealing process. Therefore, the first annealing process and the second annealing process are preferably performed separately in the first chamber and the second chamber, but not limited thereto.

In order to clearly illustrate the features of the present invention, the following is a flow chart illustrating the practice of the present invention to improve the properties of the high-k dielectric layer by an annealing process. Please refer to FIG. 6 and refer to FIG. 1 to FIG. 5 together. FIG. 6 is a flow chart showing the steps of the method for fabricating the high-k dielectric layer of the present invention. As shown in FIG. 6, first, as shown in step 601, a high-k dielectric layer having a crystallization temperature is formed on a semiconductor substrate, and at this time, the high-k dielectric layer is a loose structure. A non-crystalline film. Then, as shown in step 602, a first annealing process is performed on the high-k dielectric layer. The first annealing process can be an immersion rapid thermal processing process. The process temperature of the first annealing process is less than the crystallization temperature of the high-k dielectric layer, and a first process gas having radical ions such as radical ions of oxygen-containing elements is introduced, and the purpose of this step is to not change. Oxygen defects in the high-k dielectric layer are filled in the crystalline state of the high-k dielectric layer. Next, as shown in step 603, a second annealing process is performed on the high-k dielectric layer. The second annealing process is preferably a laser spike annealing process. The process temperature of the second annealing process is greater than the crystallization temperature of the high-k dielectric layer, and a second process gas is introduced, and the second process gas is a less reactive gas such as nitrogen relative to the first process gas. The purpose of the step is to achieve a regional crystallization effect by using a laser spike annealing process, so that the amorphous high-k dielectric layer has a crystalline region, which makes the structure denser.

In addition, the present invention can be further applied to various semiconductor processes having a high-k dielectric layer, for example, a gate-gate process including a gate first process and a gate last process. The high-k first process and the high-k last process after the gate process.

In summary, the present invention provides a two-stage annealing process for a high-k dielectric layer, the two-stage annealing process including a first annealing process and a second annealing process. The process temperature of the first annealing process is less than the crystallization temperature of the high-k dielectric layer, the process temperature of the second annealing process is greater than the crystallization temperature of the high-k dielectric layer, and the first annealing process and the second annealing The process is preferably carried out separately in different reaction chambers. The first annealing process can be used to repair defects of the high-k dielectric layer such as oxygen defects, and the second annealing process can be used to adjust the crystalline region of the high-k dielectric layer without adjacent high-k dielectric layers and semiconductors The interface between the substrates. This two-stage annealing process improves the structural integrity of the high-k dielectric layer and subsequent electrical performance integrated into the semiconductor device.

The above are only the preferred embodiments of the present invention, and all changes and modifications made to the scope of the present invention should be within the scope of the present invention.

10. . . Semiconductor substrate

12. . . High dielectric constant dielectric layer

14. . . Oxygen deficiency

16. . . Crystallized area

601,602,603. . . step

1 to 5 are schematic views showing a method of fabricating a high-k dielectric layer according to a preferred embodiment of the present invention.

FIG. 6 is a flow chart showing the steps of the method for fabricating the high-k dielectric layer of the present invention.

601,602,603. . . step

Claims (11)

A method of fabricating a high-k dielectric layer, comprising: providing a semiconductor substrate; forming a high-k dielectric layer on the semiconductor substrate, wherein the high-k dielectric layer has a crystallization temperature; a first annealing process, wherein one of the first annealing processes is substantially less than the crystallization temperature; and a second annealing process is performed, wherein one of the second annealing processes is substantially greater than the crystallization temperature. The method for fabricating a high-k dielectric layer according to claim 1, wherein the material of the high-k dielectric layer is selected from hafnium oxide (HfO ₂ ), hafnium silicon (hafnium silicon) Oxide, HfSiO ₄ ), hafnium silicon oxynitride (HfSiON), aluminum oxide (Al ₂ O ₃ ), lanthanum oxide (La ₂ O ₃ ), tantalum oxide (tantalum oxide, Ta ₂ O ₅ ), yttrium oxide (Y ₂ O ₃ ), zirconium oxide (ZrO ₂ ), strontium titanate oxide (SrTiO ₃ ), zirconium silicon oxide (zirconium silicon oxide, ZrSiO ₄ ), hafnium zirconium oxide (HfZrO ₄ ), strontium bismuth tantalate (SrBi ₂ Ta ₂ O ₉ , SBT), lead zirconate titanate (PbZr _x Ti _{1- a} group consisting of _x O ₃ , PZT), barium strontium titanate (Ba _x Sr _1-x TiO ₃ , BST), or a combination thereof. The method of fabricating a high-k dielectric layer according to claim 1, wherein the process temperature of the first annealing process is substantially less than 500 °C. The method of fabricating a high-k dielectric layer according to claim 3, wherein the process temperature of the first annealing process is substantially between 300 ° C and 400 ° C. The method of fabricating a high-k dielectric layer according to claim 1, wherein the first annealing process is performed, including introducing a first process gas. A method of fabricating a high-k dielectric layer as described in claim 5, wherein the first process gas comprises a plurality of radical ions. The method of fabricating a high-k dielectric layer according to claim 6, wherein the radical ions of the first process gas comprise oxygen radical ions or nitrogen radical ions. The method of fabricating a high-k dielectric layer according to claim 1, wherein the second annealing process comprises a laser annealing process. The method of fabricating a high-k dielectric layer according to claim 1, wherein the second annealing process comprises introducing a second process gas. A method of fabricating a high-k dielectric layer as described in claim 9, wherein the second process gas comprises nitrogen (N ₂ ). The method of fabricating a high-k dielectric layer according to claim 1, wherein the first annealing process is performed in a first chamber, and the second annealing process is performed in a second chamber.