TW201312665A - Wafer level package structure and the fabrication method thereof - Google Patents

Wafer level package structure and the fabrication method thereof Download PDF

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TW201312665A
TW201312665A TW100133173A TW100133173A TW201312665A TW 201312665 A TW201312665 A TW 201312665A TW 100133173 A TW100133173 A TW 100133173A TW 100133173 A TW100133173 A TW 100133173A TW 201312665 A TW201312665 A TW 201312665A
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wafer
layer
thinned
solder
covering
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TW100133173A
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Chinese (zh)
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TWI473178B (en
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Yan Xun Xue
Ping Huang
Yueh-Se Ho
Hamza Yilmaz
Jun Lu
Ming-Chen Lu
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Alpha & Omega Semiconductor
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/96—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/731—Location prior to the connecting process
    • H01L2224/73101—Location prior to the connecting process on the same surface
    • H01L2224/73103—Bump and layer connectors
    • H01L2224/73104—Bump and layer connectors the bump connector being embedded into the layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/13—Discrete devices, e.g. 3 terminal devices
    • H01L2924/1304—Transistor
    • H01L2924/1306—Field-effect transistor [FET]
    • H01L2924/13091—Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

This invention is aims to providing a wafer level package structure and relative assembly method, which combined WLCSP and traditional package together. In this invention, wafer backside through via etching and metallization and then wafer backside metallization to convert the electrode to top surface, such as vertical structure MOSFET. Whole chip encapsulated, and only part of port of bumps or balls exposed for external electrical interconnection. Maximize die size and minimize package size as well as flatten package thickness, and whole chip encapsulated with resin for mechanical protection and moisture insulation.

Description

一種晶圓級的封裝結構及其製備方法Wafer level package structure and preparation method thereof

本發明一般涉及一種半導體器件的封裝體及其製備方法，更確切的說，本發明涉及一種在晶圓級封裝技術中，將晶片進行整體封裝而使其並無裸露在塑封料之外的封裝結構及其製備方法。
The present invention generally relates to a package of a semiconductor device and a method of fabricating the same, and more particularly to a package in which a wafer is integrally packaged in a wafer level packaging technology so that it is not exposed outside the molding compound. Structure and preparation method thereof.

在先進晶片封裝方式中，晶圓級封裝WLCSP（Wafer Level Chip Scale Packaging）是先行在整片晶圓上進行封裝和測試，並對其進行塑封，然後才將其切割成一個個的IC封裝體顆粒，因此封裝後的封裝體的體積即幾乎等同於裸晶片的原尺寸，該封裝體具備良好的散熱及電氣性能。
通常，在晶圓級封裝的複雜工藝流程中，無論是基於考慮襯底電阻的降低還是縮小晶片的尺寸，最終需要減薄晶片至一定的厚度。而晶片愈薄愈容易碎裂，這就要求極力避免對晶片造成任何形態的損傷，但實際工藝製備流程卻恰恰不盡人意，例如晶圓的切割容易導致晶片的邊緣或角落處有所崩裂，其後果之一就是所獲得的晶片是易碎或缺角的。另一方面，當前大部分晶圓級的晶片尺度封裝體中，器件中的晶片部分是裸露在塑封料之外的，其不良影響是導致晶片抗濕能力差及塑封體無法提供全方位的機械保護，並且電氣性能在一定程度上也受到抑制。公開號為US2009/0032871的美國專利揭露了一種晶圓級封裝的方法，其中晶片完成塑封並被從晶圓上分割下來之後，晶片正面的一部分電極通過位於晶片側面的導電結構與晶片背面的電極進行連接，然而晶片背面的電極仍然是裸露在塑封料之外。專利號為6107164的美國專利同樣也公開了一種晶圓級封裝的方法，通過先在晶圓的正面進行切割並進行塑封，再從晶圓的背面減薄晶圓，之後將晶片從晶圓上分割下來，所獲得的完成塑封的晶片的背面仍然還是裸露在塑封料之外。類似的，還有專利號分別為US6420244和6852607的美國專利案，這些專利申請均沒有解決如何在減薄晶圓的同時還能將晶片進行完全密封保護的問題。

In the advanced chip packaging method, Wafer Level Chip Scale Packaging is packaged and tested on the entire wafer and molded, and then cut into individual IC packages. The particles, so the volume of the package after packaging is almost equal to the original size of the bare wafer, the package has good heat dissipation and electrical properties.
In general, in a complex process flow of wafer level packaging, whether it is based on considering the reduction in substrate resistance or reducing the size of the wafer, it is ultimately necessary to thin the wafer to a certain thickness. The thinner the wafer, the easier it is to break. This requires that any damage to the wafer be avoided. However, the actual process of preparation is just not satisfactory. For example, wafer cutting is likely to cause cracks at the edges or corners of the wafer. One of the consequences is that the wafer obtained is fragile or notched. On the other hand, in most wafer-level wafer-scale packages, the wafer portion of the device is exposed outside the molding compound, and the adverse effect is that the wafer has poor moisture resistance and the plastic body cannot provide a full range of machinery. Protection, and electrical performance is also suppressed to some extent. US Patent Publication No. US2009/0032871 discloses a wafer level package method in which a portion of an electrode on the front side of a wafer passes through a conductive structure on the side of the wafer and an electrode on the back side of the wafer after the wafer is plastically encapsulated and separated from the wafer. The connection is made, however the electrodes on the back side of the wafer are still exposed outside of the molding compound. U.S. Patent No. 6,107,164 also discloses a wafer-level packaging method in which a wafer is first cut and molded on the front side of the wafer, and then the wafer is thinned from the back side of the wafer, and then the wafer is removed from the wafer. After being divided, the back side of the obtained finished plastic wafer is still exposed outside the molding compound. Similarly, there are U.S. Patent Nos. 6,422,244 and 6,852,607, each of which do not address the problem of how to completely seal the wafer while thinning the wafer.

鑒於上述問題，本發明提出了一種晶圓級封裝的方法，在一包含有多個晶片的晶圓上，利用重分佈技術RDL將分佈在晶片頂面的焊墊重新佈局設計成位於覆蓋晶片的絕緣介質層中的排列焊點，排列焊點包含第一類排列焊點，包括以下步驟：於所述排列焊點上安置焊料凸塊；塑封所述晶圓的正面，以第一塑封層包覆位於晶圓正面的絕緣介質層及焊料凸塊；於晶圓的背面進行研磨；塗覆一層阻擋層至減薄後的晶圓的背面，並形成位於阻擋層中的開口；通過開口於減薄後的晶圓的背面進行刻蝕，於晶圓所包含的襯底及絕緣介質層中形成接觸第一類排列焊點的通孔，並移除阻擋層；填充金屬材料至所述通孔中；於減薄後的晶圓的背面覆蓋一層金屬層；於減薄後的晶圓的覆蓋有金屬層的背面對晶圓進行切割，形成隔離晶片的切割槽，並且切割槽停止在第一塑封層中；於減薄後的晶圓的覆蓋有金屬層的背面對晶圓進行塑封，形成包覆金屬層的第二塑封層，同時塑封料還填充在切割槽中；研磨第一塑封層以將焊料凸塊在減薄後的第一塑封層中予以外露；於所述切割槽中進行切割，將晶片進行分離。
上述的方法，在形成所述通孔後，還在所述通孔的內壁上沉積有隔離襯墊層，並且填充的金屬材料通過隔離襯墊層與環繞在通孔周圍的的襯底區域絕緣。上述的方法，形成通孔的方式為幹法刻蝕或濕法刻蝕或鐳射刻蝕。上述的方法，與通孔所接觸的所述第一類排列焊點的位置，位於覆蓋在的襯底內非有源器件單元區域之上的絕緣介質層中。上述的方法，所述晶片為垂直式的MOSFET。上述的方法，形成接觸第一類排列焊點的通孔的過程中，與通孔所接觸的所述第一類排列焊點構成所述MOSFET的漏極電極；以及在所有非第一類排列焊點的排列焊點中，至少一部分未構成與通孔所接觸的排列焊點構成所述MOSFET的柵極電極與源極電極。
本發明提供的另一種晶圓級封裝的方法，在一包含有多個晶片的晶圓上，利用重分佈技術RDL將分佈在晶片頂面的焊墊重新佈局設計成位於覆蓋晶片的絕緣介質層中的排列焊點，排列焊點包含第一類排列焊點，包括以下步驟：塗覆一層覆蓋位於晶圓正面的絕緣介質層及排列焊點的阻擋層，並形成位於阻擋層中接觸第一類排列焊點的開口；通過所述開口對第一類排列焊點、絕緣介質層及晶圓所包含的襯底進行刻蝕，直至於絕緣介質層、襯底中形成貫穿第一類排列焊點的通孔，之後移除阻擋層；於所述排列焊點上安置焊料凸塊，部分焊料同時填充在所述通孔中；塑封所述晶圓的正面，以第一塑封層包覆位於晶圓正面的絕緣介質層及焊料凸塊；於晶圓的背面進行研磨直至在減薄後的晶圓的背面外露出填充在所述通孔中的焊料；於減薄後的晶圓的背面覆蓋一層金屬層；於減薄後的晶圓的覆蓋有金屬層的背面對晶圓進行切割，形成隔離晶片的切割槽，並且切割槽停止在第一塑封層中；於減薄後的晶圓的覆蓋有金屬層的背面對晶圓進行塑封，形成包覆金屬層的第二塑封層，同時塑封料還填充在切割槽中；研磨第一塑封層以將焊料凸塊在減薄後第一塑封層中予以外露；於所述切割槽中進行切割，將晶片進行分離。
上述的方法，在形成所述通孔後，還在所述通孔的內壁上沉積有隔離襯墊層，並且填充的金屬材料通過隔離襯墊層與環繞在通孔周圍的的襯底區域絕緣。上述的方法，形成通孔的方式為幹法刻蝕或濕法刻蝕或鐳射刻蝕。上述的方法，所形成的通孔的平面截面尺寸小於排列焊點的平面尺寸。上述的方法，與通孔所接觸的所述第一類排列焊點的位置，位於覆蓋在的襯底內非有源器件單元區域之上的絕緣介質層中。上述的方法，所述晶片為垂直式的MOSFET。上述的方法，形成接觸第一類排列焊點的通孔的過程中，與通孔所接觸的所述第一類排列焊點構成所述MOSFET的漏極電極；以及在所有非第一類排列焊點的排列焊點中，至少一部分未構成與通孔所接觸的排列焊點構成所述MOSFET的柵極電極與源極電極的排列焊點。
本發明提供的一種晶圓級的封裝結構，在該封裝結構中，利用重分佈技術將分佈在晶片頂面的焊墊重新佈局設計成位於覆蓋晶片的頂部絕緣介質層中的排列焊點，排列焊點包含第一類排列焊點，還包括：包覆頂部絕緣介質層及焊料凸塊的頂部塑封體，其中所述焊料凸塊安置在排列焊點上，且焊料凸塊於頂部塑封體中予以外露；覆蓋在晶片背面的一層底部電極金屬層；形成在晶片所包含的襯底單元及頂部絕緣介質層中接觸第一類排列焊點的通孔，並且通孔中所填充的金屬材料將與通孔所接觸的第一類排列焊點電性連接至所述底部電極金屬層上；包覆所述晶片的底部塑封體，底部塑封體的橫向延伸部分覆蓋所述底部電極金屬層，與橫向延伸部分垂直的底部塑封體的側向延伸部分同時還將晶片的側壁、絕緣介質層的側壁、頂部塑封體的側壁予以覆蓋。
上述的晶圓級的封裝結構，在所述通孔的內壁上還設置有隔離襯墊層，並且填充的金屬材料通過隔離襯墊層與環繞在通孔周圍的襯底區域絕緣。上述的晶圓級的封裝結構，於覆蓋在晶片所包含的襯底單元內非有源器件單元區域之上的絕緣介質層中，通過所述重分佈技術設置與通孔所接觸的所述第一類排列焊點。上述的晶圓級的封裝結構，所述通孔進一步貫穿與通孔所接觸的該第一類排列焊點；以及通孔的平面截面尺寸小於排列焊點的平面尺寸，且通孔中所填充的金屬材料是安置在第一類排列焊點上的焊料凸塊的延伸部分。上述的晶圓級的封裝結構，所述晶片為垂直式的MOSFET。上述的晶圓級的封裝結構，與通孔所接觸的所述第一類排列焊點構成所述MOSFET的漏極電極；以及在所有非第一類排列焊點的排列焊點中，至少一部分未構成與通孔所接觸的排列焊點構成所述MOSFET的柵極電極與源極電極。
本發明提供的一種晶圓級封裝的方法，在一包含有多個晶片的晶圓上，在晶圓的正面形成有凸出於晶圓正面的並電性連接至晶片焊墊的焊料凸塊，包括以下步驟：塑封所述晶圓的正面，以第一塑封層包覆晶圓的正面及焊料凸塊；於晶圓的背面進行研磨；於減薄後的晶圓的背面對晶圓進行切割，形成隔離晶片的切割槽，並且切割槽停止在第一塑封層中；於減薄後的晶圓的背面對晶圓進行塑封，形成包覆減薄後的晶圓的背面的第二塑封層，同時塑封料還填充在切割槽中；研磨第一塑封層以將焊料凸塊在減薄後的第一塑封層中予以外露；於所述切割槽中進行切割，將晶片進行分離。
上述的方法，完成晶圓的背面研磨之後，還包括於減薄後的晶圓的背面覆蓋一層金屬層的步驟；以及在形成隔離晶片的切割槽的過程中，於減薄後的晶圓的覆蓋有金屬層的背面對晶圓進行切割；並且在形成包覆減薄後的晶圓的背面的第二塑封層的過程中，所述第二塑封層還同時包覆金屬層。上述的方法，所述晶片為平面結構的IC，其所有的信號輸入輸出端子均設置在晶片頂面的一側。上述的方法，所述晶片為垂直式的共漏極的雙MOSFET；並且雙MOSFET中一個MOSFET的漏極與另一個MOSFET的漏極通過所述金屬層進行電性連接，以及至少一部分排列焊點分別構成雙MOSFET中任意一個MOSFET的源極電極和柵極電極。上述的方法，所述晶片中至少包含多個二極體，並且所述二極體的一個電極端子共同電性連接在所述金屬層上；以及至少一部分排列焊點構成所述二極體的另一個電極端子。
本發明提供的一種晶圓級封裝的方法，在一包含有多個晶片的晶圓上，利用重分佈技術RDL將分佈在晶片頂面的焊墊重新佈局設計成位於覆蓋晶片的絕緣介質層中的排列焊點，包括以下步驟：於所述排列焊點上安置焊料凸塊；塑封所述晶圓的正面，以第一塑封層包覆位於晶圓正面的絕緣介質層及焊料凸塊；於晶圓的背面進行研磨；於減薄後的晶圓的背面對晶圓進行切割，形成隔離晶片的切割槽，並且切割槽停止在第一塑封層中；於減薄後的晶圓的背面對晶圓進行塑封，形成包覆減薄後的晶圓的背面的第二塑封層，同時塑封料還填充在切割槽中；研磨第一塑封層以將焊料凸塊在第一塑封層中予以外露；於所述切割槽中進行切割，將晶片進行分離。
上述的方法，完成晶圓的背面研磨之後，還包括於減薄後的晶圓的背面覆蓋一層金屬層的步驟；以及在形成隔離晶片的切割槽的過程中，於減薄後的晶圓的覆蓋有金屬層的背面對晶圓進行切割；並且在形成包覆減薄後的晶圓的背面的第二塑封層的過程中，所述第二塑封層還同時包覆金屬層。
本發明提供的一種晶圓級的封裝結構，在該封裝結構中，在晶片的頂面形成有凸出於晶片頂面的並電性連接至晶片焊墊的焊料凸塊，還包括：包覆在晶片頂面的頂部塑封體，且焊料凸塊於頂部塑封體中予以外露；包覆所述晶片的底部塑封體，底部塑封體的橫向延伸部分覆蓋晶片的底面，與橫向延伸部分垂直的底部塑封體的側向延伸部分同時還將晶片的側壁、頂部塑封體的側壁予以覆蓋。
上述的晶圓級的封裝結構，還包括覆蓋晶片底面的一層底部電極金屬層，所述第二塑封層的橫向延伸部分覆蓋晶片的背面的同時還覆蓋底部電極金屬層。上述的晶圓級的封裝結構，所述晶片為平面結構的IC，並且其所有的信號輸入輸出端子均設置在晶片頂面的一側。上述的晶圓級的封裝結構，所述晶片為垂直式的共漏極的雙MOSFET；並且雙MOSFET中一個MOSFET的漏極與另一個MOSFET的漏極通過所述金屬層進行電性連接，以及至少一部分排列焊點分別構成雙MOSFET中任意一個MOSFET的源極電極和柵極電極。上述的晶圓級的封裝結構，所述晶片中至少包含多個二極體，並且所述二極體的一個電極端子共同電性連接在所述金屬層上；以及至少一部分排列焊點構成所述二極體的另一個電極端子。
本發明提供的一種晶圓級的封裝結構，在該封裝結構中，利用重分佈技術將分佈在晶片頂面的焊墊重新佈局設計成位於覆蓋晶片的頂部絕緣介質層中的排列焊點，還包括：包覆頂部絕緣介質層及焊料凸塊的頂部塑封體，其中所述焊料凸塊安置在排列焊點上，且焊料凸塊於頂部塑封體中予以外露；包覆所述晶片的底部塑封體，底部塑封體的橫向延伸部分覆蓋晶片的底面，與橫向延伸部分垂直的底部塑封體的側向延伸部分同時還將晶片的側壁、頂部絕緣介質層的側壁、頂部塑封體的側壁予以覆蓋。
上述的晶圓級的封裝結構，還包括覆蓋晶片底面的一層底部電極金屬層，所述底部塑封體的橫向延伸部分覆蓋晶片的底面的同時還覆蓋底部電極金屬層。
本發明提供的一種晶圓級封裝的方法，在一包含有多個晶片的晶圓上，在晶圓的正面形成有凸出於晶圓正面的並電性連接至晶片焊墊的焊料凸塊，包括以下步驟：於晶圓的正面進行切割，形成位於晶圓正面一側的用於隔離晶片的切割槽，並且該切割槽停止在晶圓所包含的襯底中；於晶圓的正面進行塑封，形成包覆晶圓的正面的第一塑封層，同時塑封料還填充在位於晶圓正面一側的切割槽中；於晶圓的背面進行研磨；於減薄後的晶圓的背面對晶圓進行切割，形成位於減薄後的晶圓的背面一側的用於隔離晶片的切割槽，且位於減薄後的晶圓背面一側的切割槽停止在襯底中並進一步與填充在位於晶圓正面一側的切割槽中的塑封料接觸；於減薄後的晶圓的背面對晶圓進行塑封，形成包覆減薄後的晶圓的背面的第二塑封層，同時塑封料還填充在位於減薄後的晶圓背面一側的切割槽中；研磨第一塑封層以將焊料凸塊在減薄後的第一塑封層中予以外露；同時於位於晶圓正面一側的切割槽中、位於減薄後的晶圓背面一側的切割槽中進行切割，將晶片進行分離。
上述的方法，其特徵在於，晶圓的背面完成研磨後，還包括於減薄後的晶圓的背面進行蝕刻，並覆蓋一層金屬層至減薄後的晶圓的背面的步驟；以及形成位於減薄後的晶圓背面一側的用於隔離晶片的切割槽的過程中，於減薄後的晶圓的覆蓋有金屬層的背面對晶圓進行切割；並且在形成包覆減薄後的晶圓的背面的第二塑封層的過程中，所述第二塑封層還同時包覆所述金屬層。
本發明提供的一種晶圓級封裝的方法，在一包含有多個晶片的晶圓上，利用重分佈技術RDL將分佈在晶片頂面的焊墊重新佈局設計成位於覆蓋晶片的絕緣介質層中的排列焊點，排列焊點包含第一類排列焊點，包括以下步驟：於所述排列焊點上安置焊料凸塊；於晶圓的正面進行切割，形成位於晶圓正面一側的用於隔離晶片的切割槽，並且該切割槽停止在晶圓所包含的襯底中；塑封所述晶圓的正面，以第一塑封層包覆位於晶圓正面的絕緣介質層及焊料凸塊，同時塑封料還填充在形成位於晶圓正面一側的切割槽中；於晶圓的背面進行研磨；於減薄後的晶圓的背面對晶圓進行切割，形成位於減薄後的晶圓背面一側的用於隔離晶片的切割槽，且位於減薄後的晶圓背面一側的切割槽停止在襯底中並進一步與填充在位於晶圓正面一側的切割槽中的塑封料接觸；於減薄後的晶圓的背面對晶圓進行塑封，形成包覆減薄後的晶圓的背面的第二塑封層，同時塑封料還填充在位於減薄後的晶圓背面一側的切割槽中；研磨第一塑封層以將焊料凸塊在減薄後的第一塑封層中予以外露；同時於位於晶圓正面一側的切割槽中、位於減薄後的晶圓背面一側的切割槽中進行切割，將晶片進行分離。
上述的方法，晶圓的背面完成研磨後，還包括於減薄後的晶圓的背面進行蝕刻，並覆蓋一層金屬層至減薄後的晶圓的背面的步驟；以及形成位於減薄後的晶圓背面一側的用於隔離晶片的切割槽的過程中，於減薄後的晶圓的覆蓋有金屬層的背面對晶圓進行切割；並且在形成包覆減薄後的晶圓的背面的第二塑封層的過程中，所述第二塑封層還同時包覆所述金屬層。上述的方法，在覆蓋一層金屬層至減薄後的晶圓的背面之前，還包括以下步驟：
在減薄後的晶圓的背面塗覆一層阻擋層，並形成位於阻擋層中的開口；通過開口於減薄後的晶圓的背面進行刻蝕，於晶圓所包含的襯底及絕緣介質層中形成接觸第一類排列焊點的通孔，並移除阻擋層；填充金屬材料至所述通孔中，並且於減薄後的晶圓的背面覆蓋的一層金屬層通過填充在所述通孔中的金屬材料而電性連接至與通孔所接觸的第一類排列焊點上。上述的方法，與通孔所接觸的所述第一類排列焊點的位置，位於覆蓋在的襯底內非有源器件單元區域之上的絕緣介質層中。
上述方法，於排列焊點上安置焊料凸塊之前，還包括以下步驟：塗覆一層包覆位於晶圓正面的絕緣介質層及排列焊點的阻擋層，並形成位於阻擋層中接觸第一類排列焊點的開口；通過所述開口對所述第一類排列焊點及絕緣介質層、襯底進行刻蝕，於襯底及絕緣介質層中形成貫穿該第一類排列焊點的通孔，並移除阻擋層；之後在排列焊點上安置焊料凸塊的同時，部分焊料還一併填充在所述通孔中。上述方法，於晶圓的背面進行研磨過程中，在減薄後的晶圓的背面外露出填充在通孔中的焊料，並且之後於減薄後的晶圓的背面覆蓋的一層金屬層通過填充在通孔中的焊料而電性連接在與通孔所接觸的第一類排列焊點上。
本發明提供的一種晶圓級的封裝結構，在該結構中，在晶片的頂面形成有凸出於晶片頂面的並電性連接至晶片焊墊的焊料凸塊，包括：包覆晶片的頂部塑封體，頂部塑封體的橫向延伸部分覆蓋在晶片的正面，與頂部塑封體的橫向延伸部分垂直的頂部塑封體的側向延伸部分同時還將晶片的部分側壁予以覆蓋，且焊料凸塊於頂部塑封體中予以外露；包覆晶片的底部塑封體，底部塑封體的橫向延伸部分覆蓋在晶片的底面，與底部塑封體的橫向延伸部分垂直的底部塑封體的側向延伸部分同時還將晶片的另外一部分側壁予以覆蓋，頂部塑封體的側向延伸部分與底部塑封體的側向延伸部分相互接觸以將晶片無縫隙的密封。
上述的晶圓級的封裝結構，還包括覆蓋晶片底面的一層底部電極金屬層，所述底部塑封體的橫向延伸部分覆蓋晶片的底面的同時還覆蓋底部電極金屬層。上述的晶圓級的封裝結構，所述晶片為平面結構的IC，其所有的信號輸入輸出端子均設置在晶片頂面的一側。上述的晶圓級的封裝結構，所述晶片為垂直式的共漏極的雙MOSFET；並且雙MOSFET中一個MOSFET的漏極與另一個MOSFET的漏極通過所述底部電極金屬層進行電性連接，以及至少一部分排列焊點分別構成雙MOSFET中任意一個MOSFET的源極電極和柵極電極。上述的晶圓級的封裝結構，所述晶片中至少包含多個二極體，並且所述二極體的一個電極端子共同電性連接在所述底部電極金屬層上；以及至少一部分排列焊點構成所述二極體的另一個電極端子。
本發明提供一種晶圓級的封裝結構，在該封裝結構中，利用重分佈技術將分佈在晶片頂面的焊墊重新佈局設計成位於覆蓋晶片的頂部絕緣介質層中的排列焊點，排列焊點包含第一類排列焊點，其特徵在於，包括：包覆晶片的頂部塑封體，頂部塑封體的橫向延伸部分覆蓋在頂部絕緣介質層上，與頂部塑封體的橫向延伸部分垂直的頂部塑封體的側向延伸部分同時還將頂部絕緣介質層的側壁、晶片的部分側壁予以覆蓋，且焊料凸塊於頂部塑封體中予以外露；包覆晶片的底部塑封體，底部塑封體的橫向延伸部分覆蓋在晶片的底面，與底部塑封體的橫向延伸部分垂直的底部塑封體的側向延伸部分同時還將晶片的另外一部分側壁予以覆蓋，頂部塑封體的側向延伸部分與底部塑封體的側向延伸部分相互接觸以將晶片無縫隙的密封。
上述的晶圓級的封裝結構，還包括於晶片底面覆蓋的一層底部電極金屬層，所述底部塑封體的橫向延伸部分覆蓋晶片的底面的同時還覆蓋底部電極金屬層。上述的晶圓級的封裝結構，還包括：形成在晶片所包含的襯底單元及頂部絕緣介質層中接觸第一類排列焊點的通孔，並且通孔中所填充的金屬材料將與通孔所接觸的第一類排列焊點電性連接至所述底部電極金屬層上。上述的晶圓級的封裝結構，所述通孔進一步貫穿與通孔所接觸的該第一類排列焊點；以及通孔的平面截面尺寸小於排列焊點的平面尺寸，且通孔中所填充的金屬材料是安置在第一類排列焊點上的焊料凸塊的延伸部分。上述的晶圓級的封裝結構，其中，所述晶片為垂直式的MOSFET。
本領域的技術人員閱讀以下較佳實施例的詳細說明，並參照附圖之後，本發明的這些和其他方面的優勢無疑將顯而易見。

In view of the above problems, the present invention proposes a wafer level packaging method for re-layout a solder pad distributed on the top surface of a wafer to cover a wafer on a wafer including a plurality of wafers using a redistribution technique RDL. Arranging solder joints in the dielectric layer, the solder joints comprise a first type of solder joints, comprising the steps of: placing solder bumps on the solder joints; molding the front surface of the wafers, encapsulating the first plastic layer An insulating dielectric layer and solder bumps on the front side of the wafer; grinding on the back side of the wafer; applying a barrier layer to the back side of the thinned wafer, and forming an opening in the barrier layer; Etching the back side of the thinned wafer, forming a via hole contacting the first type of solder joints in the substrate and the insulating dielectric layer included in the wafer, and removing the barrier layer; filling the metal material to the through hole The back side of the thinned wafer is covered with a metal layer; the back surface of the thinned wafer is covered with a metal layer to cut the wafer to form a cutting groove for the isolation wafer, and the cutting groove stops at the first Plastic seal Forming a second plastic layer covering the metal layer on the back surface of the thinned wafer covered with the metal layer, and filling the metal sealing layer in the cutting groove; grinding the first plastic layer to The solder bumps are exposed in the thinned first molding layer; the cutting is performed in the cutting grooves to separate the wafers.
In the above method, after the via hole is formed, a spacer liner layer is deposited on the inner wall of the via hole, and the filled metal material passes through the spacer liner layer and the substrate region surrounding the via hole. insulation. In the above method, the through holes are formed by dry etching or wet etching or laser etching. In the above method, the position of the first type of aligning pads in contact with the vias is located in the insulating dielectric layer over the area of the non-active device cells within the substrate. In the above method, the wafer is a vertical MOSFET. In the above method, in forming a via hole contacting the first type of solder joints, the first type of solder joints in contact with the via holes constitute a drain electrode of the MOSFET; and in all non-first type arrangements Among the arranged solder joints of the solder joints, at least a part of the array pads which are not formed in contact with the via holes constitute a gate electrode and a source electrode of the MOSFET.
Another method of wafer level packaging provided by the present invention re-lays a solder pad distributed on the top surface of a wafer to an insulating dielectric layer covering the wafer by using a redistribution technique RDL on a wafer including a plurality of wafers. The arrangement of the solder joints, the arrangement of the solder joints comprising the first type of solder joints, comprising the steps of: coating a layer of insulating dielectric covering the front side of the wafer and a barrier layer arranging the solder joints, and forming a first contact in the barrier layer Arranging the openings of the solder joints; etching the first type of solder joints, the insulating dielectric layer and the substrate included in the wafer through the openings until the first type of alignment solder is formed in the insulating dielectric layer and the substrate a through hole of the dot, after which the barrier layer is removed; a solder bump is disposed on the alignment pad, a portion of the solder is simultaneously filled in the via hole; and a front surface of the wafer is molded and covered by the first plastic layer An insulating dielectric layer on the front side of the wafer and solder bumps; polishing is performed on the back side of the wafer until the solder filled in the via holes is exposed outside the back surface of the thinned wafer; on the back side of the thinned wafer Cover one a metal layer; the wafer is cut on the back surface of the thinned wafer covered with the metal layer to form a cutting groove for the isolation wafer, and the cutting groove is stopped in the first plastic sealing layer; the wafer coverage after the thinning The back side of the metal layer is plastic-sealed to form a second plastic coating layer covering the metal layer, and the molding compound is also filled in the cutting groove; the first plastic sealing layer is ground to solder the first plastic sealing layer after thinning Exposed; the cutting is performed in the cutting groove to separate the wafer.
In the above method, after the via hole is formed, a spacer liner layer is deposited on the inner wall of the via hole, and the filled metal material passes through the spacer liner layer and the substrate region surrounding the via hole. insulation. In the above method, the through holes are formed by dry etching or wet etching or laser etching. In the above method, the planar cross-sectional dimension of the formed via hole is smaller than the planar size of the alignment solder joint. In the above method, the position of the first type of aligning pads in contact with the vias is located in the insulating dielectric layer over the area of the non-active device cells within the substrate. In the above method, the wafer is a vertical MOSFET. In the above method, in forming a via hole contacting the first type of solder joints, the first type of solder joints in contact with the via holes constitute a drain electrode of the MOSFET; and in all non-first type arrangements Among the arranged solder joints of the solder joints, at least a part of the array solder joints that do not form a contact with the via holes constitute an arrangement solder joint of the gate electrode and the source electrode of the MOSFET.
The invention provides a wafer level package structure in which a solder pad distributed on a top surface of a wafer is re-arranged by using a redistribution technique to arrange the solder joints in the top insulating dielectric layer covering the wafer, and arranged The solder joint includes a first type of solder joint, and further includes: a top mold body covering the top insulating dielectric layer and the solder bump, wherein the solder bump is disposed on the array solder joint, and the solder bump is in the top mold body Exposed; a layer of bottom electrode metal covering the back surface of the wafer; forming a via hole contacting the first type of solder joints in the substrate unit and the top insulating dielectric layer included in the wafer, and the metal material filled in the via hole will be a first type of solder joints in contact with the through holes are electrically connected to the bottom electrode metal layer; a bottom molding body covering the wafer, and a laterally extending portion of the bottom molding body covers the bottom electrode metal layer, and The laterally extending portion of the laterally extending portion of the laterally-molded body simultaneously covers the sidewalls of the wafer, the sidewalls of the dielectric layer, and the sidewalls of the top molding.
In the above wafer level package structure, a spacer liner layer is further disposed on the inner wall of the through hole, and the filled metal material is insulated from the substrate region surrounding the through hole by the spacer liner layer. The above-described wafer level package structure is disposed in the insulating dielectric layer over the non-active device cell region in the substrate unit included in the wafer, and the first contact with the via hole is set by the redistribution technique One type of solder joints. In the above wafer level package structure, the through hole further penetrates the first type of arrangement solder joints that are in contact with the through holes; and the planar cross-sectional dimension of the through holes is smaller than the planar size of the arrangement of the solder joints, and the through holes are filled The metal material is an extension of the solder bumps disposed on the first type of solder joints. In the above wafer level package structure, the wafer is a vertical MOSFET. The wafer level package structure described above, the first type of solder joints in contact with the via holes constitute a drain electrode of the MOSFET; and at least a portion of all the solder joints of the non-first type of solder joints The array pads that are not formed in contact with the vias constitute the gate electrode and the source electrode of the MOSFET.
The invention provides a wafer level package method, in which a solder bump protruding from a front surface of a wafer and electrically connected to a wafer pad is formed on a front surface of a wafer on a wafer including a plurality of wafers The method includes the steps of: molding a front surface of the wafer, coating a front surface of the wafer and a solder bump with a first plastic sealing layer; performing grinding on a back surface of the wafer; and performing wafer processing on a back surface of the thinned wafer Cutting, forming a cutting groove for the isolation wafer, and the cutting groove is stopped in the first plastic sealing layer; the wafer is plastic-sealed on the back side of the thinned wafer to form a second plastic coating covering the back surface of the thinned wafer The layer, while the molding compound is also filled in the cutting groove; the first plastic sealing layer is ground to expose the solder bumps in the thinned first plastic sealing layer; cutting is performed in the cutting grooves to separate the wafers.
The above method, after finishing the back grinding of the wafer, further comprising the step of covering a back surface of the thinned wafer with a metal layer; and in the process of forming the dicing trench of the isolation wafer, after thinning the wafer The back surface is covered with a metal layer to cut the wafer; and in forming the second plastic encapsulation layer covering the back side of the thinned wafer, the second plastic encapsulation layer also simultaneously coats the metal layer. In the above method, the wafer is a planar IC, and all of the signal input and output terminals are disposed on one side of the top surface of the wafer. In the above method, the wafer is a vertical common drain dual MOSFET; and a drain of one MOSFET of the dual MOSFET is electrically connected to a drain of another MOSFET through the metal layer, and at least a part of the solder joint is arranged The source electrode and the gate electrode of any one of the dual MOSFETs are respectively formed. In the above method, the wafer includes at least a plurality of diodes, and one electrode terminal of the diode is electrically connected to the metal layer; and at least a part of the arrangement of the solder joints constitutes the diode. Another electrode terminal.
The invention provides a wafer level packaging method for re-layout a solder pad distributed on a top surface of a wafer to be placed in an insulating dielectric layer covering a wafer on a wafer including a plurality of wafers by using a redistribution technique RDL. Aligning the solder joints, comprising the steps of: placing solder bumps on the array solder joints; molding the front surface of the wafer, coating the insulating dielectric layer and the solder bumps on the front surface of the wafer with the first plastic seal layer; Grinding the back side of the wafer; cutting the wafer on the back side of the thinned wafer to form a dicing trench for the spacer wafer, and the dicing trench is stopped in the first molding layer; on the back side of the thinned wafer The wafer is plastically encapsulated to form a second plastic seal layer covering the back side of the thinned wafer, while the molding compound is further filled in the cutting groove; the first plastic sealing layer is ground to expose the solder bump in the first plastic sealing layer Cutting is performed in the cutting groove to separate the wafer.
The above method, after finishing the back grinding of the wafer, further comprising the step of covering a back surface of the thinned wafer with a metal layer; and in the process of forming the dicing trench of the isolation wafer, after thinning the wafer The back surface is covered with a metal layer to cut the wafer; and in forming the second plastic encapsulation layer covering the back side of the thinned wafer, the second plastic encapsulation layer also simultaneously coats the metal layer.
The present invention provides a wafer level package structure in which a solder bump protruding from a top surface of a wafer and electrically connected to a wafer pad is formed on a top surface of the wafer, and further includes: cladding Forming a body on top of the top surface of the wafer, and the solder bumps are exposed in the top molding body; covering the bottom molding body of the wafer, the laterally extending portion of the bottom molding body covers the bottom surface of the wafer, and the bottom portion perpendicular to the laterally extending portion The laterally extending portion of the molding body also covers the sidewalls of the wafer and the sidewalls of the top molding.
The above wafer level package structure further includes a bottom electrode metal layer covering the bottom surface of the wafer, and the lateral extension of the second plastic layer covers the back surface of the wafer while covering the bottom electrode metal layer. In the above wafer level package structure, the wafer is a planar structure IC, and all of its signal input and output terminals are disposed on one side of the top surface of the wafer. In the above wafer level package structure, the wafer is a vertical common drain dual MOSFET; and the drain of one MOSFET of the dual MOSFET and the drain of the other MOSFET are electrically connected through the metal layer, and At least a portion of the array of solder joints respectively constitute a source electrode and a gate electrode of any one of the dual MOSFETs. In the above wafer level packaging structure, the wafer includes at least a plurality of diodes, and one electrode terminal of the diode is electrically connected to the metal layer; and at least a part of the arrangement of solder joints The other electrode terminal of the diode.
The present invention provides a wafer level package structure in which a solder pad distributed on a top surface of a wafer is re-arranged into a solder joint located in a top insulating dielectric layer covering the wafer by using a redistribution technique. The method includes: a top molding body covering a top insulating dielectric layer and a solder bump, wherein the solder bump is disposed on the array solder joint, and the solder bump is exposed in the top molding body; and the bottom molding of the wafer is covered The laterally extending portion of the bottom molding body covers the bottom surface of the wafer, and the laterally extending portion of the bottom molding body perpendicular to the laterally extending portion simultaneously covers the sidewall of the wafer, the sidewall of the top insulating dielectric layer, and the sidewall of the top molding.
The above wafer level package structure further includes a bottom electrode metal layer covering the bottom surface of the wafer, and the laterally extending portion of the bottom molding body covers the bottom surface of the wafer while covering the bottom electrode metal layer.
The invention provides a wafer level package method, in which a solder bump protruding from a front surface of a wafer and electrically connected to a wafer pad is formed on a front surface of a wafer on a wafer including a plurality of wafers The method includes the steps of: cutting on the front side of the wafer to form a cutting groove for isolating the wafer on the front side of the wafer, and stopping the cutting groove in the substrate included in the wafer; performing on the front side of the wafer Molding, forming a first plastic coating layer covering the front side of the wafer, while the molding compound is also filled in a cutting groove on the front side of the wafer; grinding is performed on the back side of the wafer; and the back side of the thinned wafer is The wafer is diced to form a dicing groove for isolating the wafer on the back side of the thinned wafer, and the dicing groove on the back side of the thinned wafer is stopped in the substrate and further filled with The molding compound in the cutting groove on the front side of the wafer is in contact; the wafer is plastic-sealed on the back side of the thinned wafer to form a second plastic coating layer covering the back surface of the thinned wafer, and the molding compound is simultaneously molded Also padded after being thinned In the cutting groove on the back side of the circle; grinding the first plastic sealing layer to expose the solder bump in the thinned first plastic sealing layer; and at the same time in the cutting groove on the front side of the wafer, after being thinned The cutting is performed in the cutting groove on the back side of the wafer to separate the wafer.
The above method is characterized in that after the back side of the wafer is polished, the method further comprises etching on the back side of the thinned wafer and covering a metal layer to the back side of the thinned wafer; In the process of thinning the dicing groove for isolating the wafer on the back side of the wafer, the wafer is diced on the back surface of the thinned wafer covered with the metal layer; and after the coating is thinned During the second plastic encapsulation layer on the back side of the wafer, the second plastic encapsulation layer also simultaneously coats the metal layer.
The invention provides a wafer level packaging method for re-layout a solder pad distributed on a top surface of a wafer to be placed in an insulating dielectric layer covering a wafer on a wafer including a plurality of wafers by using a redistribution technique RDL. The arrangement of the solder joints, the arrangement of the solder joints comprising the first type of solder joints, comprising the steps of: placing solder bumps on the array solder joints; and cutting on the front side of the wafer to form a front side of the wafer for Separating the cutting groove of the wafer, and stopping the cutting groove in the substrate included in the wafer; molding the front surface of the wafer, covering the insulating dielectric layer and the solder bump on the front surface of the wafer with the first plastic sealing layer, The molding compound is also filled in a cutting groove formed on the front side of the wafer; polished on the back side of the wafer; the wafer is cut on the back side of the thinned wafer to form a back surface of the thinned wafer a cutting groove for isolating the wafer on the side, and the cutting groove on the back side of the thinned wafer is stopped in the substrate and further in contact with the molding compound filled in the cutting groove on the front side of the wafer; Less The back side of the wafer is plastically encapsulated to form a second plastic seal layer covering the back side of the thinned wafer, and the molding compound is also filled in the cutting groove on the back side of the thinned wafer; Polishing the first plastic seal layer to expose the solder bumps in the thinned first plastic seal layer; and in the cutting grooves on the front side of the wafer, in the cutting groove on the back side of the thinned wafer The cutting is performed to separate the wafers.
In the above method, after the back side of the wafer is polished, the method further comprises etching on the back side of the thinned wafer and covering a metal layer to the back side of the thinned wafer; and forming the thinned surface In the process of isolating the dicing groove of the wafer on the back side of the wafer, the wafer is cut on the back surface of the thinned wafer covered with the metal layer; and the back surface of the wafer after the thinning is formed In the process of the second plastic seal layer, the second plastic seal layer also covers the metal layer at the same time. The above method further comprises the following steps before covering a metal layer to the back side of the thinned wafer:
Applying a barrier layer on the back side of the thinned wafer and forming an opening in the barrier layer; etching through the opening on the back side of the thinned wafer, the substrate and the insulating medium contained in the wafer Forming a via hole in the layer contacting the first type of solder joints, and removing the barrier layer; filling the metal material into the via hole, and filling a metal layer covered on the back side of the thinned wafer by filling The metal material in the via is electrically connected to the first type of solder joint that is in contact with the via. In the above method, the position of the first type of aligning pads in contact with the vias is located in the insulating dielectric layer over the area of the non-active device cells within the substrate.
The above method further comprises the steps of: coating a layer of insulating dielectric covering the front side of the wafer and a barrier layer arranging the solder joints, and forming a barrier layer in the barrier layer to form the first type of solder bumps; Aligning the openings of the solder joints; etching the first type of solder joints and the insulating dielectric layer and the substrate through the openings, and forming through holes in the substrate and the insulating dielectric layer through the first type of solder joints And removing the barrier layer; then, while the solder bumps are placed on the alignment pads, part of the solder is also filled in the via holes. In the above method, during the polishing process on the back side of the wafer, the solder filled in the via hole is exposed outside the back surface of the thinned wafer, and then a metal layer covered on the back surface of the thinned wafer is filled. The solder in the via is electrically connected to the first type of solder joint that is in contact with the via.
The present invention provides a wafer level package structure in which a solder bump protruding from a top surface of a wafer and electrically connected to a wafer pad is formed on a top surface of the wafer, including: a wafer-covered wafer The top molding body, the laterally extending portion of the top molding body covers the front side of the wafer, and the laterally extending portion of the top molding body perpendicular to the laterally extending portion of the top molding body simultaneously covers a portion of the sidewall of the wafer, and the solder bumps are Exposed in the top molding; covering the bottom molding of the wafer, the lateral extension of the bottom molding covering the bottom surface of the wafer, and the lateral extension of the bottom molding perpendicular to the laterally extending portion of the bottom molding while also wafer A further portion of the side walls are covered, and the laterally extending portions of the top molding body are in contact with the laterally extending portions of the bottom molding body to seal the wafer seamlessly.
The above wafer level package structure further includes a bottom electrode metal layer covering the bottom surface of the wafer, and the laterally extending portion of the bottom molding body covers the bottom surface of the wafer while covering the bottom electrode metal layer. In the above wafer level package structure, the wafer is a planar structure IC, and all of the signal input and output terminals are disposed on one side of the top surface of the wafer. In the above wafer level package structure, the wafer is a vertical common drain dual MOSFET; and the drain of one MOSFET in the dual MOSFET and the drain of the other MOSFET are electrically connected through the bottom electrode metal layer And at least a portion of the array of solder joints respectively constitute a source electrode and a gate electrode of any one of the dual MOSFETs. In the above wafer level packaging structure, the wafer includes at least a plurality of diodes, and one electrode terminal of the diode is electrically connected to the bottom electrode metal layer; and at least a part of the solder joints are arranged The other electrode terminal constituting the diode.
The present invention provides a wafer level package structure in which a solder pad distributed on a top surface of a wafer is re-arranged by using a redistribution technique to form an arrangement of solder joints in a top insulating dielectric layer covering the wafer. The dot comprises a first type of alignment pad, characterized by comprising: a top molding body covering the wafer, a laterally extending portion of the top molding body covering the top insulating dielectric layer, and a top molding perpendicular to the laterally extending portion of the top molding body The lateral extension of the body also covers the sidewall of the top insulating dielectric layer, a portion of the sidewall of the wafer, and the solder bump is exposed in the top molding; the bottom molding of the wafer, the lateral extension of the bottom molding Covering the bottom surface of the wafer, the laterally extending portion of the bottom molding body perpendicular to the laterally extending portion of the bottom molding body simultaneously covers another portion of the sidewall of the wafer, the laterally extending portion of the top molding body and the lateral side of the bottom molding body The extensions are in contact with one another to seal the wafer seamlessly.
The wafer level package structure further includes a bottom electrode metal layer covered on the bottom surface of the wafer, and the laterally extending portion of the bottom molding body covers the bottom surface of the wafer while covering the bottom electrode metal layer. The above-mentioned wafer level package structure further includes: a via hole formed in the substrate unit and the top insulating dielectric layer included in the wafer contacting the first type of solder joint, and the metal material filled in the via hole is connected The first type of solder joints contacted by the holes are electrically connected to the bottom electrode metal layer. In the above wafer level package structure, the through hole further penetrates the first type of arrangement solder joints that are in contact with the through holes; and the planar cross-sectional dimension of the through holes is smaller than the planar size of the arrangement of the solder joints, and the through holes are filled The metal material is an extension of the solder bumps disposed on the first type of solder joints. The above wafer level package structure, wherein the wafer is a vertical MOSFET.
These and other advantages of the present invention will no doubt become apparent to those skilled in the <RTIgt;

參見第1A圖所示，在晶片100頂面的俯視示意圖中，原本沿著晶片100頂面四周的邊緣設計有連接晶片100內部電路的多個焊墊（Bond Pad）101，焊墊101通常為鋁墊（Peripheral pads）用於與外界形成電性接觸，例如在其上直接進行引線鍵合或在其上先沉積Ti/Cu/Ni等的底部金屬層UBM，再進行植球，其可為晶片100內部電路的信號輸入/輸出接觸端子（I/O Pad），或是Power 或Ground的介面等。第1B圖描述了在部分厚度的晶片100的頂面上所設置的焊墊101的截面示意圖。
參見第1C圖所示，利用重分佈技術RDL（Redistribution Layer），將晶片100頂面現有的排列在四周的焊墊101重新設計成任何合理位置的排列焊點104，排列焊點104可被重新分配到晶片100頂面的周邊、兩側或任何一側，甚至是構成矩陣式排列。為了便於理解，第1C圖展示了焊墊101完成重分佈而形成排列焊點104後的俯視示意圖，第1D圖則是焊墊101經RDL處理從新佈局之後位於絕緣介質層102中的截面示意圖，絕緣介質層102覆蓋在晶片100的頂面之上，絕緣介質層102通常為聚醯亞胺材料（Polyimide），排列焊點104可以通過同時生成在絕緣介質層102中的互聯機（Trace）103而相對應的與焊墊101電性連接，同時排列焊點104也可以選擇在RDL之後不與任何焊墊101連接而單獨存在以備後用。互聯機103通常帶有彎曲的路徑，所以第1D圖並未將互聯機103與排列焊點104、焊墊101的具體連接關係描繪出來，但此時一部分與排列焊點104連接的焊墊101與外界進行信號傳輸則依賴於與之相連的排列焊點104。
參見第1B圖及第1E圖所示，焊料凸塊（Solder bump）105直接焊接在晶片100頂面原有的焊墊101上；而第1D圖及第1F圖中，焊料凸塊105卻是焊接在排列焊點104上。
參見第2A圖-第2M圖的一種晶圓級封裝的方法，在第2A圖所示的包含有多個晶片200'的晶圓200上，多顆晶片200'相互彼此鑄造連接在一起並共同形成在晶圓200所包含的矽襯底（或矽基板）200A中，相鄰的晶片通過晶圓正面的劃片槽（Scribe Line，未示出）相互界定彼此間的邊界，晶片200'的焊墊201位於晶圓200正面的一側。利用重分佈技術將分佈在晶片200'頂面的焊墊201重新佈局設計成位於覆蓋晶圓200（同時覆蓋晶片200'）的絕緣介質層202中的排列焊點204，如第2B圖所示。並在排列焊點204上進行植球安置焊料凸塊205，如第2C圖所示。之後於晶圓200的正面進行塑封工藝，以第一塑封層206包覆焊料凸塊205及覆蓋晶圓200正面的絕緣介質層202，如第2D圖所示。之後在晶圓200的背面進行研磨以減薄晶圓200的厚度，例如進行化學機械研磨CMP，如第2E圖所示，晶圓200背面的部分厚度（如D1）被研磨掉，即襯底200A的厚度獲得減薄。再塗覆一層阻擋層207至減薄後的晶圓200的背面，如第2F圖所示，並形成位於阻擋層207中圖案化的開口207'，阻擋層207有多種選擇，如光阻或SiN或SiO2，主要是為了在阻擋層207中形成在垂直方向上對準一部分排列焊點204（如第2G圖中的第一類排列焊點204a）的開口207'，以便利用矽通孔技術（TSV，Through Silicon Via），以阻擋層207作為硬掩膜並通過開口207'於減薄後的晶圓200的背面對襯底200A及絕緣介質層202進行刻蝕，使得在開口207'中暴露的矽襯底200A區域被刻蝕掉，並且刻蝕持續到在開口207'中暴露的絕緣介質層202也被刻蝕掉，直至刻蝕停止在第一類排列焊點204a上，最終在襯底200A及絕緣介質層202中形成接觸第一類排列焊點204a的通孔208。第一類排列焊點204a其實是所有排列焊點204中的一部分，只是第一類排列焊點204a起始並未與晶片200'的任何焊墊201連接而單獨存在，第一類排列焊點204a用於在後續步驟中與形成在晶片200'底面的一些電極或信號端子進行連接，從而將這些電極引導至晶片200'正面的一側。完成通孔208的刻蝕之後移除阻擋層207，其中，通孔208的形成有多種方式，例如幹法刻蝕或濕法刻蝕或鐳射刻蝕；通常在形成通孔208之後，還需要在通孔208的內壁上沉積一層氧化膜的隔離襯墊層，以便後續填充在通孔208中的金屬材料可以通過隔離襯墊層而與環繞在通孔208周圍的的矽襯底區域，即包圍通孔208的襯底200A區域進行絕緣。為了防止通孔208尺寸過大導致第一類排列焊點204a在通孔208中懸空而無法獲得絕緣介質層202的物理支撐，可以控制開口207'的開口尺寸大小，並進一步控制通孔208的平面截面（橫截面）尺寸大小使其小於排列焊點204的平面尺寸大小，從而避免第一類排列焊點204a的脫落。
參見第2H圖-第2I圖所示，填充金屬材料208'至通孔208中，並於減薄後的晶圓200的背面覆蓋一層金屬層209，此時金屬層209接觸通孔208中的金屬材料208'。之後於覆蓋有金屬層209並且是減薄後的晶圓200的背面，對晶圓200進行切割，形成隔離相鄰晶片200'的切割槽210，此時切割刀觸及一定厚度的第一塑封層206，導致切割槽210停止在第一塑封層206中，也即多顆晶片200'此時依靠第一塑封層206而相互連接在一起，同時金屬層209被切割成位於每顆晶片200'底面的底部電極金屬層209'，絕緣介質層202也被切割成位於每顆晶片200'頂面的頂部絕緣介質層202'，如第2J圖所示。再在覆蓋有金屬層209並且是減薄後的晶圓200的背面，對晶圓200進行塑封，儘管此時金屬層209被切割成多個位於每顆晶片200'底面的底部電極金屬層209'，但所有的底部電極金屬層209'仍然共同構成一個整體的金屬層209，從而完成塑封後形成包覆金屬層209的第二塑封層211，具體而言，第二塑封層211包覆位於每顆晶片200'底面的底部電極金屬層209'，與此同時，第二塑封層211所包含的部分塑封料還填充在切割槽210中，如第2K圖所示。
參見第2L圖-第2M圖所示，對第一塑封層206進行研磨以減薄一定厚度（如D2）的第一塑封層206，以將焊料凸塊205在第一塑封層206中予以外露，如焊料凸塊205外露於減薄後的第一塑封層206'。之後於切割槽210中進行切割，第2M圖所示的切割口212即是切割痕跡，而且形成切割口212所利用的切割刀的寬度，是小於形成切割槽210所利用的切割刀的寬度的，從而最終將晶片200'從晶圓200上進行分離下來以獲得多個晶圓級的封裝結構200"A，減薄後的第一塑封層206'在該切割過程中形成覆蓋頂部絕緣介質層202'的頂部塑封體206"，第二塑封層211在該切割過程中形成覆蓋底部電極金屬層209'的底部塑封體211'，而且底部塑封體211'的橫向延伸部分211'a覆蓋底部電極金屬層209'，與橫向延伸部分211'a垂直的側向延伸部分211'b還覆蓋晶片200'的側壁、頂部絕緣介質層202'的側壁、頂部塑封體206"的側壁，其中，底部塑封體211'所包含的側向延伸部分211'b其實是第二塑封層211填充在切割槽210中的一部分塑封料經第2M圖所示的切割過程而形成。
由於在第2J圖-第2M圖所示的製備過程中，晶圓200所包含的襯底200A被切割成晶片200'所包含的襯底單元200'A，所以對於第2M圖所示的晶圓級的封裝結構200"A而言，晶片200'所包含的矽襯底單元200'A中，接觸第一類排列焊點204a的通孔208中所填充的金屬材料208'將與通孔208所接觸的第一類排列焊點204a電性連接至底部電極金屬層209'上。在一個可選實施方式中，晶片200'為垂直式（Vertical structure）的MOSFET，也即其主電流從器件頂部流至底部，或反之亦然。晶片200'的漏區通常形成在襯底單元200'A中靠近晶片200'底面的一側，為了增強底部電極金屬層209'與晶片200'漏區的歐姆接觸，可以在沉積金屬層209至減薄後的晶圓200的背面之前，在減薄後的晶圓200的背面重摻雜植入與漏區摻雜類型相同的離子。由於底部電極金屬層209'接觸靠近晶片200'底面一側的襯底單元200'A中的漏區構成漏極，所以與通孔208所接觸的第一類排列焊點204a由於與MOSFET的漏極電性連接從而構成垂直式MOSFET的漏極電極，並且在所有的排列焊點204中，除了第一類排列焊點204a之外，未構成與通孔208所接觸的排列焊點204中，至少有一部分排列焊點204連接在位於晶片200'頂面一側的MOSFET的柵極與源極上，並分別構成垂直式MOSFET的柵極電極與源極電極。由此可見，為垂直式MOSFET的晶片200'的漏極原本製作在晶片200'底面一側的底部電極金屬層209'上，但是通過通孔208中填充的金屬材料208'將第一類排列焊點204a與底部電極金屬層209'形成電接觸，從而將底漏頂源的垂直結構器件的源、漏極均設置在晶片200'頂面的一側。同樣，如果需要將底源頂漏的垂直結構器件的源、漏極均設置在晶片200'頂面的一側，只要在形成通孔208的時候選定通孔208接觸的第一類排列焊點204a是接觸MOSFET底部的源極即可。值得一提的是，在RDL製備流程中，與通孔208所接觸的第一類排列焊點204a所形成的位置，是位於覆蓋在的矽襯底200A內非有源器件單元區域之上的絕緣介質層202中，這樣刻蝕襯底200A形成通孔208的時候就不至於破壞晶片200'的積體電路單元。具體而言，任意一個通孔208的形成，務必保證通孔208形成在不參與構成晶片200'的電路結構的矽襯底區域中。
為了便於理解，以第1F圖進行解釋，與通孔108所接觸的第一類排列焊點104所形成的位置，是位於覆蓋在的襯底單元100'A內非有源器件單元區域（如R區域）之上的絕緣介質層102中，襯底單元100'A源於對晶片100所在的晶圓所包含的襯底的切割分離。圖中絕緣介質層102所包含的一部分區域102'覆蓋在的襯底單元100'A內非有源器件單元區域之上，第一類排列焊點104則形成在這部分區域102'中。襯底單元100'A所包含的用於容納通孔108的R區域範圍內，其橫向區域（X軸）和縱向區域（Y軸）以及垂直區域（Z軸）內沒有製備或者說不包含晶片100的任何有效電路單元，同時，第一類排列焊點104的平面尺寸選取不大於R區域範圍的平面尺寸（橫向區域和縱向區域）。
參見第3A圖-第3J圖，本發明還提供在第2A圖-第2M圖步驟上進行局部變化的另一種晶圓級封裝的方法，第3A圖所示的晶圓200是在第2B圖示出的晶圓200上塗覆了一層覆蓋位於晶圓200正面一側的絕緣介質層202及排列焊點204的阻擋層213，之後形成位於阻擋層213中的開口213'，並且開口213'接觸排列焊點204中的第一類排列焊點204a，開口213'的形成可以通過對光阻之類的阻擋層213進行光刻，從而選定開口213'在垂直方向上對準第一類排列焊點204a。之後通過開口213'對該第一類排列焊點204a及絕緣介質層202、晶圓200所包含的矽襯底200A進行刻蝕。其中，必須保障開口213'的平面尺寸小於第一類排列焊點204a的平面尺寸，以保證第一類排列焊點204a僅僅是暴露在開口213'中的區域被刻蝕掉而並非第一類排列焊點204a所有的區域完全被刻蝕掉，其結果是，第一類排列焊點204a暴露在開口213'中的區域先被刻蝕掉從而在開口213'暴露出絕緣介質層202，繼續對開口213'中暴露的絕緣介質層202進行刻蝕，直至在開口213'暴露出矽襯底200A，並繼續對開口213'中暴露的矽襯底200A進行刻蝕，並且刻蝕停止在矽襯底200A中，最終在絕緣介質層202、部分厚度的矽襯底200A中形成貫穿該第一類排列焊點204a的通孔214，如第3B圖所示，之後移除阻擋層213。通常在形成通孔214之後，還要在通孔214的內壁上沉積一層氧化膜的隔離襯墊層，以便為後續填充在通孔214中的金屬材料通過隔離襯墊層而與環繞在通孔214周圍的的矽襯底區域進行絕緣。
參見第3C圖所示，在包括第一類排列焊點204a的排列焊點204上安置焊料凸塊205，此過程中，部分焊料214'同時流入並填充在通孔214中，該部分焊料214'與第一類排列焊點204a上的焊料凸塊205鑄造連接在一起，可見焊料214'是安置在與通孔214所接觸的第一類排列焊點204a上的焊料凸塊205的延伸部分。完成上述步驟後，在晶圓200的正面進行塑封，以第一塑封層206包覆焊料凸塊205及覆蓋在晶圓200正面的絕緣介質層202，如第3D圖所示。並於晶圓200的背面進行CMP研磨直至在減薄後的晶圓200的背面外露出填充在通孔214中的焊料214'，如第3E圖所示，晶圓200的部分厚度（如D3）被研磨掉。再於減薄後的晶圓200的背面覆蓋一層金屬層209，如化學氣相沉積，參見第3F圖所示，此時焊料214'與金屬層209保持電性接觸。之後於覆蓋有金屬層209並且是減薄後的晶圓200的背面，對晶圓200進行切割，形成隔離相鄰晶片200'的切割槽210，切割刀在厚度上部分切割第一塑封層206，此時切割槽210停止在第一塑封層206中，如第3G圖所示。多顆晶片200'此時依靠第一塑封層206而相互連接在一起，金屬層209被切割成位於每顆晶片200'底面的底部電極金屬層209'，絕緣介質層202也被切割成位於每顆晶片200'頂面的頂部絕緣介質層202'。再在覆蓋有金屬層209並且是減薄後的晶圓200的背面，對晶圓200進行塑封，此時金屬層209被切割成多個位於每顆晶片200'底面的底部電極金屬層209'，但底部電極金屬層209'仍然共同組成一層整體性的金屬層209，從而完成塑封後形成包覆金屬層209的第二塑封層211，第二塑封層211所包含的部分塑封料同時還填充在切割槽210中。之後如第3I圖所示，研磨第一塑封層206以將焊料凸塊205在減薄後的第一塑封層206'中予以外露，第一塑封層206的部分厚度（如D4）被研磨掉。參見第3J圖，最後於切割槽210中進行切割，以將晶片200'進行分離，獲得第3J圖所示的晶圓級的封裝結構200"B。在一個實施方式中，晶片200'與第2M圖所示的器件並無區別，均為垂直式的MOSFET。晶圓級的封裝結構200"B中，在通孔214形成的刻蝕過程中，所產生的結果是通孔214貫穿與通孔214所接觸的第一類排列焊點204a，以及焊料214'與在第一類排列焊點204a上安置的焊料凸塊205同時生成，並且通孔214中所填充的金屬材料是在第一類排列焊點204a上所安置的焊料凸塊205的延伸部分。
參見第4A圖-第4E圖，本發明還提供在第2E圖所示的減薄後的晶圓200上進行其他工藝步驟的另一種晶圓級封裝的方法，值得注意的是，在此實施例中，是以RDL設計的排列焊點104作為示例，但須注意的是，將第1A圖的晶片100頂面的焊墊101重新設計成排列焊點104並不是必要條件。
參見第4A圖所示，在晶圓200正面的一側進行塑封，以第一塑封層206包覆晶圓200的正面及焊料凸塊205，第一塑封層206同時還覆蓋絕緣介質層202；於晶圓200的背面進行CMP研磨，並在完成晶圓200的背面研磨之後，還包括於減薄後的晶圓200的背面覆蓋一層金屬層209的步驟；之後於覆蓋有金屬層209並且是減薄後的晶圓200的背面，對晶圓200進行切割，形成隔離相鄰晶片200'的切割槽210，部分厚度的第一塑封層206被切割以構成切割槽210位於第一塑封層206中的深度，此時切割槽210停止在第一塑封層206中，也即多顆晶片200'此時依靠第一塑封層206而相互鑄造連接在一起，同時金屬層209被切割成覆蓋每顆晶片200'底面的底部電極金屬層209'，絕緣介質層202也被切割成覆蓋每顆晶片200'頂面的頂部絕緣介質層202'，如第4B圖所示。再在覆蓋有金屬層209並且是減薄後的晶圓200的背面，對晶圓200進行塑封，完成塑封後形成包覆金屬層209的第二塑封層211，同時第二塑封層211所包含的部分塑封料還填充在切割槽210中，如第4C圖所示。再研磨第一塑封層206獲得減薄後的第一塑封層206'，並將焊料凸塊205在減薄後的第一塑封層206'中予以外露，如第4D圖所示。於切割槽210中進行切割，將晶片200'進行分離，獲得第4E圖所示的晶圓級的封裝結構200"C，減薄後的第一塑封層206'在該切割過程中形成覆蓋頂部絕緣介質層202'的頂部塑封體206"。在此實施方式中，不必要選定一些晶片200'頂面的排列焊點204使其通過任何填充有金屬材料的通孔而連接到底部電極金屬層209'，所以，在此類晶片200'的類型中，與外界進行信號傳輸的排列焊點204都在其頂面的一側，而其底面的一側則沒有需要引導至200'頂面一側的信號端子。一個實施例中，晶片200'為垂直式的共漏極的雙MOSFET（Common Drain MOSFET），雙MOSFET中一個MOSFET的漏極與另一個MOSFET的漏極通過底部電極金屬層209'進行電性連接，並且至少一部分排列焊點204分別連接在雙MOSFET中任意一個MOSFET的源極電極和柵極電極上，並構成雙MOSFET中任意一個MOSFET的源極電極和柵極電極。在另一個實施例中，晶片200'中至少包含多個集成在襯底200A中的二極體，並且二極體的一個電極端子共同電性連接在底部電極金屬層209'上形成並聯，這樣至少一部分排列焊點204就分別構成了二極體的另一個電極端子，並且都位於晶片200'正面的一側。封裝結構200"C中，頂部絕緣介質層202'源於絕緣介質層202的切割，利用重分佈技術將分佈在晶片200'頂面的焊墊201重新佈局設計成位於覆蓋晶片的頂部絕緣介質層202'中的排列焊點204，包括減薄後的第一塑封層206'在切割過程中形成覆蓋頂部絕緣介質層202'的頂部塑封體206"，第二塑封層211在切割過程中形成覆蓋底部電極金屬層209'的底部塑封體211'，而且底部塑封體211'的橫向延伸部分211'a覆蓋底部電極金屬層209'，與橫向延伸部分211'a垂直的側向延伸部分211'b還覆蓋晶片200'的側壁、頂部絕緣介質層202'的側壁、頂部塑封體206"的側壁，其中，底部塑封體211'所包含的側向延伸部分211'b其實是第二塑封層211填充在切割槽210中的一部分塑封料經第4E圖所示的切割過程而形成，焊料凸塊205則於頂部塑封體206"中予以外露。
其實，還可以直接在第1A圖的晶片100頂面的焊墊101上安置焊球並進行第4A圖-第4E圖的流程，而且晶片的類型相同，只不過焊墊101是沒有經過RDL進行重新分佈，其間也少了沉積一層絕緣絕緣介質層202的過程，正如第5A圖-第5F圖所示。第5A圖是先在第2A圖所示的晶圓200的焊墊201上直接安置焊球205，從而在晶圓200的正面形成有凸出於晶圓200正面（也即晶片200'的頂面）的並電性連接至晶片200'焊墊201的焊料凸塊205，之後在晶圓200的正面進行塑封，以第一塑封層206包覆晶圓200的正面及焊料凸塊205；並在晶圓200的背面進行CMP研磨，完成研磨之後，還包括於減薄後的晶圓200的背面覆蓋一層金屬層209的步驟，如第5A圖-5B所示。之後於覆蓋有金屬層209並且是減薄後的晶圓200的背面，對晶圓200進行切割，形成隔離相鄰晶片200'的切割槽210，此時部分厚度的第一塑封層206被切割並構成切割槽210位於第一塑封層206中的深度，切割槽210停止在第一塑封層206中，也即多顆晶片200'此時依靠第一塑封層206而相互連接在一起，同時金屬層209被切割成位於每顆晶片200'底面的底部電極金屬層209'。再在覆蓋有金屬層209並且是減薄後的晶圓200的背面，對晶圓200進行塑封，完成塑封後形成包覆金屬層209的第二塑封層211，同時第二塑封層211所包含的部分塑封料還填充在切割槽210中，如第5D圖所示。研磨第一塑封層206以將焊料凸塊205在減薄後的第一塑封層206'中予以外露，如第5E圖所示。在切割槽210中進行切割，將晶片200'進行分離，獲得第5F圖所示的晶圓級的封裝結構200"D。值得注意的是，由於此實施例的步驟中並沒有形成矽通孔TSV，所以無需考慮矽通孔TSV要形成的位置。因此是否將第1A圖的晶片100頂面的焊墊101重新設計成排列焊點104也不是必要條件。封裝結構200"D中，在晶片200'的頂面形成有凸出於晶片200'頂面的並電性連接至晶片200'焊墊201的焊料凸塊205，包括減薄後的第一塑封層206'在切割過程中形成覆蓋晶片200'頂面的頂部塑封體206"，第二塑封層211在切割過程中形成覆蓋底部電極金屬層209'的底部塑封體211'，而且底部塑封體211'的橫向延伸部分211'a覆蓋底部電極金屬層209'，與橫向延伸部分211'a垂直的側向延伸部分211'b覆蓋晶片200'的側壁、頂部塑封體206"的側壁，焊料凸塊205於頂部塑封體206"中予以外露。
參見第6A圖-第6E圖，本發明還提供在第2E圖所示的減薄後的晶圓200上進行其他工藝步驟的另一種晶圓級封裝的方法，值得注意的是，在此實施例中，與4A-4E的區別在於，沒有在減薄後的晶圓200的背面沉積金屬層。
參見第6A圖所示，在晶圓200的正面進行塑封，以第一塑封層206包覆晶圓200的正面及焊料凸塊205，第一塑封層206同時還覆蓋絕緣介質層202；於晶圓200的背面進行CMP研磨，完成背面研磨之後對晶圓200進行切割，形成隔離相鄰晶片200'的切割槽210，此時切割槽210停止在第一塑封層206中，同時絕緣介質層202也被切割成位於每顆晶片200'頂面的頂部絕緣介質層202'，第6B圖所示。再在減薄後的晶圓200的背面，對晶圓200進行塑封，完成塑封後形成第二塑封層211，同時第二塑封層211所包含的部分塑封料還填充在切割槽210中，如第6C圖所示。研磨第一塑封層206以將焊料凸塊205在第一塑封層206中予以外露，如第6D圖所示，焊料凸塊205暴露在減薄後的第一塑封層206'之外。再於切割槽210中進行切割，將晶片200'進行分離，獲得第6E圖所示的晶圓級的封裝結構200"E，減薄後的第一塑封層206'在該切割過程中形成覆蓋頂部絕緣介質層202'的頂部塑封體206"。在此實施方式中，晶圓200減薄後其背面沒有沉積任何金屬層，晶片200'的底面也沒有任何底部電極金屬層，晶片200'的類型為平面結構（Lateral structure）的IC，排列焊點204構成該平面結構的IC的信號端子，其所有的信號輸入輸出端子均設置在晶片200'頂面的一側。封裝結構200"E中，利用重分佈技術將分佈在晶片200'頂面的焊墊201重新佈局設計成位於覆蓋晶片200'的頂部絕緣介質層202'中的排列焊點204，還包括減薄後的第一塑封層206'在切割過程中形成的覆蓋頂部絕緣介質層202'的頂部塑封體206"，第二塑封層211在切割過程中形成覆蓋晶片200'底面的橫向延伸部分211'a，而與橫向延伸部分211'a垂直的側向延伸部分211'b還覆蓋晶片200'的側壁、頂部絕緣介質層202'的側壁、頂部塑封體206"的側壁，焊料凸塊205於頂部塑封體206"中予以外露。
較於第6A圖-6E的流程，在另外一種實施方式中，還可以直接在第1A圖的晶片100頂面的焊墊101上安置焊球並進行第6A圖-第6E圖的流程，只不過焊墊101是沒有經過RDL進行重新分佈，並且少了沉積一層絕緣絕緣介質層202的過程，正如第7A圖-第7E圖所示。如第7A圖所示，在第2A圖所示的晶圓200的焊墊201上直接植焊球205，並於晶圓200的正面進行塑封，以第一塑封層206包覆晶圓200的正面及焊料凸塊205；於晶圓200的背面進行CMP研磨，減薄襯底200A的厚度；之後於減薄後的晶圓200的背面，對晶圓200進行切割，形成隔離相鄰晶片200'的切割槽210，此時切割槽210停止在第一塑封層206中，此時襯底200A被分割成每顆晶片200'所包含的襯底單元200'A。再在減薄後的晶圓200的背面，對晶圓200進行塑封，形成第二塑封層211，同時第二塑封層211所包含的部分塑封料還填充在切割槽210中，如第7C圖所示。研磨第一塑封層206以將焊料凸塊205在減薄後的第一塑封層206'中予以外露，如第7D圖所示。在切割槽210中進行切割，將晶片200'進行分離，獲得第7E圖所示的晶圓級的封裝結構200"F。由於此實施例的步驟中同樣並沒有形成矽通孔TSV，無需考慮矽通孔TSV要形成的位置。因此將第1A圖的晶片100頂面的焊墊101重新設計成排列焊點104並不是必要條件。封裝結構200"F中，晶片200'的類型為平面結構的IC，在晶片200'的頂面形成有凸出於晶片200'頂面的並電性連接至晶片200'焊墊201的焊料凸塊205，包括減薄後的第一塑封層206'在切割過程中形成覆蓋晶片200'頂面的頂部塑封體206"，第二塑封層211在切割過程中形成覆蓋晶片200'底面的底部塑封體211'，底部塑封體211'的橫向延伸部分211'a覆蓋晶片200'底面，與橫向延伸部分211'a垂直的側向延伸部分211'b還覆蓋晶片200'的側壁、頂部塑封體206"的側壁，焊料凸塊205於頂部塑封體206"中予以外露。
以上實施例均是先實施在晶圓的背面的一側進行切割形成切割槽，再對切割槽中的塑封料進行切割從而將晶片進行分離。下述內容將提供先實施在晶圓的正面的一側進行切割，再在晶圓的背面一側進行切割以分離晶片的實施方式。
參見第8A圖-第8I圖的一種晶圓級封裝的方法，在晶圓200的正面形成有凸出於晶圓200正面的並電性連接至晶片200'焊墊201的焊料凸塊205，如第8A圖-第8B圖所示。並於焊墊201上進行植球安置焊料凸塊205，如第8B圖所示，之後於晶圓200的正面進行切割，形成位於晶圓200正面一側的用於隔離晶片200'的切割槽215，並且該切割槽215停止在晶圓200的襯底200A中，相鄰的晶片200'之間切割槽215可以在晶圓正面的劃片槽（Scribe Line）處進行切割形成。之後於晶圓200的正面進行塑封，以第一塑封層206包覆晶圓200的正面及焊料凸塊205，如第8C圖所示，同時第一塑封層206所包含的塑封料還填充在切割槽215中。再在晶圓200的背面進行CMP研磨以減薄晶圓200的厚度，即減薄晶圓200所包含的襯底200A的厚度，如第8D圖所示，晶圓200的部分厚度（如D5）被研磨掉，即襯底200A的厚度獲得減薄，之後可以選擇於減薄後的晶圓200的背面進行蝕刻，以修復其研磨造成的晶格損傷或消除減薄後的晶圓200的背面所殘存的應力層。參見第8E圖所示，於減薄後的晶圓200的背面覆蓋一層金屬層209。之後於覆蓋有金屬層209並且是減薄後的晶圓200的背面，對晶圓200進行切割，形成位於減薄後的晶圓200背面一側的用於隔離晶片200'的切割槽216，且位於減薄後的晶圓200背面一側的切割槽216停止在晶圓200的襯底200A中並進一步與填充在位於晶圓200正面一側的切割槽215中的塑封料接觸，即保持切割槽216與切割槽215在垂直方向上對準並相互接觸，如第8F圖所示。同時金屬層209被切割成覆蓋每顆晶片200'底面的底部電極金屬層209'。於減薄後的晶圓200的背面對晶圓200進行塑封，形成包覆減薄後的晶圓200的背面的第二塑封層211，第二塑封層211還同時包覆金屬層209，同時第二塑封層211所包含的塑封料還填充在位於減薄後的晶圓200背面一側的切割槽216中，如第8G圖所示。之後研磨第一塑封層206以將焊料凸塊205在減薄後的第一塑封層206'中予以外露，獲得第8H圖中減薄的第一塑封層206'。同時於位於晶圓200正面一側的切割槽216中、位於減薄後的晶圓200背面一側的切割槽215中進行切割，將多個晶片200'進行分離以獲得晶圓級的封裝結構200"G，如第8I圖所示，減薄後的第一塑封層206'在該切割過程中形成覆蓋晶片200'正面的頂部塑封體206"。
晶圓級的封裝結構200"G中，包括包覆晶片200'的頂部塑封體206''，頂部塑封體206''的橫向延伸部分206''a覆蓋在晶片200'的正面，與頂部塑封體206''的橫向延伸部分206''a垂直的頂部塑封體206''的側向延伸部分206''b同時還將晶片200'的一部分側壁予以覆蓋，且焊料凸塊205於頂部塑封體206''中予以外露。還包括包覆晶片200'的底部塑封體211'，底部塑封體211'的橫向延伸部分211'a覆蓋在晶片200'的底面，並同時還覆蓋在底部電極金屬層209'上；與底部塑封體211'的橫向延伸部分211'a垂直的底部塑封體211'的側向延伸部分211'b，同時還將晶片200'的另外一部分未被側向延伸部分206''b包覆的側壁予以覆蓋，此時頂部塑封體206''的側向延伸部分206''b與底部塑封體211'的側向延伸部分211'b相互接觸並將晶片200'無縫隙的密封。一種實施方式中，在上述製備流程中取消金屬層209的沉積過程，則後續獲得的器件中就不存在底部電極金屬層209'，此時晶片200'為平面結構的IC，其所有的信號輸入輸出端子均設置在晶片200'頂面的一側。一種實施方式中，包含底部電極金屬層209'的晶片200'則可以為垂直式的共漏極的雙MOSFET；並且雙MOSFET中一個MOSFET的漏極與另一個MOSFET的漏極通過所述底部電極金屬層209'進行電性連接，以及至少一部分排列焊點204分別構成雙MOSFET中任意一個MOSFET的源極電極和柵極電極。一種實施方式中，包含底部電極金屬層209'的晶片200'中至少包含多個二極體，並且所述二極體的一個電極端子共同電性連接在底部電極金屬層上209'，以及至少一部分排列焊點204分別構成所述二極體的另一個電極端子，每一個排列焊點204構成一個二極體的另一個電極端子。
基於第8A圖-第8I圖，封裝體200"G還可以按照第9A圖-第9E圖所示的流程進行製備，完成第8C圖中塑封晶圓200的正面，以第一塑封層206包覆晶圓200的正面及焊料凸塊205之後，如第9A圖所示，先研磨第一塑封層206以將焊料凸塊205在減薄後的第一塑封層206'中予以外露，再在晶圓200的背面進行CMP研磨以減薄晶圓200的厚度，如第9B圖所示。晶圓200的部分厚度（如D6）被研磨掉之後，可以選擇於減薄後的晶圓200的背面進行蝕刻並在減薄後的晶圓200的背面覆蓋一層金屬層209，如第9C圖。之後於覆蓋有金屬層209並且是減薄後的晶圓200的背面，對晶圓200進行切割，形成位於減薄後的晶圓200背面一側的用於隔離晶片200'的切割槽216，且位於減薄後的晶圓200背面一側的切割槽216停止在晶圓200的襯底200A中並進一步與填充在位於晶圓200正面一側的切割槽215中的塑封料接觸，即保持切割槽216與切割槽215在垂直方向上對準並相互接觸，如第9D圖所示。再於減薄後的晶圓200的背面對晶圓200進行塑封，形成包覆減薄後的晶圓200的背面的第二塑封層211，第二塑封層211還同時包覆金屬層209，同時第二塑封層211所包含的塑封料還填充在位於減薄後的晶圓200背面一側的切割槽216中，如第9E圖所示。此時，第9E圖即第8H圖，兩者並無區別。如第8I圖所示的晶圓級的封裝結構200"G中，包括包覆晶片200'的頂部塑封體206"，頂部塑封體206"的橫向延伸部分206"a覆蓋在晶片200'的正面，與頂部塑封體206"的橫向延伸部分206"a垂直的頂部塑封體206"的側向延伸部分206"b同時還將晶片200'的部分側壁予以覆蓋，且焊料凸塊205於頂部塑封體206"中予以外露；第二塑封層211在切割過程中形成覆蓋底部電極金屬層209'的底部塑封體211'，底部塑封體211'的橫向延伸部分211"a覆蓋在晶片200'的底面的底部電極金屬層209'上，與底部塑封體211'的橫向延伸部分211"a垂直的底部塑封體211'的側向延伸部分211"b同時還將晶片200'的另外一部分側壁予以覆蓋，則剛好頂部塑封體206"的側向延伸部分206"b與底部塑封體211'的側向延伸部分211"b相互接觸並將晶片200'無縫隙的密封。
上述第8A圖-第8I圖或第9A圖-第9E圖所示的流程適用於平面結構的IC及垂直結構的MOSFET的製備，並且同樣也適用於經由RDL技術處理或未經過RDL技術處理的晶片的製備。
參見第10A圖-第10G圖的一種晶圓級封裝的方法，結合第1B圖-第1D圖，利用重分佈技術RDL將分佈在晶片200'頂面的焊墊201重新佈局設計成位於覆蓋晶片200'的絕緣介質層202中的排列焊點204，如第10A圖所示。並於排列焊點204上進行植球安置焊料凸塊205，之後於晶圓200的正面進行切割，形成位於晶圓200正面一側的用於隔離晶片200'的切割槽215，並且該切割槽215停止在晶圓200的襯底200A中。之後於晶圓200的正面進行塑封，以第一塑封層206包覆絕緣介質層202及焊料凸塊205，如第10B圖所示，同時第一塑封層206所包含的塑封料還填充在切割槽215中。再在晶圓200的背面進行CMP研磨以減薄晶圓200的厚度，如第10C圖所示，之後可以選擇於減薄後的晶圓200的背面進行蝕刻，並於減薄後的晶圓200的背面覆蓋一層金屬層209。之後於覆蓋有金屬層209並且是減薄後的晶圓200的背面，對晶圓200進行切割，形成位於減薄後的晶圓200背面一側的用於隔離晶片200'的切割槽216，且位於減薄後的晶圓200背面一側的切割槽216停止在晶圓200的襯底200A中並進一步與填充在位於晶圓200正面一側的切割槽215中的塑封料接觸，即保持切割槽216與切割槽215在垂直方向上對準並相互接觸，如第10D圖所示。金屬層209被切割成位於每顆晶片200'底面的底部電極金屬層209'。於減薄後的晶圓200的背面對晶圓200進行塑封，形成包覆減薄後的晶圓200的背面的第二塑封層211，第二塑封層211還同時包覆金屬層209，同時第二塑封層211所包含的塑封料還填充在位於減薄後的晶圓200背面一側的切割槽216中，如第10E圖所示。研磨第一塑封層206以將焊料凸塊205在減薄後的第一塑封層206'中予以外露，獲得第10F圖中減薄的第一塑封層206'。同時於位於晶圓200正面一側的切割槽216中、位於減薄後的晶圓200背面一側的切割槽215中進行切割，將多個晶片200'進行分離以獲得晶圓級的封裝結構200"H，如第10G圖所示，絕緣介質層202也被切割成位於每顆晶片200'頂面的頂部絕緣介質層202'，減薄後的第一塑封層206'在該切割過程中形成覆蓋頂部絕緣介質層202'的頂部塑封體206"，並且晶圓200所包含的襯底200A被切割成每個晶片200'所包含的襯底單元200'A。
第10A圖-第10G圖所示的方法流程中，在覆蓋一層金屬層209至減薄後的晶圓200的背面之前，還可以選擇實施類似2F-2I的步驟：在減薄後的晶圓200的背面塗覆一層阻擋層207，並形成位於阻擋層207中的開口207'；通過開口207'於減薄後的晶圓200的背面進行刻蝕，於晶圓所包含的襯底200A及絕緣介質層202中形成接觸第一類排列焊點204a的通孔208，之後移除阻擋層207；填充金屬材料208'至所述通孔208中，並且於減薄後的晶圓200的背面覆蓋的一層金屬層209通過填充在所述通孔208中的金屬材料208'而電性連接至與通孔208所接觸的第一類排列焊點204a上，此時選擇與通孔208所接觸的所述第一類排列焊點204a的位置，位於覆蓋在的襯底200A內非有源器件單元區域之上的絕緣介質層202中。
第10A圖-第10G圖所示的方法流程中，於排列焊點204上安置焊料凸塊205之前，還可以選擇實施類似第3A圖-第3F圖的步驟：塗覆一層包覆位於晶圓200正面的絕緣介質層202及排列焊點204的阻擋層213，並形成位於阻擋層213中接觸第一類排列焊點204 a的開口213'；通過所述開口213'對所述第一類排列焊點204 a及絕緣介質層202、襯底200A進行刻蝕，於襯底200A及絕緣介質層202中形成貫穿該第一類排列焊點204 a的通孔214，並移除阻擋層213；之後在排列焊點204上安置焊料凸塊205的同時，部分焊料214'還一併填充在所述通孔214中。此流程中，於晶圓200的背面進行研磨過程中，在減薄後的晶圓200的背面外露出填充在通孔214中的焊料214'，並且之後於減薄後的晶圓200的背面覆蓋的一層金屬層209通過填充在通孔214中的焊料214'而電性連接在與通孔214所接觸的第一類排列焊點204 a上。
晶圓級的封裝結構200"H中，包覆晶片200'的頂部塑封體206''，頂部塑封體206''的橫向延伸部分206''a覆蓋在頂部絕緣介質層202'上，與頂部塑封體206''的橫向延伸部分206''a垂直的頂部塑封體206''的側向延伸部分206''b同時還將頂部絕緣介質層202'的側壁、晶片200'的部分側壁予以覆蓋，且焊料凸塊205於頂部塑封體206''中予以外露；及包覆晶片200'的底部塑封體211'，底部塑封體211'的橫向延伸部分211'a覆蓋在晶片200'的底面，與底部塑封體211'的橫向延伸部分211'a垂直的底部塑封體211'的側向延伸部分211'b同時還將晶片200'的另外一部分側壁予以覆蓋，頂部塑封體206''的側向延伸部分206''b與底部塑封體211'的側向延伸部分211'b相互接觸以將晶片200'無縫隙的密封。還包括於晶片200'底面覆蓋的一層底部電極金屬層209'，底部塑封體211'的橫向延伸部分211'a覆蓋晶片200'的底面的同時還覆蓋底部電極金屬層209'。第10G圖中還可以包含有類似第2M圖所示的通孔208，此時晶片200'為垂直式的MOSFET，形成在晶片200'所包含的襯底單元200'A及頂部絕緣介質層202'中接觸第一類排列焊點204a的通孔208，並且通孔208中所填充的金屬材料208'將與通孔208所接觸的第一類排列焊點204a電性連接至所述底部電極金屬層209'上，底部電極金屬層209'構成MOSFET的漏極。如第10H圖所示的晶圓級封裝結構200"H-1。在另一個實施例中，第10G圖中的晶片200'也為垂直式的MOSFET，並且還可以包含有類似第3J圖所示的通孔214，此時通孔214貫穿與通孔214所接觸的第一類排列焊點204a，並將與通孔214所接觸的第一類排列焊點204a電性連接至底部電極金屬層209'上；以及通孔214的平面截面尺寸小於排列焊點204的平面尺寸，且通孔214中所填充的金屬材料是安置在第一類排列焊點204a上的焊料凸塊205的延伸部分，如第10I圖所示的晶圓級封裝結構200"H-2。
上述實施例中，完成對第一塑封層206進行研磨後獲得一個減薄後的第一塑封層206'的頂面，並且該研磨過程中可以選擇將焊料凸塊205進行部分研磨直至焊料凸塊205外露於減薄後的第一塑封層206'，同時焊料凸塊205由於被研磨而形成的表面（未標注）外露於減薄後的第一塑封層206'（也即外露於頂部塑封體206"），且焊料凸塊205的表面與減薄後的第一塑封層206'的頂面（也即頂部塑封體206"的頂面）保持共面。所以所形成的各封裝體中，頂部塑封體206"並未將焊料凸塊205完全包覆住，而是頂部塑封體206"圍繞在焊料凸塊205的側面的周圍，並且頂部塑封體206"的頂面與任意一個焊料凸塊205的外露於頂部塑封體206"的表面共面。在上述實施例中，可以利用不同的塑封材料進行塑封工藝以分別獲得不同塑封材質的第一塑封層206、第二塑封層211。
通過說明和附圖，給出了具體實施方式的特定結構的典型實施例，例如，本案是以MOSFET、共漏極雙MOSFET進行闡述，基於本發明精神，晶片還可作其他類型的轉換。儘管上述發明提出了現有的較佳實施例，然而，這些內容並不作為局限。
對於本領域的技術人員而言，閱讀上述說明後，各種變化和修正無疑將顯而易見。因此，所附的申請專利範圍應看作是涵蓋本發明的真實意圖和範圍的全部變化和修正。在申請專利範圍範圍內任何和所有等價的範圍與內容，都應認為仍屬本發明的意圖和範圍內。

Referring to FIG. 1A, in a top plan view of the top surface of the wafer 100, a plurality of bond pads 101 connecting the internal circuits of the wafer 100 are originally designed along the edges of the top surface of the wafer 100. The pads 101 are usually The aluminum pad is used for making electrical contact with the outside, for example, directly bonding the wire thereon or depositing a bottom metal layer UBM of Ti/Cu/Ni or the like thereon, and then performing ball implantation, which may be The signal input/output contact terminal (I/O Pad) of the internal circuit of the chip 100, or the interface of the Power or Ground. FIG. 1B depicts a schematic cross-sectional view of a pad 101 disposed on the top surface of a portion of the wafer 100 having a thickness.
Referring to FIG. 1C, the existing solder pads 101 arranged on the top surface of the wafer 100 are redesigned into the solder joints 104 at any reasonable position by using the redistribution layer RDL (Redistribution Layer). The array pads 104 can be re-arranged. Distributed to the perimeter, sides, or either side of the top surface of the wafer 100, even forming a matrix arrangement. For ease of understanding, FIG. 1C shows a schematic top view of the pad 101 after it has been redistributed to form the aligning pads 104. FIG. 1D is a schematic cross-sectional view of the pad 101 in the insulating dielectric layer 102 after being newly laid out by RDL processing. The insulating dielectric layer 102 is overlaid on the top surface of the wafer 100. The insulating dielectric layer 102 is typically a polyimide material. The array solder joints 104 can be formed by interconnecting the traces 103 in the insulating dielectric layer 102. Correspondingly, the pads 101 are electrically connected, and the solder pads 104 may be arranged to be separately connected to the pads 101 after the RDL and used separately for later use. The interconnector 103 usually has a curved path. Therefore, the first connection diagram does not depict the specific connection relationship between the interconnector 103 and the array pad 104 and the pad 101, but at this time, a portion of the pad 101 connected to the array pad 104 is formed. Signal transmission to the outside world depends on the array of solder joints 104 connected thereto.
Referring to FIGS. 1B and 1E, the solder bumps 105 are directly soldered to the pads 101 on the top surface of the wafer 100. In the first and the first F, the solder bumps 105 are Soldered on the aligned pads 104.
Referring to a method of wafer level packaging in FIGS. 2A-2M, on a wafer 200 including a plurality of wafers 200' shown in FIG. 2A, a plurality of wafers 200' are cast and connected to each other and together. Formed in the germanium substrate (or germanium substrate) 200A included in the wafer 200, adjacent wafers define a boundary between each other through a scribe groove (not shown) on the front side of the wafer, the wafer 200' The pad 201 is located on one side of the front side of the wafer 200. The solder pads 201 distributed on the top surface of the wafer 200' are re-arranged by the redistribution technique to form the solder joints 204 in the insulating dielectric layer 202 covering the wafer 200 (while covering the wafer 200'), as shown in FIG. 2B. . The solder bumps 205 are placed on the alignment pads 204 as shown in FIG. 2C. Thereafter, a molding process is performed on the front surface of the wafer 200, and the solder bumps 205 and the insulating dielectric layer 202 covering the front surface of the wafer 200 are covered with the first molding layer 206, as shown in FIG. 2D. Thereafter, polishing is performed on the back side of the wafer 200 to thin the thickness of the wafer 200, for example, chemical mechanical polishing CMP, as shown in FIG. 2E, a portion of the thickness of the back surface of the wafer 200 (eg, D 1 ) is ground off, that is, the thickness of the substrate 200A is thinned. A barrier layer 207 is further applied to the back side of the thinned wafer 200, as shown in FIG. 2F, and an opening 207' is formed in the barrier layer 207. The barrier layer 207 has various options such as photoresist or SiN or SiO2 is mainly for forming an opening 207' in the barrier layer 207 which is aligned in a vertical direction with a part of the arrangement of the solder joints 204 (such as the first type of arrangement solder joints 204a in FIG. 2G) in order to utilize the through-hole technology. (TSV, Through Silicon Via), with the barrier layer 207 as a hard mask and etching the substrate 200A and the insulating dielectric layer 202 through the opening 207' on the back side of the thinned wafer 200, so that in the opening 207' The exposed germanium substrate 200A region is etched away, and etching continues until the insulating dielectric layer 202 exposed in the opening 207' is also etched away until the etch stops on the first type of solder joint 204a, ultimately A through hole 208 contacting the first type of arrangement pad 204a is formed in the substrate 200A and the insulating dielectric layer 202. The first type of solder joint 204a is actually a part of all the solder joints 204, except that the first type of solder joints 204a are not separately connected to any of the pads 201 of the wafer 200', and the first type of solder joints are present. 204a is used to connect some of the electrodes or signal terminals formed on the bottom surface of the wafer 200' in a subsequent step to direct the electrodes to the side of the front side of the wafer 200'. After the etching of the via hole 208 is completed, the barrier layer 207 is removed, wherein the via hole 208 is formed in various manners, such as dry etching or wet etching or laser etching; generally, after the via hole 208 is formed, An isolation liner layer of an oxide film is deposited on the inner wall of the via hole 208, so that the metal material subsequently filled in the via hole 208 can pass through the spacer liner layer and the germanium substrate region surrounding the via hole 208. That is, the region of the substrate 200A surrounding the via 208 is insulated. In order to prevent the size of the through hole 208 from being too large, the first type of arrangement pad 204a is suspended in the through hole 208 to obtain physical support of the insulating dielectric layer 202, the opening size of the opening 207' can be controlled, and the plane of the through hole 208 can be further controlled. The cross-section (cross-section) is sized such that it is smaller than the planar size of the array of solder joints 204, thereby avoiding the shedding of the first type of array pads 204a.
Referring to FIG. 2H to FIG. 2I, the metal material 208' is filled into the via hole 208, and a metal layer 209 is covered on the back surface of the thinned wafer 200. At this time, the metal layer 209 contacts the via hole 208. Metal material 208'. Thereafter, after the metal layer 209 is covered and the back surface of the thinned wafer 200 is cut, the wafer 200 is cut to form a cutting groove 210 that isolates the adjacent wafer 200'. At this time, the cutting blade touches a certain thickness of the first plastic sealing layer. 206, causing the cutting groove 210 to stop in the first molding layer 206, that is, the plurality of wafers 200' are connected to each other by the first molding layer 206 at the same time, while the metal layer 209 is cut into the bottom surface of each of the wafers 200' The bottom electrode metal layer 209', the dielectric dielectric layer 202 is also cut into a top insulating dielectric layer 202' on the top surface of each wafer 200', as shown in FIG. 2J. The wafer 200 is then encapsulated on the back side of the wafer 200 that is covered with the metal layer 209 and is thinned, although the metal layer 209 is now diced into a plurality of bottom electrode metal layers 209 located on the bottom surface of each wafer 200'. ', but all of the bottom electrode metal layers 209' still form a unitary metal layer 209, thereby completing the second molding layer 211 forming the cladding metal layer 209 after molding, specifically, the second plastic sealing layer 211 is located The bottom electrode metal layer 209' of the bottom surface of each wafer 200', at the same time, a part of the molding compound contained in the second plastic sealing layer 211 is also filled in the cutting groove 210, as shown in Fig. 2K.
Referring to FIG. 2L - FIG. 2M, the first plastic seal layer 206 is ground to reduce a certain thickness (eg, D 2 The first plastic encapsulation layer 206 is to expose the solder bumps 205 in the first molding layer 206, such as the solder bumps 205 being exposed to the thinned first molding layer 206'. Thereafter, the cutting is performed in the cutting groove 210, and the cutting opening 212 shown in FIG. 2M is a cutting mark, and the width of the cutting blade used to form the cutting opening 212 is smaller than the width of the cutting blade used to form the cutting groove 210. Thus, the wafer 200' is finally separated from the wafer 200 to obtain a plurality of wafer level package structures 200"A, and the thinned first plastic seal layer 206' forms a top insulating dielectric layer during the cutting process. a top molding body 206" of 202', the second plastic sealing layer 211 forms a bottom molding body 211' covering the bottom electrode metal layer 209' during the cutting process, and the laterally extending portion 211'a of the bottom molding body 211' covers the bottom electrode The metal layer 209', the laterally extending portion 211'b perpendicular to the laterally extending portion 211'a also covers the sidewall of the wafer 200', the sidewall of the top insulating dielectric layer 202', the sidewall of the top molding 206", wherein the bottom molding The laterally extending portion 211'b included in the body 211' is actually formed by a part of the molding compound filled in the cutting groove 210 by the second plastic sealing layer 211 through the cutting process shown in FIG. 2M.
Since the substrate 200A included in the wafer 200 is cut into the substrate unit 200'A included in the wafer 200' in the preparation process shown in FIGS. 2J to 2M, the crystal shown in FIG. 2M is In the case of the circular package structure 200"A, in the germanium substrate unit 200'A included in the wafer 200', the metal material 208' filled in the via hole 208 contacting the first type of solder joint 204a will be connected to the via hole. The first type of alignment pads 204a contacted by 208 are electrically connected to the bottom electrode metal layer 209'. In an alternative embodiment, the wafer 200' is a vertical structure MOSFET, that is, its main current is from The top of the device flows to the bottom, or vice versa. The drain region of the wafer 200' is typically formed on the side of the substrate unit 200'A near the bottom surface of the wafer 200' in order to enhance the bottom electrode metal layer 209' and the wafer 200' drain region. The ohmic contact may be heavily doped with ions of the same type of doping and drain doping on the back side of the thinned wafer 200 before depositing the metal layer 209 to the back side of the thinned wafer 200. The metal layer 209' contacts the drain region in the substrate unit 200'A near the bottom surface of the wafer 200'. Forming a drain, so the first type of solder joint 204a in contact with the via 208 is electrically connected to the drain of the MOSFET to form the drain electrode of the vertical MOSFET, and in all of the array pads 204, except Of the arrangement of the solder joints 204 that are not in contact with the vias 208, at least a portion of the array pads 204 are connected to the gate and source of the MOSFET on the top side of the wafer 200'. And forming the gate electrode and the source electrode of the vertical MOSFET respectively. It can be seen that the drain of the wafer 200' which is a vertical MOSFET is originally formed on the bottom electrode metal layer 209' on the bottom side of the wafer 200', but passes through The metal material 208' filled in the via 208 electrically contacts the first type of alignment pads 204a with the bottom electrode metal layer 209', thereby placing the source and drain of the bottom structure of the bottom drain device in the wafer 200'. Similarly, if it is necessary to set the source and the drain of the vertical structure device with the bottom drain of the bottom source on one side of the top surface of the wafer 200', as long as the via hole 208 is selected when the via hole 208 is formed. The first type of arrangement of solder joints 204a is contact MOSF The source of the bottom of the ET is sufficient. It is worth mentioning that in the RDL preparation process, the position formed by the first type of solder joint 204a in contact with the via 208 is located in the covered germanium substrate 200A. In the insulating dielectric layer 202 over the active device cell region, the etched substrate 200A is formed such that the integrated circuit 208 is formed without damaging the integrated circuit unit of the wafer 200'. Specifically, the formation of any one of the via holes 208 It is necessary to ensure that the via hole 208 is formed in the germanium substrate region which does not participate in the circuit structure constituting the wafer 200'.
For ease of understanding, as explained in FIG. 1F, the position formed by the first type of alignment pads 104 in contact with the vias 108 is located in the area of the non-active device cells within the covered substrate unit 100'A (eg, In the insulating dielectric layer 102 over the R region, the substrate unit 100'A is derived from the dicing separation of the substrate contained in the wafer on which the wafer 100 is located. A portion of the region 102' included in the insulating dielectric layer 102 is overlying the non-active device cell region within the substrate unit 100'A, and a first type of solder joint 104 is formed in the portion 102'. The area of the R region included in the substrate unit 100'A for accommodating the through hole 108 is not prepared or included in the lateral region (X axis) and the vertical region (Y axis) and the vertical region (Z axis). At any effective circuit unit of 100, at the same time, the planar size of the first type of solder joints 104 is selected to be no larger than the planar size (lateral area and longitudinal area) of the R area.
Referring to FIGS. 3A-3J, the present invention also provides another method of wafer level packaging which is locally changed in the steps of FIGS. 2A-2M, and the wafer 200 shown in FIG. 3A is in FIG. 2B. The illustrated wafer 200 is coated with a barrier layer 213 covering the insulating dielectric layer 202 on the front side of the wafer 200 and arranging the solder joints 204, and then forming an opening 213' in the barrier layer 213, and the opening 213' is in contact. Arranging the first type of solder joints 204a in the solder joints 204, the openings 213' may be formed by photolithography of the barrier layer 213 such as photoresist, so that the selected openings 213' are aligned in the vertical direction with the first type of alignment soldering. Point 204a. Thereafter, the first type of bonding pads 204a and the insulating dielectric layer 202 and the germanium substrate 200A included in the wafer 200 are etched through the opening 213'. Wherein, it is necessary to ensure that the planar size of the opening 213' is smaller than the planar size of the first type of solder joint 204a to ensure that the first type of the solder joint 204a is only etched away from the opening 213' and is not the first type. All of the regions of the alignment pads 204a are completely etched away. As a result, the regions of the first type of alignment pads 204a exposed in the openings 213' are first etched away to expose the dielectric layer 202 at the openings 213'. The insulating dielectric layer 202 exposed in the opening 213' is etched until the germanium substrate 200A is exposed at the opening 213', and the germanium substrate 200A exposed in the opening 213' is continuously etched, and the etching is stopped at 矽In the substrate 200A, a via hole 214 penetrating the first-type array pad 204a is finally formed in the insulating dielectric layer 202 and the partial thickness germanium substrate 200A, as shown in FIG. 3B, after which the barrier layer 213 is removed. Usually, after the via hole 214 is formed, an isolation liner layer of an oxide film is deposited on the inner wall of the via hole 214 to pass through the spacer layer for the metal material subsequently filled in the via hole 214. The germanium substrate region around the aperture 214 is insulated.
Referring to FIG. 3C, solder bumps 205 are disposed on the alignment pads 204 including the first type of alignment pads 204a. During this process, a portion of the solder 214' simultaneously flows into and fills the vias 214. 'The solder bumps 205 on the first type of solder joints 204a are cast and joined together, and the solder 214' is visible as an extension of the solder bumps 205 disposed on the first type of solder joints 204a in contact with the vias 214. . After the above steps are completed, the front surface of the wafer 200 is plastic-sealed, and the solder bump 205 and the insulating dielectric layer 202 covering the front surface of the wafer 200 are covered with the first plastic sealing layer 206, as shown in FIG. 3D. And performing CMP polishing on the back surface of the wafer 200 until the solder 214' filled in the via hole 214 is exposed outside the back surface of the thinned wafer 200. As shown in FIG. 3E, a part of the thickness of the wafer 200 (such as D) 3 ) is ground off. The back side of the thinned wafer 200 is then covered with a metal layer 209, such as chemical vapor deposition, as shown in FIG. 3F, at which point the solder 214' remains in electrical contact with the metal layer 209. Thereafter, after the metal layer 209 is covered and the back surface of the thinned wafer 200 is cut, the wafer 200 is cut to form a cutting groove 210 that isolates the adjacent wafer 200'. The cutting blade partially cuts the first plastic sealing layer 206 in thickness. At this time, the cutting groove 210 is stopped in the first molding layer 206 as shown in FIG. 3G. The plurality of wafers 200' are now connected to each other by means of a first plastic encapsulation layer 206, which is cut into a bottom electrode metal layer 209' located on the bottom surface of each wafer 200', and the dielectric dielectric layer 202 is also cut into A top insulating dielectric layer 202' on the top surface of the wafer 200'. The wafer 200 is further encapsulated on the back side of the wafer 200 covered with the metal layer 209 and thinned, at which time the metal layer 209 is diced into a plurality of bottom electrode metal layers 209' located on the bottom surface of each wafer 200'. However, the bottom electrode metal layer 209' still collectively constitutes a monolithic metal layer 209, thereby completing the second molding layer 211 of the cladding metal layer 209 after the plastic molding, and the part of the molding compound contained in the second plastic sealing layer 211 is also filled. In the cutting groove 210. Thereafter, as shown in FIG. 3I, the first molding layer 206 is ground to expose the solder bumps 205 in the thinned first molding layer 206', and a portion of the thickness of the first molding layer 206 (eg, D 4 ) is ground off. Referring to FIG. 3J, a dicing is finally performed in the dicing trench 210 to separate the wafer 200' to obtain a wafer level package structure 200"B as shown in FIG. 3J. In one embodiment, the wafer 200' and the The devices shown in Figure 2M are indistinguishable and are vertical MOSFETs. In the wafer-level package structure 200"B, in the etching process formed by the vias 214, the result is that the vias 214 are through and through. The first type of solder joints 204a contacted by the holes 214, and the solder 214' are simultaneously formed with the solder bumps 205 disposed on the first type of solder joints 204a, and the metal material filled in the vias 214 is at the first The extension of the solder bumps 205 disposed on the solder joints 204a is arranged.
Referring to FIG. 4A to FIG. 4E, the present invention also provides another wafer level packaging method for performing other process steps on the thinned wafer 200 shown in FIG. 2E, and it is worth noting that it is implemented herein. In the example, the arrangement of the solder joints 104 of the RDL design is taken as an example, but it should be noted that it is not necessary to redesign the pads 101 on the top surface of the wafer 100 of FIG. 1A to arrange the solder joints 104.
As shown in FIG. 4A, the front side of the wafer 200 is plastically encapsulated, and the front surface of the wafer 200 and the solder bumps 205 are covered by the first plastic sealing layer 206, and the first plastic sealing layer 206 also covers the insulating dielectric layer 202; CMP polishing is performed on the back side of the wafer 200, and after the back surface polishing of the wafer 200 is completed, a step of covering the back surface of the thinned wafer 200 with a metal layer 209 is further included; after that, the metal layer 209 is covered and After the thinned back surface of the wafer 200, the wafer 200 is cut to form a cutting groove 210 that isolates the adjacent wafer 200', and a portion of the thickness of the first plastic sealing layer 206 is cut to form the cutting groove 210 at the first plastic sealing layer 206. In the depth, the cutting groove 210 is stopped in the first molding layer 206, that is, the plurality of wafers 200' are cast and joined to each other by the first molding layer 206, and the metal layer 209 is cut to cover each The bottom electrode metal layer 209' of the bottom surface of the wafer 200', the insulating dielectric layer 202 is also cut to cover the top insulating dielectric layer 202' of the top surface of each wafer 200', as shown in FIG. 4B. Further, after the metal layer 209 is covered and the back surface of the wafer 200 is thinned, the wafer 200 is plastic-sealed to form a second plastic sealing layer 211 covering the metal layer 209 after molding, and the second plastic sealing layer 211 is included. A portion of the molding compound is also filled in the cutting groove 210 as shown in Fig. 4C. The first plastic encapsulation layer 206 is further ground to obtain a thinned first encapsulation layer 206', and the solder bumps 205 are exposed in the thinned first encapsulation layer 206', as shown in FIG. 4D. Cutting is performed in the cutting groove 210 to separate the wafer 200' to obtain a wafer level package structure 200"C shown in FIG. 4E, and the thinned first plastic sealing layer 206' is formed to cover the top portion during the cutting process. The top molding body 206" of the insulating dielectric layer 202'. In this embodiment, it is not necessary to select the alignment pads 204 of the top surface of the wafer 200' to be connected to the bottom electrode metal layer 209' through any via filled with metal material, so that in the wafer 200' In the type, the array pads 204 for signal transmission from the outside are on one side of the top surface, and one side of the bottom surface has no signal terminals to be guided to the top side of the 200'. In one embodiment, the wafer 200' is a vertical common drain dual MOSFET (Common Drain MOSFET). The drain of one MOSFET in the dual MOSFET is electrically connected to the drain of the other MOSFET through the bottom electrode metal layer 209'. And at least a portion of the arrangement pads 204 are respectively connected to the source electrode and the gate electrode of any one of the dual MOSFETs, and constitute a source electrode and a gate electrode of any one of the dual MOSFETs. In another embodiment, the wafer 200' includes at least a plurality of diodes integrated in the substrate 200A, and one electrode terminal of the diode is electrically connected in common to form a parallel connection on the bottom electrode metal layer 209'. At least a portion of the array of solder joints 204 respectively constitute the other electrode terminal of the diode and are located on the side of the front side of the wafer 200'. In the package structure 200"C, the top insulating dielectric layer 202' is derived from the dicing of the insulating dielectric layer 202, and the solder pads 201 distributed on the top surface of the wafer 200' are re-arranged by the redistribution technique to be located on the top insulating dielectric layer covering the wafer. The alignment solder joint 204 in 202' includes a thinned first plastic seal layer 206' forming a top molding body 206" covering the top insulating dielectric layer 202' during the cutting process, and the second plastic sealing layer 211 forms a cover during the cutting process. The bottom electrode metal layer 209' has a bottom molding body 211', and the laterally extending portion 211'a of the bottom molding body 211' covers the bottom electrode metal layer 209', and the laterally extending portion 211'b perpendicular to the laterally extending portion 211'a The sidewall of the wafer 200', the sidewall of the top insulating dielectric layer 202', and the sidewall of the top molding 206" are also covered, wherein the laterally extending portion 211'b included in the bottom molding 211' is actually filled with the second molding layer 211. A portion of the molding compound in the cutting groove 210 is formed by the cutting process shown in Fig. 4E, and the solder bumps 205 are exposed in the top molding body 206".
In fact, it is also possible to directly place the solder balls on the pads 101 on the top surface of the wafer 100 of FIG. 1A and perform the processes of FIGS. 4A-4E, and the types of the wafers are the same, except that the pads 101 are not subjected to RDL. The redistribution also eliminates the process of depositing a layer of insulating dielectric material 202, as shown in Figures 5A-5F. 5A is a view in which the solder ball 205 is directly placed on the pad 201 of the wafer 200 shown in FIG. 2A, so that a front surface of the wafer 200 is formed on the front surface of the wafer 200 (that is, the top of the wafer 200'). And electrically connected to the solder bump 205 of the wafer 200' pad 201, and then plastically sealed on the front side of the wafer 200, covering the front surface of the wafer 200 and the solder bump 205 with the first plastic sealing layer 206; The CMP polishing is performed on the back surface of the wafer 200, and after the polishing is completed, the step of covering the back surface of the thinned wafer 200 with a metal layer 209 is also shown, as shown in FIGS. 5A-5B. Thereafter, after the metal layer 209 is covered and the back side of the thinned wafer 200 is cut, the wafer 200 is cut to form a cutting groove 210 that isolates the adjacent wafer 200', at which time the partial thickness of the first molding layer 206 is cut. And forming the depth of the cutting groove 210 in the first plastic sealing layer 206, the cutting groove 210 is stopped in the first plastic sealing layer 206, that is, the plurality of wafers 200' are connected to each other by the first plastic sealing layer 206 at the same time, and the metal Layer 209 is cut into a bottom electrode metal layer 209' located on the bottom surface of each wafer 200'. Further, after the metal layer 209 is covered and the back surface of the wafer 200 is thinned, the wafer 200 is plastic-sealed to form a second plastic sealing layer 211 covering the metal layer 209 after molding, and the second plastic sealing layer 211 is included. A portion of the molding compound is also filled in the cutting groove 210 as shown in Fig. 5D. The first molding layer 206 is ground to expose the solder bumps 205 in the thinned first molding layer 206' as shown in FIG. 5E. Cutting is performed in the dicing groove 210, and the wafer 200' is separated to obtain a wafer-level package structure 200"D shown in FIG. 5F. It is noted that the boring hole is not formed in the step of this embodiment. TSV, so there is no need to consider the position where the via TSV is to be formed. Therefore, it is not necessary to redesign the pad 101 on the top surface of the wafer 100 of FIG. 1A to arrange the pads 104. The package structure 200"D, in the wafer The top surface of the 200' is formed with solder bumps 205 protruding from the top surface of the wafer 200' and electrically connected to the wafer 200' pads 201, including the thinned first plastic sealing layer 206' forming a cover during the cutting process. The top molding body 206" of the top surface of the wafer 200', the second plastic sealing layer 211 forms a bottom molding body 211' covering the bottom electrode metal layer 209' during the cutting process, and the laterally extending portion 211'a of the bottom molding body 211' is covered. The bottom electrode metal layer 209', the laterally extending portion 211'b perpendicular to the laterally extending portion 211'a covers the sidewall of the wafer 200', the sidewall of the top molding 206", and the solder bump 205 is in the top molding 206" Exposed.
Referring to FIGS. 6A-6E, the present invention also provides another wafer level packaging method for performing other process steps on the thinned wafer 200 shown in FIG. 2E. It is worth noting that the implementation is performed here. In the example, the difference from 4A-4E is that no metal layer is deposited on the back side of the thinned wafer 200.
As shown in FIG. 6A, the front surface of the wafer 200 is plastic-sealed, and the front surface of the wafer 200 and the solder bumps 205 are covered by the first plastic sealing layer 206. The first plastic sealing layer 206 also covers the insulating dielectric layer 202. The back surface of the circle 200 is subjected to CMP polishing, and after the back surface polishing is completed, the wafer 200 is cut to form a cutting groove 210 that isolates the adjacent wafer 200'. At this time, the cutting groove 210 is stopped in the first molding layer 206 while the insulating dielectric layer 202 is It is also cut into a top insulating dielectric layer 202' located on the top surface of each wafer 200', as shown in Fig. 6B. Then, on the back surface of the thinned wafer 200, the wafer 200 is plastically sealed to form a second plastic sealing layer 211 after the plastic molding is completed, and a part of the molding compound contained in the second plastic sealing layer 211 is further filled in the cutting groove 210, such as Figure 6C shows. The first molding layer 206 is ground to expose the solder bumps 205 in the first molding layer 206. As shown in FIG. 6D, the solder bumps 205 are exposed outside the thinned first molding layer 206'. The dicing is further performed in the dicing trench 210 to separate the wafer 200' to obtain a wafer level package structure 200"E as shown in FIG. 6E, and the thinned first plastic sealing layer 206' forms a cover during the dicing process. The top molding body 206" of the top insulating dielectric layer 202'. In this embodiment, after the wafer 200 is thinned, no metal layer is deposited on the back surface, and the bottom surface of the wafer 200' does not have any bottom electrode metal layer. The wafer 200' is a flat structure IC, and the array is soldered. A dot 204 constitutes a signal terminal of the IC of the planar structure, and all of the signal input and output terminals are disposed on one side of the top surface of the wafer 200'. In the package structure 200"E, the solder pads 201 distributed on the top surface of the wafer 200' are re-arranged by the redistribution technique to form the solder joints 204 in the top insulating dielectric layer 202' of the cover wafer 200', and also include thinning The first first molding layer 206' is formed in the cutting process to cover the top molding body 206' of the top insulating dielectric layer 202'. The second molding layer 211 forms a laterally extending portion 211'a covering the bottom surface of the wafer 200' during the cutting process. The laterally extending portion 211'b perpendicular to the laterally extending portion 211'a also covers the sidewall of the wafer 200', the sidewall of the top insulating dielectric layer 202', the sidewall of the top molding 206", and the solder bump 205 is molded on top Body 206" is exposed.
Compared with the flow of FIG. 6A-6E, in another embodiment, the solder ball can be placed directly on the pad 101 on the top surface of the wafer 100 of FIG. 1A and the flow of FIG. 6A to FIG. 6E can be performed. However, the pad 101 is redistributed without passing through the RDL, and the process of depositing an insulating dielectric layer 202 is less, as shown in Figures 7A-7E. As shown in FIG. 7A, the ball 205 is directly implanted on the pad 201 of the wafer 200 shown in FIG. 2A, and is molded on the front surface of the wafer 200 to cover the wafer 200 with the first molding layer 206. The front surface and the solder bump 205 are CMP-polished on the back surface of the wafer 200 to thin the thickness of the substrate 200A; then, on the back surface of the thinned wafer 200, the wafer 200 is diced to form an isolated adjacent wafer 200. The cutting groove 210, at which time the cutting groove 210 is stopped in the first molding layer 206, at which time the substrate 200A is divided into the substrate unit 200'A included in each of the wafers 200'. Further, on the back surface of the thinned wafer 200, the wafer 200 is plastically sealed to form a second plastic sealing layer 211, and a part of the molding compound contained in the second plastic sealing layer 211 is further filled in the cutting groove 210, as shown in FIG. 7C. Shown. The first molding layer 206 is ground to expose the solder bumps 205 in the thinned first molding layer 206' as shown in FIG. 7D. The dicing is performed in the dicing trench 210 to separate the wafer 200' to obtain the wafer-level package structure 200"F shown in Fig. 7E. Since the step of the embodiment does not form the 矽 via hole TSV, it is not necessary to consider The location where the via TSV is to be formed. Therefore, it is not necessary to redesign the pad 101 on the top surface of the wafer 100 of FIG. 1A to arrange the pads 104. In the package structure 200"F, the type of the wafer 200' is a planar structure. IC, on the top surface of the wafer 200' is formed with solder bumps 205 protruding from the top surface of the wafer 200' and electrically connected to the wafer 200' pads 201, including the thinned first plastic layer 206' During the cutting process, a top molding body 206" covering the top surface of the wafer 200' is formed. The second plastic sealing layer 211 forms a bottom molding body 211' covering the bottom surface of the wafer 200' during the cutting process, and a laterally extending portion 211' of the bottom molding body 211'. a covering the bottom surface of the wafer 200', the laterally extending portion 211'b perpendicular to the laterally extending portion 211'a also covers the sidewall of the wafer 200', the sidewall of the top molding 206", and the solder bumps 205 in the top molding 206" Be exposed.
In the above embodiments, the cutting groove is formed on one side of the back surface of the wafer, and the molding compound in the cutting groove is cut to separate the wafer. The following will provide an embodiment in which a side of the front side of the wafer is cut and then cut on the back side of the wafer to separate the wafer.
Referring to a method of wafer level packaging according to FIG. 8A to FIG. 8I, a solder bump 205 protruding from the front surface of the wafer 200 and electrically connected to the wafer 200' pad 201 is formed on the front surface of the wafer 200, As shown in Figure 8A - Figure 8B. And soldering the solder bumps 205 on the solder pads 201, as shown in FIG. 8B, and then cutting on the front side of the wafer 200 to form a cutting trench for isolating the wafer 200' on the front side of the wafer 200. 215, and the cutting groove 215 is stopped in the substrate 200A of the wafer 200, and the cutting groove 215 between the adjacent wafers 200' can be formed by cutting at the Scribe Line on the front side of the wafer. Then, the front surface of the wafer 200 is plastic-sealed, and the front surface of the wafer 200 and the solder bumps 205 are covered by the first plastic sealing layer 206, as shown in FIG. 8C, while the molding compound contained in the first plastic sealing layer 206 is also filled in In the cutting groove 215. Then, CMP polishing is performed on the back surface of the wafer 200 to thin the thickness of the wafer 200, that is, the thickness of the substrate 200A included in the wafer 200 is thinned, as shown in FIG. 8D, a part of the thickness of the wafer 200 (eg, D). 5 ) is polished off, that is, the thickness of the substrate 200A is thinned, and then the back side of the thinned wafer 200 can be selectively etched to repair the lattice damage caused by the polishing or to eliminate the wafer 200 after the thinning. The stress layer remaining on the back side. Referring to FIG. 8E, the back side of the thinned wafer 200 is covered with a metal layer 209. Then, after the metal layer 209 is covered and the back surface of the thinned wafer 200 is cut, the wafer 200 is cut to form a cutting groove 216 for isolating the wafer 200' on the back side of the thinned wafer 200. And the dicing groove 216 on the back side of the thinned wafer 200 is stopped in the substrate 200A of the wafer 200 and further contacts the molding compound filled in the cutting groove 215 on the front side of the wafer 200, that is, remains The cutting groove 216 is aligned with the cutting groove 215 in the vertical direction and in contact with each other as shown in Fig. 8F. At the same time, the metal layer 209 is cut into a bottom electrode metal layer 209' covering the bottom surface of each wafer 200'. The wafer 200 is plastic-sealed on the back surface of the thinned wafer 200 to form a second plastic sealing layer 211 covering the back surface of the thinned wafer 200. The second plastic sealing layer 211 also covers the metal layer 209 at the same time. The molding compound contained in the second plastic sealing layer 211 is also filled in the cutting groove 216 on the back side of the thinned wafer 200 as shown in Fig. 8G. The first molding layer 206 is then polished to expose the solder bumps 205 in the thinned first molding layer 206' to obtain a thinned first molding layer 206' in FIG. At the same time, in the cutting groove 216 located on the front side of the wafer 200, the cutting is performed in the cutting groove 215 on the back side of the thinned wafer 200, and the plurality of wafers 200' are separated to obtain a wafer level package structure. 200"G, as shown in Fig. 8I, the thinned first plastic encapsulation layer 206' forms a top molding 206" covering the front side of the wafer 200' during the cutting process.
In the wafer level package structure 200"G, including the top molding body 206" of the cladding wafer 200', the laterally extending portion 206"' of the top molding body 206" covers the front side of the wafer 200', and the top molding The laterally extending portion 206" of the vertical portion 206" of the body 206"'s the laterally extending portion 206" of the vertical top body 206" is also covered by a portion of the sidewall of the wafer 200', and the solder bumps 205 are over the top molding. Exposed in 206''. Also included is a bottom molding body 211' covering the wafer 200'. The laterally extending portion 211'a of the bottom molding body 211' covers the bottom surface of the wafer 200' while also covering the bottom electrode metal layer. 209'; a laterally extending portion 211'b of the bottom molding 211' perpendicular to the laterally extending portion 211'a of the bottom molding 211', while also leaving another portion of the wafer 200' unlaterally extending portion 206' The side walls of the 'b cladding are covered, at which time the laterally extending portions 206''b of the top molding body 206'' and the laterally extending portions 211'b of the bottom molding body 211' are in contact with each other and the wafer 200' is seamless. Sealing. In one embodiment, the deposition process of the metal layer 209 is eliminated in the above preparation process, There is no bottom electrode metal layer 209' in the subsequently obtained device. At this time, the wafer 200' is a planar IC, and all of the signal input and output terminals are disposed on one side of the top surface of the wafer 200'. In one embodiment, The wafer 200' including the bottom electrode metal layer 209' may be a vertical common drain dual MOSFET; and the drain of one MOSFET and the drain of the other MOSFET through the bottom electrode metal layer 209' Electrically coupled, and at least a portion of the array of solder joints 204 respectively form a source electrode and a gate electrode of any one of the dual MOSFETs. In one embodiment, the wafer 200' including the bottom electrode metal layer 209' includes at least two a pole body, and one electrode terminal of the diode is electrically connected to the bottom electrode metal layer 209', and at least a part of the array solder joints 204 respectively constitute the other electrode terminal of the diode, and each of the electrodes is arranged Point 204 constitutes the other electrode terminal of a diode.
Based on FIG. 8A to FIG. 8I, the package 200"G can also be prepared according to the flow shown in FIG. 9A to FIG. 9E, and the front surface of the molded wafer 200 in FIG. 8C is completed, and the first plastic sealing layer 206 is packaged. After the front surface of the wafer 200 and the solder bumps 205, as shown in FIG. 9A, the first molding layer 206 is first polished to expose the solder bumps 205 in the thinned first molding layer 206', and then The back side of the wafer 200 is subjected to CMP polishing to thin the thickness of the wafer 200 as shown in Fig. 9B. Part of the thickness of the wafer 200 (e.g., D 6 After being polished off, the back side of the thinned wafer 200 may be selectively etched and covered with a metal layer 209 on the back side of the thinned wafer 200, as shown in FIG. 9C. Then, after the metal layer 209 is covered and the back surface of the thinned wafer 200 is cut, the wafer 200 is cut to form a cutting groove 216 for isolating the wafer 200' on the back side of the thinned wafer 200. And the dicing groove 216 on the back side of the thinned wafer 200 is stopped in the substrate 200A of the wafer 200 and further contacts the molding compound filled in the cutting groove 215 on the front side of the wafer 200, that is, remains The cutting groove 216 is aligned with the cutting groove 215 in the vertical direction and in contact with each other as shown in Fig. 9D. The wafer 200 is further encapsulated on the back surface of the thinned wafer 200 to form a second plastic sealing layer 211 covering the back surface of the thinned wafer 200. The second plastic sealing layer 211 also covers the metal layer 209 at the same time. At the same time, the molding compound contained in the second plastic sealing layer 211 is also filled in the cutting groove 216 on the back side of the thinned wafer 200, as shown in Fig. 9E. At this time, the 9E picture is the 8H picture, and there is no difference between the two. In the wafer level package structure 200"G shown in FIG. 8I, including the top molding body 206" of the cladding wafer 200', the laterally extending portion 206"a of the top molding body 206" covers the front side of the wafer 200'. The laterally extending portion 206"b of the top molding 206" perpendicular to the laterally extending portion 206"a of the top molding 206" also covers a portion of the sidewall of the wafer 200' and the solder bump 205 is over the top molding Exposed in 206"; the second plastic sealing layer 211 forms a bottom molding body 211' covering the bottom electrode metal layer 209' during the cutting process, and the laterally extending portion 211"a of the bottom molding body 211' covers the bottom surface of the wafer 200'. On the bottom electrode metal layer 209', the laterally extending portion 211"b of the bottom molding body 211' perpendicular to the laterally extending portion 211"a of the bottom molding body 211' also covers another portion of the sidewall of the wafer 200'. The laterally extending portions 206"b of the top molding body 206" and the laterally extending portions 211"b of the bottom molding body 211' are in contact with each other and the wafer 200' is sealed without a gap.
The above-described processes shown in FIG. 8A to FIG. 8I or FIG. 9A to FIG. 9E are applicable to the preparation of planar structure ICs and vertical structure MOSFETs, and are also applicable to processing via RDL technology or not processed by RDL technology. Preparation of wafers.
Referring to a method of wafer level packaging in FIGS. 10A-10G, in conjunction with FIG. 1B to FIG. 1D, the solder pad 201 distributed on the top surface of the wafer 200' is re-arranged to be placed on the overlay wafer by using the redistribution technique RDL. Arranged solder joints 204 in the insulating dielectric layer 202 of 200', as shown in FIG. 10A. And soldering the solder bumps 205 on the alignment pads 204, and then cutting on the front side of the wafer 200 to form a cutting groove 215 for isolating the wafer 200' on the front side of the wafer 200, and the cutting groove 215 is stopped in the substrate 200A of the wafer 200. Then, the front surface of the wafer 200 is plastic-sealed, and the insulating dielectric layer 202 and the solder bumps 205 are covered with the first plastic sealing layer 206, as shown in FIG. 10B, while the molding compound contained in the first plastic sealing layer 206 is also filled in the cutting. In the slot 215. Then, CMP polishing is performed on the back surface of the wafer 200 to thin the thickness of the wafer 200, as shown in FIG. 10C, and then the back surface of the thinned wafer 200 may be selectively etched and thinned. The back side of the 200 is covered with a metal layer 209. Then, after the metal layer 209 is covered and the back surface of the thinned wafer 200 is cut, the wafer 200 is cut to form a cutting groove 216 for isolating the wafer 200' on the back side of the thinned wafer 200. And the dicing groove 216 on the back side of the thinned wafer 200 is stopped in the substrate 200A of the wafer 200 and further contacts the molding compound filled in the cutting groove 215 on the front side of the wafer 200, that is, remains The cutting groove 216 is aligned with the cutting groove 215 in the vertical direction and in contact with each other as shown in Fig. 10D. The metal layer 209 is cut into a bottom electrode metal layer 209' located on the bottom surface of each wafer 200'. The wafer 200 is plastic-sealed on the back surface of the thinned wafer 200 to form a second plastic sealing layer 211 covering the back surface of the thinned wafer 200. The second plastic sealing layer 211 also covers the metal layer 209 at the same time. The molding compound contained in the second plastic sealing layer 211 is also filled in the cutting groove 216 on the back side of the thinned wafer 200 as shown in Fig. 10E. The first plastic encapsulation layer 206 is ground to expose the solder bumps 205 in the thinned first encapsulation layer 206' to obtain a thinned first encapsulation layer 206' in FIG. At the same time, in the cutting groove 216 located on the front side of the wafer 200, the cutting is performed in the cutting groove 215 on the back side of the thinned wafer 200, and the plurality of wafers 200' are separated to obtain a wafer level package structure. 200"H, as shown in FIG. 10G, the insulating dielectric layer 202 is also cut into a top insulating dielectric layer 202' on the top surface of each wafer 200', and the thinned first plastic sealing layer 206' is in the cutting process. A top molding 206" covering the top insulating dielectric layer 202' is formed, and the substrate 200A included in the wafer 200 is cut into the substrate unit 200'A included in each wafer 200'.
In the method flow shown in FIG. 10A to FIG. 10G, before the metal layer 209 is covered to the back surface of the thinned wafer 200, a step similar to 2F-2I may be selected: the thinned wafer The back surface of 200 is coated with a barrier layer 207, and an opening 207' is formed in the barrier layer 207; the back surface of the wafer 200 is etched through the opening 207', and the substrate 200A included in the wafer is A via hole 208 is formed in the insulating dielectric layer 202 to contact the first type of solder joint 204a, and then the barrier layer 207 is removed; a metal material 208' is filled into the via hole 208, and is on the back side of the thinned wafer 200. The covered metal layer 209 is electrically connected to the first type of solder joint 204a contacting the through hole 208 through the metal material 208' filled in the through hole 208, and is selected to be in contact with the through hole 208. The first type of alignment pads 204a are located in the dielectric layer 202 overlying the non-active device cell regions within the substrate 200A.
In the method flow shown in FIG. 10A to FIG. 10G, before the solder bumps 205 are disposed on the array pads 204, steps similar to those of FIGS. 3A-3F may be selected: coating a layer on the wafer 200 a front insulating dielectric layer 202 and a barrier layer 213 arranging the solder joints 204, and forming an opening 213' in the barrier layer 213 contacting the first type of solder joint 204a; the first type is through the opening 213' The solder joints 204 a and the insulating dielectric layer 202 and the substrate 200A are etched, and the via holes 214 penetrating the first type of solder joints 204 a are formed in the substrate 200A and the insulating dielectric layer 202 , and the barrier layer 213 is removed. Then, while the solder bumps 205 are placed on the alignment pads 204, a portion of the solder 214' is also filled in the vias 214. In this process, during the polishing process on the back side of the wafer 200, the solder 214' filled in the via hole 214 is exposed outside the back surface of the thinned wafer 200, and then on the back side of the thinned wafer 200. A covered metal layer 209 is electrically connected to the first type of alignment pads 204a that are in contact with the vias 214 by solder 214' filled in the vias 214.
In the wafer level package structure 200"H, the top molding body 206" of the cladding wafer 200', the laterally extending portion 206"' of the top molding body 206" is overlaid on the top insulating dielectric layer 202', with the top The laterally extending portion 206'' of the laterally extending portion 206''a of the molded body 206"'s laterally extending portion 206"' of the top molding body 206"' also covers the sidewall of the top insulating dielectric layer 202', a portion of the sidewall of the wafer 200'. And the solder bumps 205 are exposed in the top molding body 206''; and the bottom molding body 211' of the wafer 200' is covered, and the laterally extending portion 211'a of the bottom molding body 211' covers the bottom surface of the wafer 200'. The laterally extending portion 211'b of the bottom molding 211' perpendicular to the laterally extending portion 211'a of the bottom molding 211' also simultaneously covers another portion of the sidewall of the wafer 200', the lateral side of the top molding 206'' The extended portion 206''b and the laterally extending portion 211'b of the bottom molding body 211' are in contact with each other to seal the wafer 200' seamlessly. Also included is a layer of bottom electrode metal layer 209' covered by the bottom surface of the wafer 200', bottom The laterally extending portion 211'a of the molded body 211' covers the bottom surface of the wafer 200' while still The bottom electrode metal layer 209' is covered. The 10G can also include a via 208 similar to that shown in FIG. 2M. At this time, the wafer 200' is a vertical MOSFET formed on the substrate unit 200 included in the wafer 200'. The 'A and top insulating dielectric layer 202' contacts the via hole 208 of the first type of solder joint 204a, and the metal material 208' filled in the via 208 will contact the first type of solder joint 204a of the via 208. Electrically connected to the bottom electrode metal layer 209', the bottom electrode metal layer 209' constitutes the drain of the MOSFET. The wafer level package structure 200"H-1 as shown in FIG. 10H. In another embodiment, the wafer 200' in the 10Gth diagram is also a vertical MOSFET, and may further include a via 214 similar to that shown in FIG. 3J, in which case the via 214 is in contact with the via 214. The first type of solder joints 204a are arranged, and the first type of solder joints 204a in contact with the vias 214 are electrically connected to the bottom electrode metal layer 209'; and the planar cross-sectional dimension of the vias 214 is smaller than the array solder joints 204. The planar dimension, and the metal material filled in the via 214 is an extension of the solder bump 205 disposed on the first type of solder joint 204a, such as the wafer level package structure 200"H- shown in FIG. 2.
In the above embodiment, the first molding layer 206 is polished to obtain a top surface of the thinned first molding layer 206', and the solder bump 205 may be partially polished to the solder bump during the polishing process. 205 is exposed to the thinned first plastic encapsulation layer 206 ′, and the surface of the solder bump 205 formed by being polished (not labeled) is exposed to the thinned first plastic encapsulation layer 206 ′ (ie, exposed to the top molding body) 206"), and the surface of the solder bump 205 remains coplanar with the top surface of the thinned first molding layer 206' (ie, the top surface of the top molding 206". Therefore, in each of the formed packages, the top molding body 206" does not completely cover the solder bumps 205, but the top molding body 206" surrounds the sides of the solder bumps 205, and the top molding body 206" The top surface is coplanar with the surface of any one of the solder bumps 205 exposed to the top molding 206". In the above embodiment, the plastic sealing process may be performed by using different molding materials to obtain the first plastic sealing layer 206 and the second plastic sealing layer 211 of different molding materials, respectively.
Exemplary embodiments of specific structures of the specific embodiments are given by way of illustration and the accompanying drawings. For example, the present invention is illustrated by a MOSFET, a common drain dual MOSFET, and the wafer can be converted into other types based on the spirit of the present invention. Although the above invention proposes a prior preferred embodiment, these are not intended to be limiting.
Various changes and modifications will no doubt become apparent to those skilled in the <RTIgt; Accordingly, the appended claims are intended to cover all such modifications and modifications Any and all equivalent ranges and contents within the scope of the claims are considered to be within the spirit and scope of the invention.

100．．．晶片100. . . Wafer

100’A．．．襯底單元100’A. . . Substrate unit

101、201．．．焊墊101, 201. . . Solder pad

102、202．．．絕緣介質層102, 202. . . Insulating dielectric layer

102’．．．部分區域102’. . . partial area

103．．．互聯機103. . . Interconnected machine

104、204．．．排列焊點104, 204. . . Arrange solder joints

105．．．焊料凸塊105. . . Solder bump

108、214．．．通孔108, 214. . . Through hole

200．．．晶圓200. . . Wafer

200’．．．晶片200’. . . Wafer

200A．．．襯底200A. . . Substrate

200’A．．．襯底單元200’A. . . Substrate unit

200"A、200"B、200"C、200"D、200"E．．．封裝結構200"A, 200"B, 200"C, 200"D, 200"E... package structure

200"F、200"G、200"H’ 200"H-1’ 200"H-2．．．封裝結構200"F, 200"G, 200"H' 200"H-1' 200"H-2... package structure

202’．．．頂部絕緣介質層202’. . . Top dielectric layer

204a．．．第一類排列焊點204a. . . First type of solder joints

205．．．焊料凸塊205. . . Solder bump

206、206’．．．第一塑封層206, 206’. . . First plastic seal

206"．．．頂部塑封體206"...top molding

207、213．．．阻擋層207, 213. . . Barrier layer

207’、213’．．．開口207’, 213’. . . Opening

208、214．．．通孔208, 214. . . Through hole

208’．．．金屬材料208’. . . metallic material

209．．．金屬層209. . . Metal layer

209’．．．底部電極金屬層209’. . . Bottom electrode metal layer

210、215、216．．．切割槽210, 215, 216. . . Cutting slot

211．．．第二塑封層211. . . Second plastic seal

211’．．．底部塑封體211’. . . Bottom molding

206"a、211’a．．．橫向延伸部分206"a, 211'a... lateral extension

206"b、211’b．．．側向延伸部分206"b, 211'b... lateral extension

212．．．切割口212. . . Cutting mouth

214’．．．焊料214’. . . solder

參考所附附圖，以更加充分的描述本發明的實施例。然而，所附附圖僅用於說明和闡述，並不構成對本發明範圍的限制。
第1A圖-第1B圖是晶片頂面的焊墊的原有設計示意圖。
第1C圖-第1D圖是將晶片頂面原有的焊墊進行從新佈局設計成排列焊點的示意圖。
第1E圖、第1F圖分別是在原有的焊墊和在從新佈局的排列焊點上進行植球的示意圖。
第2A圖-第2M圖是一種實施方式中，將晶片的一部分排列焊點通過通孔中的填充金屬材料連接至晶片背面的電極的製備流程。
第3A圖-第3J圖是另一種實施方式中，將晶片的一部分排列焊點通過通孔中的填充金屬材料連接至晶片背面的電極的製備流程。
第4A圖-第4E圖是一種實施方式中，經RDL技術處理後在晶片的背面形成電極並將晶片封裝的製備流程。
第5A圖-第5E圖是一種實施方式中，在無RDL技術處理的晶片的背面形成電極並將晶片封裝的製備流程。
第6A圖-第6E圖是一種實施方式中，經RDL技術處理後在晶片的背面不形成電極並將晶片封裝的製備流程。
第7A圖-第7E圖是一種實施方式中，在無RDL技術處理的晶片的背面不形成電極並將晶片封裝的製備流程。
第8A圖-第8I圖是一種實施方式中，在無RDL技術處理的晶圓的正面進行切割並塑封，再在減薄後的晶圓的背面進行塑封並切割，將晶片從晶圓上分離的製備流程。
第9A圖-第9E圖是一種實施方式中，在無RDL技術處理的晶圓的正面進行切割並塑封，減薄晶圓正面的塑封料，在減薄後的晶圓的背面塑封並切割，將晶片從分離的製備流程。
第10A圖-第10I圖是一種實施方式中，經RDL技術處理後在晶圓的正面進行切割並塑封再在減薄後的晶圓的背面進行塑封並切割，將晶片從晶圓上分離的製備流程。



Embodiments of the present invention are described more fully with reference to the accompanying drawings. However, the attached drawings are for illustration and illustration only and are not intended to limit the scope of the invention.
Figure 1A - Figure 1B is a schematic view of the original design of the pad on the top surface of the wafer.
Fig. 1C - Fig. 1D is a schematic view of designing the original pads of the top surface of the wafer from a new layout to arrange the pads.
Fig. 1E and Fig. 1F are schematic views showing the original pad and the ball placement on the newly arranged arrangement of the pads.
2A-2M is a preparation flow in which an electrode of a portion of the wafer is arranged to be connected to the electrode on the back surface of the wafer through a filler metal material in the via hole.
3A-3E is a preparation flow of another embodiment in which a portion of a wafer is arranged to be soldered to a surface of the wafer by a filler metal material in the via hole.
4A to 4E are preparation processes for forming an electrode on the back surface of a wafer and encapsulating the wafer after being processed by the RDL technique in an embodiment.
5A-5E is a flow chart for preparing an electrode on the back side of a wafer processed without RDL technology and encapsulating the wafer in an embodiment.
6A-6E is a preparation flow in which an electrode is not formed on the back surface of the wafer and the wafer is packaged by the RDL technique after being processed by the RDL technique.
7A to 7E are diagrams showing a preparation process in which an electrode is not formed on the back surface of a wafer processed without the RDL technique and the wafer is packaged in an embodiment.
8A-8I is an embodiment in which the front side of a wafer processed without RDL technology is cut and molded, and then the back side of the thinned wafer is molded and cut to separate the wafer from the wafer. Preparation process.
9A-9E is an embodiment in which the front surface of the wafer processed without the RDL technology is cut and molded, the molding material on the front side of the wafer is thinned, and the back surface of the thinned wafer is molded and cut. The preparation process for separating the wafer from the separation.
10A-10I is an embodiment in which the surface of the wafer is cut and molded by RDL technology, and then the back surface of the thinned wafer is molded and cut to separate the wafer from the wafer. Preparation process.



200’．．．晶片200’. . . Wafer

200’A．．．襯底單元200’A. . . Substrate unit

200"A．．．封裝結構200"A... package structure

202’．．．頂部絕緣介質層202’. . . Top dielectric layer

204．．．排列焊點204. . . Arrange solder joints

204a．．．第一類排列焊點204a. . . First type of solder joints

205．．．焊料凸塊205. . . Solder bump

206"．．．頂部塑封體206"...top molding

208、214．．．通孔208, 214. . . Through hole

208’．．．金屬材料208’. . . metallic material

209’．．．底部電極金屬層209’. . . Bottom electrode metal layer

211’．．．底部塑封體211’. . . Bottom molding

211’a．．．橫向延伸部分211’a. . . Lateral extension

211’b．．．側向延伸部分211’b. . . Lateral extension

212．．．切割口212. . . Cutting mouth

Claims (29)

一種晶圓級封裝的方法，包括以下步驟：
提供一包含有多個晶片的晶圓，在晶圓的正面形成凸出於晶圓正面並電性連接至晶片焊墊的焊料凸塊，
塑封所述晶圓的正面，以第一塑封層包覆晶圓的正面及焊料凸塊；
於晶圓的背面進行研磨；
於減薄後的晶圓的背面對晶圓進行切割，形成隔離晶片的切割槽，並且切割槽停止在第一塑封層中；
於減薄後的晶圓的背面對晶圓進行塑封，形成包覆減薄後的晶圓的背面的第二塑封層，同時塑封料還填充在切割槽中；
研磨第一塑封層以將焊料凸塊在減薄後的第一塑封層中予以外露；
於所述切割槽中進行切割，將晶片進行分離，所述第一塑封層及第二塑封層包覆所述分離的晶片，所述焊料凸塊在減薄後的第一塑封層中予以外露。A method of wafer level packaging, comprising the steps of:
Providing a wafer including a plurality of wafers, and forming solder bumps on the front surface of the wafer protruding from the front surface of the wafer and electrically connected to the wafer pads,
Forming a front surface of the wafer, covering a front surface of the wafer and a solder bump with a first plastic sealing layer;
Grinding on the back side of the wafer;
Cutting the wafer on the back side of the thinned wafer to form a cutting groove of the isolation wafer, and the cutting groove is stopped in the first plastic sealing layer;
Forming a wafer on the back side of the thinned wafer to form a second plastic seal layer covering the back side of the thinned wafer, and the molding compound is also filled in the cutting groove;
Grinding the first plastic seal layer to expose the solder bumps in the thinned first plastic seal layer;
Cutting is performed in the cutting groove to separate the wafer, the first plastic sealing layer and the second plastic sealing layer coating the separated wafer, and the solder bump is exposed in the thinned first plastic sealing layer . 如申請專利範圍第1項所述的方法，其中，還包括在晶圓的背面研磨之後，於減薄後的晶圓的背面，穿透晶圓所包含的襯底及絕緣介質層形成接觸第一類焊墊的通孔，並填充金屬材料至所述通孔中；與通孔所接觸的所述第一焊墊的位置，位於覆蓋在晶圓的襯底內非有源器件單元區域之上的絕緣介質層上。The method of claim 1, further comprising forming a contact between the substrate and the insulating dielectric layer of the wafer after the back surface of the wafer is polished on the back side of the thinned wafer. a through hole of a pad and filling a metal material into the via; a position of the first pad contacting the via is located in a region of the non-active device cell covering the substrate of the wafer On the insulating dielectric layer. 如申請專利範圍第2項所述的方法，其中，在形成所述通孔後，還在所述通孔的內壁上沉積有隔離襯墊層，並且填充的金屬材料通過隔離襯墊層與環繞在通孔周圍的的襯底區域絕緣。The method of claim 2, wherein after the through hole is formed, a release liner layer is deposited on the inner wall of the through hole, and the filled metal material is passed through the release liner layer The substrate area surrounding the via hole is insulated. 如申請專利範圍第3項所述的方法，其中，還覆蓋一層金屬層至減薄後的晶圓的背面。The method of claim 3, further comprising covering a metal layer to the back side of the thinned wafer. 如申請專利範圍第4項所述的方法，其中，所述晶片為垂直式的MOSFET，所述的背面金屬層通過所述填充通孔的金屬材料電連接到所述第一類焊墊構成所述MOSFET的漏極電極。The method of claim 4, wherein the wafer is a vertical MOSFET, and the back metal layer is electrically connected to the first type of pad through the metal material filling the via hole. The drain electrode of the MOSFET. 如申請專利範圍第2項所述的方法，其中，所形成的通孔的平面截面尺寸小於焊墊的平面尺寸。The method of claim 2, wherein the through hole has a planar cross-sectional dimension that is smaller than a planar size of the bonding pad. 如申請專利範圍第1項所述的方法，其中，還包括在晶圓的正面形成焊料凸塊之前，於晶圓的正面，穿透第一類焊墊、絕緣介質層及部分晶圓所包含的襯底，形成接觸第一類焊墊的通孔；所述第一焊墊的位置，位於覆蓋在晶圓的襯底內非有源器件單元區域之上的絕緣介質層上；以及
於所述焊墊上安置焊料凸塊的過程中，部分焊料同時填充在所述通孔中。The method of claim 1, further comprising: before the solder bump is formed on the front side of the wafer, on the front side of the wafer, the first type of solder pad, the insulating dielectric layer, and a portion of the wafer are included a substrate, forming a via hole in contact with the first type of pad; the first pad is located on the dielectric layer overlying the area of the non-active device cell in the substrate of the wafer; During the process of placing the solder bumps on the pads, part of the solder is simultaneously filled in the via holes. 如申請專利範圍第7項所述的方法，其中，在形成所述通孔後，還在所述通孔的內壁上沉積有隔離襯墊層，並且填充在所述通孔中的焊料通過隔離襯墊層與環繞在通孔周圍的襯底區域絕緣。The method of claim 7, wherein after the through hole is formed, a spacer liner layer is deposited on the inner wall of the through hole, and the solder filled in the through hole passes The spacer liner layer is insulated from the substrate region surrounding the via. 如申請專利範圍第8項所述的方法，其中，還覆蓋一層金屬層至減薄後的晶圓的背面。The method of claim 8, wherein the metal layer is further covered to the back side of the thinned wafer. 如申請專利範圍第9項所述的方法，其中，所述晶片為垂直式的MOSFET，所述的背面金屬層通過所述填充通孔的焊料電連接到所述第一類焊墊構成所述MOSFET的漏極電極。The method of claim 9, wherein the wafer is a vertical MOSFET, and the back metal layer is electrically connected to the first type of solder pad by the solder filling the via hole to form the The drain electrode of the MOSFET. 如申請專利範圍第7項所述的方法，其中，形成通孔的方式為幹法刻蝕或濕法刻蝕或鐳射刻蝕。The method of claim 7, wherein the through hole is formed by dry etching or wet etching or laser etching. 如申請專利範圍第1項所述的方法，其中，還包括以下步驟：
於晶圓的正面進行塑封之前，在晶圓的正面進行切割，形成位於晶圓正面一側的用於隔離晶片的切割槽，並且該切割槽停止在晶圓所包含的襯底中；
在形成包覆晶圓的正面的第一塑封層的過程中，塑封料還填充在位於晶圓正面一側的切割槽中；
且形成位於減薄後的晶圓背面一側的切割槽停止在襯底中並進一步與填充在位於晶圓正面一側的切割槽中的塑封料接觸。The method of claim 1, wherein the method further comprises the following steps:
Before the front side of the wafer is molded, cutting is performed on the front side of the wafer to form a cutting groove for isolating the wafer on the front side of the wafer, and the cutting groove is stopped in the substrate included in the wafer;
In the process of forming the first plastic layer covering the front side of the wafer, the molding compound is also filled in a cutting groove on the front side of the wafer;
And the dicing groove formed on the back side of the thinned wafer is stopped in the substrate and further in contact with the molding compound filled in the cutting groove on the front side of the wafer. 如申請專利範圍第12項所述的方法，其中，晶圓的背面完成研磨後，還包括於減薄後的晶圓的背面進行蝕刻，並覆蓋一層金屬層至減薄後的晶圓的背面的步驟；以及
形成位於減薄後的晶圓背面一側的用於隔離晶片的切割槽的過程中，於減薄後的晶圓的覆蓋有金屬層的背面對晶圓進行切割；並且
在形成包覆減薄後的晶圓的背面的第二塑封層的過程中，所述第二塑封層還同時包覆所述金屬層。The method of claim 12, wherein after the back side of the wafer is polished, the method further comprises etching the back side of the thinned wafer and covering a metal layer to the back side of the thinned wafer. And forming a dicing groove for isolating the wafer on the back side of the thinned wafer, cutting the wafer on the back surface of the thinned wafer covered with the metal layer; and forming In the process of coating the second plastic seal layer on the back side of the thinned wafer, the second plastic seal layer also covers the metal layer at the same time. 如申請專利範圍第12項所述的方法，其中，在覆蓋一層金屬層至減薄後的晶圓的背面之前，還包括以下步驟：
在減薄後的晶圓的背面塗覆一層阻擋層，並形成位於阻擋層中的開口；
通過開口於減薄後的晶圓的背面進行刻蝕，於晶圓所包含的襯底及絕緣介質層中形成接觸第一類焊墊的通孔，並移除阻擋層；
填充金屬材料至所述通孔中，並且於減薄後的晶圓的背面覆蓋的一層金屬層通過填充在所述通孔中的金屬材料而電性連接至與通孔所接觸的第一類焊墊上。The method of claim 12, further comprising the steps of: covering a metal layer to the back side of the thinned wafer:
Coating a backing layer on the back side of the thinned wafer and forming an opening in the barrier layer;
Etching through the back surface of the thinned wafer, forming a via hole contacting the first type of bonding pad in the substrate and the insulating dielectric layer included in the wafer, and removing the barrier layer;
Filling a metal material into the through hole, and a metal layer covered on the back surface of the thinned wafer is electrically connected to the first type in contact with the through hole by a metal material filled in the through hole On the pad. 如申請專利範圍第14項所述的方法，其中，與通孔所接觸的所述第一類焊墊的位置，位於覆蓋在的襯底內非有源器件單元區域之上的絕緣介質層中。The method of claim 14, wherein the position of the first type of pad in contact with the via hole is located in an insulating dielectric layer over the area of the non-active device cell overlying the substrate . 如申請專利範圍第12項所述的方法，其中，於焊墊上安置焊料凸塊之前，還包括以下步驟：
塗覆一層包覆位於晶圓正面的絕緣介質層及焊墊的阻擋層，並形成位於阻擋層中接觸第一類焊墊的開口；
通過所述開口對所述第一類焊墊及絕緣介質層、襯底進行刻蝕，形成貫穿該第一類焊墊及絕緣介質層並終止於襯底一預定深處的通孔，並移除阻擋層；
之後在焊墊上安置焊料凸塊的同時，部分焊料還一併填充在所述通孔中。The method of claim 12, wherein before the solder bump is placed on the pad, the method further comprises the steps of:
Coating a barrier layer covering the insulating dielectric layer and the pad on the front side of the wafer, and forming an opening in the barrier layer contacting the first type of pad;
The first type of pad and the insulating dielectric layer and the substrate are etched through the opening to form a through hole extending through the first type of pad and the dielectric layer and ending at a predetermined depth of the substrate, and moving In addition to the barrier layer;
After the solder bumps are placed on the pads, a portion of the solder is also filled in the via holes. 如申請專利範圍第16項所述的方法，其中，於晶圓的背面進行研磨過程中，在減薄後的晶圓的背面外露出填充在通孔中的焊料，並且之後於減薄後的晶圓的背面覆蓋的一層金屬層通過填充在通孔中的焊料而電性連接在與通孔所接觸的第一類焊墊上。The method of claim 16, wherein during the polishing process on the back side of the wafer, the solder filled in the via hole is exposed outside the back surface of the thinned wafer, and then after thinning A metal layer covered on the back side of the wafer is electrically connected to the first type of pad that is in contact with the via hole by solder filled in the via hole. 如申請專利範圍第1項所述的方法，其中，完成晶圓的背面研磨之後，還包括於減薄後的晶圓的背面覆蓋一層金屬層的步驟；以及
在形成隔離晶片的切割槽的過程中，於減薄後的晶圓的覆蓋有金屬層的背面對晶圓進行切割；並且
在形成包覆減薄後的晶圓的背面的第二塑封層的過程中，所述第二塑封層還同時包覆金屬層。The method of claim 1, wherein after the back grinding of the wafer is completed, the step of covering the back side of the thinned wafer with a metal layer; and the process of forming the cutting trench of the isolation wafer Cutting the wafer on the back surface of the thinned wafer covered with the metal layer; and in forming the second plastic seal layer covering the back surface of the thinned wafer, the second plastic seal layer The metal layer is also coated at the same time. 如申請專利範圍第18項所述的方法，其中，所述晶片為垂直式的共漏極的雙MOSFET；並且
雙MOSFET中一個MOSFET的漏極與另一個MOSFET的漏極通過所述金屬層進行電性連接，以及至少一部分焊墊分別構成雙MOSFET中任意一個MOSFET的源極電極和柵極電極。The method of claim 18, wherein the wafer is a vertical common drain dual MOSFET; and the drain of one MOSFET and the drain of the other MOSFET in the dual MOSFET pass through the metal layer Electrically connected, and at least a portion of the pads respectively form a source electrode and a gate electrode of any one of the dual MOSFETs. 如申請專利範圍第1項所述的方法，其中，利用重分佈技術將分佈在晶片頂面的焊墊重新佈局設計成位於覆蓋晶片的絕緣介質層中的排列焊墊，於所述排列焊墊上安置焊料凸塊。The method of claim 1, wherein the redistribution technique is used to re-lay the pads distributed on the top surface of the wafer into alignment pads located in the insulating dielectric layer covering the wafer, on the alignment pads. Place the solder bumps. 一種晶圓級的封裝結構，在該封裝結構中，在晶片的頂面形成有凸出於晶片頂面的並電性連接至晶片焊墊的焊料凸塊，其中，還包括：
包覆在晶片頂面的頂部塑封體，所述頂部塑封體圍繞在所述焊料凸塊的側面的周圍，所述頂部塑封體的頂面與任意一個所述焊料凸塊的外露於頂部塑封體的表面共面；
包覆所述晶片底部的底部塑封體，所述底部塑封體的橫向延伸部分覆蓋晶片的底面，與橫向延伸部分垂直的底部塑封體的側向延伸部分同時還將晶片的側壁予以覆蓋，所述底部塑封體的側向延伸部分延伸接觸所述頂部塑封體以將晶片無縫隙的密封。A wafer-level package structure in which a solder bump protruding from a top surface of a wafer and electrically connected to a wafer pad is formed on a top surface of the wafer, wherein:
a top molding overlying the top surface of the wafer, the top molding surrounding the side of the solder bump, the top surface of the top molding and any one of the solder bumps being exposed to the top molding Surface coplanar;
a bottom molding body covering the bottom of the wafer, the laterally extending portion of the bottom molding body covering the bottom surface of the wafer, and the laterally extending portion of the bottom molding body perpendicular to the laterally extending portion simultaneously covering the sidewall of the wafer, A laterally extending portion of the bottom molding extends into contact with the top molding to seal the wafer seamlessly. 如申請專利範圍第21項所述的晶圓級的封裝結構，其中，還包括覆蓋晶片底面的一層底部電極金屬層，所述底部塑封體的橫向延伸部分覆蓋晶片的背面的同時還覆蓋底部電極金屬層。The wafer level package structure of claim 21, further comprising a bottom electrode metal layer covering the bottom surface of the wafer, the laterally extending portion of the bottom molding body covering the back surface of the wafer and covering the bottom electrode Metal layer. 如申請專利範圍第22項所述的晶圓級的封裝結構，其中，還包括
形成在晶片所包含的襯底單元及頂部絕緣介質層中接觸第一類焊墊的通孔，並且通孔中所填充的金屬材料將與通孔所接觸的第一類焊墊電性連接至所述底部電極金屬層上。The wafer-level package structure of claim 22, further comprising a via hole formed in the substrate unit and the top insulating dielectric layer included in the wafer and contacting the first type of solder pad, and the through hole is The filled metal material is electrically connected to the first electrode pad in contact with the via hole to the bottom electrode metal layer. 如申請專利範圍第23項所述的晶圓級的封裝結構，其中，在所述通孔的內壁上還設置有隔離襯墊層，並且填充的金屬材料通過隔離襯墊層與環繞在通孔周圍的襯底區域絕緣。The wafer-level package structure of claim 23, wherein a spacer layer is further disposed on an inner wall of the through hole, and the filled metal material is passed through the spacer layer The substrate area around the hole is insulated. 如申請專利範圍第24項所述的晶圓級的封裝結構，其中，所述通孔進一步貫穿與通孔所接觸的該第一類焊墊；以及
通孔的平面截面尺寸小於焊墊的平面尺寸，且通孔中所填充的金屬材料是安置在第一類焊墊上的焊料凸塊的延伸部分。The wafer-level package structure of claim 24, wherein the through hole further penetrates the first type of pad in contact with the through hole; and the planar cross-sectional dimension of the through hole is smaller than a plane of the pad Dimensions, and the metal material filled in the vias is an extension of the solder bumps disposed on the first type of pads. 如申請專利範圍第23項所述的晶圓級的封裝結構，其中，所述晶片為垂直式的MOSFET，與通孔所接觸的所述第一類焊點構成所述MOSFET的漏極電極。The wafer level package structure of claim 23, wherein the wafer is a vertical MOSFET, and the first type of solder joints in contact with the vias constitute a drain electrode of the MOSFET. 如申請專利範圍第21項所述的晶圓級的封裝結構，其中：
所述頂部塑封體包括橫向延伸部分覆蓋在晶片的正面，以及與頂部塑封體的橫向延伸部分垂直的頂部塑封體的側向延伸部分同時還將晶片的部分側壁予以覆蓋；
包覆晶片的底部塑封體，底部塑封體的橫向延伸部分覆蓋在晶片的底面，與底部塑封體的橫向延伸部分垂直的底部塑封體的側向延伸部分同時還將晶片的另外一部分側壁予以覆蓋，頂部塑封體的側向延伸部分與底部塑封體的側向延伸部分相互接觸以將晶片無縫隙的密封。A wafer level package structure as described in claim 21, wherein:
The top molding body includes a laterally extending portion covering the front side of the wafer, and a laterally extending portion of the top molding body perpendicular to the laterally extending portion of the top molding body while also covering a portion of the sidewall of the wafer;
Covering the bottom molding of the wafer, the laterally extending portion of the bottom molding covering the bottom surface of the wafer, and the laterally extending portion of the bottom molding perpendicular to the laterally extending portion of the bottom molding body simultaneously covers another sidewall of the wafer, The laterally extending portions of the top molding body are in contact with the laterally extending portions of the bottom molding body to seal the wafer seamlessly. 如申請專利範圍第21項所述的晶圓級的封裝結構，其中：所述的第一塑封體和所述的第二塑封體由不同的塑封材料組成。The wafer level package structure of claim 21, wherein the first molding body and the second molding body are composed of different molding materials. 如申請專利範圍第22項所述的晶圓級的封裝結構，其中，所述晶片為垂直式的共漏極的雙MOSFET；並且
雙MOSFET中一個MOSFET的漏極與另一個MOSFET的漏極通過所述金屬層進行電性連接。
The wafer level package structure of claim 22, wherein the wafer is a vertical common drain dual MOSFET; and the drain of one MOSFET and the drain of the other MOSFET in the dual MOSFET pass The metal layer is electrically connected.
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