TW201310907A - Reset signal generator and method for generating reset signal - Google Patents

Abstract

A reset signal generator, producing the required reset signal to reset the integrated circuit, includes a D-latch, a second delay circuit and a first delay circuit, in which the D-Latch has a first input terminal, a second input terminal and an inverting output terminal. The second delay circuit delaying the power signal with a second delay time is electrically connected to the first input terminal of the D-latch. The first delay circuit, electrically connected between the inverting output terminal and the second input terminal, delays the inverting output signal from the inverting output terminal with a first delay time, in which the first delay time is shorter than the second delay time, and the delayed inverting output signal, i.e. the reset signal, is delivered to the second input terminal.

Description

Reset signal generator and reset signal generation method

The present invention relates to a reset signal generator, and more particularly to a reset signal generator for resetting an integrated circuit.

In general, signal processing systems often rely on a reset signal for initialization to explicitly operate the system from a predetermined state to achieve the desired performance. In memory devices and other integrated circuits, it is often desirable or necessary to initialize or reset the circuit. The reset process sets the internal register to a certain state. The input pins can be configured by the end user to be in a logic state "1" (electrically connected to voltage Vcc), a logic state "0" (electrically connected to ground potential), or floating. In the case where the input is configured to a logic state "1", a circuit is used to ensure that the input is automatically fixed to Vcc during the power-on reset function of the device. In the case where the input is configured to a logic state of "0" or floating, a circuit is used to ensure that the input is automatically fixed to ground potential during the power-on reset function of the device.

In the case where the system cannot provide a reset signal or the delay time of the reset signal provided by the system cannot meet the sequence requirements of the chip, the conventional method is to use a simple resistor and capacitor to delay the power signal as a reset. The signal is called a power-on reset signal. However, the shortcoming of the power reset signal is that the rising edge is slow, and the delay time (tpr) of the reset signal in the timing and the power signal is limited, and cannot be guaranteed. The wafer can be reset correctly.

Therefore, an aspect of the present invention provides a reset signal generator capable of generating two reset signals for use by an integrated circuit, improving the effect of initializing the integrated circuit, and adjusting the power reset signal as needed. Timing.

According to an embodiment of the invention, the reset signal generator generates a reset signal required to reset an integrated circuit, the reset signal generator including a D-type latch, a second delay circuit, and a first Delay circuit. The D-type latch has a first input, a second input, and an inverting output. The second delay circuit is electrically connected to the first input end of the D-type latch. The second delay circuit delays a power signal for a second delay time and then sends the signal to the first input terminal. The first delay circuit is electrically connected between the inverting output end and the second input end to delay the output of the inverted output signal of the inverted output terminal, and then delays to a second input time, and then sends the signal to the second input. The first delay time is shorter than the second delay time, and the inverted signal is delayed after the inverted output signal is delayed.

Another aspect of the present invention provides a reset signal generating method capable of generating two reset signals for use by an integrated circuit, improving the effect of initializing the integrated circuit, and adjusting the power reset signal as needed. Timing.

According to another embodiment of the present invention, the reset signal generating method generates a reset signal required to reset an integrated circuit reset, the reset signal generating method providing a D-type latch, the D-type latch An inverted output signal outputted by one of the inverting outputs of the latch is delayed by a first delay time, sent to a second input of the D-type latch, and delayed by a power signal. After the second delay time, it is fed to one of the first inputs of the D-type latch, wherein the second delay time is made longer than the first delay time. The signal on the second input of the D-type latch is then output as a reset signal.

In the reset signal generator and the reset signal generating method of the above embodiment, the reset signal can be generated twice to initialize the integrated circuit twice, thereby improving the effect of the integrated circuit initialization; and the power signal can be adjusted as needed. The delay time between the power reset signals increases the flexibility and applicability of the reset signal.

In the following embodiments, the reset signal generator and the reset signal generating method can generate two reset signals to initialize the integrated circuit twice without additional startup information, thereby improving the effect of the integrated circuit initialization and avoiding initialization. It does not completely affect the operation of the integrated circuit; it can adjust the delay time between the power signal and the power reset signal as needed, which increases the flexibility and applicability of the reset signal.

Please refer to FIG. 1A, FIG. 1B and Table 1. FIG. 1A and FIG. 1B are circuit diagrams and signal waveform diagrams of a reset signal generator according to an embodiment of the present invention, and a D-type latch (D) The truth table of -latch is shown in Table 1. A D-type latch composed of two NAND gates 106 has a signal logic level on the second input terminal B of 0, 1, 0, 1 from front to back, with two times. The change from logic 0 to logic 1 happens to be the reset signal required to reset the integrated circuit.

As shown in FIG. 1A, the D-type latch 101 has a first input terminal A, a second input terminal B, a positive phase output terminal Q, and an inverting output terminal Q'; the second delay circuit 103 is electrically connected to the D The first input terminal A of the latch type 101, the second delay circuit 103 delays the power signal Vdd for a second delay time and then sends it to the first input terminal A. The first delay circuit 105 is electrically connected between the inverting output terminal Q' and the second input terminal B to delay the inverted output signal outputted by the inverting output terminal Q' by a first delay time. And sent to the second input terminal B, wherein the first delay time generated by the first delay circuit 105 is shorter than the second delay time generated by the second delay circuit 103, and the inverted output signal after the delay (ie, the first The signal on the two input terminals B is the reset signal.

In this way, logic 0 and logic 1 can be input to the first input terminal and the second input terminal of the D-type latch 101 in the order of top-down according to the truth table, after passing through the D-type latch 101 and the first After a delay circuit 105, a signal with a logic level of 0, 1, 0, 1 can be sequentially generated to the second input terminal B as a reset signal twice from 0 to 1; after 0, 1 After 0 and 1 transitions from 0 to 1, the potential on the second input terminal B will continue to be at logic 1 consistent with the reset signal level required by the integrated circuit.

It can be clearly seen from Fig. 1B that after a period of time tdelay after the power signal 107 transitions to logic 1, the reset signal 109 will transition from logic 0 to logic 1, and then the second transition. The delay time between the power signal 107 and the reset signal 109 can be adjusted as needed, and thus more flexible.

Referring to FIG. 2A, FIG. 2B, and FIG. 2C, a circuit diagram of a first delay circuit or a second delay circuit according to an embodiment of the present invention is shown. The first delay circuit and the second delay circuit each comprise a resistor R and a capacitor C. The resistor R is electrically connected to the capacitor C. The input terminal In is responsible for receiving the undelayed power signal or the inverting of the D-shaped latch. output signal.

In FIGS. 2A and 2B, the signal on the connection terminal W of the resistor R and the capacitor C is the inverted output signal after the delay or the power supply signal after the delay, so the connection terminal W in FIG. 2B, It can be directly connected to the first input or the second input of the D-type latch; the first delay circuit or the second delay circuit of FIG. 2A adds the buffer 201 to enhance the power signal after the delay or The phase output signal is thus connected to the first input or the second input of the D-type latch by the output Output.

On the other hand, the first delay circuit or the second delay circuit of FIG. 2C includes a transistor T, a capacitor C, and a resistor R. The transistor T has a gate G, a source S, and a drain D, wherein the drain The D output is the inverted output signal after the delay or the delayed power signal, and the source S receives the undelayed power signal or the inverted output signal of the D-shaped latch; the capacitor C is electrically connected to the transistor. Between the gate G of the T and the source S, the resistor R is electrically connected between the gate G of the transistor and a ground.

The length of the delay provided by the first delay circuit and the second delay circuit is related to the capacitance value of the capacitor C and the resistor R and the resistance value, that is, the capacitance value of the capacitor C and the resistor R and the resistance value can be adjusted to change the delay time. The length of time.

Please refer to FIG. 3, which is a flowchart of a method for generating a reset signal according to an embodiment of the present invention. The reset signal generating method generates a reset signal required to reset an integrated circuit reset. The reset signal generating method first provides a D-type latch (step 301), and the D-type latch needs The first input terminal, the second input terminal, the positive phase output terminal and the inverted output terminal are provided.

Then, the inverted output signal outputted from the inverting output terminal of the D-type latch is delayed by a first delay time and then sent to a second input terminal of the D-type latch (step 303). The voltage logic level on the second input of the D-type latch should initially be a low logic level before the change in level is generated.

At the same time, after delaying the power signal for a second delay time, it is sent to the first input end of the D-type latch (step 305). The power signal needs to be a low logic level at the initial time. After a period of time. Then the change becomes a high logic level. In this step 305, the second delay time needs to be longer than the first delay time, so that the received signal on the second input continuously produces a change of 0, 1, 0, 1. For example, the first delay time may be equal to, greater than, or less than half of the second delay time, that is, the first delay time may not be equal to or longer than the second delay time. Finally, the signal on the second input of the D-type latch is output as a reset signal (step 307).

Referring to FIG. 4A, FIG. 4B and FIG. 4C, FIG. 4 is a signal waveform diagram of a reset signal generator according to an embodiment of the present invention. The reset signal generator has a first input end and a second D-type latch for input, positive-phase output, and inverting output. It can be seen from FIG. 4A, FIG. 4B and FIG. 4C that within the timing phase P1 in the initial state, the logic level of the signal 403 on the first input terminal and the signal 405 on the second input terminal are both 0, it can be seen that the logic level of the positive phase output signal 407 and the inverted output signal 409 will be a logic one. Then, in the timing phase P2, the first delay circuit delays the inverted output signal 409 of the logic 1 by the first delay time and then sends it to the second input terminal; at the same time, the signal 403 on the first input terminal remains Logic 0 is maintained such that the logic levels of the positive phase output signal 407 and the inverted output signal 409 are logic 1 and logic 0, respectively.

In the subsequent timing phase P3, the three waveforms are subdivided according to the length ratio between the first delay time and the second delay time, which are respectively shown in FIG. 4A, FIG. 4B and FIG. 4C. It should be particularly noted that even if the ratio of the length of the first delay time to the second delay time is not the same, the three embodiments can generate a reset signal with a sequential phase of 0, 1, 0, and 1.

In the timing phase P3 of FIG. 4A, since the first delay time Td1 associated with the signal 405 on the second input terminal is shorter than half of the second delay time Td2, the signal 405 on the second input terminal is prematurely turned. The state is logic 0, at this time, the signal 403 on the first input terminal is still logic 0, (that is, the logic level on the two input terminals of the D-type latch is 0, 0), so that the positive phase output signal 407 and the opposite The logic level of the phase output signal 409 is a logic one.

Then, in the timing phase P4 of FIG. 4A, the signal 403 on the first input is changed from a logic 0 to a logic 1, and the signal 405 on the second input is still a logic 0, and the input is 1, 0. The combination will cause the D-type latch to output a positive phase output signal 407 of logic 0 and an inverted output signal of logic 1. The inverted output signal of the logic 1 appears on the second input after the delay of the first delay time, so that the signal 405 on the second input transitions to a logic 1 at the timing phase P5, that is, the second input The signal 405 on the terminal can normally generate logic 0, 1, 0, 1 in sequence.

In addition, in the timing phase P3 of FIG. 4B, that is, the first delay time Td1 is exactly equal to half of the second delay time, the signal 403 on the first input terminal and the signal 405 on the second input terminal are simultaneously converted into logic. 1 and logic 0, that is, the logic level on the two input terminals of the D-type latch is 1, 0, so that the positive phase output signal 407 and the inverted output signal 409 are logic 0 and logic 1, respectively.

Subsequently, in the timing phase P4 of FIG. 4B, the inverted output signal 409 of the logic 1 appears on the second input after the delay of the first delay time, so that the signal 405 on the second input is at the timing phase P4. The transition state is logic 1, so that the signal 405 on the second input has sequentially generated logic 0, 1, 0, 1 and the signal 405 on the second input continues to remain logic 1 in the subsequent timing phase. .

Finally, in the timing phase P3 of FIG. 4C, since the first delay time Td1 associated with the signal 405 on the second input terminal is longer than half of the second delay time Td2, the signal 405 on the second input terminal is in time series. Logic 1 remains in phase P3, at which point signal 403 on the first input has transitioned to logic 1, (ie, the logic level on both inputs of the D-type latch is 1, 1), making the phase The logic levels of the output signal 407 and the inverted output signal 409 are both logic ones.

Then, in the timing phase P4 of FIG. 4C, the signal 405 on the second input is changed from a logic 1 state to a logic 0. At this time, the signal 403 on the first input terminal is still logic 1, and the input is 1, 0. The combination will cause the D-type latch to output a positive phase output signal 407 of logic 0 and an inverted output signal of logic 1. The inverted output signal of logic 1 appears on the second input after delaying the first delay time, causing the signal 405 on the second input to transition to logic 1 at timing phase P5, the signal on the second input 405 can still normally generate logic 0, 1, 0, 1.

In the reset signal generator and the reset signal generating method of the above embodiment, the delay circuit is used to delay the signal of the D-type latch, and the reset signal can be generated twice to initialize the integrated circuit twice to improve the integrated body. The effect of circuit initialization, and the delay time does not need to be very precise, as long as it is within a certain range; the delay time between the power signal and the reset signal can be adjusted as needed, and the flexibility and applicability of the reset signal are increased. .

The present invention has been disclosed in the above embodiments, and is not intended to limit the present invention. Any one of ordinary skill in the art to which the present invention pertains can be variously modified without departing from the spirit and scope of the invention. The scope of protection of the present invention is therefore defined by the scope of the appended claims.

101. . . D type latch

103. . . Second delay circuit

105. . . First delay circuit

106. . . Reverse gate

107. . . Power signal

109. . . Reset signal

201. . . buffer

301~307. . . step

401. . . Power signal

403. . . Signal on the first input

405. . . Signal on the second input

407. . . Positive phase output signal

409. . . Inverted output signal

A. . . First input

B. . . Second input

D. . . Bungee

G. . . Gate

In. . . Input

Q. . . Positive phase output

Q’. . . Inverting output

S. . . Source

Td1. . . First delay time

Td2. . . Second delay time

P1. . . Timing phase

P2. . . Timing phase

P3. . . Timing phase

P4. . . Timing phase

P5. . . Timing phase

W. . . Connection end

The above and other objects, features, advantages and embodiments of the present invention will become more apparent and understood.

FIG. 1A is a circuit block diagram showing a reset signal generator according to an embodiment of the present invention.

FIG. 1B is a diagram showing signal waveforms of a reset signal generator according to an embodiment of the present invention.

2A, 2B, and 2C are circuit diagrams showing a first delay circuit and a second delay circuit according to an embodiment of the present invention.

FIG. 3 is a flow chart showing a method for generating a reset signal according to an embodiment of the present invention.

4A, 4B, and 4C are signal waveform diagrams of the reset signal generators of the three embodiments of the present invention.

101. . . D type latch

103. . . Second delay circuit

105. . . First delay circuit

106. . . Reverse gate

Claims (10)

A reset signal generator for generating a reset signal required to reset an integrated circuit, the reset signal generator comprising: a D-type latch having a first input and a second input And an inverting output terminal; a second delay circuit electrically connected to the first input end of the D-type latch, the second delay circuit delaying a power signal backward by a second delay time, Sending to the first input terminal; a first delay circuit electrically connected between the inverting output terminal and the second input terminal to invert an output signal of the output of the inverting output terminal, After being delayed by a first delay time, it is sent to the second input terminal, wherein the first delay time is shorter than the second delay time, and the inverted output signal is a reset signal after being delayed. The reset signal generator of claim 1, wherein the first delay time is equal to one half of the second delay time. The reset signal generator of claim 1, wherein the first delay time is greater than or less than half of the second delay time. The reset signal generator of claim 1, wherein the first delay circuit and the second delay circuit each comprise a resistor and a capacitor electrically connected in series to the capacitor, the resistor and the capacitor connection The signal on the terminal is the inverted output signal after the delay or the power signal after the delay. The reset signal generator of claim 1, wherein the first delay circuit and the second delay circuit each comprise: a transistor having a gate, a source, and a drain, wherein the drain The output signal after the delay is output or the power signal after the delay; a capacitor electrically connected between the gate of the transistor and the source; and a resistor electrically connected to the power Between the gate of the crystal and a ground. A reset signal generating method for generating a reset signal required to reset an integrated circuit reset, the reset signal generating method comprising: providing a D-type latch; one of the D-type latches An inverted output signal outputted by the inverting output is delayed by a first delay time and sent to a second input of the D-type latch; a power signal is delayed by a second delay time Thereafter, feeding to one of the first input terminals of the D-type latch, wherein the second delay time is longer than the first delay time; and the second input end of the D-type latch The signal output becomes the reset signal. The method for generating a reset signal according to claim 6, wherein the power signal is initially at a low logic level, and after a period of time, changes to a high logic level. The method for generating a reset signal according to claim 7, wherein the power signal is initially at a low logic level, and after a period of time, the power signal is changed to a high logic level. The reset signal generating method of claim 8, wherein the voltage logic level on the second input terminal of the D-type latch is initially a low logic level. The reset signal generating method of claim 6, wherein the first delay time is equal to, greater than, or less than half of the second delay time.