TW201306488A - All-digital clock data recovery device and transceiver implemented thereof - Google Patents

Abstract

The present invention relates to an all-digital clock data recovery (CDR) which is implemented by a digital filter and a digitally controlled oscillator. The CDR of the present invention comprises a phase detector producing a digital sequence of data and a digital sequence of edge by sampling the serial data stream with a clock, a de-serializer transforming the digital sequences of data and edge into n-bit bus, a digitally controlled oscillator (DCO) implemented by a multi-stage chain of inverters having a variable resistance switching matrix wherein the resistance of each element of the variable resistance switching matrix is varied in such a way that the supply current being fed to each inverter is controlled in pursuant to a digital control code, and thereby producing a clock whose oscillation frequency is updated and fed to the phase detector, a digital synthesis control logic circuit generating a thermometer-code-type digital control code out of the n-bit data and n-bit edge from the de-serializer wherein the thermometer-code-type digital control code is fed to the DCO, and a 2-bit direct forward path directly controlling the frequency of the clock being produced by the DCO with an operating speed which is faster than the digital synthesis control logic circuit by n times.

Description

Digital clock data recovery device and its associated transceiver

The invention relates to a clock data recovery (CDR) and a related transceiver (transceiver) for recovering clock signals and data from a bit stream input in a serial data communication mode, in particular, There is no analog circuit in all circuits of the pulse data restorer, which consists only of digital circuits.

Recently, a high-speed serial link communication method of one billion bits per GB (GB/s) has begun to spread, and serial interface transceivers are mounted in a single chip. These serial interface methods are chip-to-chip. In the communication, in order to prevent the receiving side from transmitting the clock signal separately, only the data is transmitted through the communication channel. Therefore, in order to process the bit data bit input of one billion bits per second, it is necessary to extract the clock data recovery (CDR) of the clock information and the data information from the serial data bit.

Nowadays, the industry generally adopts a voltage controlled oscillator (VCO; voltage controlled oscillator) and a charge pump phase-locked loop (CPPLL).

Figure 1 illustrates a charge pump phase locked loop commonly used in the industry.

Referring to FIG. 1, the conventional clock data recovery (CDR) circuit is composed of a phase detector (10), a frequency detector (20), a voltage controlled oscillator (VCO), and a charge excitation circuit. (40) Composition, the phase detector (10) of the conventional clock data recovery circuit samples the serial data bit stream through the clock provided by the VCO (30), and detects the phase of the data and the edge value and the sampled data.

At this time, if the phase measurement is delayed, the current clock frequency is slow, a rising (UP) signal occurs, the transistor (42) is turned on, the transistor (43) is turned off, the charge pump is activated, and the capacitance (41) is increased. Voltage at both ends. As a result, the applied voltage of the voltage controlled oscillator (30) becomes large, and thus the recovery clock frequency of the oscillator is tuned to become large.

On the contrary, if the phase of the phase detector (10) is too fast, the clock frequency needs to be made smaller, a falling (DN) signal is generated, and the charge excitation circuit (40) is used to lower the voltage across the capacitor (41). It acts as a pull down.

As described above, the conventional mode clock recovery circuit feeds back the output of the voltage controlled oscillator (30), monitors the detected phase of the serial data signal, and fine-tunes the recovery clock. At this time, if there is a significant error between the frequency of the signal input and the serial data registration frequency, the frequency detector (20) will force the sampling of the data by the lock and reference clock frequencies. .

The conventional CPPLL (charge pump phase-locked loop) mode clock recovery circuit is composed of an analog circuit or an analog-digital hybrid circuit. That is, in the conventional manner, the phase detector (10) and the frequency detector (20) are composed of digital circuits, and the right-side structure voltage-controlled oscillator (VCO; 30) and the driving charge excitation circuit (40) in FIG. 1 are generally analogous. An analog-digital hybrid circuit composed of circuits.

However, with the recent integration of semiconductor integrated circuits becoming more and more complex, the design rule will be reduced to less than one hundred nanometers, and the thickness of the logic gate oxide film is also reduced to several nanometers or ten nanometers according to the law of proportionality. range.

The capacitance on the semiconductor integrated circuit is usually a logic gate oxide film capacitor. If the thickness of the logic gate oxide film is reduced to the nanometer level, the capacitor (41) that constitutes the charge excitation circuit (40) in the conventional manner will have a leakage current (leakage current). ) A significant increase in the problem. Therefore, the control voltage of the voltage controlled oscillator (30) is affected by the leakage current, and the engineering of fine-tuning the recovery of the clock in the nano-scale semiconductor engineering is extremely difficult.

Moreover, the power supply voltage in the semiconductor integrated circuit using the design rule of a reduction ratio of 100 nm or less is less than 1.0 V, and as a result, the current source (45) required for the charge excitation circuit (40) shown in Fig. 1 cannot be generated.

If you want to use a MOS transistor to generate a current source, you should operate the transistor in a saturation mode. At least 1.0 V or more is required between the power line and the ground line.

Therefore, it is difficult to form an analog circuit type charge excitation circuit in an integrated circuit project of less than one hundred nanometers that uses a power supply voltage of 1.0 V or less.

Technical issues

SUMMARY OF THE INVENTION Accordingly, it is a first object of the present invention to provide a technique for forming an analog circuit type charge excitation circuit and a voltage control oscillator circuit by digital circuits and digitally circuiting all of the clock data restorers.

A second object of the present invention is to provide a jitter problem caused by quantization error and a slow action characteristic of a digital filter when a charge excitation circuit and a voltage control oscillator circuit are converted into a digital circuit by a digital circuit or a digital filter. And other issues provide solutions and their structure.

A third object of the present invention is to provide a circuit configuration for controlling the circuit structure size of a numerically controlled oscillator by a hardware method and a method of minimizing spikes and equalizing a frequency tuning step at the same interval and a circuit thereof.

The present invention describes a method of digitally circuiting all clock data recoverers to solve the jitter problem caused by leakage current in an analog semiconductor integrated circuit, even if the power supply voltage design is limited to less than 1.0V. The circuit does not have any problems. In addition, the present invention provides a solution to many technical problems occurring in the digital circuit process of the clock data recovery device.

In order to achieve the above object, the clock data recovery device digital filter of the present invention constitutes a charge excitation circuit, and a numerically controlled oscillator (DCO) is used to form a voltage controlled oscillator. The numerically controlled oscillator of the present invention is composed of multiple inverses. A multistage inverter chain is formed, a variable resistance switching matrix is generated between the supply voltage of each inverter and the inverter, and the resistance is adjusted. As a result, the method of tuning the oscillation frequency is used.

Industrial application possibility

As described above, the present invention uses a digital circuit to form all the circuits of the clock data recovery device, and solves the VCO leakage current problem of the conventional analog charge pump PLL circuit and the difficulty in reflecting the current in the semiconductor engineering applying the design rule of one hundred nanometer or less. Source problem. Moreover, the present invention realizes a frequency modulation structure by a digital filter and a numerically controlled oscillator (DCO), and can overcome the circuit design difficulty caused by a leakage current caused by a leakage current and a power supply voltage ratio reduction in a conventional analog circuit, and has a circuit design difficulty. The characteristics of the programmable filter coefficients.

In addition, in order to improve the speed of the digital filter, the direct forward path and the integral path of the loop stability are ensured, and the integral path can be operated by the auxiliary clock, and the problem of quantization noise and uneven tuning can be solved by the jitter circuit. The clock data restorer of the present invention can be applied to a one billion bit transfer speed transceiver at a supply voltage of 1.0 V or less.

As a representative embodiment of the present invention, the PMOS transistor array is composed of a variable resistance switching matrix, and the PMOS transistor will be controlled according to the input signal of the logic gate, and will function as a variable resistor. At this time, the present invention proposes a method of inserting a vertical resistance between the rows of the switching matrix in order to equalize the low bit frequency tuning step and the high bit frequency tuning step. It is clear that the vertical resistance consists of a PMOS transistor and the logic gate is grounded.

In addition, in order to cancel the jitter caused by the quantization error when the numerically controlled oscillator (DCO) is compared with the analog-mode voltage controlled oscillator (VCO), the first-order incremental sum modulator (1st ΣΔ modulator) performs jitter in the present invention ( The dithering algorithm, for example, ensures that errors can be prevented even if there is no pulse change in the digital signal input after the jitter processing of the 10-bit MSB and the 7-bit LSB by the 17-bit resolution.

When the clock data recovery device of the present invention inputs the numerical control oscillator oscillation frequency control code in a binary manner, the control circuit scale becomes larger, and the wafer size is also increased. The present invention employs a segmented thermometer. In this way, the numerically controlled oscillator is tuned with a small number of routing lines.

The invention is described in detail in the first item to the seventh item of the application, wherein the data clock recovery device of the invention has a current clock, samples the serial input data, and detects the phase of the output data and the edge digital signal sequence. a serial-to-parallel converter that performs an 1:n conversion on the output signal of the phase detector and the digital signal sequence of the edge value in a manner of n-bit bus signals; by a multi-stage inverter chain (multi- Stage inverter chain) A variable resistance switching matrix composed of a supply voltage for each inverter constituting the inverter chain and a supply current between the inverters, externally numerically controlling the current supplied to the power supply The frequency-adjusted clock is supplied to the numerically controlled oscillator (DCO) of the phase detector; the n-bit output data of the serial-to-parallel converter and the n-bit edge data are received, and a thermometer code-like numerical control code is generated and provided to the above a digitally synthesized oscillator control logic circuit; receiving the output data of the phase detector and the edge and forming a 2-bit direct forward path, which is synthesized by the above digital The n-speed of the control logic circuit directly controls the direct forward path circuit of the clock frequency of the numerically controlled oscillator, and the above-mentioned constituent factors are all composed of digital circuits. The present invention provides a clock data recovery device characterized by the above.

In addition, the digital synthesis control logic circuit constituting the clock data recovery device of the present invention comprises: receiving the n-bit output data and the n-bit edge data of the serial-to-parallel converter and outputting the frequency at the [-n∼+n] range level. a pulse signal generator for increasing or decreasing a command code; a digital integrator that integrates a pulse signal output of the pulse signal generator and generates (m+k) a bit digital code; (m+k) bits of the digital integrator The low-order LSB k bits in the meta-output digital code are dithering and output a first-order incremental sum modulator having a resolution of m-bit digital code (m+k) bits composed of a high-order MSB; A total of 2m frequency tuning levels of the m-bit output code of the first-order incremental sum modulator are converted into 2m/2+ (2m/2-1) digit thermometer codes and supplied to the variable resistors constituting the numerically controlled oscillator Binary-to-Segment thermometer converter for switching the row and row routing lines of the matrix; when the clock frequency output of the numerically controlled oscillator generates an error above the selected value of the reference frequency, forcibly inputting a frequency check corresponding to the reference frequency digital code Device.

In addition, in the present invention, in order to remove the spike generated when the variable resistance switching matrix data is changed, the first row element of the variable resistance switching matrix becomes "on" state when the row code of the variable resistance matrix is "1", even number The row elements become "on" when their row code is "1", and the odd row elements become "on" when their row code is "0".

In addition, in order to equalize the frequency tuning step, the variable resistance switching matrix constituting the numerically controlled oscillator of the present invention has an element for controlling the initial oscillation when the frequency is tuned to have a 2m/2x2m/2 element and a power-up. The PMOS gate voltage control resistor matrix is formed, preferably by inserting a PMOS gate voltage control resistor whose logic gate is grounded between rows.

Exemplary embodiments of the clock data restorer of the present invention and their features will be described in detail below with reference to Figs. 2 through 14.

2 illustrates the configuration of a clock data restorer in the present invention, as shown in FIG. 2, as a representative embodiment of the present invention, a phase detector (PD; 10), a frequency detector (20), and a digital filter. (100) is composed of a numerically controlled oscillator (DCO; 200).

However, in the case of using a digital filter (100) and a numerically controlled oscillator (DCO; 200) as shown in FIG. 2, it is necessary to solve the technical problem when the clock generating circuit is formed by a digital circuit. That is, the numerically controlled oscillator (200) constituting the CDR of the present invention cannot actually avoid the jitter caused by the quantization error according to its characteristics, and should be designed high in order to alleviate the time uncertainty. Resolution CNC oscillator.

In addition, when there is no pulse change in the serial data bit stream input to the phase detector (10), for example, when the "1" signal or the "0" signal such as 11111111000... has no continuous pulse change When the phase and frequency are detected, error accumulation will occur.

Therefore, the ADPLL (all-digital phase-locked loop) clock data recovery device of the present invention provides a technical solution for the digital circuitization process such as the aforementioned quantization error occurrence problem and the phase and frequency detection cumulative error occurrence problem.

In addition, as shown in FIG. 2, the structure of the digital data filter (100) constituting the clock data recovery device of the present invention has a very slow operation speed of about several hundred MHz, and it is difficult to process billions of bits per second (GBPS). The phase detector (10) of the stream input data is synchronized. The operation speed of the digital element filter circuit is slow, so that it is difficult to form a digital circuit, and the present invention provides a solution as follows.

3 illustrates the construction of a clock data restorer according to an exemplary embodiment of the present invention. As shown in FIG. 3, the clock data restorer of the present invention is characterized by a direct forward path having a transmission speed of one billion bits (direct Forward path) with a low-speed integral path of several hundred megahertz, that is, its composition distinguishes the synthesis control logic circuit (600), and the synthesis control logic circuit (600) passes the string through a 1:8 serial-parallel converter (deserializer; 8) The serial data is transformed into an 8-bit parallel data bus pattern, which is divided by eight times and transmitted to the digital filter (100). Thus, the clock speed of the digital synthesis control logic circuit (600) is reduced by one eighth, and as a result, the digital filter (100) can accurately track the frequency.

3 is a 1:8 serial-to-parallel conversion for convenience of explanation of the present invention, 7 bits of 17 bits are used for the LSB for dithering, and a 10-bit numerical control code is generated. The embodiment exemplifies the generation of the 32-bit thermometer code, but The invention is not limited to this.

The data sampler and retimer (9) sample the serial data registration, perform XOR calculation (65) on the sampled data and the edge value, and then integrate the phase information through the integrator (66) to control The numerically controlled oscillator (200) provides proper damping during the clock recovery phase.

That is, by directly detecting the sampling data and the edge phase of the data flow of the billion-digit data per second of the serial input data as shown in FIG. 3, the numerical control oscillator (200) is directly controlled, and A damping factor effect is applied to ensure the tuning stability of the circuit.

Meanwhile, an 8-bit bus input data and an edge signal which are deserialized at a 1:8 ratio according to an exemplary embodiment of the present invention are input to a pulse and adder (up/dn ∑ 28) - The 16 levels between 8∼+8 are output as 4-bit information, and the tracking information and filter coefficients of the 4-bit phase are multiplied by the integrator (29) and then passed through the digital integrator (29). Addition calculus.

At the same time, the 17-bit output information of the digital integrator (29) is converted into 10-bit information by the first-order incremental sum modulator (300), and the first-order incremental sum modulator (300) not only performs so-called jitter The dithering process, as described above, solves the frequency error accumulation problem when the detection result shows that the input serial data signal is continuous equivalent and has no phase change.

According to an exemplary embodiment of the present invention, the upper 10 bits of the 17-bit information represent a positive number, and the remaining 7 bits represent values below the decimal point, and the frequency accumulation error is solved. That is, when the digital data is continuously input as 111..., the dither circuit supplies its value to the value below the decimal point and compensates for the quantization error.

At the same time, the 10-bit digital signal output from the first-order incremental sum modulator (300) is divided into 5 bits by the Binary-to-Segment thermometer transducer (400) and converted into a 32-bit thermometer. In this way, the 10-bit data becomes a 32-bit x32-bit thermometer signal after being segmented by 5 bits, and the hardware can be made smaller.

Figure 4 is a diagram showing the operation principle of the Binary-to-Segment thermometer (400) constituting the clock data recovery device of the present invention. As shown in Fig. 4, the inverter (350) is connected to the ring oscillation connected by the feedback chain. Composition. At the same time, the supply current of the ring oscillator inverter (350) can be controlled by the variable resistor (351) to increase the size of the variable resistor (351), and the oscillation frequency of the ring oscillator will vary with the supply current. Conversely, if the variable resistor (351) is turned down, the oscillation frequency will increase.

The Binary-to-Segment thermometer converter (400) of the present invention focuses on outputting information of a 10-bit bus of the first-order incremental sum modulator (300), that is, 210=1024 level input is 25×25, that is, Reflects the 32×32 switching matrix. That is, the present invention replaces 1024 control lines with a 32×32 switching matrix and performs tuning control on the oscillation frequency. For example, when the performance level 131 is 131 = 32×4+3, 4 is the MSB, and the row displays “1111000”. ...00", the remaining 3 is LSB, and the column shows "11100...000".

As shown in Figure 4, MSB 4 is a total of 32 bits "11100...000", the line is displayed, LSB 3 is "1110000...000", the line is displayed. At this time, when the line data is 1, the switching matrix becomes ON. When the data is 0, the reference line data is turned ON when it is 1 and becomes OFF when it is 0, and it becomes as shown in Fig. 4. In this way, 1024 levels can be represented by a 32 × 32 switching matrix, so that the hardware size can be greatly reduced by replacing the 1024-level hardware with 64 or so hardware.

However, in the case of the segmented thermometer converter of the matrix switching method of the present invention, a glitch can occur when the line code changes from 1 to 0 or from 0 to 1. That is, for example, a Binary-to-Segment thermometer converter (400) that controls the input current of the numerically controlled oscillator (200) when level 127 (127 = 32 × 3 + 31) -> 128 (128 = 32 × 4 + 0) is transformed. The MSB of the switching matrix is transformed from (11100...0) to (11110000...0), and the LSB is transformed from (11111...1) to (000...0). At this time, all bits of LSB 1 → 0, signal noise spikes can occur ( Glitch), in the present invention, provides a solution for preventing the above spikes.

5 and FIG. 6 illustrate an algorithm and composition method of a switching matrix mode segmented thermometer converter capable of preventing spikes according to an exemplary embodiment of the present invention. As shown in FIG. 6, an even row and a row are distinguished in an MSB row. Odd lines and inverting the input line data of the odd line control logic circuit, the result prevents most LSBs from being simultaneously transformed from (1111...1) to (00...0) when the MSB changes from 0 to 1.

As shown in FIG. 6, the even row cell constitutes an OAI (OR-AND-INVERT; 88) circuit, the OR gate inputs the current row (2n) and the row (m), and the switch when the row code is "1" In the "ON" state, on the contrary, the odd row cell is flipped (89) and the OAI line input is input. When the row code is "0", the switch becomes "ON" state, thus ensuring that only one switch can be always used. Perform state switching.

That is, in the present invention, the variable resistance switching matrix constituting the numerically controlled oscillator (200) is provided with a 2 ^m/2 x 2 ^m/2 element for frequency tuning and an element for controlling initial oscillation when power-up is performed, and the above element is a PMOS gate. The voltage control resistor matrix is composed, and the PMOS gate voltage control resistor whose logic gate is grounded is inserted between the rows, the inverted row data is input in the logic gate of the first row component, and the row data and the row data are input in the logic gate of the even row component The OAI (or-and-invert, 88) calculation result of the calculus result and the AND calculation result of the preceding data, and the OR calculation result of the row data and the row data of the input of the logical gate of the odd row element are inverted (89) The not-OAI (not-or-and-invert) calculation result of the AND calculation result of the preceding data.

The invention uses a 32×32-bit switching matrix to change the resistance connected to the power supply and controls the input current of the numerically controlled oscillator (200), but the current change is 100% when 1->2 conversion occurs in 1024 current levels. When the 1023->1024 level conversion occurs, the change is only 0.1%, so the amount of change is required to equalize the job.

Thus, in order to reduce the influence of the high-order switch and equalize the influence of the low-order switch in the switching matrix, the array of the first PMOS transistor (91) constructed in order to embody the variable resistance factor (91') in the present invention A second PMOS transistor (92) showing a vertical resistance (92') is additionally inserted between the rows to equalize the current rate of change.

FIG. 7 illustrates a configuration in which a resistor array constituting a switching matrix is added to a first PMOS transistor (91) and a second PMOS transistor (92) is inserted between rows in order to achieve equalization of resistance variation, according to an exemplary embodiment of the present invention.

Figure 8 is a view showing the structure of the direct forward path constituting the clock data restorer in the present invention. As described above, the clock data restorer of the present invention passes the 1:8 serial-to-parallel converter (8) to the numerically controlled oscillator (200). FM, 8-bit data and 8-bit edge information are input to the control logic circuit (not shown) and output 32+32-bit thermometer code, in order to ensure the stability of the feedback loop 2-bit forward path connection phase detection (10) and numerically controlled oscillator (200).

The invention is characterized in that the charge pump PLL is used to replace the conventional mode charge excitation circuit and the RC loop filter, and the numerically controlled oscillator (200) shown in FIG. 8 can be composed of a 3-stage inverter chain. The power supply can be composed of a digitally controlled variable resistor (digitally controlled). As a representative embodiment of the present invention, the digitally controlled variable resistor is composed of 1024 PMOS transistor switches for frequency tuning, and 96 switches are formed to control the initial oscillation when the power is raised.

The numerically controlled oscillator (200) of the clock data recovery device of the present invention is a 2-bit direct path with a tuning element (700), and receives a pulse signal from the phase detector (10), directly to the tuning element of the forward path (700). It is eight times faster than the integral path (not shown) and directly controls the frequency of the numerically controlled oscillator (200) to ensure circuit stability.

The numerically controlled oscillator (200) controls the pulse (UP/DNb) signal between 1 and 8 tuning elements according to the CPROP value, and analyzes the tuning step of the numerically controlled oscillator (200) from the viewpoint of loop stability and bandwidth (fstep = Fn+1/fn) is preferably equal. Equalization of the frequency tuning steps means that as the numerical control code increases the frequency, an increase occurs in the form of an exponential function fn = f0fstepn.

To this end, the present invention additionally inserts a PMOS transistor between rows and forms a switching matrix such that the resistance is adjusted in a manner similar to the exponential function of the row code to bring the frequency tuning close to the exponential function.

9 and FIG. 10 illustrate frequency tuning results obtained when another resistor is inserted between the rows of the switching matrix in accordance with the present invention. As shown in FIG. 9, when the digital oscillator (200) constituting the clock data restorer of the present invention is numerically controlled, When the code is changed from 0 to 1024, the value is almost equal to the ideal value. Further, as shown in Fig. 10, the numerically controlled oscillator (200) constituting the clock data restorer of the present invention has an almost equal rate of change in the level change of the control code.

As a representative embodiment of the present invention, FIG. 11 illustrates an integral path constituting a clock data restorer structure, and FIG. 11 illustrates an operation principle of the composite control logic circuit (600) of FIG. 3, and a synthetic control circuit (fully synthesized control) Logic; 600) by pulse (UP / DN) signal generator (28), digital integrator (29), first-order incremental sum modulator (300), Binary-to-Segment thermometer (400) frequency detector (31) Composition.

The pulse signal generator (28) generates a [-8∼+8] pulse signal from the 16-bit signal transmitted by the 1:8 serial-to-parallel converter (8) at the front end, and at the same time, the digital integrator (29) pairs are input. -8∼+8] The phase information of the range is integrated and a 17-bit frequency code is generated. It is extremely difficult to form a numerically controlled oscillator (DCO; 200) with 17-bit resolution by hardware, so the first-order increment is utilized. The sum modulator (1 ^st order ΣΔmodulator; 300) dithers the LSB 7 bits in 17 bits and generates an MSB 10-bit frequency control code. In this way, the jitter algorithm is applied, and when the serial input data has no pulse change, the LSB 7 bits can be used to generate a code below the decimal point.

12 and 13 show an embodiment in which the clock is recovered by the clock data restorer of the present invention. Referring to Figures 12 and 13, it can be seen that the resolution of the center frequency is 8 ppm, which is equivalent to the 17-bit resolution of the digital integrator (29). As shown in Fig. 12, the spur jitter frequency also appears in 312.5 MHz, which is consistent with the 1/8 speed action of the jitter logic circuit when the bit transfer rate of the input serial data is 2.5 Gb/s.

The quantization effect will be transformed into jitter in its field. Figure 14 illustrates the PRBS 231-1 mode at 1.2V power supply and 2.5Gb/s bit transfer speed. As shown in Figure 11, the RMS jitter is 7.2 PS. The inter-jitter is 47.2 PS, which is sufficient for the purpose of the one-bit transceiver.

The above description may explain the scope of the invention patent application described below, and the following describes the additional features and the like which constitute the scope of the patent application of the present invention. Those skilled in the related art of the present invention should keep in mind that the concept and specific embodiment of the present invention can be Other structural designs or modifications are contemplated for use with the present invention and the like.

In addition, those skilled in the art to which the invention pertains can make reference to the concepts and embodiments of the present invention and apply to other structures for the same purpose of the present invention. In addition, modifications or alterations, etc., which are Various modifications, alterations and changes can be made in the structure of the invention without departing from the scope of the invention.

8. . . 1:8 serial to parallel converter

9. . . Data sampler and retimer

10. . . Phase detector

20. . . Frequency detector

28. . . Pulse signal generator

29. . . Digital integrator

30. . . Voltage controlled oscillator

31. . . Frequency detector

40. . . Charge excitation circuit

41. . . capacitance

42. . . Transistor

45. . . Battery

65. . . Calculus

66. . . Integrator

88. . . OAI circuit

89. . . Flip

91. . . First PMOS transistor

91’. . . Variable resistance factor

92. . . Second PMOS transistor

92’. . . Display vertical resistance

100. . . Digital filter

200. . . Numerically controlled oscillator

300. . . First order incremental sum modulator

350. . . inverter

351. . . Variable resistance

400. . . Binary-to-Segment thermometer converter

600. . . Synthetic control logic

700. . . Tuning element

Figure 1 illustrates a conventional charge pump phase-locked loop (CPPLL) receiver.

Figure 2 illustrates the construction of the clock data recovery (CDR) of the present invention using a digital circuit.

Figure 3 illustrates a clock data restorer constructed using digital circuitry in accordance with an exemplary embodiment of the present invention.

Fig. 4 is a view showing the principle of operation of the Binary-to-Segment thermometer transducer (B2T) in the constituent elements of the clock data recovery device of the present invention.

5 and 6 illustrate a method of constructing an algorithm for preventing glitch and a digital circuit in advance according to an exemplary embodiment of the present invention.

Figure 7 illustrates a process of adding a vertical resistor between the rows of a variable resistance switching matrix in accordance with an exemplary embodiment of the present invention, the purpose of which is to equalize the resistance change.

Figure 8 is a diagram showing the construction of a direct forward path in the clock data recovery device of the present invention.

9 and 10 illustrate frequency tuning results obtained after another resistor is inserted between the rows of the switching matrix in accordance with an exemplary embodiment of the present invention.

Figure 11 illustrates an integral path constituting a clock data restorer structure in accordance with an exemplary embodiment of the present invention.

12 and 13 illustrate an embodiment of recovering a clock using the clock data restorer of the present invention.

Figure 14 is a diagram showing a PRBS (231-1) mode for a 1.2V power supply and a 2.5 Gb/s bit transfer rate in accordance with an embodiment of the present invention.

8. . . 1:8 serial to parallel converter

9. . . Data sampler and retimer

10. . . Phase detector

28. . . Pulse signal generator

29. . . Digital integrator

31. . . Frequency detector

65. . . Calculus

66. . . Integrator

200. . . Numerically controlled oscillator

300. . . First order incremental sum modulator

400. . . Binary-to-Segment thermometer converter

600. . . Synthetic control logic

Claims (7)

A digital clock data recovery device, which recovers data and time-stamped data in a clock recovery device (CDR) after receiving serial data, wherein the data clock recovery device samples the serial data registration through the current clock. a phase detector for outputting a data and an edge digital signal sequence; a serial-to-parallel converter for 1:n conversion of an output signal of the phase detector and a digital signal sequence of edge values with an n-bit bus signal (deserializer); a variable consisting of a multi-stage inverter chain and adjusting the resistance between the supply voltages of the inverters of the inverter chain and the inverters for current digital control The resistance switching matrix controls the current through an external digital control, generates a frequency-adjusted clock, and supplies the numerically controlled oscillator (DCO) to the phase detector; receives n-bit output data and n-bit edge data of the serial-to-parallel converter, Generating a numerical control code of the thermometer code form and providing the digital synthesis control logic circuit to the numerical control oscillator; receiving the output data and edge of the phase detector And a 2-bit direct forward path is formed, and the direct forward path circuit of the numerical control oscillator clock frequency is directly controlled by the n-times of the above-mentioned digital synthesis control logic circuit, and the above-mentioned constituent factors are all composed of digital circuits. The digital clock data recovery device according to claim 1, wherein the digital synthesis control logic circuit receives the n-bit output data of the serial-to-parallel converter and the n-bit edge data, and outputs [-n∼+n a pulse signal generator for increasing or decreasing the frequency of the command code; a digital integrator that integrates the pulse signal output of the pulse signal generator and generates a (m+k) bit digital code; output to the digital integrator ( m+k) The low-order LSB k-bit of the bit-digit code is subjected to dithering processing, and the m-bit digital code composed of the upper MSB is output, and the first-order incremental sum of the (m+k) bit resolution is obtained. a modulator; converting a total of 2n frequency tuning levels corresponding to the first-order incremental sum modulator m-bit output code into a 2s/2+ (2m/2-1)-bit thermometer code and providing the above-mentioned numerical control oscillation Binary-to-Segment thermometer transducer for the row and row routing of the variable resistance switching matrix of the device; when the clock frequency output of the numerically controlled oscillator is more than the selected value compared with the reference frequency, the forced input is equivalent The above mentioned The frequency detector of the frequency digital code. The digital clock data recovery device according to claim 1, wherein the variable resistance switching matrix constituting the numerically controlled oscillator has a 2s/2x2x/2 component and a power-up control initial oscillation for frequency tuning. The first row component becomes "on" when its row value is "1", and the even row component becomes "on" when its row code is "1", and the odd row component is in its row code. When it is "0", it becomes "on" state. The digital clock data recovery device according to claim 1, wherein the variable resistance switching matrix constituting the numerically controlled oscillator has a 2x/2x2m/2 component and a power-up control initial oscillation for frequency tuning. The component is composed of a PMOS gate voltage control resistor matrix, and a PMOS gate voltage control resistor whose logic gate is grounded is inserted between the rows. The digital clock data recovery device according to claim 1, wherein the variable resistance switching matrix constituting the numerically controlled oscillator has 2m/2x2m/2 elements and power-up for frequency tuning in order to control the initial stage. The oscillation has another component, and the component is composed of a PMOS gate voltage control resistor matrix, and a PMOS gate voltage control resistor whose logic gate is grounded is inserted between rows, and a row row data, an even row is input in a logic gate of the first row component In the logic gate of the component, the OR calculation result of the line data and the line data is input, and the OAI (or-and-invert) calculation result of the forward data and the calculation result is inverted, and the input of the logic gate of the odd row element is inverted (invert) The not-OAI (not-or-and-in-vert) calculation result of the OR data of the line data and the line data and the AND calculation result of the line data. The digital clock data recovery device according to claim 1, wherein the direct forward path circuit performs XOR calculation on the data and the edge value of the phase detector to generate a pulse signal to the numerically controlled oscillator variable resistance switching matrix. The lowermost 2m/2 element logic gate provides a pulse signal that is n times faster than the above-described digital synthesis control logic circuit to tune the frequency of the numerically controlled oscillator. A transceiver having a digital clock data recovery device, wherein the transceiver has the digital clock data recovery device according to any one of claims 1 to 6.