TW201306172A - A method for making a semiconductor device - Google Patents
A method for making a semiconductor device Download PDFInfo
- Publication number
- TW201306172A TW201306172A TW100126388A TW100126388A TW201306172A TW 201306172 A TW201306172 A TW 201306172A TW 100126388 A TW100126388 A TW 100126388A TW 100126388 A TW100126388 A TW 100126388A TW 201306172 A TW201306172 A TW 201306172A
- Authority
- TW
- Taiwan
- Prior art keywords
- wafer
- tsv
- dry film
- semiconductor device
- semiconductor
- Prior art date
Links
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Mechanical Treatment Of Semiconductor (AREA)
Abstract
Description
本發明是有關於一種半導體裝置的製造方法,特別是指一種包含直通矽晶穿孔(Through Silicon Via,TSV)製程的半導體裝置的製造方法。The present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a semiconductor device including a through silicon via (TSV) process.
在三維積體電路(3D IC)中利用直通矽晶穿孔(TSV)製程技術來電連接堆疊的晶片是近年來較受矚目的新一代技術。現有製作矽穿孔的製程主要有兩類,其一為前穿孔(via first)製程,另一為後穿孔(via last)製程,前穿孔製程是在晶片製造步驟之前完成矽穿孔,後穿孔製程則是在晶片製造步驟之後的封裝階段才進行TSV製程,兩種製程各有其優缺點,因為使用需求不同,而成為TSV技術的兩大主流。The use of through-transistor via (TSV) process technology to electrically connect stacked chips in a three-dimensional integrated circuit (3D IC) is a new generation technology that has attracted much attention in recent years. There are two main processes for making the perforation of the crucible, one is the via first process and the other is the via last process. The front perforation process is to complete the perforation before the wafer fabrication step, and the post perforation process is The TSV process is performed at the packaging stage after the wafer fabrication step. Both processes have their own advantages and disadvantages, and become the two mainstreams of TSV technology because of different usage requirements.
目前以前穿孔製程形成半導體裝置的具體製程步驟是:先在一晶圓上形成多個位於特定位置的盲孔,再於各盲孔填滿導電材料,之後,實施半導體製程步驟,例如形成互補金氧半導體(CMOS),及晶圓後段導線製程(BEOL),然後研磨晶圓背面將晶圓薄化,以使盲孔變成貫穿晶圓的穿孔。At present, the specific process steps for forming a semiconductor device by a via process are: firstly forming a plurality of blind holes at a specific position on a wafer, filling the blind holes with conductive materials, and then performing a semiconductor process step, for example, forming a complementary gold. Oxygen semiconductor (CMOS), and post-wafer wire processing (BEOL), then polishing the backside of the wafer to thin the wafer so that the blind via becomes a through-wafer.
然而,由於盲孔之間的距離很近,在晶圓薄化的研磨過程中,容易造成晶圓的破裂,導致製程良率低,而增加製造成本。However, since the distance between the blind vias is very close, the wafer is easily broken during the polishing process of the wafer thinning, resulting in low process yield and increased manufacturing cost.
因此,本發明之目的,即在提供一種可以使晶圓不易破裂以提高製程良率的半導體裝置之製造方法。Accordingly, it is an object of the present invention to provide a method of fabricating a semiconductor device that can prevent wafers from being broken and improve process yield.
於是,本發明半導體裝置之製造方法,包含:直通矽晶穿孔(TSV)製程步驟及半導體製程步驟,其中在進行直通矽晶穿孔(TSV)製程步驟及半導體製程步驟之前,先將一晶圓薄化至一預定厚度,再於薄化後的晶圓的兩表面分別被覆一乾膜,接著在晶圓進行直通矽晶穿孔(TSV)製程步驟,其後再進行半導體製程步驟。Therefore, the method for fabricating the semiconductor device of the present invention comprises: a through-silicon via (TSV) process step and a semiconductor process step, wherein a wafer is thinned before the through-silicon via (TSV) process step and the semiconductor process step are performed. After a predetermined thickness is formed, a dry film is respectively coated on both surfaces of the thinned wafer, and then a through-silicon via (TSV) process step is performed on the wafer, and then a semiconductor process step is performed.
本發明之功效,本發明在進行TSV製程之前先將晶圓薄化,亦即在晶圓研磨薄化的過程中,晶圓為完整的塊體,具有較高的強度以抵抗研磨過程所施加的外力,使晶圓在薄化過程較不易破裂,而且,在薄化後的晶圓兩表面分別被覆乾膜,可以在TSV製程中分別作為保護層和支撐結構,不僅能製作較深的穿孔,且能避免薄化後的晶圓破裂,而能提高整體製程的良率。The effect of the present invention is that the wafer is thinned before the TSV process is performed, that is, in the process of wafer grinding and thinning, the wafer is a complete block and has high strength to resist the application of the grinding process. The external force makes the wafer less susceptible to cracking during the thinning process, and the dry film is coated on both surfaces of the thinned wafer, which can be used as a protective layer and a support structure in the TSV process, respectively, and can not only make deep perforations. And can avoid wafer cracking after thinning, and can improve the overall process yield.
有關本發明之前述及其他技術內容、特點與功效,在以下配合參考圖式之一個較佳實施例的詳細說明中,將可清楚的呈現。The above and other technical contents, features and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments.
在本發明被詳細描述之前,要注意的是,在以下的說明內容中,類似的元件是以相同的編號來表示。Before the present invention is described in detail, it is noted that in the following description, similar elements are denoted by the same reference numerals.
本發明半導體裝置之製造方法之一較佳實施例包含直通矽晶穿孔(TSV)製程步驟及半導體製程步驟,其中半導體製程的具體實施步驟可以採用現有的半導體製程技術,且可以依據使用需求調整,並非本發明的重點,以下僅針對TSV製程的部分詳細說明。A preferred embodiment of the method for fabricating a semiconductor device of the present invention comprises a through-silicon via (TSV) process step and a semiconductor process step, wherein the specific implementation steps of the semiconductor process can be performed by using existing semiconductor process technology, and can be adjusted according to usage requirements. It is not the focus of the present invention, and only the details of the TSV process are described in detail below.
參閱圖1,在進行TSV製程前,先將晶圓1薄化至一預定厚度,亦即將晶圓1薄化,薄化後的晶圓1’的厚度可依據使用需求調整。Referring to Fig. 1, before performing the TSV process, the wafer 1 is thinned to a predetermined thickness, that is, the wafer 1 is thinned, and the thickness of the thinned wafer 1' can be adjusted according to the use requirements.
再於薄化後的晶圓1’的兩表面分別被覆一乾膜2,可以利用熱壓合將乾膜2貼合於晶圓1’的表面。在本實施例中,被覆於晶圓1’上表面的乾膜2用以圖案化,以定義出欲在晶圓1’上形成穿孔的位置,並做為蝕刻晶圓1’以形成穿孔時的保護層。由於乾膜2的厚度可達幾十微米,甚至可達100微米,相較於一般濕式光阻的厚度較厚,而能在製作較深的穿孔時,足以抵擋較長時間的蝕刻,以保護不需要蝕刻的部分。此外,被覆於晶圓1’下表面的乾膜2是用來支撐晶圓1’。由於晶圓1’形成穿孔後的結構較為脆弱,尤其是穿孔密度較高時,而藉由下表面的乾膜2可以提供支撐,以避免晶圓1’破裂。Further, a dry film 2 is coated on both surfaces of the thinned wafer 1', and the dry film 2 can be bonded to the surface of the wafer 1' by thermal compression bonding. In the present embodiment, the dry film 2 coated on the upper surface of the wafer 1' is patterned to define a position where a via is to be formed on the wafer 1', and is used as the etched wafer 1' to form a via. Protective layer. Since the thickness of the dry film 2 can be several tens of micrometers or even 100 micrometers, it is thicker than the general wet photoresist, and can be used to resist etching for a long time when making deep perforations. Protect the parts that do not require etching. Further, the dry film 2 coated on the lower surface of the wafer 1' is used to support the wafer 1'. Since the structure after the formation of the perforations of the wafer 1' is relatively fragile, especially when the perforation density is high, the dry film 2 of the lower surface can provide support to prevent the wafer 1' from being broken.
接著在覆有乾膜2的晶圓1’進行直通矽晶穿孔(TSV)製程步驟,直通矽晶穿孔(TSV)製程步驟包括:圖案化其中之一乾膜2(即上表面之乾膜2),以定義預備在晶圓1’形成多個貫穿晶圓1’的穿孔11的位置,如圖1所示,在晶圓1’上表面的乾膜2被圖案化,而在乾膜2上形成多個貫孔21,此等貫孔21所在的位置即預備形成由貫孔21延伸而貫穿晶圓1’的穿孔11的位置。Then, a through-silicon via (TSV) process step is performed on the wafer 1' coated with the dry film 2, and the through-silicon via (TSV) process includes: patterning one of the dry films 2 (ie, the dry film on the upper surface 2) To define a position for forming a plurality of through holes 11 through the wafer 1' at the wafer 1', as shown in FIG. 1, the dry film 2 on the upper surface of the wafer 1' is patterned, and on the dry film 2 A plurality of through holes 21 are formed, and the positions of the through holes 21 are formed to be positions where the through holes 21 extend to penetrate the through holes 11 of the wafer 1'.
接著,通過已圖案化的乾膜2形成貫穿晶圓1’的多個穿孔11。具體而言,在本實施例中,在晶圓1’上形成貫穿的穿孔11可以採用現有的晶圓蝕刻技術,藉由圖案化的乾膜2作為保護層,使晶圓1’表面覆蓋有乾膜2的部分不會被蝕刻或受損。Next, a plurality of through holes 11 penetrating the wafer 1' are formed by the patterned dry film 2. Specifically, in the embodiment, the through-holes 11 formed in the wafer 1' can be covered by the existing wafer etching technology, and the patterned dry film 2 is used as a protective layer to cover the surface of the wafer 1'. The portion of the dry film 2 is not etched or damaged.
形成穿孔11後,移除晶圓1’兩表面的乾膜2。After the perforations 11 are formed, the dry film 2 on both surfaces of the wafer 1' is removed.
然後在穿孔11內形成貫穿晶圓1’的垂直導線3。形成垂直導線3的步驟可以採用現有的技術實施,於此不再詳述。A vertical wire 3 extending through the wafer 1' is then formed in the through hole 11. The step of forming the vertical wires 3 can be carried out using existing techniques and will not be described in detail herein.
其後在具有垂直導線3的晶圓1’上再進行半導體製程步驟。Thereafter, a semiconductor process step is performed on the wafer 1' having the vertical wires 3.
綜上所述,本發明在進行TSV製程之前先將晶圓1薄化,亦即在晶圓1研磨薄化的過程中,晶圓1為完整的塊體,具有較高的強度以抵抗研磨過程所施加的外力,使晶圓1在薄化過程較不易破裂,而且,在薄化後的晶圓1’兩表面分別被覆乾膜2,可以在TSV製程中分別作為保護層和支撐結構,不僅能製作較深的穿孔11,且能避免薄化後的晶圓1’破裂,而能提高整體製程的良率。In summary, the present invention thins the wafer 1 before performing the TSV process, that is, during the polishing and thinning of the wafer 1, the wafer 1 is a complete block with high strength to resist grinding. The external force applied by the process makes the wafer 1 less susceptible to cracking during the thinning process, and the dry film 2 is respectively coated on both surfaces of the thinned wafer 1', which can be used as a protective layer and a support structure in the TSV process, respectively. Not only can the deeper perforations 11 be made, but the thinned wafer 1' can be prevented from being broken, and the overall process yield can be improved.
惟以上所述者,僅為本發明之較佳實施例而已,當不能以此限定本發明實施之範圍,即大凡依本發明申請專利範圍及發明說明內容所作之簡單的等效變化與修飾,皆仍屬本發明專利涵蓋之範圍內。The above is only the preferred embodiment of the present invention, and the scope of the invention is not limited thereto, that is, the simple equivalent changes and modifications made by the scope of the invention and the description of the invention are All remain within the scope of the invention patent.
1...晶圓1. . . Wafer
1’...晶圓1'. . . Wafer
11...穿孔11. . . perforation
2...乾膜2. . . Dry film
21...貫孔twenty one. . . Through hole
3...垂直導線3. . . Vertical wire
圖1是一說明本發明半導體裝置之製造方法的一較佳實施例的步驟流程示意圖。BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a flow chart showing the steps of a preferred embodiment of a method of fabricating a semiconductor device of the present invention.
1...晶圓1. . . Wafer
1’...晶圓1'. . . Wafer
11...穿孔11. . . perforation
2...乾膜2. . . Dry film
21...貫孔twenty one. . . Through hole
3...垂直導線3. . . Vertical wire
Claims (2)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW100126388A TW201306172A (en) | 2011-07-26 | 2011-07-26 | A method for making a semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
TW100126388A TW201306172A (en) | 2011-07-26 | 2011-07-26 | A method for making a semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
TW201306172A true TW201306172A (en) | 2013-02-01 |
Family
ID=48169265
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
TW100126388A TW201306172A (en) | 2011-07-26 | 2011-07-26 | A method for making a semiconductor device |
Country Status (1)
Country | Link |
---|---|
TW (1) | TW201306172A (en) |
-
2011
- 2011-07-26 TW TW100126388A patent/TW201306172A/en unknown
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP6484116B2 (en) | High density film for IC package | |
JP6391999B2 (en) | Manufacturing method of laminated device | |
TWI405321B (en) | 3d multi-wafer stacked semiconductor structure and method for manufacturing the same | |
JP5543992B2 (en) | Integrated circuit structure and backside illuminated image sensor device | |
US8421193B2 (en) | Integrated circuit device having through via and method for preparing the same | |
JP5662947B2 (en) | High yield method for exposing and contacting through silicon vias (TSV) | |
JP5682897B2 (en) | Method for forming a via in a portion of a semiconductor wafer including a substrate and via structure formed in a portion of a semiconductor wafer including a substrate | |
TW201230279A (en) | Integrated circuit device and method of forming the same | |
US20120315710A1 (en) | Method for producing reconstituted wafers and method for producing semiconductor devices | |
TW201830531A (en) | Method of package singulation | |
JP2004128063A (en) | Semiconductor device and its manufacturing method | |
TW201133773A (en) | 3DIC architecture with die inside interposer | |
US10199519B2 (en) | Method of making a sensor package with cooling feature | |
KR20140112442A (en) | Bumpless build-up layer(bbul) semiconductor package with ultra-thin dielectric layer | |
JP2013251511A (en) | Method for manufacturing 3d stacked multichip module | |
WO2022121121A1 (en) | Chip bonding method | |
JP2013030537A (en) | Method of manufacturing semiconductor device | |
TWI641880B (en) | Electrical and optical via connections on a same chip | |
JP2015508234A (en) | Method for three-dimensional mounting of electronic devices | |
CN103367139B (en) | A kind of TSV hole bottom medium layer lithographic method | |
US20120193809A1 (en) | Integrated circuit device and method for preparing the same | |
TW201306172A (en) | A method for making a semiconductor device | |
TWI606528B (en) | Method for fabricating a semiconductor device | |
TW202117873A (en) | Method of manufacturing a semiconductor structure | |
TW201603228A (en) | Integrated circuit device and its fabrication method |