201250857 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種具有金屬閘極(metal gate)之半導體 元件及其製作方法，尤指一種實施後閘極(gate last)製程之具 有金屬閘極之半導體元件及其製作方法。 【先前技術】 隨著半導體元件持續地微縮，功函數(work function)金屬 係用以取代傳統多晶矽作為匹配高介電常數(high-K)介電層 的控制電極。而雙功能函數金屬閘極之製作方法係可概分為 前閘極(gate first)與後閘極(gate last)製程兩大類，其中後閘 極製程又因可避免源極/汲極超淺接面活化回火以及金屬矽 化物等高熱預算製程，而具有較寬的材料選擇，故漸漸地取 代前閘極製程。 請參閱第1圖，第1圖係為一習知實施後閘極製程之具 有金屬閘極之半導體元件之剖面示意圖。在習知後閘極製裎 中，係先於基底100上形成一虛置閘極(dummy gate)或取代 閘極(replacement gate)，並在完成一般金氡半導體 (metal-oxide semiconductor，MOS)電晶體元件 110 的與内層 介電層（inter-layer dielectric ’ ILD)層120之製作後，將虚置/ 取代閘極移除’而形成一閘極溝渠（gate trench)，再依電性需 求填入不同的金屬。然而’在移除虛置/取代閘極之後與填入 201250857 功函數金屬之前’常先填入其他的膜層130如阻障層（barrier layer)甚或應力層（strained layer)等。而每一膜層13〇的形 成’都會導致閘極溝渠之開口寬度縮小，形成如第1圖圓圈 A所示之懸突部（overhang)，並造成後續膜層如功函數金屬 層140不易填入閘極溝渠的問題。嚴重的懸突部問題甚至可 能導致懸突部本身或後續填入的功函數金屬層14〇密合，進 而使得最後填入的填充金屬（fiUing metal)層丨5〇無法填入閘 極溝渠而形成空隙160，影響電晶體元件11〇的電性表現。 【發明内容】 因此，本發明之一目的即在於提供一種可解決上述懸突 部問題之實施後閘極製程之製作具有金屬閘極之半導體元 件之方法。 根據本發明所提供之申請專利範圍，係提供一種具有金 屬閘極之半導體元件之製作方法。該製作方法包含提供一基 底，該基底表面形成有一第一電晶體與一第二電晶體，且該 第電日日體内形成有一第一閘極溝渠（gate trench)。該第一電 曰曰體具有一第一導電型式，該第二電晶體具有一第二導電型 式，且該第一導電型式與該第二導電型式相反。接下來於該 第一閘極溝渠内形成一第一功函數金屬 (work function metal) 層。形成該第一功函數金屬層之後，係於該第一閘極溝渠内 形成一犧牲遮罩層（sacrificial masking layer)，隨後移除部分 201250857 忒犧牲遮罩層，以暴露出部分該第—功函數金屬層。之後， 移除暴露之部分該第-功函數金屬層，以於部分之該第—閣 極溝渠内形成-u形功函數金屬i在形成該㈣功函數 金屬層之後，係移除該犧牲遮罩層。 根據本發明所提供之申請專利範圍，另提供—種具有金 屬閘極之半導體凡件之製作方法^該製作方法首先提供一基 底，該基底表面形成有-第—電晶體與—第二電晶體，該第 -電晶體内形成有-第—閘極溝渠，而該第二電晶體内形成 有第-閘極溝渠，且該第二閘極溝渠之開口寬度係大於該 =閘極溝渠之開口寬度。之後，於該第—閘極溝渠内形成 一第-功函數金屬層。在形成該第—功函數金屬層之後，係 於該第1極溝渠錢第二閘極溝渠⑽成-犧牲遮罩 j Ik後於4基底上形成—圖案化光阻’該圖案化光阻係覆 蓋該第一電曰曰體並暴露出該第一閘極溝渠内之該犧牲遮罩 θ之後’移除部分該犧牲遮罩層，以暴露&部分該第一功 函數金屬層。最後移除部分該第—功函數 一間極溝渠_成-_功函數金屬層。 竭 根據本發明所提供之申料韻圍，更提供—種具有金 屬閉極之半導體树。該半導體元件包含有-具有—第一閘 極溝二與—L溝渠之基底、-設置於該第-閘極溝渠 與該第二閘極溝渠内之閘極介電層、-設置於該第-閘極溝 201250857 渠内之該閘極介電層上之第一功函數金屬層、〆設置於該第 二閘極溝渠與該第一閘極溝渠内之第二功函數金屬層、以及 一設置於該第一功函數金屬層與該第二功函數金屬層上之 填充金屬層。值得注意的是，該第一閘極溝渠内之該第二功 函數金屬層係包含一倒Q形。 根據本發明所提供之具有金屬閘極之半導體元件之製作 方法，係利用未填滿該第一閘極溝渠之該犧牲遮罩層保護該 第一閘極溝渠内的該第一功函數金屬層，以順利移除該基底 上非必要的該第一功函數金屬層，更重要的是，移除第一閘 極溝渠開口附近的該等懸突部。因此，後續欲填入該第一問 極溝渠内的膜層如第二功函數金屬層與填充金屬層係V順 利地填入第一閘極溝渠内，避免空隙的形成並玎避免空隙對 半導體元件電性的負面影響。 【實施方式】. 請參閱第2A圖至第8圖，第2A圖至第8圖係為本發曰月 所提供之具有金屬閘極之半導體元件之製作方法之一第一 較佳實施例之示意圖。如第2A圖所示，本較佳實施例首先 提供一基底200，例如一 ί夕基底、含碎基底、或$夕覆絕緣 (silicon-on-insulator，SOI)基底。基底200内形成有衩數個 提供電性隔離的淺溝隔離(shallow trench isolation ’ STI) 202,而基底200上則形成有一第一電晶體210、一第二電晶 201250857 體212與一第三電晶體214。第一電晶體210與第三電晶體 214具有一第一導電型式，第二電晶體212則具有一第二導 電型式，且第一導電型式與第二導電型式相反。另外在具有 相反導電型式的第一電晶體210與第二電晶體212之間則有 STI 202提供電性隔離。第一電晶體210與第三電晶體214 雖然具有相同的導電型式，但具有線寬大小的差別，舉例來 說第一電晶體210可為線寬小於40奈米（nanometer，nm)的 電晶體元件，例如邏輯電路元件；而第三電晶體214則為線 寬大於0· 15微米（micrometer，μιη)的電晶體元件，例如靜態 隨機存取記憶體(static random access memory，SRAM)元 件。在本較佳實施例中，第一導電型式係為P型；而第二導 電型式係為N型，但熟習該項技藝之人士應知反之亦可。 請參閱第2A圖。第一電晶體210、第二電晶體212與第 三電晶體214各包含一閘極介電層204與一虛置閘極206如 一多晶矽層’閘極介電層204可為一傳統二氧化石夕層或一高 介電常數閘極介電層。此外第一電晶體21〇、第二電晶體212 與第三電晶體214分別包含一第一輕摻雜汲極⑴辿“叩以 drain，LDD) 220、一第二 LDD 222 與一第三 LDD 224、一 側壁子226、與一第一源極/汲極230、一第二源極/汲極232 與一第二源極/>及極234。另外，第一源極/汲極Mo、第二源 極/没極232與第三源極/汲極234表面係分別包含有一金屬 矽化物236。而在第一電晶體210、第二電晶體212與第三 201250857 電晶體214上’係依序形成一接觸洞敍刻停止層（contact etch stop layer，CESL) 240 與一内層介電（inter-layer dielectric， ILD)層242。上述元件之製作步驟以及材料選擇，甚至是半 導體業界中為提供應力作用更改善電性表現而實施選擇性 磊晶成長（selective epitaxial growth，SEG)方法形成源極/汲 極230/232/234等皆為該領域之人士所熟知，故於此皆不再 贅述。 請繼續參閱第2A圖。在形成CESL240與ILD層242後， 係藉由一平坦化製程移除部分的CESL 240與ILD層242， 直至暴露出第一電晶體210、第二電晶體212與第三電晶體 214的虛置閘極206。接下來，於基底2〇〇上形成一圖案化 硬遮罩250。圖案化硬遮罩25〇係覆蓋第二電晶體212，且 較佳為一複合層結構。待形成圖案化硬遮罩25〇後，係利用 一適合之蝕刻製程移除第一電晶體21〇與第三電晶體214之 虛置閘極’分別於第一電晶體210内形成一第一閘極溝渠 260以及於第三電晶體214内形成一第三閘極溝渠崩，而 圖案化硬遮罩25G係於形成第—閘極溝渠與第三閘極溝 渠264時覆蓋保護第二電晶體212。如第2A圖所示，由於 閘極溝渠之開口寬度係等於虛置閘極施之線寬，因此第三 閘極溝渠264之開口寬度係大於第—閘極溝渠之開口寬 度。當此⑽j製程結束後，閘極介電層2()4縣露於第一問 極溝渠260肖第三閘極溝渠施之底部。值得注意的是，本 201250857 車乂佳實施例係可與先閘極介電層（high_Kf㈣)製程整合，此 叶閘極"電層204係包含—高介電常數（high_K)閘極介電 層’其可遥自氮化石夕(SiN)、氮氧化石夕(si〇N)以及金屬氧化物 所組成之—群組，其中金屬氧化物則包含氧化铪(hafnium oxide Hf02)石夕酉欠铪氧化合物（hafnium 3丨以〇11似丨心， HfSi04)、石夕酸給氮氧化合物（hafnium似邮他， HfSiON)、氧化銘（aiuminum 〇xide，Al2〇3)、氧化鑭㈣出麵爪 oxide ’ La203)、！呂酸鑭（ianthanum aluminum 〇xide，LaA1〇 )、 氧化组（tantalum oxide ’ Ta2〇5)、氧化ϋ·(ζίιχοηίιπη oxide， Zr02)、矽酸锆氧化合物（zirc〇njuin siiic〇n 〇xide，zrsi〇4)、 或錯酸給(hafnium zirconium oxide，HfZr04)等。 在本較佳實施例之一變化型中，係可在平坦化製程暴露 出第一電晶體210、第二電晶體214與第三電晶體214的虛 置閘極206後，於基底200上直接形成一圖案化光阻（圖未 示）。圖案化光阻係覆蓋第二電晶體212，而暴露出第一電晶 體210與第三電晶體214。圖案化光阻係可在移除第一電晶 體210與第三電晶體214之虛置閘極206，而於第一電晶體 210以及第三電晶體214内分別形成第一閘極溝渠260與第 三閘極溝渠264時，作為保護第二電晶體212的遮罩。 另外請參閱第2B圖，第2B圖係為本第一較佳實施例另 一變化型之示意圖。如第2B圖所示，本較佳實施例亦可與 201250857 :間，電層㈣h-K_呈整合，則問極介電層 為-傳統的二氧化石夕層，而在形成第—閘極溝渠_ =渠加之後，係移除.暴露於第—間極溝渠與第： ^溝渠264底部的閘極介電層2〇4，隨後形成— 數閑極介電層施，其可包含上述材料。且如第⑸圖所干 在第-閘極溝渠施與第三閘極溝渠⑽内的高介電常數 極介電層204a係具有-u型形狀，覆蓋第一閘極溝渠⑽甲 與第二閘極溝渠264之側壁與底部。 另外，請重新參考第2A圖。在形成第一閘極溝渠26〇愈 第三閘極溝渠264之後，或在形成高介電㈣閘極介電層。 2〇4a之後，係可依產品需要於第一閘極溝渠26〇與第三^極 溝渠264内再形成一中間層2〇8，例如一阻；層 (bamer layer)、-應力層（strained “職 la㈣、—功函數調 1金屬層（tuning metal layer)或其組合，且不限於此。 。 請仍然參閱第2 A圖。隨後，係於第一閘極溝渠2 6 〇與第 二閘極溝渠264内形成一第一功函數金屬層27〇。值得注意 的是’形成第一功函數金屬層27〇時，會於第一閘極溝渠2的 之開口附近形成一如圓圈272所標示之懸突部。由第2A圖 可明顯地觀察到，由於第一閘極溝渠26〇之開口寬度較小‘， 因此懸突部272對第一閘極溝渠26〇之開口寬度的影響更為 明顯，即懸突部272更加縮小了第一閘極溝渠遍之開口寬 12 201250857 度。第一功函數金屬層270係為一滿足p型電晶體所需功函 數要求的金屬’其可為單層結構或複合層結構，例如氮化鈦 (titanium nitride，TiN)、碳化鈦（titanium carbide，TiC)、氮 化钽（tantalum nitride ’ TaN)、碳化钽（tantalum carbide，TaC)、 石炭化鶴（tungsten carbide ’ WC)、或氮化铭鈦（aluminum titanium nitride，TiAIN)等。然而值得注意的是，由於第一電 晶體210為一 P型電晶體’而其金屬閘極之功函數係介於4.8 eV與5.2eV之間’因此本較佳實施例所提供的第一功函數 金屬層270亦不限於任何適合的金屬材料。 請參閱第3圖。待形成第一功函數金屬層270之後，係 於基底200上形成一犧牲遮罩層280。犧牲遮罩層280可為 一填洞能力良好的膜層，例如可用旋轉塗佈方式形成的一底 部抗反射（bottom anti-reflective coating，BARC)層、一多晶 石夕(polysilicon)層、一矽懸垂鍵(silicon dangling bond，SHB) 低於43%的多石夕層（Si-rich layer)、一旋塗式玻璃（spin-on glass，S0G)層、一犧牲吸光材料（sacrificial light absorbing material，SLAM)層、一富氧化物（oxide-rich)層如由美國 Honeywell公司販售的DU0TM等，但不限於此。此外，犧牲 遮罩層280可如第3圖所示為一單一膜層，但其亦可為一複 合膜層（multi layer)。犧牲遮罩層280係填入了第一閘極溝渠 260與第三閘極溝渠264 ;而在形成犧牲遮罩層280之後， 更於基底200上形成一圖案化光阻282。如第3圖所示，圖 13 201250857 案化光阻282至少覆蓋第三電晶體214，而暴露出第一電晶 體210與第二電晶體212所在區域。 。青參閱第4圖。接下來，係進行一回餘刻（etching back) 製程，利用適合之蝕刻劑，例如一氧化碳(c〇)或氧氣(〇2)電 漿，移除基底200表面以及第一閘極溝渠26〇内之部分犧牲 遮罩層280。在回蝕刻製程之後，第一閘極溝渠26〇内之犧 牲遮罩層280之表面係低於第一閘極溝渠26〇之開口，亦即 低於ILD層242之表面。此時，基底2〇〇表面以及第一閘極 溝渠260内之部分第一功函數金屬層27〇係被暴露出來。在 此回蝕刻製程中’第三閘極溝渠264内的犧牲遮罩層28〇係 由圖案化光阻282所保護，因此未受回蝕刻製程之影響。由 於第三閘極溝渠264之開口寬度較第一閘極溝渠260之開口 寬度大’為了避免微負載效應(microloadingeffect)的影響， 即為了避免蝕刻劑對接觸面積較大的蝕刻標的具有較高的 蝕刻率此一狀況發生，而造成第三閘極溝渠264内的犧牲遮 罩層280被過度蝕刻而損害到第三閘極溝渠264底部的第一 功函數金屬層270 ’本較佳實施例係更形成圖案化光阻282 保護第三閘極溝渠264内的犧牲遮罩層280。 請參閱第5圖。隨後利用另一回蝕刻製程，利用適合之 蝕刻劑，例如氯(C1)或氨水與過氧化氫混合物 (ammonium peroxide mixture，APM)，移除未被犧牲遮罩層；覆蓋之 201250857 第一功函數金屬層270與中間層208。換句話說，回蝕刻製 程係移除暴露於基底2〇〇與第一閘極溝渠260内之第一功函 數金屬層270與中間層208 ;同時更進一步地移除第二電晶 體212上方的圖案化硬遮罩25(^更重要的是，此一回蝕刻 製程更同時移除了第一閘極溝渠26〇開口處形成的懸突部 272 ’因此可將原本被懸突部272縮小的第一閘極溝渠開口 寬度回復至原來大小。當此一回触刻製程結束時，第一閘極 溝渠260内係形成一由犧牲遮罩層28〇所覆蓋保護的U塑功 函數金屬層274，而第二電晶體212内的虛置閘極206則被 暴露出來。 請參閱第6圖。之後，利用一合適的蝕刻劑，例如一包 含氧、氫、氮的蝕刻劑，移除犧牲遮罩層280。該蝕刻劑之 氧含量係低於10%，以避免移除犧牲遮罩層280時氧化第一 功函數金屬層270 ’而降低半導體元件之電性表現。另外， 針對不同材料的犧牲遮罩層28〇仍可採用不同的蝕刻劑，例 如當犧牲遮罩層280為多矽材料時，係可選用濃度低於2 5 % 的四曱基氧氧化錢(tetramethylammonium hydroxide， TMAH)溶液移除。另外值得注意的是，犧牲遮罩層28〇之回 钱刻製程、移除部分第一功函數金屬層270、懸突部272及 圖案化硬遮罩250的回蝕刻製程、與移除犧牲遮罩層28〇等 上述一步驟係可為同位(in-situ)實施。而在移除犧牲遮罩層 280之後，係藉由另一合適之蝕刻製程移除第二電晶體212 15 201250857 的虛置閘極206’而於第二電晶體212内形成如第6圖所示 之第二閘極溝渠262。值得注意的是，第二閘極溝渠262之 開口寬度係與第-閘極溝渠26〇之開σ寬度招同。此關製 程結束後，閘極介電層204係暴露於第二閘極溝渠262之底 部。如前所述，當本較佳實施例與先閘極介電層製程整合一 時，閘極介電層204係包含一高介電常數閘極介電層；當本 較佳實施例與後閘極介電層製程整合時，閘極介電層曰二可 先為一傳統的二氧化矽層，並在形成第二閘極溝渠262之後 移除’隨後形成-具有U型形狀之高介電常數閘極介電層 204a。由於尚介電常數閘極介電層之材料選擇形狀可參考上 述圖式與揭示内容，故於此及不再贅述。 、請參閱第7圖。另外，在形成第二閘極溝渠加或在形 成局介電常數閘極介電層之後，係可選擇性地依產品需要於 第二間極溝渠262内再形成一中間層（圖未示），中間^之選 擇係可參閱上述說明，故於此不再贅述。而在形成中二層之 後，係於第一閘極溝渠260、第二閘極溝渠262與第三~;極 ，渠264之内形成一第二功函數金屬層咖。值得注意的 是’由於第-閘極溝渠26G之開口處不再有之前膜層形成的 懸突部，因此第二功函數金屬| 276係可輕易地填入所有的 閘極溝渠26〇/262/264。此外，由於第一閘極溝渠26〇内已 有U型功函數金屬層274的存在，因此第一問極溝準細内 形成於u型功函數金屬層274上的第二功函數金屬層w合 16 201250857 隨著此一特殊輪廓而具有一倒Ω或倒鐘(inverted bell)的形 狀。第一功函數金屬層276係為一滿足N型電晶體所需功禹 數要求的金屬，其可為單層結構或複合層結構。第二功函數 金屬層276可選自鋁化鈦(TiAl)、鋁化锆(ZrAl)、鋁化鎢 (WA1)、鋁化鈕(TaAl)或鋁化銓（HfAl)所組成之一群組。然而 值得注意的是’由於第二電晶體212為一 N型電晶體，而其 金屬閘極之功函數係介於3.9 ev與4.3 eV之間，因此本較 佳貫施例所提供的第二功函數金屬層276亦不限於任何適合 的金屬材料。 請繼續參閱第7圖與第8圖。在形成第二功函數金屬層 276之後，係於基底200表面形成一填充金屬層278 ,用以 填滿第一閘極溝渠260、第二閘極溝渠262與第三閘極溝柒 264。填充金屬層278係為具有較佳填洞能力的單層金屬層 或複合金屬層’其可選自鋁（A1)、鈦(Ti)、鈕(Ta)、鎢（W)、 鈮(Nb)、鉬（Mo)、銅（Cu)、氮化鈦(TiN)、碳化鈦(TiC)、氮化 钽(TaN)、鈦鎢(Ti/W)、或鈦與氮化鈦(Ti/TiN)等複合金屬所 組成之一群組。如第8圖所示，在形成填充金屬層278之後， 係可進行一平坦化製程，用以移除ILD層242表面多餘的填 充金屬層278、第二功函數金屬層276、第一功函數金屬層 270與中間層208 ’而獲得一約略平坦之表面，並形成具有 金屬閘極之半導體元件。熟習該項技藝之人士應知，平坦化 製程之後’ ILD層242之表面係與填充金屬層278之頂部表 17 201250857 面共平面。上述平坦化製程係為該熟習該技藝之人士所知 者，故於此係不再贅述。 在第一較佳實施例中，U型功函數金屬層274係用以滿足 P型金屬閘極的功函數要求，因此對第一電晶體210來說， 第二功函數金屬層276與填充金屬層278可視為一複合型態 的填充金屬層。值得注意的是，由於U型功函數金屬層274 的形狀特徵，第一閘極溝渠260的上半部開口可維持原來大 小，並有效降低第一閘極溝渠260的深寬比(aspect rati〇), 故第二功函數金屬層276與填充金屬層278可順利填入，得 以避免填補第一閘極溝渠260時發生縫隙（seam)，確保第— 電晶體210的可靠度。更重要的是，本較佳實施例係利用回 蝕刻第一功函數金屬層270之步驟同時移除保護第二電晶體 212的圖案化硬遮罩250，與習知技術需多形成一圖案化光 阻於移除圖案化硬遮罩時保護第一電晶體之步驟相較，不作 可節省製程步驟、製程成本，更可避免光阻殘留等問題。 另外值得注意的是，由於單一晶圓上遍布線寬尺寸大小 不同的各元件，而該等尺寸範圍小至 30 nm以下，大至5以坩 以上，為了避免蝕刻製程中發生微負載效應導致線寬較大的 疋件被過度蝕刻而影響表現甚或造成損壞’本較佳實施例係 更於形成犧牲遮罩層280後於基底上線寬大於0.15 的元 件所在區域形成如第3圖與第4圖所示的圖案化光阻282 , 201250857 以於回蝕刻犧牲遮罩層280時保護該等元件。當然，當晶圓 上大部分皆為線寬小於0.15 /mi的元件時，本較佳實施例中 形成圖案化光阻282此一步驟係可省略，直接進行回蝕刻製 程，以回蝕刻犧牲遮罩層280至其表面低於第一閘極溝渠 260之開口。 請參閱第9圖至第12圖，第9圖至第12圖係為本發明 所提供之具有金屬閘極之半導體元件之製作方法之一第二 較佳實施例之示意圖。首先值得注意的是，第二較佳實施例 中，與第一較佳實施例相同之元件係以相同的元件符號說 明，且相同元件的材料選擇以及形成步驟係可直接參閱上述 第一較佳實施例所揭示者，故於此皆不再贅述。此外，第9 圖中係僅繪示第一電晶體210與第二電晶體212，用以說明 當晶圓上大部分皆為線寬小於0.15 μιη的元件的情況。然 而，當晶圓上亦存有線寬大於0.15/mi的元件如第一較佳實 施例所例示的第三電晶體214時，熟習該項技藝之人士應可 根據第2A圖至第8圖輕易思及第三電晶體214所在區域之 .實施狀況。 請參閱第9圖。第二較佳實施例不同於第一較佳實施例 之處在於：在第一電晶體210内形成第一閘極溝渠260，以 及在第一閘極溝渠260内形成第一功函數金屬層270之後， 係於基底上先形成一多晶矽層280a與一可用旋轉塗佈方式 19 201250857 形成的膜層280b，例如一底部抗反射層、一矽懸垂鍵低於 43%的多矽層、一旋塗式玻璃層、一犧牲吸光材料層、一富 氧化物層如由美國Honeywell公司販售的DUOTM等，但不 限於此。如前所述第一功函數金屬層270係為一滿足P型電 晶體所需功函數要求的金屬，其可為單層結構或複合層結 構。且在形成第一功函數金屬層270時，會於第一閘極溝渠 260之開口附近形成一如圓圈272所標示之懸突部。另外， 形成第一功函數金屬層270之前，亦可選擇性地形成一如前 所述之中間層（圖未示）。多晶矽層280a與膜層280b分別 作為一第一遮罩層與一第二遮罩層，且構成一犧牲遮罩層 280，換句話說，本較佳實施例所提供之犧牲遮罩層28〇係 為一複合膜層。 值得注意的是，考慮到高溫對第一功函數金屬層270的 影響’在形成多晶矽層280a時，係以低溫製程為較佳的實 施型態。舉例來說，係可利用實施溫度較低的物理氣相沈積 製程（physical vapor deposition，PVD)形成多晶矽層 280a。 另外’多晶矽層280a之厚度以不超過15〇埃為主。多晶石夕 層280a之存在，係可在形成第一功函數金屬層之後與 形成膜層280b之前的等待時間（Q_time)中保護第一功函數金 屬層270，避免第一功函數金屬層27〇氧化而影響其功函 數。另外，當膜層280b在旋轉塗佈製程甚或圖案化製程中 發生不良而需重工(rework)時，多晶矽層28〇a係可在移除不 201250857 良臈層280b時保護第一功函數金屬層270。 請參閱第10圖。接下來，係進行一回蝕刻製程，利用適 合之蝕刻劑，例如一氧化碳(CO)、氧(02)電漿、較佳為一氧 化碳與溴化氫(HBr)等，移除基底200表面以及第一閘極溝 渠260内之部分犧牲遮罩層280。當利用氧電漿回蝕刻犧牲 遮罩層280時’可能會發生氧電漿接觸到第一功函數金屬層 27〇而氧化第一功函數金屬層270，並導致元件的效能漂移 (drift)的缺失。而在本較佳實施例中，係可利用多晶矽層280a 作為保護層，避免氧電漿接觸第一功函數金屬層270。在回 餘刻製程之後，第一閘極溝渠260内之犧牲遮罩層280之表 面係低於第一閘極溝渠260之開口，亦即低於ILD層242之 表面。此時’基底200表面以及第一閘極溝渠260内之部分 第一功函數金屬層270係被暴露出來。 請繼續參閱第10圖。隨後利用另一回蝕刻製程，利用適 合之蝕刻劑移除未被犧牲遮罩層2 8 〇覆蓋之第一功函數金屬 層270。換句話說，回蝕刻製程係移除暴露於基底2〇〇與第 —閘極溝渠260内之第一功函數金屬層27〇 ;同時更進一步 地移除第一電晶體212上方的圖案化硬遮罩25〇。更重要的 是，此一回蝕刻製程更同時移除了第一閘極溝渠26〇開口處 七成的懸突部272 ’ @此可將原本被懸突部272縮小的第一 閘極溝渠260開口寬度回復至原來大小。當此一回蝕刻製程 21 201250857 結束時，第一閘極溝渠260内係形成一由犧牲遮罩層280所 保護的U型功函數金屬層274,而第二電晶體212内的虛置 閘極206則被暴露出來。 另外，在本較佳實施例之一變化型中，係可在基底200 上形成第一功函數金屬層270之後，先將第二電晶體212上 方的第一功函數金屬層270移除。此外在本變化型中，甚至 可在移除第一功函數金屬層270時，亦將圖案化硬遮罩250 一同移除。而在移除第二電晶體212上的第一功函數金屬層 270之後，方於基底200上形成複合的犧牲遮罩層280。隨 後藉由上述的回Ί虫刻製程移除基底200表面以及第一閘極溝 渠260内之部分犧牲遮罩層280，使第一閘極溝渠260内之 犧牲遮罩層280之表面係低於第一閘極溝渠260之開口。並 藉由另一合適之回蝕刻製程移除未被犧牲遮罩層280覆蓋之 第一功函數金屬層270以及懸突部272,形成如第10圖所示 之U型功函數金屬層274。 請參閱第11圖。接下來，利用一合適的蝕刻劑移除犧牲 遮罩層280的膜層280b。舉例來說，係可利用一氧化碳或氧 電漿移除。由於多晶矽層208a可作為第一功函數金屬層270 的保護層，避免氧電漿接觸第一功函數金屬層270而造成氧 化，因此本較佳實施例更可採用一氧化碳或氧電漿作為蝕刻 劑。如前所述，上述犧牲遮罩層280之回蝕刻製程、移除部 22 201250857 分第一功函數金屬層270、懸突部272及圖案化硬遮罩250 的回蝕刻製程、與移除膜層280b等上述三步驟係可為同位 實施。 請參閱第12圖。而在移除膜層280b之後，係藉由另一 合適之蝕刻製程移除第二電晶體212的虛置閘極206，而於 第二電晶體212内形成如第12圖所示之第二閘極溝渠262。 由於虛置閘極206多半包含多晶矽，因此在移除虛置閘極 206時係可同時移除第一閘極溝渠260内剩餘的多晶矽層 280a。如前所述，第二閘極溝渠262之開口寬度係與第一閘 極溝渠260之開口寬度相同。此蝕刻製程結束後，閘極介電 層204係暴露於第二閘極溝渠262之底部。而在形成第二閘 極溝渠262之後，係可如第一較佳實施例所述進行形成高介 電常數閘極介電層、選擇性地形成中間層、形成第二功函數 金屬層、形成填充金屬層、平坦化製程等步驟，於此係不再 贅述。 根據本第二較佳實施例所提供之有金屬閘極之半導體元 件之製作方法，係形成一具有多晶矽層280a的犧牲遮罩層 280，以改善犧牲遮罩層280的回蝕刻製程結果，·並於回蝕 刻製程或重工製程、等待時間中保護第一功函數金屬層 270，故可更改善最終形成之金屬閘極之效能。 23 201250857 請參閱第！3圖至第17圓，第13圖至第i7_為本發 明所提供之具有金屬閑極之半導體元件之製作方法之一第 ^佳f施狀示意圖。首先值得注意的是，第三較佳實施 歹| 第-較佳實施例相同或對應之元件，其材料選擇係 可直接參閱上述第-較佳實施例所揭示者，故於此皆不再費 述。此外1 Π圖至第17圖係騎示當晶圓上大部分皆為 線寬小於G.15㈣的元件的情況。然而，當晶圓上亦存有線 寬大於0.15 "m的元件如第一較佳實施例所例示的第三電晶 體214時’熟習該項技藝之人士應可根據第2A圖至第8圖 輕易思及第三電晶體所在區域之實施狀況。 如第13圖所示，本較佳實施例首先提供一基底3〇〇，基 底300内形成有複數個提供電性隔離的sti搬，而基底細 上則形成有-第-電晶體31〇與一第二電晶體犯。第一電201250857 VI. Description of the Invention: [Technical Field] The present invention relates to a semiconductor device having a metal gate and a method of fabricating the same, and more particularly to a metal having a gate last process Gate semiconductor device and method of fabricating the same. [Prior Art] As the semiconductor element is continuously shrunk, a work function metal is used to replace the conventional polysilicon as a control electrode for matching a high dielectric constant (high-k) dielectric layer. The bi-function function metal gate can be divided into two types: front gate (gate first) and back gate (gate last). The latter gate process can avoid the source/bungee ultra-shallow. The joint activation tempering and high-heat budget process such as metal telluride, and a wider material selection, gradually replaced the front gate process. Please refer to FIG. 1. FIG. 1 is a schematic cross-sectional view showing a semiconductor device having a metal gate in a gate process after the conventional implementation. In the conventional post gate fabrication, a dummy gate or a replacement gate is formed on the substrate 100, and a metal-oxide semiconductor (MOS) is completed. After the fabrication of the inter-layer dielectric ' ILD layer 120 of the transistor element 110 , the dummy/replacement gate is removed to form a gate trench, and then the electrical requirements are required. Fill in different metals. However, other film layers 130 such as a barrier layer or even a strained layer are often filled in before the dummy/replacement gate is removed and before the 201250857 work function metal is filled. The formation of each film layer 13' will cause the opening width of the gate trench to shrink, forming an overhang as shown by circle A in Fig. 1, and causing subsequent film layers such as work function metal layer 140 to be difficult to fill. The problem of entering the gate ditches. Severe overhang problems may even cause the overhang itself or the subsequently filled work function metal layer 14 to be tightly bonded, so that the last filled fiUing metal layer 〇5〇 cannot be filled into the gate trench. The void 160 is formed to affect the electrical performance of the transistor element 11 . SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a method of fabricating a semiconductor device having a metal gate after the implementation of the gate process described above. According to the scope of the invention provided by the present invention, a method of fabricating a semiconductor device having a metal gate is provided. The fabrication method includes providing a substrate having a first transistor and a second transistor formed on the surface of the substrate, and a first gate trench is formed in the body of the first day. The first electrode body has a first conductivity type, the second transistor has a second conductivity pattern, and the first conductivity pattern is opposite to the second conductivity pattern. A first work function metal layer is formed in the first gate trench. After the first work function metal layer is formed, a sacrificial masking layer is formed in the first gate trench, and then a portion of the 201250857 忒 sacrificial mask layer is removed to expose a portion of the first work. Function metal layer. Thereafter, removing the exposed portion of the first work function metal layer to form a -u-shaped work function metal i in the portion of the first-pole trench to remove the sacrificial mask after forming the (four) work function metal layer Cover layer. According to the scope of the patent application provided by the present invention, a method for fabricating a semiconductor device having a metal gate is provided. The fabrication method first provides a substrate having a -first transistor and a second transistor formed on the surface of the substrate. a first-gate trench is formed in the first transistor, and a first-gate trench is formed in the second transistor, and an opening width of the second gate trench is greater than an opening of the gate trench width. Thereafter, a first work function metal layer is formed in the first gate trench. After the first work function metal layer is formed, the second gate trench (10) of the first pole trench is formed into a sacrificial mask j Ik and then formed on the 4 substrate - the patterned photoresist 'the patterned photoresist system After covering the first electrical body and exposing the sacrificial mask θ in the first gate trench, a portion of the sacrificial mask layer is removed to expose a portion of the first work function metal layer. Finally, part of the first work function is removed. A pole trench _ into - _ work function metal layer. In addition, according to the claim rhyme provided by the present invention, a semiconductor tree having a metal closed pole is further provided. The semiconductor device includes a base having a first gate trench 2 and a -L trench, a gate dielectric layer disposed in the first gate trench and the second gate trench, and disposed on the first - gate pole 201250857, a first work function metal layer on the gate dielectric layer, a second work function metal layer disposed in the second gate trench and the first gate trench, and a a filler metal layer disposed on the first work function metal layer and the second work function metal layer. It is worth noting that the second work function metal layer in the first gate trench comprises an inverted Q shape. The method for fabricating a semiconductor device having a metal gate according to the present invention protects the first work function metal layer in the first gate trench by using the sacrificial mask layer that does not fill the first gate trench To smoothly remove the first work function metal layer that is not necessary on the substrate, and more importantly, to remove the overhangs near the opening of the first gate trench. Therefore, the film layer to be filled in the first gate trench, such as the second work function metal layer and the filling metal layer V, is smoothly filled into the first gate trench to avoid void formation and avoid voids to the semiconductor. The negative effects of component electrical properties. [Embodiment] Please refer to FIG. 2A to FIG. 8 , and FIG. 2A to FIG. 8 are a first preferred embodiment of a method for fabricating a semiconductor device having a metal gate provided by the present invention. schematic diagram. As shown in Fig. 2A, the preferred embodiment first provides a substrate 200, such as a substrate, a broken substrate, or a silicon-on-insulator (SOI) substrate. A shallow trench isolation (STI) 202 for providing electrical isolation is formed in the substrate 200, and a first transistor 210, a second transistor 201250857 212 and a third are formed on the substrate 200. Transistor 214. The first transistor 210 and the third transistor 214 have a first conductivity pattern, and the second transistor 212 has a second conductivity pattern, and the first conductivity pattern is opposite to the second conductivity pattern. Additionally, STI 202 provides electrical isolation between first transistor 210 and second transistor 212 having opposite conductivity patterns. Although the first transistor 210 and the third transistor 214 have the same conductivity type, but have a difference in line width, for example, the first transistor 210 may be a transistor having a line width of less than 40 nanometers (nm). The component is, for example, a logic circuit component; and the third transistor 214 is a transistor component having a line width greater than 0.15 micrometers, such as a static random access memory (SRAM) component. In the preferred embodiment, the first conductivity type is P-type; and the second conductivity type is N-type, but those skilled in the art should know the reverse. Please refer to Figure 2A. The first transistor 210, the second transistor 212 and the third transistor 214 each include a gate dielectric layer 204 and a dummy gate 206 such as a polysilicon layer. The gate dielectric layer 204 can be a conventional dioxide. a layer or a high dielectric constant gate dielectric layer. In addition, the first transistor 21, the second transistor 212 and the third transistor 214 respectively comprise a first lightly doped drain (1), a "drain, LDD" 220, a second LDD 222 and a third LDD. 224, a sidewall 226, a first source/drain 230, a second source/drain 232 and a second source/> and a pole 234. In addition, the first source/drain Mo The second source/ditpole 232 and the third source/drain 234 surface system respectively comprise a metal telluride 236. On the first transistor 210, the second transistor 212 and the third 201250857 transistor 214' A contact etch stop layer (CESL) 240 and an inter-layer dielectric (ILD) layer 242 are sequentially formed. The fabrication steps and material selection of the above components are even in the semiconductor industry. The selective epitaxial growth (SEG) method for forming a source/drain 230/232/234 is also known to those skilled in the art for providing stress and improving electrical performance. Please repeat. Please continue to refer to Figure 2A. After forming CESL240 and ILD layer 242, A portion of the CESL 240 and ILD layer 242 are removed by a planarization process until the dummy gates 206 of the first transistor 210, the second transistor 212, and the third transistor 214 are exposed. Next, on the substrate 2 A patterned hard mask 250 is formed on the crucible. The patterned hard mask 25 is covered with the second transistor 212, and is preferably a composite layer structure. After the patterned hard mask 25 is formed, a A suitable etching process removes the first transistor 21 and the dummy gate of the third transistor 214 to form a first gate trench 260 in the first transistor 210 and a third transistor 214 in the etching process. The third gate trench collapses, and the patterned hard mask 25G covers the second transistor 212 when the first gate trench and the third gate trench 264 are formed. As shown in FIG. 2A, due to the gate trench The opening width is equal to the line width of the dummy gate, so the opening width of the third gate trench 264 is larger than the opening width of the first gate trench. When the (10)j process is finished, the gate dielectric layer 2 () 4 The county is exposed in the bottom of the first spur dike 260 XI third gate ditch. The 201250857 Che Yijia embodiment can be integrated with the first gate dielectric layer (high_Kf (4)) process. The gate gate "electric layer 204 includes a high dielectric constant (high_K) gate dielectric layer. A group consisting of cerium (SiN), oxynitride (si〇N), and metal oxides, wherein the metal oxide contains hafnium oxide (Hf02) Hafnium 3丨 〇11 like 丨, HfSi04), oxalic acid to oxynitride (hafnium like him, HfSiON), oxidized inscription (aiuminum 〇xide, Al2〇3), cerium oxide (four) out of the claw oxide ' La203 ),! Oanthanum aluminum 〇xide (LaA1〇), oxidation group (tantalum oxide 'Ta2〇5), yttrium oxide (ζίιχοηίιπη oxide, Zr02), zirconium oxynitride (zirc〇njuin siiic〇n 〇xide, zrsi 〇 4), or wrong acid (hafnium zirconium oxide, HfZr04) and the like. In a variation of the preferred embodiment, the first transistor 210, the second transistor 214, and the dummy gate 206 of the third transistor 214 are exposed on the substrate 200 after the planarization process exposes the dummy gate 206 of the first transistor 210, the second transistor 214, and the third transistor 214. A patterned photoresist is formed (not shown). The patterned photoresist covers the second transistor 212 to expose the first transistor 210 and the third transistor 214. The patterned photoresist system can remove the dummy gate 206 of the first transistor 210 and the third transistor 214, and form the first gate trench 260 and the first transistor 210 and the third transistor 214, respectively. The third gate trench 264 serves as a mask for protecting the second transistor 212. Further, please refer to Fig. 2B, which is a schematic view showing another variation of the first preferred embodiment. As shown in FIG. 2B, the preferred embodiment can also be integrated with 201250857: the electrical layer (4) h-K_, and the pole dielectric layer is a conventional tungsten dioxide layer, and the first gate is formed. The pole trench _ = after the channel is added, is removed. The gate dielectric layer 2〇4 exposed at the bottom of the first-dipole trench and the first: ^ trench 264, and then formed a number of idle dielectric layers, which may include The above materials. And the high dielectric constant dielectric layer 204a in the first gate trench and the third gate trench (10) as in the figure (5) has a -u shape, covering the first gate trench (10) A and the second The sidewall and bottom of the gate trench 264. In addition, please refer back to Figure 2A. After forming the first gate trench 26, the third gate trench 264 is cured, or a high dielectric (four) gate dielectric layer is formed. After 2〇4a, an intermediate layer 2〇8 may be formed in the first gate trench 26〇 and the third gate trench 264 according to product requirements, for example, a barrier; a bamer layer, a stress layer (strained) ""la" (4), "gonging metal layer" or a combination thereof, and is not limited thereto. Please still refer to Figure 2A. Subsequently, it is attached to the first gate trench 2 6 〇 and the second gate A first work function metal layer 27 is formed in the pole trench 264. It is noted that when the first work function metal layer 27 is formed, a circle 272 is formed near the opening of the first gate trench 2 The overhanging portion can be clearly observed from Fig. 2A. Since the first gate trench 26 has a small opening width, the overhang portion 272 has a greater influence on the opening width of the first gate trench 26 Obviously, the overhang portion 272 further reduces the opening width of the first gate trench 12 201250857 degrees. The first work function metal layer 270 is a metal that satisfies the required work function of the p-type transistor. Layer structure or composite layer structure, such as titanium nitride (TiN), carbon Titanium carbide (TiC), tantalum nitride 'TaN, tantalum carbide (TaC), tungsten carbide 'WC', or aluminum titanium nitride (TiAIN) Etc. However, it is worth noting that since the first transistor 210 is a P-type transistor and its metal gate has a work function between 4.8 eV and 5.2 eV, the first embodiment provides The work function metal layer 270 is also not limited to any suitable metal material. Please refer to Fig. 3. After the first work function metal layer 270 is to be formed, a sacrificial mask layer 280 is formed on the substrate 200. The sacrificial mask layer 280 It can be a film with good filling ability, such as a bottom anti-reflective coating (BARC) layer formed by spin coating, a polysilicon layer, and a dangling bond. Dangling bond, SHB) less than 43% of the Si-rich layer, a spin-on glass (S0G) layer, a sacrificial light absorbing material (SLAM) layer, An oxide rich (ox The ide-rich layer is, for example, DU0TM sold by the American Honeywell Company, but is not limited thereto. Further, the sacrificial mask layer 280 may be a single film layer as shown in Fig. 3, but it may also be a multi layer. The sacrificial mask layer 280 is filled with the first gate trench 260 and the third gate trench 264; and after the sacrificial mask layer 280 is formed, a patterned photoresist 282 is formed on the substrate 200. As shown in FIG. 3, the 2012/05857 patterned photoresist 282 covers at least the third transistor 214 to expose the region where the first transistor 210 and the second transistor 212 are located. . See Figure 4 for green. Next, an etching back process is performed to remove the surface of the substrate 200 and the first gate trench 26 by using a suitable etchant such as carbon monoxide (c〇) or oxygen (〇2) plasma. Part of the sacrificial mask layer 280. After the etch back process, the surface of the sacrificial mask layer 280 within the first gate trench 26 is lower than the opening of the first gate trench 26, i.e., below the surface of the ILD layer 242. At this time, the surface of the substrate 2 and a portion of the first work function metal layer 27 in the first gate trench 260 are exposed. The sacrificial mask layer 28 in the third gate trench 264 is protected by the patterned photoresist 282 during this etch back process and is therefore unaffected by the etch back process. Since the opening width of the third gate trench 264 is larger than the opening width of the first gate trench 260, in order to avoid the influence of the microloading effect, that is, to avoid the etchant having a higher etching target with a larger contact area. The etch rate occurs when the sacrificial mask layer 280 in the third gate trench 264 is over-etched to damage the first work function metal layer 270 at the bottom of the third gate trench 264. A patterned photoresist 282 is formed to protect the sacrificial mask layer 280 within the third gate trench 264. Please refer to Figure 5. Subsequent use of another etch process, using a suitable etchant, such as chlorine (C1) or ammonia water and an ammonium peroxide mixture (APM), removes the unsaved mask layer; covering the 201250857 first work function Metal layer 270 and intermediate layer 208. In other words, the etch back process removes the first work function metal layer 270 and the intermediate layer 208 exposed to the substrate 2 and the first gate trench 260; while further removing the second transistor 212 The patterned hard mask 25 (more importantly, this etchback process removes the overhang portion 272 formed at the opening of the first gate trench 26 ' at the same time. Therefore, the overhang portion 272 can be shrunk. The width of the opening of the first gate trench is restored to the original size. When the end of the etching process is completed, a U plastic work function metal layer 274 is covered by the sacrificial mask layer 28 第一 in the first gate trench 260. The dummy gate 206 in the second transistor 212 is exposed. Please refer to Fig. 6. Thereafter, the sacrificial mask is removed by using a suitable etchant, such as an etchant containing oxygen, hydrogen, and nitrogen. The cover layer 280. The etchant has an oxygen content of less than 10% to avoid oxidation of the first work function metal layer 270' when the sacrificial mask layer 280 is removed, thereby reducing the electrical performance of the semiconductor device. Sacrificial mask layer 28〇 can still be used for different etching The agent, for example, when the sacrificial mask layer 280 is a multi-tanning material, may be removed with a tetramethylammonium hydroxide (TMAH) solution having a concentration of less than 25 %. Also noteworthy is the sacrificial mask. The layer 28 process, the removal of a portion of the first work function metal layer 270, the overhanging process of the overhang portion 272 and the patterned hard mask 250, and the removal of the sacrificial mask layer 28, etc. Can be implemented in-situ. After removing the sacrificial mask layer 280, the dummy gate 206' of the second transistor 212 15 201250857 is removed by another suitable etching process. A second gate trench 262 is formed in the transistor 212 as shown in Fig. 6. It is noted that the opening width of the second gate trench 262 is the same as the opening σ width of the first gate trench 26. After the process is completed, the gate dielectric layer 204 is exposed to the bottom of the second gate trench 262. As described above, when the preferred embodiment is integrated with the first gate dielectric layer process, the gate dielectric layer 204 includes a high dielectric constant gate dielectric layer; when the preferred embodiment and the back gate When the electrical layer process is integrated, the gate dielectric layer can be a conventional germanium dioxide layer, and after forming the second gate trench 262, the 'subsequently formed-high dielectric constant gate having a U-shape is removed. The dielectric layer 204a. Since the material selection shape of the dielectric constant gate dielectric layer can be referred to the above drawings and disclosures, it will not be described here. Please refer to Fig. 7. In addition, in the second form. After the gate trench is added or formed into a dielectric constant gate dielectric layer, an intermediate layer (not shown) may be selectively formed in the second interpole trench 262 according to product requirements. Please refer to the above description, so it will not be described here. After forming the second layer, a second work function metal layer is formed in the first gate trench 260, the second gate trench 262, and the third to the drain 264. It is worth noting that 'the second work function metal| 276 can be easily filled in all the gate trenches 26〇/262 because there is no more overhang at the opening of the first gate trench 26G. /264. In addition, since the U-type work function metal layer 274 is present in the first gate trench 26, the second work function metal layer w formed on the u-type work function metal layer 274 in the first gate trench is quasi-fine. 16 201250857 With this special contour, it has a shape of inverted Ω or inverted bell. The first work function metal layer 276 is a metal that satisfies the required work order number of the N-type transistor, and may be a single layer structure or a composite layer structure. The second work function metal layer 276 may be selected from the group consisting of titanium aluminide (TiAl), zirconium aluminide (ZrAl), tungsten aluminide (WA1), aluminum aluminide (TaAl), or hafnium aluminide (HfAl). . However, it is worth noting that 'because the second transistor 212 is an N-type transistor and the metal gate has a work function between 3.9 ev and 4.3 eV, the second embodiment provided by the preferred embodiment The work function metal layer 276 is also not limited to any suitable metal material. Please continue to see Figures 7 and 8. After forming the second work function metal layer 276, a fill metal layer 278 is formed on the surface of the substrate 200 for filling the first gate trench 260, the second gate trench 262 and the third gate trench 264. The filler metal layer 278 is a single metal layer or a composite metal layer having a better hole filling capability. It may be selected from the group consisting of aluminum (A1), titanium (Ti), button (Ta), tungsten (W), and niobium (Nb). Molybdenum (Mo), copper (Cu), titanium nitride (TiN), titanium carbide (TiC), tantalum nitride (TaN), titanium tungsten (Ti/W), or titanium and titanium nitride (Ti/TiN) A group of composite metals. As shown in FIG. 8, after the filling metal layer 278 is formed, a planarization process can be performed to remove the excess filling metal layer 278, the second work function metal layer 276, and the first work function on the surface of the ILD layer 242. The metal layer 270 and the intermediate layer 208' obtain an approximately flat surface and form a semiconductor element having a metal gate. Those skilled in the art will recognize that the surface of the ILD layer 242 after the planarization process is coplanar with the top surface of the fill metal layer 278, Table 17, 201250857. The above-described planarization process is known to those skilled in the art and will not be described again. In the first preferred embodiment, the U-type work function metal layer 274 is used to satisfy the work function requirement of the P-type metal gate, so for the first transistor 210, the second work function metal layer 276 and the filler metal Layer 278 can be viewed as a composite type of filled metal layer. It should be noted that due to the shape characteristic of the U-shaped work function metal layer 274, the upper half opening of the first gate trench 260 can maintain the original size and effectively reduce the aspect ratio of the first gate trench 260 (aspect rati〇) Therefore, the second work function metal layer 276 and the filling metal layer 278 can be smoothly filled in order to avoid a gap when the first gate trench 260 is filled, and the reliability of the first transistor 210 is ensured. More importantly, the preferred embodiment utilizes the step of etching back the first work function metal layer 270 while removing the patterned hard mask 250 protecting the second transistor 212, which is more patterned than the prior art. When the photoresist is used to protect the first transistor when the patterned hard mask is removed, the process steps and the process cost are saved, and the problem of photoresist residue and the like can be avoided. It is also worth noting that since a single wafer has various components with different line widths and sizes, the size ranges from as small as 30 nm or less to as large as 5 or more, in order to avoid micro-loading effects in the etching process. A wider-sized member is over-etched to affect performance or even cause damage. The preferred embodiment is formed in the region of the component having a line width greater than 0.15 on the substrate after forming the sacrificial mask layer 280, as shown in Figures 3 and 4. The patterned photoresist 282, 201250857 is shown to protect the elements when the sacrificial mask layer 280 is etched back. Of course, when most of the wafers are components having a line width of less than 0.15 /mi, the step of forming the patterned photoresist 282 in the preferred embodiment may be omitted, and the etchback process is directly performed to etch back the sacrificial mask. The cover layer 280 is at a lower surface than the opening of the first gate trench 260. Referring to Fig. 9 through Fig. 12, Fig. 9 through Fig. 12 are schematic views showing a second preferred embodiment of a method for fabricating a semiconductor device having a metal gate according to the present invention. It should be noted that in the second preferred embodiment, the same components as those in the first preferred embodiment are denoted by the same reference numerals, and the material selection and forming steps of the same components can be directly referred to the first preferred embodiment. The embodiments are disclosed, and thus are not described herein. In addition, in FIG. 9, only the first transistor 210 and the second transistor 212 are illustrated to illustrate the case where most of the components on the wafer are elements having a line width of less than 0.15 μm. However, when an element having a cable width greater than 0.15/mi is also present on the wafer, such as the third transistor 214 illustrated in the first preferred embodiment, those skilled in the art should be able to easily follow the second to eighth figures. Consider the implementation status of the area where the third transistor 214 is located. Please refer to Figure 9. The second preferred embodiment is different from the first preferred embodiment in that a first gate trench 260 is formed in the first transistor 210, and a first work function metal layer 270 is formed in the first gate trench 260. Thereafter, a polycrystalline germanium layer 280a and a film layer 280b formed by spin coating method 19 201250857 are formed on the substrate, such as a bottom anti-reflective layer, a multi-turn layer with a dangling bond of less than 43%, and a spin coating. The glass layer, a sacrificial light absorbing material layer, an oxide rich layer such as DUOTM sold by Honeywell Corporation of the United States, etc., is not limited thereto. As described above, the first work function metal layer 270 is a metal which satisfies the required work function of the P-type transistor, and may be a single layer structure or a composite layer structure. When the first work function metal layer 270 is formed, an overhang portion as indicated by a circle 272 is formed near the opening of the first gate trench 260. Further, an intermediate layer (not shown) as described above may be selectively formed before the first work function metal layer 270 is formed. The polysilicon layer 280a and the film layer 280b respectively serve as a first mask layer and a second mask layer, and constitute a sacrificial mask layer 280. In other words, the sacrificial mask layer 28 provided in the preferred embodiment. It is a composite film layer. It is worth noting that, in view of the influence of high temperature on the first work function metal layer 270, when the polysilicon layer 280a is formed, a low temperature process is preferred. For example, the polycrystalline germanium layer 280a can be formed by performing a physical vapor deposition (PVD) with a lower temperature. Further, the thickness of the polycrystalline germanium layer 280a is not more than 15 Å. The presence of the polycrystalline layer 280a protects the first work function metal layer 270 in a waiting time (Q_time) after forming the first work function metal layer and before forming the film layer 280b, avoiding the first work function metal layer 27 Oxidation affects its work function. In addition, when the film layer 280b is defective in a spin coating process or a patterning process and requires rework, the polysilicon layer 28〇a can protect the first work function metal layer when the 201250857 beryllium layer 280b is removed. 270. Please refer to Figure 10. Next, an etching process is performed to remove the surface of the substrate 200 and the first using a suitable etchant such as carbon monoxide (CO), oxygen (02) plasma, preferably carbon monoxide and hydrogen bromide (HBr). A portion of the gate trench 260 sacrifices the mask layer 280. When etching the sacrificial mask layer 280 with oxygen plasma, it may happen that the oxygen plasma contacts the first work function metal layer 27 and oxidizes the first work function metal layer 270, and causes the performance drift of the element. Missing. In the preferred embodiment, the polysilicon layer 280a can be utilized as a protective layer to prevent the oxygen plasma from contacting the first work function metal layer 270. After the engraving process, the surface of the sacrificial mask layer 280 in the first gate trench 260 is lower than the opening of the first gate trench 260, i.e., below the surface of the ILD layer 242. At this time, the surface of the substrate 200 and a portion of the first work function metal layer 270 in the first gate trench 260 are exposed. Please continue to see Figure 10. A first work function metal layer 270 that is not covered by the sacrificial mask layer 28 is then removed using a suitable etchant using another etch back process. In other words, the etch back process removes the first work function metal layer 27〇 exposed to the substrate 2 and the first gate trench 260; while further removing the patterned hard layer above the first transistor 212 The mask is 25 inches. More importantly, the etching process further removes the overhanging portion 272 ' of the first gate trench 26 opening at the same time. The first gate trench 260 which is originally reduced by the overhang portion 272 can be removed. The opening width returns to its original size. When the etching process 21 201250857 ends, a U-shaped work function metal layer 274 protected by the sacrificial mask layer 280 is formed in the first gate trench 260, and the dummy gate in the second transistor 212 is formed. 206 was exposed. Additionally, in a variation of the preferred embodiment, the first work function metal layer 270 above the second transistor 212 can be removed after the first work function metal layer 270 is formed on the substrate 200. Further in this variation, the patterned hard mask 250 can be removed together even when the first work function metal layer 270 is removed. After the first work function metal layer 270 on the second transistor 212 is removed, a composite sacrificial mask layer 280 is formed on the substrate 200. Then, the surface of the substrate 200 and a portion of the sacrificial mask layer 280 in the first gate trench 260 are removed by the above-described enamel engraving process, so that the surface of the sacrificial mask layer 280 in the first gate trench 260 is lower than The opening of the first gate trench 260. The first work function metal layer 270 and the overhang portion 272, which are not covered by the sacrificial mask layer 280, are removed by another suitable etch back process to form a U-type work function metal layer 274 as shown in FIG. Please refer to Figure 11. Next, the film layer 280b of the sacrificial mask layer 280 is removed using a suitable etchant. For example, it can be removed using carbon monoxide or oxygen plasma. Since the polysilicon layer 208a can serve as a protective layer of the first work function metal layer 270, and the oxygen plasma is prevented from contacting the first work function metal layer 270 to cause oxidation, the preferred embodiment can further use carbon monoxide or oxygen plasma as an etchant. . As described above, the etch back process of the sacrificial mask layer 280, the removal portion 22 201250857, the first work function metal layer 270, the overhang portion 272, and the patterned hard mask 250 are etched back, and the film is removed. The above three steps of layer 280b and the like may be performed in the same place. Please refer to Figure 12. After the removal of the film layer 280b, the dummy gate 206 of the second transistor 212 is removed by another suitable etching process, and the second electrode as shown in FIG. 12 is formed in the second transistor 212. Gate ditches 262. Since the dummy gate 206 mostly includes polysilicon, the remaining polysilicon layer 280a in the first gate trench 260 can be removed simultaneously when the dummy gate 206 is removed. As previously mentioned, the opening width of the second gate trench 262 is the same as the opening width of the first gate trench 260. After the etch process is completed, the gate dielectric layer 204 is exposed to the bottom of the second gate trench 262. After forming the second gate trench 262, forming a high dielectric constant gate dielectric layer, selectively forming an intermediate layer, forming a second work function metal layer, and forming the same as described in the first preferred embodiment. The steps of filling the metal layer, the planarization process, and the like are not described herein. According to the method for fabricating a semiconductor device having a metal gate according to the second preferred embodiment, a sacrificial mask layer 280 having a polysilicon layer 280a is formed to improve the etch back process of the sacrificial mask layer 280. The first work function metal layer 270 is protected during the etch back process or the rework process and the waiting time, so that the performance of the finally formed metal gate can be further improved. 23 201250857 See the first! 3 to 17th, and 13th to i7th are schematic diagrams of a method for fabricating a semiconductor element having a metal idle electrode according to the present invention. First of all, it should be noted that the third preferred embodiment is the same or corresponding components of the first preferred embodiment, and the material selection can be directly referred to the above-mentioned first preferred embodiment. Said. In addition, 1 to 17 are the case where most of the wafers are components with a line width smaller than G.15 (four). However, when a component having a cable width greater than 0.15 "m is also present on the wafer as the third transistor 214 illustrated in the first preferred embodiment, a person familiar with the art should be able to follow Figures 2A through 8. Easily consider the implementation of the area where the third transistor is located. As shown in FIG. 13, the preferred embodiment first provides a substrate 3, wherein the substrate 300 is formed with a plurality of sti-transmissions for providing electrical isolation, and the substrate is thinned to form a -------- A second transistor is committed. First electricity
Ba體310具有-第—導電型式，第二電晶體則具有一第 -導電型式’且第-導電型式與第二導電型式相反。另外在 具有相反導電型式的第一電晶體31G與第二電晶體312之間 則有STI 302提供電性隔離。在本較佳實施例中，第一導電 型式係為P型；*第二導電型式係為㈣，但熟習該項技藝 之人士應知反之亦可。 請參閱第13圖。第一電晶體310與第二電晶體312各包 含-閘極介電層3G4與-虛置閘極（圖未示），間極介電層 24 201250857The Ba body 310 has a -first conductivity type, the second transistor has a first conductivity type and the first conductivity pattern is opposite to the second conductivity pattern. Additionally, STI 302 provides electrical isolation between first transistor 31G and second transistor 312 having opposite conductivity patterns. In the preferred embodiment, the first conductivity type is P-type; and the second conductivity type is (4), but those skilled in the art should know the reverse. Please refer to Figure 13. The first transistor 310 and the second transistor 312 each include a gate dielectric layer 3G4 and a dummy gate (not shown), and an interlayer dielectric layer 24 201250857
304可為一傳統二氧化矽層或一高介電常數閘極介電層。此 外第一電晶體310與第二電晶體312分別包含一第一 lDD 320與一第二LDD 322、一側壁子320、與一第一源極/汲極 330與一第二源極/汲極332、以及形成於其表面之一金屬矽 化物336。而在第一電晶體31〇與第二電晶體312上，係依 序形成一 CESL 340與一 ILD層342。上述元件之製作步驟 以及材料選擇，甚至是半導體業界中為提供應力作用更改善 電性表現而實施的SEG方法等皆為該領域之人士所熟知， 故於此皆不再贅述。 請繼續參閱第13圖。在形成CESL34〇與ILD層342後， 係藉由一平坦化製程移除CESL34〇與ILD層342，直至暴 露出第一電晶體310與第二電晶體312的虛置閘極。接下 來，係利用一適合之蝕刻製程移除第一電晶體31〇與第二電 晶體312之虛置閘極，分別於第一電晶體31〇與第二電晶體 312内形成一第一閘極溝渠36〇與一第二閘極溝渠362。當 此蝕刻製程結束後，閘極介電層3〇4係暴露於第一閘極溝渠 .360與第二間極溝渠362之底部。如前所述，本較佳實施= 係可與先閘極介電層製程整合，此時閘極介電層3〇4係包含 一南介電常數閘極介電層，材料選項係可參閱第—較佳實: 例。另外，本較佳實施例亦可與後閘極介電層製程整合，2 間極介電層304可先為-傳統的二氧化石夕層，而在形 閘極溝渠360與第二閘極溝渠362之後，係移除暴露於第一 25 201250857 $極溝渠360與第二間極溝渠362底部的閉極介電層3〇4, 隨後形成—高介電常數祕介電層（圖未示），其可包含上 述材料。 請仍然參閱第U圖。隨後，係於基底3〇〇上形成一第一 f函數金屬層370，另外在形成第-功函數金屬層37〇之 則’係可依產品需要於各第—閘極溝渠36G與第二閘極溝渠 362内再形成一中間層删，例如一阻障層、一應力層、二、 功函數調整金屬層或其組合，以限於此。而在形成日第一功 函數金屬層37G之後，係藉由—圖案化製程移除第二閘極溝 渠362内的第一功函數金屬層37()，使第一功函數金屬層別 主要存在於第-閘極溝渠遍内。另外值得注意的是，形成 第一功函數金屬層370時，會於第一閘極溝渠36〇之開口附 近形成一如圓圈372所標示之懸突部。由第13圖可明顯地 觀察到’由於第一閘極溝渠遍之開口寬度較小，因此第一 功函數金屬層3 7 0的懸突部3 7 2對第一閘極溝渠3 6 〇之開口 寬度的影響非常明顯’即懸突部372更加縮小了第—閑極溝 渠360之開口寬度。由於第一電晶體31〇為一 p型電晶體， 而其金屬閘極之功函數係介於486乂與52eV之間，因此 本較佳實施例所提供的第一功函數金屬層係可來閱第一 較佳實施例，但亦不限於任何適合的金屬材料。且第一功函 數金屬層370可為一單層結構或複合層結構。 “ 26 201250857 請參閱第14圖。待形成第一功函數金屬層⑽ 於基底300上形成一犧牲遮罩層38〇。犧牲遮罩屏之後，係 -填洞能力良好的膜層，例如可用旋轉塗佈方式為 部抗反射層、-多晶石夕層、-石夕懸垂鍵低於43%的二;底 一旋塗式玻璃層、一犧牲吸光材料層、一富氧化物層如由美 國Honey well公司販售的DU0™等，但不限於此。如前所 述，犧牲遮罩層380可如第14圖所示為一單一膜層，但其 亦可為一複合膜層。犧牲遮罩層380係填入了第一閘極溝渠 360與第二閘極溝渠362之内。而在形成犧牲遮罩層38〇之 後，更於基底300上形成一圖案化光阻382。如第14圖所示， 圖案化光阻382係暴露出第一電晶體31〇，尤其第一閘極溝 渠360内的犧牲遮罩層380。 請參閱第15圖。接下來，係進行一回蝕刻製程，剎用適 合之触刻劑，触刻暴露出來的部分犧牲遮罩層380。在回餘 刻製程之後，犧牲遮罩層380之表面係低於第一閘極溝渠 360之開口，亦即低於ILD層342之表面。此時，基底300 表面以及第一閘極溝渠360内之部分第一功函數金屬層370 係被暴露出來。在此回蝕刻製程中，第二閘極溝渠362内的 犧牲遮罩層380係由圖案化光阻382所保護，因此未受回蝕 刻製程之影響。換句話說，第二閘極溝渠362内之犧牲遮罩 層380仍可於後續製程中繼續保護第二閘極溝渠362底部的 閘極介電層304。 27 201250857 請參閱第16圖。隨後利用另一回韻刻製程 蝕刻劑，移除未被犧牲遮罩層 u 3川與t間層31更重要的9 /紅第—功函數金屬層 除了坌一Η“ #的疋&-回蝕刻製程更同時移 =了第-間極溝渠遍開口處形成的懸突部奶 =突r2縮小的第-間極溝渠開口寬度： ’、來 自此1㈣製程結束時’第-閘極溝竿362内 成一由犧牲遮罩層380所覆蓋保護的U型功函數金屬層 入咕參閱第_ 17圖。之後’利用一合適的姓刻劑，例如一包 含氧、氫、氮㈣刻劑，移除圖案化光阻382與犧牲遮罩層 80另外值得注意的是，犧牲遮罩層380之回钮刻製程、 移除部分第-功函數金屬層37〇與懸突部372的回餘刻製 転、與移除犧牲遮罩層38〇等上述三步驟係可為同位實施。 在移除圖案化光阻382與犧牲遮罩層38〇之後，。型功函數 金屬層374係暴露於第一閘極溝渠360内，而閘極介電層3〇4 則暴露於第二閘極溝渠362之底部。之後，係可如第—較佳 實施例所述進行形成高介電常數閘極介電層、選擇性地形成 中間層、形成第二功函數金屬層、形成填充金屬層、平垣化 製程等步驟，於此係不再贅述。 在本較佳實施例中，由於U型功函數金屬層374的形狀 28 201250857 特徵，第一閘極溝渠360的上半部開口可維持原來大小，並 有效降低第一閘極溝渠360的深寬比（aspect ratio)，故第二 功函數金屬層與填充金屬層可順利填入，得以避免填補第一 閘極溝渠360時發生縫隙（seam)，確保第一電晶體310的可 靠度。 ' 另外值得注意的是，由於單一晶圓上遍布電性相反、線 ' 寬尺寸大小不同的各元件，而該等尺寸範圍小至30 nm以 下，大至5 /xm以上，為了避免蝕刻製程中發生微負載效應 導致線寬較大的元件區域被過度蝕刻而影響表現甚或造成 損壞，以及避免電性相反的元件區域被蝕刻而影響到閘極介 電層，本較佳實施例係可在形成犧牲遮罩層380後，於基底 上線寬大於0.15 /xm的元件所在區域以及具相反導電型式的 元件所在區域形成圖案化光阻382，以於回蝕刻犧牲遮罩層 380時保護該等元件。因此，即使導電型式相反、尺寸大小 不同的閘極溝渠同時形成，本較佳實施例仍可確保僅有需形 成U型功函數金屬層374之處為回蝕刻製程之蝕刻標的，而 * 不影響到其他元件區域。 另外請參閱第18圖，第18圖係為第三較佳實施例之一 變化型之示意圖。本第三較佳實施例中的犧牲遮罩層380可 如第14圖至第16圖所示為一單層結構，亦可如第18圖所 示為一複合層結構。本變化型係在第一閘極溝渠360内形成 29 201250857 第一功函數金屬層370之後，係於基底上先形成一多晶矽層 380a與一可用旋轉塗佈方式形成的膜層380b，例如一底部 抗反射層、一矽懸垂鍵低於43%的多矽層、一旋塗式玻璃 層、一犧牲吸光材料層、一富氧化物層如由美國Honeywell 公司販售的DUOTM等，但不限於此。多晶矽層380a與膜層 380b分別作為一第一遮罩層與一第二遮罩層，且構成一複合 型態之犧牲遮罩層380。 如前所述，考慮到高溫對第一功函數金屬層370的影響， 在形成多晶矽層380a時，係以低溫製程為較佳的實施型態。 舉例來說，係可利用實施溫度較低的物理氣相沈積製程形成 多晶矽層380a。另外，多晶矽層380a之厚度以不超過_ 150埃為主。多晶矽層380a之存在，係可在形成第一功函數 金屬層370之後與形成膜層380b之前的等待時間（Q-time) 中保護第一功函數金屬層370,避免護第一功函數金屬層370 接觸到氧氣而影響其功函數。另外，當膜層380b在旋轉塗 佈製程甚或圖案化製程中發生不良而需重工時，多晶矽層 380a係可在移除不良膜層380b時保護第一功函數金屬層 370。 根據本變化型，係形成一具有多晶矽層380a的犧牲遮罩 層380，以改善犧牲遮罩層380的回蝕刻製程結果，並於回 蝕刻製程或重工製程、等待時間中保護第一功函數金屬層 201250857 370故可更改善最終形成之金屬閘極之效能。 根據本^明所提供之具有金屬閑極之半導 Γ門=用，'該第一閘極溝渠之該犧牲::二製作 弟-間極溝渠内的該第一功函數金屬層：層保護該 上非必要的該第—功函數金屬層，更重要的θ移除該基底 極溝渠開Π附近的該等懸突部。因此，後埴移除第1 極溝渠内的臈層如第_ 真入該第一Μ 利地填人Μ心! 屬層與填充金屬 η 渠内，避免空隙的形成c， +導體7L件電性的負面影響。 冑免空隙斜 以上所述僅為本發明之較佳實施例，凡依本發 所做之均等變化與修飾，皆應屬本發明之涵蓋範Β。睛專利範固 【圖式簡單說明】 導她版W閑極之半 笛Q 第—較佳實施例之示意圖； 導體-:至第12圖係為本發明所提供之具有金屬閘極之半 v體^件之製作方法之-第二㈣實施例之示意圖； 半導體本發料提供之具有金屬閉極之 之第二較佳實施例之示意圖，以及 31 201250857 第18圖係為第三較佳實施例之一變化型之示意圖。 【主要元件符號說明】 100 基底 110 電晶體元件 120 内層介電層 130 膜層 140 功函數金屬層 150 填充金屬層 160 空隙 A 圓圈 200 、 300 基底 202 、 302 淺溝隔離 204 、 304 閘極介電層 204a 高介電常數閘極介電層 206 虛置閘極 208 、 308 中間層 210 、 310 第一電晶體 212 、 312 第二電晶體 214 第三電晶體 220 、 320 第一輕摻雜汲極 222 ' 322 第二輕摻雜没極 32 201250857 224 第三輕換雜没極 226 、 326 側壁子 230 、 330 第一源極/沒極 232 > 332 第二源極/汲極 234 第三源極/汲極 236 金屬梦化物 240 、 340 接觸洞蝕刻停止層 242 > 342 内層介電層 250 圖案化硬遮罩 260 、 360 第一閘極溝渠 262 、 362 第二閘極溝渠 264 第三閘極溝渠 270 、 370 第一功函數金屬層 272 、 372 懸突部 274 、 374 U型功函數金屬層 276 第二功函數金屬層 278 填充金屬層 280 、 380 犧牲遮罩層 280a、380a 多晶矽層 280b 、 380b 膜層 282、382 圖案化光阻 33304 can be a conventional hafnium oxide layer or a high dielectric constant gate dielectric layer. In addition, the first transistor 310 and the second transistor 312 respectively include a first lDD 320 and a second LDD 322, a sidewall 320, a first source/drain 330, and a second source/drain 332, and a metal halide 336 formed on a surface thereof. On the first transistor 31A and the second transistor 312, a CESL 340 and an ILD layer 342 are formed in sequence. The fabrication steps and material selection of the above-mentioned components, and even the SEG method for improving the electrical performance in the semiconductor industry to provide a stress effect are well known to those skilled in the art, and thus will not be described herein. Please continue to see Figure 13. After forming the CESL 34 〇 and ILD layers 342, the CESL 34 〇 and ILD layers 342 are removed by a planarization process until the dummy gates of the first transistor 310 and the second transistor 312 are exposed. Next, the dummy gates of the first transistor 31〇 and the second transistor 312 are removed by a suitable etching process, and a first gate is formed in the first transistor 31〇 and the second transistor 312, respectively. The pole ditch 36〇 and the second gate ditch 362. When the etching process is completed, the gate dielectric layer 3〇4 is exposed to the bottom of the first gate trench .360 and the second pole trench 362. As described above, the preferred embodiment can be integrated with the first gate dielectric layer process, in which case the gate dielectric layer 3〇4 includes a south dielectric constant gate dielectric layer, and the material options can be referred to First - better: Example. In addition, the preferred embodiment can also be integrated with the process of the back gate dielectric layer. The two dielectric layers 304 can be a conventional tungsten dioxide layer, and the gate gate 360 and the second gate. After the trench 362, the closed dielectric layer 3〇4 exposed to the bottom of the first 25 201250857 $pole ditch 360 and the second interpole trench 362 is removed, and then a high dielectric constant secret dielectric layer is formed (not shown) ), which may comprise the above materials. Please still refer to Figure U. Subsequently, a first f-function metal layer 370 is formed on the substrate 3, and in addition, a first work function metal layer 37 is formed, which can be applied to each of the first gate trenches 36G and the second gate according to product requirements. An intermediate layer is further formed in the pole trench 362, such as a barrier layer, a stress layer, a work function adjusting metal layer or a combination thereof, to be limited thereto. After forming the first work function metal layer 37G, the first work function metal layer 37() in the second gate trench 362 is removed by a patterning process, so that the first work function metal layer is mainly present. Within the first gate trench. It is also worth noting that when the first work function metal layer 370 is formed, an overhang as indicated by a circle 372 is formed near the opening of the first gate trench 36. It can be clearly seen from Fig. 13 that since the opening width of the first gate trench is small, the overhanging portion 372 of the first work function metal layer 370 is opposite to the first gate trench 3 6 The effect of the width of the opening is very pronounced 'i.e., the overhang 372 further reduces the opening width of the first idle stub 360. Since the first transistor 31 is a p-type transistor and the work function of the metal gate is between 486 52 and 52 eV, the first work function metal layer provided by the preferred embodiment can come. The first preferred embodiment is, but is not limited to, any suitable metallic material. And the first work function metal layer 370 can be a single layer structure or a composite layer structure. 26 201250857 Please refer to Fig. 14. The first work function metal layer (10) is to be formed to form a sacrificial mask layer 38 on the substrate 300. After the sacrificial mask screen, the film is well-filled, for example, can be rotated The coating method is a partial anti-reflection layer, a polycrystalline stone layer, a diarrhea bond of less than 43%, a spin-coated glass layer, a sacrificial light absorbing material layer, and an oxide-rich layer such as the United States. DU0TM, etc., sold by Honeywell, is not limited thereto. As described above, the sacrificial mask layer 380 may be a single film layer as shown in Fig. 14, but it may also be a composite film layer. The cap layer 380 is filled in the first gate trench 360 and the second gate trench 362. After the sacrificial mask layer 38 is formed, a patterned photoresist 382 is formed on the substrate 300. As shown, the patterned photoresist 382 exposes the first transistor 31, and in particular the sacrificial mask layer 380 in the first gate trench 360. See Figure 15. Next, an etch process is performed, The portion of the sacrificial mask layer 380 is exposed by a suitable etchant, which is exposed to the engraved process. The surface of the sacrificial mask layer 380 is lower than the opening of the first gate trench 360, that is, lower than the surface of the ILD layer 342. At this time, the surface of the substrate 300 and a portion of the first work function in the first gate trench 360. The metal layer 370 is exposed. During this etch back process, the sacrificial mask layer 380 in the second gate trench 362 is protected by the patterned photoresist 382 and is therefore unaffected by the etch back process. The sacrificial mask layer 380 in the second gate trench 362 can still continue to protect the gate dielectric layer 304 at the bottom of the second gate trench 362 in a subsequent process. 27 201250857 Please refer to Fig. 16. Then use another The engraving process etchant removes the 9/red-first work function metal layer which is more important than the sacrificial mask layer u 3 and the inter-t layer 31. In addition to the 疋 Η # # # amp amp amp # # Shift = overhanging portion formed at the opening of the first-interpole trench = the width of the first-dipole trench opening reduced by the protrusion r2: ', from the end of the 1 (four) process, the first-gate gully 362 is sacrificed The U-shaped work function metal layer covered by the mask layer 380 is referred to _17Then, using a suitable surname engraving, such as an oxygen, hydrogen, nitrogen (four) engraving agent, removing the patterned photoresist 382 and the sacrificial mask layer 80, it is also worth noting that the sacrificial mask layer 380 is turned back. The above three-step process of the process, removing a portion of the first work function metal layer 37A and the overhanging of the overhang portion 372, and removing the sacrificial mask layer 38 can be performed in-situ. After the patterned photoresist 382 and the sacrificial mask layer 38 are removed. The type of work function metal layer 374 is exposed to the first gate trench 360, and the gate dielectric layer 3〇4 is exposed to the bottom of the second gate trench 362. Thereafter, steps of forming a high dielectric constant gate dielectric layer, selectively forming an intermediate layer, forming a second work function metal layer, forming a filling metal layer, and forming a planarization process may be performed as described in the first preferred embodiment. This will not be repeated here. In the preferred embodiment, due to the shape of the U-shaped work function metal layer 374 28 201250857, the upper half opening of the first gate trench 360 can maintain the original size and effectively reduce the depth of the first gate trench 360. The aspect ratio is such that the second work function metal layer and the fill metal layer can be smoothly filled in order to avoid a gap when the first gate trench 360 is filled, and the reliability of the first transistor 310 is ensured. It is also worth noting that, due to the fact that the individual wafers are distributed with different elements of different thickness and width, the size ranges from as small as 30 nm to as large as 5 / xm or more, in order to avoid etching. The occurrence of the micro-loading effect causes the area of the element having a large line width to be over-etched to affect the performance or even cause damage, and to avoid the area of the opposite element being etched to affect the gate dielectric layer, and the preferred embodiment can be formed. After sacrificial mask layer 380, patterned photoresist 382 is formed over the region of the substrate having a line width greater than 0.15 / xm and the region of the component having the opposite conductivity pattern to protect the components when etch back sacrificial mask layer 380. Therefore, even if gate trenches of opposite conductivity types and sizes are formed at the same time, the preferred embodiment can ensure that only the U-type work function metal layer 374 needs to be formed as an etch mark of the etch-etch process, and * does not affect Go to other component areas. Further, please refer to Fig. 18, which is a schematic view showing a variation of the third preferred embodiment. The sacrificial mask layer 380 in the third preferred embodiment may have a single layer structure as shown in Figs. 14 to 16, or may be a composite layer structure as shown in Fig. 18. The present variation forms a 201250857 first work function metal layer 370 in the first gate trench 360, and first forms a polysilicon layer 380a on the substrate and a film layer 380b formed by spin coating, such as a bottom. An anti-reflective layer, a multi-layer layer having a dangling bond of less than 43%, a spin-on glass layer, a sacrificial light-absorbing material layer, an oxide-rich layer such as DUOTM sold by Honeywell, USA, but not limited thereto. . The polysilicon layer 380a and the film layer 380b serve as a first mask layer and a second mask layer, respectively, and constitute a composite sacrificial mask layer 380. As described above, in consideration of the influence of the high temperature on the first work function metal layer 370, in the formation of the polysilicon layer 380a, a low temperature process is preferred. For example, the polysilicon layer 380a can be formed using a physical vapor deposition process that is performed at a lower temperature. Further, the thickness of the polysilicon layer 380a is not more than _150 Å. The polysilicon layer 380a is present to protect the first work function metal layer 370 in a waiting time (Q-time) after forming the first work function metal layer 370 and before forming the film layer 380b, avoiding the first work function metal layer 370 is exposed to oxygen and affects its work function. In addition, the polysilicon layer 380a protects the first work function metal layer 370 when the poor film layer 380b is removed when the film layer 380b is defective in the spin coating process or even in the patterning process. According to the variation, a sacrificial mask layer 380 having a polysilicon layer 380a is formed to improve the etch back process result of the sacrificial mask layer 380, and to protect the first work function metal during the etch back process or the rework process and the waiting time. The layer 201250857 370 can further improve the performance of the resulting metal gate. According to the semi-guided door with metal idle pole provided by the present invention, the sacrifice of the first gate trench: the first work function metal layer in the second fabrication-interpole trench: layer protection The non-essential first work function metal layer, more importantly θ, removes the overhangs near the base trench opening. Therefore, the ruthenium layer in the first pole trench is removed as in the first 如 真 真 真 真 真 真 真 真 真 真 真 真 真 真 真 真 真 真 真 真 真 真 真 真 真 真 真 真 真 真 真 真 真 真 真 真 真 真 真 真 真Negative effects of sex. The above description is only a preferred embodiment of the present invention, and all variations and modifications made in accordance with the present invention are intended to be within the scope of the present invention. Eye Patent [Flat Description] Directly introduce her version of the semi-flute Q. The first embodiment of the preferred embodiment; conductor-: to the 12th figure is a half of the metal gate provided by the present invention. A schematic diagram of a second (four) embodiment of a method for fabricating a body; a schematic diagram of a second preferred embodiment having a metal closed pole provided by the semiconductor present invention, and 31 201250857 FIG. 18 is a third preferred embodiment A schematic diagram of a variant of the example. [Main component symbol description] 100 substrate 110 transistor component 120 inner dielectric layer 130 film layer 140 work function metal layer 150 filled metal layer 160 void A circle 200, 300 substrate 202, 302 shallow trench isolation 204, 304 gate dielectric Layer 204a high dielectric constant gate dielectric layer 206 dummy gate 208, 308 intermediate layer 210, 310 first transistor 212, 312 second transistor 214 third transistor 220, 320 first lightly doped drain 222 ' 322 second lightly doped immersion 32 201250857 224 third lightly exchanged pole 226, 326 side wall 230, 330 first source / no pole 232 > 332 second source / drain 234 third source Pole/bungee 236 metal dreaming 240, 340 contact hole etch stop layer 242 > 342 inner dielectric layer 250 patterned hard mask 260, 360 first gate trench 262, 362 second gate trench 264 third gate Polar trenches 270, 370 first work function metal layer 272, 372 overhang 274, 374 U-type work function metal layer 276 second work function metal layer 278 fill metal layer 280, 380 sacrificial mask layer 280a 380a polycrystalline germanium layer 280b, 380b film layer 282, 382 patterned photoresist 33