201248853 ’ 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體結構及其操作方法，特別 係有關於同時改善崩潰電壓與開啟電阻（開啟電流）的半導 體結構其操作方法。 【先前技術】 在半導體技術中，舉例來說，半導體結構例如功率裝 置係使用適合當下⑽s製程的橫向雙擴散金屬氧化半導 體（LDMOS)與減表面場（reduced surface fieid; resuRF)技 術。為了提高半導體結構的崩潰電壓（breakdown voltage; BVdss)種方法係降低沒極區的摻雜濃度並增加漂移長 又、:而此方法會提尚半導體結構的開啟電阻。此外， 需要大的設計面積。 L發明内容] 本發明係有關於一種半導體結構及其 時改=潰:麼與開啟電阻(開啟電流)。設計面積一 雜區、第二捧雜區、第三摻雜區、第底、第-摻 結構。第-摻雜區位於基底中。第：槽、、、。構與第二閘 型。第二摻雜區位於第一摻雜區中。‘：：具有第-導電 於第一導電型的第二導電型。第三—杉雜區具有相反 中且具有第—導電型。第一溝槽結構具第二摻雜區 -閘結構與第二間結構分別位於第二二-閘結構。第 —穋雜區的不同側上。 4 201248853 j w /uj〇r/\ 半導體結構的操作方法。半導體結構包括基底、 弟一L雜區、第二摻雜區、第三推雜區、第一溝槽結 第^間結構。第一推雜區位於基底令。第一摻雜區具有第 二，。第二，雜區位於第-摻雜區中。第二摻雜區呈 J相反於第一導電型的第二導電型。第三摻雜區 ： =雜區中且具有第-導電型。第—溝槽結構具有第一_ ,閘結構與第二閘結構分別位於第二摻雜區的不同 側上。半導體結構的操作方法包括以下步驟。施加第一偏 f於分別位於第二閘結構之相對側邊上的第三摻雜區與 一-摻雜區之間。施加第二偏壓至第一間結構，並施加第201248853 ′′. Description of the Invention: TECHNICAL FIELD The present invention relates to a semiconductor structure and a method of operating the same, and more particularly to a semiconductor structure for simultaneously improving a breakdown voltage and an on-resistance (on current). [Prior Art] In semiconductor technology, for example, a semiconductor structure such as a power device uses a lateral double-diffused metal oxide semiconductor (LDMOS) and a reduced surface fieid (resuRF) technique suitable for the current (10) s process. In order to improve the breakdown voltage (BVdss) of the semiconductor structure, the method is to reduce the doping concentration of the non-polar region and increase the drift length, and this method will increase the opening resistance of the semiconductor structure. In addition, a large design area is required. SUMMARY OF THE INVENTION The present invention relates to a semiconductor structure and its subsequent modification (opening current). The design area is a miscellaneous region, a second doped region, a third doped region, a bottom, and a first doped structure. The first doped region is located in the substrate. The first: slot, ,,. Constructed with a second gate. The second doped region is located in the first doped region. ':: has a second conductivity type which is first-conducting to the first conductivity type. The third-firty area has the opposite and has a first conductivity type. The first trench structure has a second doped region - the gate structure and the second interstructure are respectively located in the second two-gate structure. On the different sides of the first-noisy zone. 4 201248853 j w /uj〇r/\ Method of operation of the semiconductor structure. The semiconductor structure includes a substrate, a second impurity region, a second doped region, a third dummy region, and a first trench structure. The first doffer zone is located at the base order. The first doped region has a second. Second, the impurity region is located in the first doped region. The second doped region is J opposite to the second conductivity type of the first conductivity type. The third doping region: = in the hetero region and has a first conductivity type. The first trench structure has a first _, and the gate structure and the second gate structure are respectively located on different sides of the second doped region. The method of operation of the semiconductor structure includes the following steps. A first bias is applied between the third doped region and the one-doped region on opposite sides of the second gate structure, respectively. Applying a second bias to the first structure and applying the first
Si至IS閘結構’以控制半導體結構為開啟狀態或關 才，半導體結構在開啟狀態下，電流流過的通道至少 包^第一通道與第二通道。第一通道包括第二摻雜區鄰近 於第一閘結構的部分。第二通道包括第二摻雜區鄰近於 二閘結構的部分。 下文特舉—些實施例，並配合所附圖式，作詳細說明 如下： 【實施方式】 本揭露係有關於半導體結構及其操作方法。半導體結 構包括絕緣閘極雙極性電晶體(〗G B τ)、二極體或 半導體例如橫向雙擴散金屬氧化半導體(LDMOS)或增強 金屬氧化半導體電晶體(EDMOS)。 第1圖與第2圖繪示一實施例中半導體結構的立體 圖°清參照第1圖’半導體結構包括基底2。第-摻雜區 4位於基底2中。基底2可包括絕緣層上覆碎（SOI)以節省 201248853The Si to IS gate structure is used to control the semiconductor structure to be turned on or off. In the on state, the current flowing through the channel includes at least the first channel and the second channel. The first channel includes a portion of the second doped region adjacent to the first gate structure. The second channel includes a portion of the second doped region adjacent to the second gate structure. DETAILED DESCRIPTION OF THE INVENTION The following detailed description of the embodiments, together with the accompanying drawings, is as follows: [Embodiment] The disclosure relates to a semiconductor structure and a method of operating the same. The semiconductor structure includes an insulating gate bipolar transistor ("G B τ"), a diode or a semiconductor such as a lateral double-diffused metal oxide semiconductor (LDMOS) or a reinforced metal oxide semiconductor transistor (EDMOS). 1 and 2 illustrate a perspective view of a semiconductor structure in an embodiment. The semiconductor structure includes a substrate 2. The first doped region 4 is located in the substrate 2. The substrate 2 may include an overlying layer of insulation (SOI) to save 201248853
i w /oo»rA t 設計面積’並降低開啟電阻。第 12、次摻雜層14與次摻雜層μ 區4包括次推雜層 摻雜區4中。第三摻雜區8A =雜區6位於第一 雜區6中。井區以位於第一換雜;摻4雜，立於第二摻 f於井區18中。井區18與第二雜摻第四摻雜區Π) 二互，分開。第五推雜區28位於=藉由第-換雜區 ^ 32位於第1雜區4與底層$ 6中。埋介電 括氧化物。第三摻雜區8A、第：採雜埋介電層32包 28、第四摻雜區】〇與次摻雜们2^^8Β、第五摻雜區 於-些實施例中’第1圖與 :雜的。 包括LDMOS或EDM〇s。第一換雜區=之半導體結構 次摻雜層14與次摻雜層16)、井區°° (匕括次摻雜層12、 第三摻雜區8A與第三播雜區8b='第四摻雜區10、 導電型。底層56、第二摻雜“、有第—導電型例如N 反於第一導電型的第二導電型例如、P =雜區28具有相 於-些實施例中，第巧 2電型。 匕括IGBT。帛一摻雜區4(包括 戶斤不之半導體結構 2摻雜層16)、第三摻雜區8a :第雜、次摻雜層14 導電型例如N導電型。底屑 一摻雜區8B具有第 雜區28、井區18與第四摻雜日、第二摻雜區6、第五換 的第二導電型例如1>導電型。具有相反於第一導電型 於其他實施例中，第— 導電型係例如N導電型。第一$型係例如P導電型 係用作源極。第四穆雜雜區认與第三穆雜區8—B 具有第-閘結構2〇 :用作汲極。 、溝槽結構係位於基底2 6 201248853 I w /〇j〇r/\ 中。第二溝槽結構34也位於基底2中。第-閘綠構20包 括閘電極層22與位於閘電極層22上的閘介電層24。閘電 二!!包括多晶石夕、金屬或_石夕化物。第：溝槽結構 件36與形成在導電^件36上的介電70件 么Γ嫌:凡件36包括多晶石夕、金屬或金屬梦化物。介電 二STT、位於第—摻雜區4上。介電結構3°包括淺溝槽隔 ()。為深溝槽的第二溝槽結構％具有隔離其他裝置 此能幫助半導體結構維持高的崩潰電壓。第二 或二可視4與具'有第-閘結構2。的第-溝槽結構的深: %分別位於第調變。第1結構與第二閘結構 延伸至介電結雜區6的不同側上。第二閘結構26也 與位於間介電居44第二間結構26包括間介電層4 晶石夕、金屬‘屬々上的問電極層42。閘電極層42包括多 ★ 甸-X &屬矽化物。 第2圖係透視作41㈤ 例中超接面結構的，2所示的部分元件以了解實施 第六摻雜區40，葬照第2圖，半導體結構包括 開。第六摻雜區^ 換雜區4的次摻雜層16互相分 來說，第六摻雜區40、二二電型例如ρ導電型。舉例 介電結構30例如㈣槽=區4的次掺雜層16係在 推雜區40與第—摻_ 27。於實施例中，第六 (s啊細ction)結構 1摻雜層16係形成一超接面 壓(BVdSS)與開啟電阻(她了構能幫助㈣改善崩潰電 雜區40與第一摻雜 形成超接面結構的第六摻 狀（矩形；rectangk)\:可勺於如第2圖所示的條紋形 ^ 角形（hexagonal)、八角形 201248853 I W /Oj〇r/\ * (octagonal)或圓形（circie)。 於實施例中，請參照第 包括使第三摻雜區8A與第^，半導體結構的操作方法 使第三摻雜區8B與第四摻雜，雜區1〇之間具有偏壓，或 加至第1結構20的偏壓5G°° 1G之間具有偏壓。調控施 2〇的第—通道48為開啟控制鄰近於第一閘結構 26的偏壓52,以控制鄰 才加至第二閘结構 ㈣啟或關閉。偏壓50與偏立7第二通道46 壓％與偏壓52可為相 查52可獨立或一起控制。偏 半導體結構在 ^ At —同。於實施例中，舉例來說， 二通道46、/狀 電流係從第三捧雜區8B經第 四摻雜區1〇 *摻雜區4的次摻雜層16、井區18流至第 -摻雜區4的？流也從第三摻雜區8A經第-通道48、第 四摻雜區10。_人推雜層14與次摻雜層12、井區18流至第 構的開啟雷4 Γ此應用雙間極(dual gate)概念之半導體結 12也能幫開啟纽(RdSCm)小。重摻雜的次摻雜層 實施扣阿開啟電流（降低開啟電阻）。 此係同時丄:半導體結構係結合超接面與雙閘極概念，因 說，半導體社。崩潰電壓與開啟電阻（開啟電流）。舉例來 ' °構此以高電壓例如12〇〇v操作。 第3圖格； 係透視化部I 實施例中半導體結構的立體圖。第3圖 第2圖所示刀^件。第3圖所示之半導體結構與第1圖與 第2圖所^ =半導體結構的差異在於，係省略如第1圖與 所示之半導俨井區18。於一實施例中，舉例來說，第3圖 區108A與^結構包括1GBT。第一摻雜區104、第三摻雜 ”弟二摻雜區108B具有第一導電型例如N導電 8 201248853 1 W/ΟΜίΡΑ 型。第二捧雜區106、第五摻雜區128與第四摻雜區no 具有相反於第一導電型的第二導電型例如p導電型。於實 施例中’舉例來說’半導體結構在開啟狀態下，電流係從 第三摻雜區108B經第二通道146與第―摻雜區1()4的次 摻雜層116流至第四摻雜@ 11〇。電流也從第三播雜區 108A經第一通道148、第一推雜區1〇4的次換雜層ιΐ4與 次摻雜層U2流至第四為雜區110。 第4圖繪示一實施例中半導體結構的立體圖。第4圖 係透視化:[5^7 it件。第4圖所示之半導體結構與第i圖斑 第2圖所示之半導體結構的差異在於，係省略如第i圖與 第2圖所示的介電結構30。 _第5圖繪示一實施例中半導體結構的立體圖。第5圖 2透視化部分70件。第5圖所示之半導體結構與第1圖盘 f 2圖所示之半導體結構的差異在於，係省略如第！圖盘 第2圖所示的埋介電層32。第一接雜區2〇4中為埋播雜層 的次捧雜層212 #近具有第1結構220的第-溝槽結構 摻雜濃度係小於遠離第―溝槽結構之部分的推 沾道又▲此4錢升流經第—通道248且路徑長之電流 ^效果’提南半導體結構的導通電流並降低導通電 層度的差異’使得在退火製程之後，次摻雜 曰隸t —溝槽結構之部分的輪庵高度係小於遠離第 之部分的輪廓高度，如第5圖所示。摻雜區254 電型掺雜區254的導電型係與底層256的導 例如ρ導電型’而相反於第 型例如Ν導電型。 干电 201248853 1 vr / r\ 第6圖繪示一實施例中半導體結構的立體圖。第6 所示之半導體結構與第5圖所示之半導體結構的差異在 於，係省略如第5圖所示的介電結構230。 、 第7圖繪示一實施例中半導體結構的立體圖。第7 所示之半導體結構與第1圖與第2圖所示之半導體結構= 差異在於，介電結構330係場氧化隔離(FOX)。 第8圖繪示一實施例中半導體結構的立體圖。第8 所示之半導體結構與第5圖所示之半導體結構的差異$ 於，摻雜區458形成在摻雜區454中。摻雜區458與摻雜 區454具有相同的導電型例如p導電型。 ” 第9圖繪示一實施例中半導體結構的上視圖。第1〇 圖與第11圖分別係沿第9圖中…剖面線與CD剖面線所 綠製出的半導體結構的剖面圖。請參照第9圖，第六推雜 區540係藉由第-摻雜區5〇4互相分開。第六播雜區· ”有矩开虚g /、換雜區54〇並不限於如第9圖所示的矩 形（贈⑽抑），而可包括六角形（hexag〇nai)、八角形 麵⑽圓形（咖le)。半導體結構係結合超接面 閘極概念的金屬氧仆主道 ' 六摻雜區54。係以多i:=::DM〇S。舉例來說，第 圖與第u @，槽卿成。請參照第 &層556可為摻雜層或磊晶層。 第圖繪不一實施例中半導 圖係沿第12圖中EF a丨丨&站μα A ^ 圖。往知第12 @ 製出的半導體結構的剖面 雜「…、第蜂巢狀的第六摻雜區640與第一摻 =604係交錯排列。交錯排列的第六換雜區64〇與第一 區_係形成超接面結構。構成超接面結構的第六摻 201248853 i w /ojorn 雜區640與第^一換r- 角形（hexagonal) / 區604並不限於如第i2圖所示的六 而可包括矩形（rectangle)、八角形 (〇Ctag°nal)或圓形(咖呦。半導體結構係結合超接面盘雙 閘極概念的金屬氧化半導體例如⑶職了 成超接面結構的第六摻雜區64〇與第一摻雜區6〇4分別= •以離子植人所形成。請參照第13..圖，底層㈣可為播雜 層或磊晶層。 第14圖曰示實施例中半導體結構的剖面圖。請參 照第14圖，第-摻雜區7〇4包括（導電型相同的）緩衝區 760,位於底層756與超接面結構術之間。第14圖所示 之半導體結構係省略如第13圖中所示的井區618。 第15圖所示之半導體結構與第14圖所示之半導體結 構的差異在於，第一摻雜區804之緩衝區86〇靠近第二閘 結構826的部分的高度係大於遠離第二閘結構826的部分 的高度。更詳細地來說，第一摻雜區8〇4之緩衝區_的 高度係從靠近第-間結構826往遠離第二閘結構_的方 向逐漸變小。 第16圖繪示一實施例中半導體結構的上視圖。第17 圖與第18圖分別係沿第16圖中如剖面線與 繪製出的半導體結構的剖面圖。請參照第18_，第^ 結構92G係電性連接至偏壓966例如閘極偏壓。第: 區908係電性連接至偏壓964例如源極偏壓。第^ 926係電性連接至偏壓968例如閘極偏壓。第四‘區口籌 係電性連接至隸970例如錄關。於—實施例; 有第-導電型例如N導電型的第—摻雜區_ 中％ 201248853i w /oo»rA t design area' and lower the on resistance. The 12th sub-doped layer 14 and the sub-doped layer μ region 4 are included in the sub-doped layer doped region 4. The third doping region 8A = the impurity region 6 is located in the first impurity region 6. The well zone is located in the first mixed zone; the doped 4 is mixed, and the second doped f is in the well zone 18. The well region 18 and the second impurity doped fourth doping region 二) are mutually separated and separated. The fifth doping region 28 is located in the first miscellaneous region 4 and the bottom layer $6 by the first interleave region ^32. Buried dielectric oxide. The third doped region 8A, the first: the buried dielectric layer 32 package 28, the fourth doped region 〇 and the sub-doping 2 ^ ^ 8 Β, the fifth doped region in some embodiments - the first Figure and: Miscellaneous. Includes LDMOS or EDM〇s. First change region = semiconductor structure sub-doped layer 14 and sub-doped layer 16), well region ° ° (including sub-doped layer 12, third doped region 8A and third doped region 8b = ' The fourth doped region 10, the conductive type. The underlayer 56, the second doping ", the first conductivity type, such as N, the second conductivity type opposite to the first conductivity type, for example, P = the impurity region 28 has a phase In the example, the second electrical type includes an IGBT, a doped region 4 (including a semiconductor structure 2 doped layer 16), and a third doped region 8a: the first and second doped layers 14 are electrically conductive. The type is, for example, an N-conducting type. The chip-doped region 8B has a first impurity region 28, a well region 18 and a fourth doping region, a second doping region 6, and a fifth exchanged second conductivity type such as 1> conductivity type. In contrast to the first conductivity type, in other embodiments, the first conductivity type is, for example, an N conductivity type. The first type, for example, the P conductivity type is used as the source. The fourth impurity region is recognized as the third impurity. The region 8-B has a first gate structure 2: used as a drain. The trench structure is located in the substrate 2 6 201248853 I w /〇j〇r/\. The second trench structure 34 is also located in the substrate 2. The first gate green structure 20 includes the brake The layer 22 and the gate dielectric layer 24 on the gate electrode layer 22. The gate electrode includes a polycrystalline stone, a metal or a stellite compound. The first: the trench structure member 36 is formed on the conductive member 36. 70 pieces of dielectric material: the piece 36 includes polycrystalline stone, metal or metal dreaming. Dielectric two STT, located in the first doping zone 4. The dielectric structure 3° includes shallow trench isolation (). The second trench structure % for the deep trench has isolation from other devices which can help the semiconductor structure maintain a high breakdown voltage. The second or second visible 4 is deeper with the first trench structure having the first gate structure 2. % is located in the first modulation. The first structure and the second gate structure extend to different sides of the dielectric junction region 6. The second gate structure 26 also includes a dielectric between the second dielectric structure 26 and the second dielectric structure Layer 4 is a spar, and the metal 'is a question electrode layer 42. The gate electrode layer 42 includes a plurality of dynasty-X & genus telluride. Fig. 2 is a perspective view of the super-junction structure in the case of 41 (f) Some of the elements are known to implement the sixth doped region 40, and the buried structure is shown in Fig. 2. The semiconductor structure includes the sixth doped region. In other words, the sixth doped region 40, the two-second electrical type, for example, the p-conducting type, for example, the dielectric structure 30 such as (four) trench = region 4 of the sub-doped layer 16 is in the doping region 40 and the first doping_27. In an embodiment, the sixth doped layer 16 forms a super junction voltage (BVdSS) and an on-resistance (she has a configuration to help (4) improve the collapsed electrical region 40 and the first doping. Forming a sixth blend of the super junction structure (rectangular; rectangk): can be scooped in a stripe shape as shown in Fig. 2, hexagonal, octagonal 201248853 IW /Oj〇r/\ * (octagonal) or Round (circie). In an embodiment, please refer to the method of including the third doping region 8A and the semiconductor structure, so that the third doping region 8B and the fourth doping region have a bias voltage between the doping regions, or There is a bias voltage between the bias voltage 5G°° 1G of the first structure 20. The first channel 48 of the regulation control is to open the control bias 52 adjacent to the first gate structure 26 to control the addition of the neighbor to the second gate structure (4). The bias voltage 50 and the bias 7 second channel 46 pressure % and bias voltage 52 can be independently or together controlled for the comparison 52. The partial semiconductor structure is at ^At. In an embodiment, for example, the two-channel 46, /-type current flows from the third doping region 8B through the fourth doped region 1 〇 * doped region 4 of the doped layer 16, the well region 18 to the first - Doped area 4? The flow also passes from the third doping region 8A through the first channel 48 and the fourth doping region 10. The human doping layer 14 and the sub-doped layer 12, the well region 18 flow to the first opening of the thunder 4, and the semiconductor junction 12 of the dual gate concept can also be used to help the opening (RdSCm). The heavily doped sub-doped layer implements a turn-on current (lowering the turn-on resistance). At the same time, the semiconductor structure is combined with the concept of super junction and double gate, because of the semiconductor society. Crash voltage and turn-on resistance (on current). For example, '° is constructed with a high voltage such as 12〇〇v. Figure 3 is a perspective view of the semiconductor structure in the embodiment of the perspective portion I. Figure 3 The tool shown in Figure 2. The semiconductor structure shown in Fig. 3 differs from the semiconductor structure of Figs. 1 and 2 in that the semiconductor well region 18 as shown in Fig. 1 and FIG. In one embodiment, for example, the third region 108A and the structure include 1 GBT. The first doped region 104 and the third doped "di-doped region 108B" have a first conductivity type such as an N conductive 8 201248853 1 W/ΟΜίΡΑ type. The second doping region 106, the fifth doping region 128 and the fourth The doped region no has a second conductivity type opposite to the first conductivity type, such as a p-conductivity type. In the embodiment, 'for example, the semiconductor structure is in an on state, and the current is from the third doped region 108B through the second channel. 146 and the doped layer 116 of the first doping region 1 () 4 flow to the fourth doping @ 11 〇. The current also flows from the third doping region 108A through the first channel 148, the first doping region 1 〇 4 The sub-division layer ιΐ4 and the sub-doped layer U2 flow to the fourth impurity region 110. Fig. 4 is a perspective view showing the semiconductor structure in an embodiment. Fig. 4 is a perspective view: [5^7 it piece. The difference between the semiconductor structure shown in FIG. 4 and the semiconductor structure shown in FIG. 2 is that the dielectric structure 30 as shown in FIGS. i and 2 is omitted. FIG. 5 illustrates an implementation. A perspective view of a semiconductor structure in the example. Fig. 5 is a perspective view of a portion 70. The difference between the semiconductor structure shown in Fig. 5 and the semiconductor structure shown in Fig. 1 is The buried dielectric layer 32 as shown in Fig. 2 of the Fig. 2 is omitted. The second impurity layer 212 in the first impurity region 2〇4 is a buried layer of the first layer 220. - the doping concentration of the trench structure is smaller than the pushing track away from the portion of the first-trench structure. ▲ This 4 liters flows through the first channel 248 and the path length of the current ^ effect 'the conduction current of the semiconductor structure is lowered and lowered The difference in conductivity of the conduction layer is such that after the annealing process, the height of the rim of the portion of the sub-doped t--the trench structure is less than the height of the profile away from the portion, as shown in Fig. 5. Doped region 254 The conductivity type of the electrically doped region 254 is opposite to the conductivity of the bottom layer 256, such as the p-conductivity type, and is opposite to the first type, such as the Ν conductivity type. Dry electricity 201248853 1 vr / r\ Figure 6 illustrates the semiconductor structure of an embodiment The difference between the semiconductor structure shown in FIG. 6 and the semiconductor structure shown in FIG. 5 is that the dielectric structure 230 as shown in FIG. 5 is omitted. FIG. 7 is a perspective view showing the semiconductor structure in an embodiment. The semiconductor structure shown in FIG. 7 and the semiconductor structure shown in FIGS. 1 and 2 The difference is that the dielectric structure 330 is field oxide isolation (FOX). Figure 8 is a perspective view of the semiconductor structure in an embodiment. The difference between the semiconductor structure shown in Fig. 8 and the semiconductor structure shown in Fig. 5 is A doped region 458 is formed in the doped region 454. The doped region 458 has the same conductivity type as the doped region 454, such as a p-conducting type." Figure 9 illustrates a top view of a semiconductor structure in an embodiment. Fig. 1 and Fig. 11 are respectively sectional views of the semiconductor structure which is formed green along the hatching line and the CD hatching line in Fig. 9. Referring to Fig. 9, the sixth doping region 540 is separated from each other by the first doping region 5〇4. The sixth broadcast area · "The moment opening virtual g /, the replacement area 54" is not limited to the rectangle shown in Fig. 9 (gif (10)), but may include hexagonal (hexag〇nai), octagonal surface (10) A circular structure. The semiconductor structure is combined with the metal oxide servant of the super junction gate concept. The six-doped region 54 is multi-i:=::DM〇S. For example, the figure The first u @, 槽卿成. Please refer to the & layer 556 can be a doped layer or an epitaxial layer. In the first embodiment, the semi-conducting system is along the EF a丨丨 & station μα in Fig. 12. A ^Fig. The cross-section of the semiconductor structure produced by the 12th @@", the sixth doped region 640 of the honeycomb shape is staggered with the first doping 604. The staggered sixth mismatch region 64〇 Forming a super junction structure with the first region _ system. The sixth doped 201248853 iw /ojorn miscellaneous region 640 and the first r-angled hexagonal region / region 604 constituting the super junction structure are not limited to the i2-th image The six shown may include a rectangle, an octagonal shape, or a circular shape. The semiconductor structure is combined with a metal oxide semiconductor having a double gate concept of a super-connected disk, for example, (3) The sixth doping region 64〇 of the super junction structure and the first doping region 6〇4 are respectively formed by ion implantation. Please refer to Fig. 13., the bottom layer (4) may be a hybrid layer or an epitaxial layer. Figure 14 is a cross-sectional view showing the semiconductor structure in the embodiment. Referring to Figure 14, the first doped region 7〇4 includes a buffer 760 (of the same conductivity type) located at the bottom layer 756 and the super junction structure. The semiconductor structure shown in Fig. 14 omits the well region 618 as shown in Fig. 13. The semiconductor structure shown in Fig. 15 differs from the semiconductor structure shown in Fig. 14 in that the first doping region The height of the portion of the buffer 86 804 near the second gate structure 826 is greater than the height of the portion remote from the second gate structure 826. In more detail, the height of the buffer region of the first doped region 8〇4 16 is a top view of the semiconductor structure in an embodiment, and FIG. Section line and cross-section of the drawn semiconductor structure. Please refer to the 18th, the ^2 structure 92G is electrically connected to the partial 966, for example, a gate bias. Section: 908 is electrically coupled to a bias voltage 964, such as a source bias. The second 926 is electrically coupled to a bias voltage 968, such as a gate bias. Sexually connected to the 970, for example, recorded. In the embodiment; there is a first-conducting type, such as an N-conducting type - doped region _ % 201248853
i W /tO»PA 長的方式形成在具有第二導電型例如p型 請參照第η圖，位於第三摻雜區908之間：：:二 似亦電性連接至· 964 β請參照第16圖， 溝槽結構934係具有環型，以定義半導體結_ = 效縮減設計面積。介電結構-包括淺 ΐίη導體結構的操作方法包括控制偏壓 且有=970，使第三摻雜區犠與第四摻雜區则之 」閉:=流的:壓。調控偏壓966，以控制鄰近於第 _，、、n 通道948為開啟或關閉。調控偏壓 Γ二鄰近於第二問結構926的第二通道_為開 例來說’半導體結構在開啟狀態下，電流係 〇 一多雜區908經第二通道946、第一摻雜區9〇4、井 ^ 9'流至第四摻雜區91〇。電流也從第三摻雜區簡經 第-通道948、第-摻雜區904、井區918流至第四摻雜 區91 〇二因此應用雙閘極(dual 概念之半導體結構的開 啟電流高且開啟電阻(Rdson)小。 於些實施例中’第！ 8圖所示之半導體結構包括 LDMOS或EDM0S。第一摻雜區9〇4、井區918、第四換 雜區910、第三換雜區9〇8具有第一導電型例如n導電型。 底層956、第二摻雜區906與第五摻雜區928(第17圖）具 有相反於第二導電型的第二導電型例如P導電型。八 於-些實施例中，第18圖所示之半導體結構包括 IGBT。帛#雜區9〇4、第三摻雜區规具有第一導電型 例如N導電型。底層956、第二摻雜區906、第五摻雜區 12 201248853 I W/ΟΟδΚΛ 92=17圖）、井區918與第四摻雜區9K)具有相反於第 -導電型的第二導電型例如？導電型。於其他實施例中弟 包括IGBT的半導體結構係具有導電型為例如_導電型 的井區918。於-些實施例中，係省略井區918，如第a 圖所示的半導體結構。 k於-些實施例中，半導體結構包括二極體，如第2〇 圖所示。第20圖所示的半導體結構與第18圖所示之 體結構的差異在於，第一閘結構1〇2〇、第三摻雜區则 與第二閘結構1026係電性連接至偏壓1〇72例如低電壓。 第四摻雜區1010係電性連接至偏壓刪例如高電壓。於 一些實施例中，係省略井區1〇18，如第Μ圖所示的半 體結構。 第22圖與第23圖繪示一實施例中半導體結構的剖面 圖。第22圖與第23圖分別係例如沿第16圖中GH剖面線 與IJ剖面線所繪製出。第2 2圖與第2 3圖所示之半導體結 構與第17圖與第18圖所示之半導體結構的差異在於，具 有第一導電型例如N導電型的第一摻雜區11〇4包括次推 雜層1112與次摻雜層1114。於一實施例中，次摻雜層up 係以磊晶成長的方式形成具有第二導電型例如p導電型的 底層1156上。於其他實施例中’次摻雜層1112係具有與 底層1156相同的第二導電型例如p導電型而視為底層 1156的一部分。 第24圖與帛25 ®料一實施例中半導體結構的剖面 圖。第24圖與第25圖分別係例如沿第丨6圖中gh剖面線 與IJ剖面線所繪製出。第24圖與第25圖所示之半導體結 201248853 j vy / ^ 構與第17圖與第18圖所示之半導體結構的差異在於埋 介電層1232位於第一摻雜區12〇4與底層1256之間。埋 介電層1232包括氧化物。於一實施例中，第一播雜區蘭 係以蟲晶的方式形成。 第26圖與帛27圖綠示-實施例中半導體結構的剖面 圖。第26圖與第27圖分別係例如沿第16圖中GH剖面線 與IJ剖面線所繪製出。第26圖與第27圖所示之半導體結 構與第17圖與第18圖所示之半導體結構的差異在於，介 電結構1330係場氧化隔離(FQX)。 於一實施例中，第18圖所示的第一閘結構92〇與第 二溝槽結構934係視情況調變成更長的如第28圖中所示 的第-間結構1420與第二溝槽結構1434。於其他實施例 中’第18圖所示的第一閘結構92〇與第二溝槽結構9料 係視情況觀成更短的如第29圖巾所示的第—間結構 1520與第二溝槽結構1534。請參照第29圖摻雜區〗554 形成在第二溝槽結構1534與底層1556之間。 第30圖繪示一實施例申半導體結構的上視圖。第3ι 圖與第32圖分別係沿第3〇圖中KL剖面線與_剖面線 所繪製出的半導體結構的剖面圖。第3〇、31、％圖所示 之半導體結構與第16、17、18圖所示之半導體結構的差 異在於，第三溝槽結構1676配置在第二溝槽結構⑹4的 外側。 第33圖繪示一實施例中半導體結構的上視圖。第％ 圖與第35圖分別係沿第33圖中〇p剖面線與qr剖面線 所綠製出的半導體結構的剖面圖。第圖所示 201248853 =導紅構與第16、17、18圖所示之半導體結構的差 在於’具有第一導電型例如㈣電型的第—摻雜區聰 包括次摻雜層1712與次摻雜層1714。於一實施例中次 摻雜層1714係以蟲晶成長的方式形成在具有第二導電型 例如P導電型的底層1756上。 第36圖繪示一實施例中半導體結構的上視圖。第36 圖繪7F之半導體結構與第16圖綠示之半導體結構的差里 2 ’係形成第-閘結構删。半導體結構沿st剖面線 、，曰製出的剖面圖可相似於第18圖。 第37圖繪示一實施例中半導體結構的上視圖。第π 圖綠示之半導體結構與第33圖繪示之半導體結構的差異 在於，係形成第-閘結構192〇。第38圖係沿第37圖中 W剖面線所繪製出的半導體結構的剖面圖。第％圖繪示 之半導體結構與第35圖緣示之半導體結構的差異在於， 埋介電層1932係位於底層觸與第—摻雜區19〇4的次 摻雜層1912之間。第37圖所示之半導體結構沿剖面 線繪製出的剖面圖也可相似於第35圖。 第39圖繪示一實施例中半導體結構的剖視圖。第％ 圖繪示之半導體結構與第38圖綠示之半導體結構的差異 在於，第一摻雜區2004的次摻雜層2〇12係延伸在第一閘 結構2020與第二溝槽結構2034之間。 /第4〇圖繪示一實施例中半導體結構的上視圖。第41 圖係沿第40圖中Wx剖面線所緣製出的半導體結構的剖 面圖:第40、41圖所示之半導體結構與第16、18圖所示 之半導體結構的差異在於，第五換雜區2128配置在第三 201248853 摻雜區2舰與第三摻雜_娜之間。 圖係==一實施例中半導體結構的上視圖。第43 圖。第42 f 剖面線所綠製出的半導體結構的剖面 半導體沾棋3圖繪不之半導體結構與第4〇、41圖繪示之 構的差異在於，具有第一導電型例 區_包括次擦雜層2212與次換雜層驗於 具有第次捧雜層2214係以蠢晶成長的方式形成在 導電型例如—P導電型的底層上。 圖會干夕4丄圖、會不一實施例中半導體結構的剖視圖。第44 ^ 結構與^ 43圖㈣之半導㈣構的差異 的次摻雜層加Hi係位於底層Μ%與第一播雜區2304 圖繪二二圖繪示一實施例中半導體結構的剖視圖。第45 在於，、第I導體結構與第44圖繪示之半導體結構的差異 結構24)n—f雜區2404的次播雜層2412係延伸在第一閘 ^2〇與第二溝槽結構2434之間。 念。半導之貫化例中’半導體結構係使用雙閘極概 潰電壓心。構也可結合超接面概念。因此係同時改善崩 結構能贫站，電阻（開啟電流）。具有隔離功能的第二溝槽 積。第一摻?體結構維持高的崩潰電壓，並縮減設計面 結構之部：雜區中為埋摻雜層的次摻雜層靠近具有第-閘 的摻雜濃戶、^雜濃度係小於遠離第一溝槽結構之部分 欵果，接::能提升流經第一通道且路徑長之電流的導通 雖然導體結構的導通電流並降低導通電阻。 月已以較佳貫施例揭露如上，然其並非用以 201248853The method of i W /tO»PA is formed in a second conductivity type, for example, p-type, please refer to the n-th diagram, and is located between the third doping regions 908::: two-like and electrically connected to the 964 β, please refer to In Fig. 16, the trench structure 934 has a ring shape to define a semiconductor junction _ = reduction in design area. The dielectric structure - including the shallow η η conductor structure operation method includes controlling the bias voltage and having = 970 such that the third doped region 犠 and the fourth doped region are "closed: = flow: pressure. The bias voltage 966 is regulated to control the opening/closing of the channel 948 adjacent to the _, , n. The second biasing Γ is adjacent to the second channel of the second structure 926. For the sake of the example, the semiconductor system is in the open state, and the current system 〇 a multi-interval 908 passes through the second channel 946 and the first doping region 9 〇4, the well 9' flows to the fourth doping region 91〇. The current also flows from the third doped region via the first channel 948, the first doped region 904, the well region 918 to the fourth doped region 91. Therefore, a double gate is applied (the semiconductor structure of the dual concept has a high turn-on current). And the turn-on resistance (Rdson) is small. In some embodiments, the semiconductor structure shown in Fig. 8 includes LDMOS or EDMOS. The first doping region 9〇4, the well region 918, the fourth impurity-changing region 910, and the third The dummy region 9〇8 has a first conductivity type such as an n-conductivity type. The bottom layer 956, the second doping region 906, and the fifth doping region 928 (FIG. 17) have a second conductivity type opposite to the second conductivity type, for example. P conductive type. In some embodiments, the semiconductor structure shown in Fig. 18 includes an IGBT. The doped region 9〇4, the third doped region has a first conductivity type such as an N conductivity type. The second doped region 906, the fifth doped region 12 201248853 IW / ΟΟ δ ΚΛ 92 = 17 map), the well region 918 and the fourth doped region 9K) have a second conductivity type opposite to the first conductivity type, for example? Conductive type. In other embodiments, the semiconductor structure including the IGBT has a well region 918 of a conductivity type such as a conductivity type. In some embodiments, the well region 918 is omitted, such as the semiconductor structure shown in FIG. In some embodiments, the semiconductor structure comprises a diode, as shown in Figure 2. The difference between the semiconductor structure shown in FIG. 20 and the bulk structure shown in FIG. 18 is that the first gate structure 1〇2〇, the third doped region and the second gate structure 1026 are electrically connected to the bias voltage 1 〇 72 is for example a low voltage. The fourth doped region 1010 is electrically connected to a bias voltage such as a high voltage. In some embodiments, the well region 1 〇 18 is omitted, such as the half structure shown in the figure. 22 and 23 illustrate cross-sectional views of a semiconductor structure in an embodiment. Fig. 22 and Fig. 23 are drawn, for example, along the GH section line and the IJ section line in Fig. 16. The difference between the semiconductor structure shown in FIGS. 2 and 2 and the semiconductor structure shown in FIGS. 17 and 18 is that the first doped region 11〇4 having the first conductivity type such as the N conductivity type includes The dummy layer 1112 and the sub-doped layer 1114 are sub-doped. In one embodiment, the sub-doped layer is formed on the underlayer 1156 having a second conductivity type such as a p-conductivity type by epitaxial growth. In other embodiments, the sub-doped layer 1112 has the same second conductivity type as the underlayer 1156, such as the p-conductivity type, and is considered part of the underlayer 1156. Figure 24 is a cross-sectional view of the semiconductor structure in an embodiment of the 帛25® material. Fig. 24 and Fig. 25 are respectively plotted, for example, along the gh section line and the IJ section line in Fig. 6. The difference between the semiconductor junction 201248853 j vy / ^ structure shown in Figs. 24 and 25 and the semiconductor structure shown in Figs. 17 and 18 is that the buried dielectric layer 1232 is located in the first doped region 12 〇 4 and the bottom layer. Between 1256. Buried dielectric layer 1232 includes an oxide. In one embodiment, the first dissemination zone is formed in the form of insect crystals. Fig. 26 and Fig. 27 are green diagrams showing a cross-sectional view of the semiconductor structure in the embodiment. Fig. 26 and Fig. 27 are respectively plotted, for example, along the GH section line and the IJ section line in Fig. 16. The difference between the semiconductor structures shown in Figs. 26 and 27 and the semiconductor structures shown in Figs. 17 and 18 is that the dielectric structure 1330 is field oxide isolation (FQX). In one embodiment, the first gate structure 92A and the second trench structure 934 shown in FIG. 18 are adjusted to be longer as the inter-structure 1420 and the second groove are shown in FIG. Slot structure 1434. In other embodiments, the first gate structure 92 and the second trench structure 9 shown in FIG. 18 are shorter as the case, and the first structure 1520 and the second as shown in FIG. Trench structure 1534. Referring to FIG. 29, the doping region 554 is formed between the second trench structure 1534 and the bottom layer 1556. Figure 30 is a top plan view showing an embodiment of the semiconductor structure. The third and the third figures are cross-sectional views of the semiconductor structure drawn along the KL and _section lines in the third figure, respectively. The semiconductor structure shown in Figs. 3, 31, and % is different from the semiconductor structures shown in Figs. 16, 17, and 18 in that the third trench structure 1676 is disposed outside the second trench structure (6) 4. Figure 33 is a top plan view of the semiconductor structure in an embodiment. Fig. 100 and Fig. 35 are respectively sectional views of the semiconductor structure which is formed green along the 〇p hatching and the qr hatching in Fig. 33. The figure shown in Fig. 201248853 = the red structure and the semiconductor structure shown in Figs. 16, 17, and 18 are different in that the first doped region having the first conductivity type, for example, the (four) type, includes the sub-doped layer 1712 and the second. Doped layer 1714. In one embodiment, the sub-doped layer 1714 is formed on the underlayer 1756 having a second conductivity type such as a P conductivity type in a manner of crystal growth. Figure 36 is a top plan view of the semiconductor structure in an embodiment. Figure 36 depicts the difference between the semiconductor structure of 7F and the semiconductor structure of green of Figure 16 to form the first gate structure. The cross-sectional view of the semiconductor structure along the st section line can be similar to that of Fig. 18. Figure 37 is a top plan view of the semiconductor structure in an embodiment. The difference between the semiconductor structure of the πth green display and the semiconductor structure shown in Fig. 33 is that the first gate structure 192 is formed. Figure 38 is a cross-sectional view of the semiconductor structure taken along line W of Figure 37. The difference between the semiconductor structure shown in Fig. 100 and the semiconductor structure shown in Fig. 35 is that the buried dielectric layer 1932 is located between the underlying doped layer 1912 of the first doped region 19〇4. The cross-sectional view of the semiconductor structure shown in Fig. 37 along the section line can also be similar to that of Fig. 35. Figure 39 is a cross-sectional view showing the semiconductor structure in an embodiment. The difference between the semiconductor structure shown in FIG. 10 and the semiconductor structure shown in FIG. 38 is that the sub-doped layer 2 〇 12 of the first doping region 2004 extends in the first gate structure 2020 and the second trench structure 2034. between. / Figure 4 is a top view of the semiconductor structure in an embodiment. Figure 41 is a cross-sectional view of the semiconductor structure formed along the Wx section line in Fig. 40: the semiconductor structure shown in Figs. 40 and 41 differs from the semiconductor structure shown in Figs. 16 and 18 in that the fifth The changeover region 2128 is disposed between the third 201248853 doped zone 2 ship and the third doping_na. Figure = = top view of the semiconductor structure in one embodiment. Figure 43. The cross section of the semiconductor structure made by the green line of the 42th f-line is different from the structure of the semiconductor structure of the fourth and 41st, and has the difference of the first conductive type region _ including the secondary rubbing The impurity layer 2212 and the sub-division layer are formed on the underlayer of a conductive type such as a -P conductive type in such a manner that the second holding layer 2214 is grown in a stray crystal. The figure will be a cross-sectional view of the semiconductor structure in one embodiment. The 44th structure and the 43th structure (4) of the semiconducting (four) structure of the sub-doped layer plus Hi is located in the bottom layer Μ% and the first dying region 2304. Figure 22 shows a cross-sectional view of the semiconductor structure in an embodiment . The 45th is that the first conductor structure and the semiconductor structure difference structure shown in FIG. 44 are 24) the n-f hybrid region 2404 of the second hybrid layer 2412 extends in the first gate 2 and the second trench structure Between 2434. Read. In the semi-conducting example, the semiconductor structure uses a double-gate absolute voltage core. The structure can also be combined with the super junction concept. Therefore, it is simultaneously improving the collapse of the structure energy, the resistance (opening current). A second trench with isolation. The first dopant structure maintains a high breakdown voltage and reduces the portion of the design surface structure: the sub-doped layer in the impurity region is a doped layer having a first gate, and the dopant concentration is less than Part of the result of the first trench structure is that: the conduction of the current flowing through the first channel and the path length is increased, although the conduction current of the conductor structure reduces the on-resistance. The month has been disclosed as a better example, but it is not used 201248853
乾圓當視後附之申請專利範圍 :蟄者’在不脫離本發明之精 與潤飾’因此本發明之保護 所界定者為準》 【圖式簡單說明】 · 第1圖繪示一實施例中半導體 弟2圖繪示—φ，^ 貫施例中半導體結構的立體圖。 ^圍繪實施例中半導體結構的立體圖。 f 3圖、’a示一'貫施例中半導體結構的立體圖。 f 4圖繪示一實施例中半導體結構的立體圖。 第5圖繪示一實施例中半導體結構的立體圖。 第6圖繪不―實施射半導魅構的立體圖。 f 7圖繪'貫施例巾半導體結構的立體圖。 第8圖繪示—實_中半導體結構的立體圖。 第9圖料—實施财半導赌構的上視圖。 第10圖纟會示―實施例中半導體結構的剖面圖。 ^ 11圖㈣—實_中半導體結構的剖面圖。 ★ 12圖繪示—實施例中半導體結構的上視圖。 第13⑽示—實施例中半導體結構的剖面圖。 第14圖繪示-實施例中半導體結構的剖面圖。 第15圖㈣—實施例中半導體結構的剖面圖。 =16圖㈣—實施例中半導體結構的上視圖。 第17圖繪示—實施例中半導體結構的剖面圖。 第18圖繪示-實施例中半導體結構的剖面圖。 第19圖繪示_實施例中半導體結構的剖面圖。 第20圖繪示—實施例中半導體結構的剖面圖。 17 201248853The scope of the patent application is as follows: the present invention is not limited to the essence and refinement of the present invention, and therefore the definition of the protection of the present invention shall prevail. [Simplified description of the drawings] FIG. 1 illustrates an embodiment. The middle semiconductor brother 2 diagram shows a perspective view of the semiconductor structure in the φ, ^ embodiment. ^ A perspective view of the semiconductor structure in the embodiment. The f 3 diagram, 'a shows a perspective view of the semiconductor structure in the embodiment. Figure 4 is a perspective view of the semiconductor structure in an embodiment. Figure 5 is a perspective view of a semiconductor structure in an embodiment. Figure 6 depicts a perspective view of a semi-conducting charm. Figure 7 is a perspective view of a semiconductor structure of a conventional towel. Figure 8 is a perspective view of the semiconductor structure of the real_middle. Figure 9 - The top view of the implementation of the financial semi-guided gambling structure. Figure 10 is a cross-sectional view showing the semiconductor structure in the embodiment. ^ 11 Figure (4) - a cross-sectional view of the semiconductor structure in the real_. ★ Figure 12 is a top view of the semiconductor structure in the embodiment. Figure 13 (10) shows a cross-sectional view of the semiconductor structure in the embodiment. Figure 14 is a cross-sectional view showing the semiconductor structure in the embodiment. Figure 15 (4) - A cross-sectional view of a semiconductor structure in an embodiment. = 16 Figure (4) - Top view of the semiconductor structure in the embodiment. Figure 17 is a cross-sectional view showing the semiconductor structure in the embodiment. Figure 18 is a cross-sectional view showing the semiconductor structure in the embodiment. Figure 19 is a cross-sectional view showing the semiconductor structure in the embodiment. Figure 20 is a cross-sectional view showing the semiconductor structure in the embodiment. 17 201248853
1 W/0D5KA 第21圖繪示一實施例中半導體結構的剖面圖。 第22圖繪示一實施例中半導體結構的剖面圖。 第23圖繪示一實施例中半導體結構的剖面圖。 第24圖繪示一實施例中半導體結構的剖面圖。 第25圖繪示一實施例中半導體結構的剖面圖。 第26圖繪示一實施例中半導體結構的剖面圖。 第27圖繪示一實施例中半導體結構的剖面圖。 第28圖繪示一實施例中半導體結構的剖面圖。 第29圖繪示一實施例中半導體結構的剖面圖。 第30圖繪示一實施例中半導體結構的上視圖。 第31圖繪示一實施例中半導體結構的剖面圖。 第32圖繪示一實施例中半導體結構的剖面圖。 第33圖繪示一實施例中半導體結構的上視圖。 第34圖繪示一實施例中半導體結構的剖面圖。 第35圖繪示一實施例中半導體結構的剖面圖。 第36圖繪示一實施例中半導體結構的上視圖。 第37圖繪示一實施例中半導體結構的上視圖。 第38圖繪示一實施例中半導體結構的剖面圖。 第39圖繪示一實施例中半導體結構的剖面圖。 第40圖繪示一實施例中半導體結構的上視圖。 第41圖繪示一實施例中半導體結構的剖面圖。 第42圖繪示一實施例中半導體結構的上視圖。 第43圖繪示一實施例中半導體結構的剖面圖。 第44圖繪示一實施例中半導體結構的剖面圖。 第45圖繪示一實施例中半導體結構的剖面圖。1 W/0D5KA Figure 21 is a cross-sectional view showing the semiconductor structure in an embodiment. Figure 22 is a cross-sectional view showing a semiconductor structure in an embodiment. Figure 23 is a cross-sectional view showing the semiconductor structure in an embodiment. Figure 24 is a cross-sectional view showing a semiconductor structure in an embodiment. Figure 25 is a cross-sectional view showing a semiconductor structure in an embodiment. Figure 26 is a cross-sectional view showing a semiconductor structure in an embodiment. Figure 27 is a cross-sectional view showing the semiconductor structure in an embodiment. Figure 28 is a cross-sectional view showing a semiconductor structure in an embodiment. Figure 29 is a cross-sectional view showing a semiconductor structure in an embodiment. Figure 30 is a top plan view of a semiconductor structure in an embodiment. Figure 31 is a cross-sectional view showing a semiconductor structure in an embodiment. Figure 32 is a cross-sectional view showing a semiconductor structure in an embodiment. Figure 33 is a top plan view of the semiconductor structure in an embodiment. Figure 34 is a cross-sectional view showing the semiconductor structure in an embodiment. Figure 35 is a cross-sectional view showing a semiconductor structure in an embodiment. Figure 36 is a top plan view of the semiconductor structure in an embodiment. Figure 37 is a top plan view of the semiconductor structure in an embodiment. Figure 38 is a cross-sectional view showing a semiconductor structure in an embodiment. Figure 39 is a cross-sectional view showing the semiconductor structure in an embodiment. Figure 40 is a top plan view of a semiconductor structure in an embodiment. Figure 41 is a cross-sectional view showing a semiconductor structure in an embodiment. Figure 42 is a top plan view of the semiconductor structure in an embodiment. Figure 43 is a cross-sectional view showing the semiconductor structure in an embodiment. Figure 44 is a cross-sectional view showing a semiconductor structure in an embodiment. Figure 45 is a cross-sectional view showing a semiconductor structure in an embodiment.
201248853 iw/o^erA 【主要半導體元件符號說明】 2 :基底 4、104、204、504、604、704、804、904、11〇4、12〇4、 1704、1904、2004、2204、2304、2404:第一摻雜區 6、106、906 :第二摻雜區 8A、8B、108A、108B、908、1〇〇8、2108A、2108B : 第三摻雜區 10、110、910、1010 :第四摻雜區 12、14、16、112、114、116、212、1112、1114、1712、 1714、1912、2012、2212、2214、2312、2412 :次摻雜層 18、618、918、1018 :井區 20、220、920、1020、1420、1520、1820、1920、2020、 2420 :第一閘結構 22、42 :閘電極層 24、44 :閘介電層 26、126、226、826、926、1026 :第二閘結構 28、128、928、2128 :第五摻雜區 30、130、230、330、930、1330 :介電結構 32、1232、1932、2332 :埋介電層 34、934、1434、1534、1634、2034、2434 ··第二溝 槽結才冓 36 :導電元件 38 :介電元件 40、540、640 :第六摻雜區 19 201248853201248853 iw/o^erA [Description of main semiconductor device symbols] 2: Substrates 4, 104, 204, 504, 604, 704, 804, 904, 11〇4, 12〇4, 1704, 1904, 2004, 2204, 2304, 2404: first doped regions 6, 106, 906: second doped regions 8A, 8B, 108A, 108B, 908, 1 〇〇 8, 2108A, 2108B: third doped regions 10, 110, 910, 1010: Fourth doped regions 12, 14, 16, 112, 114, 116, 212, 1112, 1114, 1712, 1714, 1912, 2012, 2212, 2214, 2312, 2412: sub-doped layers 18, 618, 918, 1018 : Well regions 20, 220, 920, 1020, 1420, 1520, 1820, 1920, 2020, 2420: first gate structures 22, 42: gate electrode layers 24, 44: gate dielectric layers 26, 126, 226, 826, 926, 1026: second gate structure 28, 128, 928, 2128: fifth doped region 30, 130, 230, 330, 930, 1330: dielectric structure 32, 1232, 1932, 2332: buried dielectric layer 34, 934, 1434, 1534, 1634, 2034, 2434 · Second trench junction 36: Conductive element 38: Dielectric element 40, 540, 640: Sixth doping region 19 201248853
1 W /05»FA 46、146、946 :第二通道 48、148、248、948 :第一通道 50、52、964、966、968、970、1072、1074 :偏壓 254、454、458、1554 :摻雜區 56、256、556、656、756、956、1156、1256、1556、 1756、1956、2256、2356 :底層 760、860 :緩衝區 762 :超接面結構 1676 :第三溝槽結構 AB、CD、EF、GH、IJ、KL、MN、OP、QR、ST、 UV、WX、YZ :剖面線 201 W /05»FA 46, 146, 946: second channel 48, 148, 248, 948: first channel 50, 52, 964, 966, 968, 970, 1072, 1074: bias 254, 454, 458, 1554: doped regions 56, 256, 556, 656, 756, 956, 1156, 1256, 1556, 1756, 1956, 2256, 2356: bottom layer 760, 860: buffer 762: super junction structure 1676: third trench Structure AB, CD, EF, GH, IJ, KL, MN, OP, QR, ST, UV, WX, YZ: section line 20