201248647 六、發明說明： 【發明所屬之技術領域】 本技術係關於積體電路§己憶裝置’及如此裝置中的感測電路。 【先前技術】 積體電路記憶裝置不斷地變得更小及更快。記憶裝置尺寸及 速度的一個限制條件是在陣列中準備感測資料所使用的位元線預 充電及偏壓電路。為了這些目的所使用之典型結構可參見張等人 發明標題為"MEMORY CELL SENSE AMPLIFIER”之美國專利第201248647 VI. Description of the Invention: [Technical Field] The present technology relates to an integrated circuit § a device and a sensing circuit in such a device. [Prior Art] Integrated circuit memory devices are continually becoming smaller and faster. One limitation of the size and speed of the memory device is the bit line precharge and bias circuit used to prepare the sensed data in the array. For the typical structure used for these purposes, see Zhang et al., entitled "US MEMORY CELL SENSE AMPLIFIER"
6219290 號；Ordonez 等人標題為"FAST SENSE AMPLIFIERTOH NONVOLATILE MEMORY”之美國專利第 6498751 號；及 Rai 等 人標題為"SENSE AMPLIFIER WITH IMPROCED SENSITIVITY'， 之美國專利第6392447號。No. 6,219, 290; U.S. Patent No. 6,487, 517 issued to Ordonez et al., "FAST SENSE AMPLIFIERT OH NONVOLATILE MEMORY; and U.S. Patent No. 6,392,447, to Rai et al., "SENSE AMPLIFIER WITH IMPROCED SENSITIVITY.
而先前的由朱等人發明標題為”MEMORY ARRAY WITH LOW POWER BIT LINE PRECHARGE”之美國專利第 7082061 號，在此引為參考資料，是討論先前的偏壓結構。如美國專利第 7082061號中所解釋的’ 一個使用於傳統記憶裝置中的基本偏壓電 ，包括一制壓電晶體及一負載電晶體與每一條位元線耦接。此制 壓電晶體可以包含具有閘極與各自回授反向器之輸出耦接的疊接 電晶體。此回授反向器之輸入與制壓電晶體的源極和資料線導體 耦接。因此提供一個動態的回授電路，其設定具有小電流通過負 載電晶體的平衡條件。在感測節點的電壓會穩定在目標準位，且 此時位元線準備好被感測。於允許感測節點的電壓穩定在目標準 位的一段時間之後，記憶胞藉由施加字元線電位於此記憶胞的閘 極而被存取來感測。如此的方案需要在每一條位元線中有著回授 反向器。 201248647 在傳統的替代貫施例中，動態回授反向器可以由靜態偏壓電 壓vbias來取代。此電路在沒有動態回授情況下係以類似於上述的 方式來操作。當位元線上的電壓Vbl到達約為偏壓電壓減去 通過制壓電晶體臨界電壓的準位時，此制壓電晶體開始關閉且降 低其電流。動態回授可以達成將感測節點的電壓穩定在目標準 位。在此情況下，完成此預充電步驟，且位元線準備好被感測。 如此可以節省佈局面積。然而，其會依賴使用一條額外的位元線 且需要額外的偏壓電壓以供偏壓電壓調整器使用。此外。為了實 把低電壓位元線的預充電，必須先施加較高的偏壓準位，之後再 於當假位元線的電壓接近目標電壓時施加較低的偏壓準位。然 而，此較尚然後較低的偏壓方法因為舉例而言於預充電操作期間 自位元線與偏壓調節器輸出充電耦合的緣故在同一時間僅能驅動 與感測放大|§搞接之相對少數目的位元線。 當這些傳統的方法成功地應用於記憶裝置中，但是隨著記憶 體存取速度增加、元件尺寸減少且使用更複雜及更高度平行運作 的感測結構時，每一條字元線上所需的複雜感測結構變成了積體 電路記憶體在尺寸及製造成本的一個限制條件。此外，隨著供應 電壓的大小持續地降低且操作速度提升，於預充電時發生的電壓 過大現象也會減少記憶陣列中感測資料值的邊界。因此需要提供 一種感測系統，其於積體電路中佔用較小的面積而且可以操作的 更快速與消耗較少的功率。 【發明内容】 本技術係揭露一種積體電路裝置，此積體電路裝置包含一 合適作為尚速及低電壓操作的記憶胞陣列。此處所描述之對資 料線預充電的偏壓電路可以在防止電壓過大的同時又能達成 快速預充電。此外，此處所描述之電路也可以在占用裝置非常 小布局面積的情況下實施。 4 201248647 =明所描之一實施例包括揭露一種 有稷數個行和列的記憶胞陣列。複數歸 _=搞 接’及複數條字元線與該陣列的列減。制壓電路 條資料線中的各自㈣_接，且適合防止在該各自’資料 的感測節點超過一目標值。一偏壓雷踗，/ 貝枓4·上 雪颅丨、；产〜士一 偏I電路，在其輸出提供一偏壓 電£以在_充電區間中的—第—階段使用—第—電壓 開啟該制壓電路’且在該預充電區間中的—第二階段使用 二電壓準㈣啟該繼電路，其巾該第二電壓準位大於 一 電壓準位。 、^ 此處所描述之偏壓電路包括一預充電電晶體、一疊接電晶 體及-電阻性元件串接在—起。具有—回授電路與該^接電= 體的，極自一對應字元線介於該疊接電晶體與該電阻元件之 間的節點耦接。此處所描述之偏壓電路，該回授電路係響應一 時序信號以於該第一階段設定該第一偏壓準位及於該第二階 段設定該第二偏壓準位。 、 通常而言，本發明所描之另一實施例包括揭露一種感測一 纪憶裝置中資料的方法，其中該記憶裝置包含一記憶胞陣列、 複數條資料線與該陣列的行耦接、複數條字元線與該陣列的列 耦接。將該複數條資料線中的各自資料線上之節點制壓在一接 近一目標準位以響應一個以兩階段或以上施加的偏壓電壓，該 第二電壓準位大於該第一電壓準位。 本發明之目的，特徵，和實施例，會在下列實施方式的章 節中搭配圖式被描述。 【實施方式】 本發明以下的實施例描述係搭配圖式1到5進行說明。 第1圖顯示一個記憶電路的示意圖，其包括感測電 路、預充電路、制壓電路及分享偏壓電路以作為兩階段、 201248647 低功耗預充電之用。一記憶陣列由記憶胞1 〇〇〜1 〇2所代 表’在記憶胞陣列中沿著位元線的方向上具有各自的行， 其中在選取位元線上的電壓VBL藉由行解碼電路（未示）而 與資料線DL0、DL1 ._.DLn耗接。這些資料線DL0、 DL1 ...DLn在對應的節點經由各自的資料線電路與感測放 大器SA0、SA1...SAn叙接’在此例示範例中，資料線電路 包括會在以下詳細描述的預充電路、負載電路及制壓電 路。圖示中亦顯示標示為CBL的電容，其與每一條位元線 相關。標示為Cbl的電容係代表通過一選取位元線上的整 體位元線電容值。在此例示的實施例中，記憶胞陣列中具 有n+1條資料線DL0、DLl...DLn。制壓電晶體1〇3〜105 及負載電晶體106〜108包括於各自的資料線DL0〜DLn中， 且在此例示實施例中安排成完全相同的。制壓電晶體1〇3 作為資料線DL0上的一制壓電路。在此實施例中，制壓電 晶體103是一個疊接組態的N通道MOS電晶體，具有源 極與一導體耦接，此導體隨後經由解碼電路而與所選取記 憶胞耦接’其汲極則與感測節點VCELL耦接，及閘極與偏 壓節點VBIAS耦接。負載電晶體106作為資料線dl〇上的 一負載。此負載電晶體是一個N通道MOS電晶體，具有 汲極與閘極和供應電位VDD耦接，而源極與感測節點 VCELL耦接。預充電電晶體12〇〜122也與各自的資料線 DL0〜DLn耦接。此預充電電晶體是一個p通道M〇s電晶 體’具有源極與供應電位VDD耦接，汲極與偏壓節點VB1AS 耦接’而閘極與時序信號SAEB耦接，其在某些實施例中 也可以施加至感測放大器109〜111作為致能信號。資料線 DL1上的制壓電晶體104、負載電晶體107及預充電電晶 體121也是以類似的方式安排。類似地，資料線DLn上的 制壓電晶體105、負載電晶體1〇8及預充電電晶體122也 6 201248647 疋以同樣的方式安排。如圖中所示，制壓電晶體1⑹〜1 05 的閘極在一兩階段制壓偏壓電路13〇的輸出與一共同節點 耦接，此制壓偏壓電路130提供偏壓電壓Vbias。雖然，在 此例示實施例中，制壓偏壓電路13〇以兩階段操作，在替 代實施例中也可以是超過兩階段。 負料線DL0上的感測節點vCELL與感測放大器1 〇9輕 ，。類似地，資料線DL1上的感測節點Vcell與感測放大 窃上10耦接，而資料線DLn上的感測節點Vcell與感測放 大态ill耦接。此範例中的每一個感測放大器1〇9〜包 括一個與參考電壓Vref耦接的第二輸入。這些感測放大器 =9 111 &供用來指示儲存於各自選取記憶胞1〇〇〜1〇2中 資料的輸出資料。此參考電壓Vref可以使用假記憶胞或是 類似的方式產生。 控制信號係用來控制包括一預充電區間及一感測區間 之感測操作的時序。在第丨圖中，控制信號saeb、cntu cN 2與兩階段制壓偏壓電路13 0耦接以控制此預充電 區間的第一及第二階段的時序。此外，控制信號saeb和 SE NB分別與預充電電晶體12 0〜12 2和感測放大 器109〜111 f接，以控制施加預充電電壓至資料線的時序以及感測放 ’在感測節點上感測資料的時序。通常而言，此控制信 係首先施加以預充電感測節點上的資料線，而兩 偏壓電路13〇產生偏㈣壓v_以防止感測節 期的準位。在預充電區間結束時，控制信號 關閉預充電電晶體⑽〜122，且發出控制信號 儲在於寺序以使得感測節點上的電屢Vc亂反映出 储存於所選取記憶胞中的資料值。 南p比ί ^ t例中’控制信號SAEB、CNTL1和CNTL2控制 兩階段中施加至陣列中所有資料線⑽〜DLn之㈣電晶 201248647 體。103〜105閘極上的電壓Vbias。當然也可以使用其他控制 信號的組合，可以包括相同數目或是不同數目的控制信號。 、在感測節點上的目標電壓值是根據此預充電區間結束 或接近結束時的電壓vBIAS，及在此疊接組態下此制壓電晶 體103〜105 ό^閘極至源極電壓慶降而蚊。如㈤此處所描 ，的，電壓VBIAS在至少兩個階段中施加，在第一階段中電 壓VBIAS具有一第一電壓準位，而在第二階段中電壓Vbias ΐ有一第二電壓準位，其是高於此第一電壓準位。即，此 f料線上的VBIAS在預充電期間自一低電壓準位轉變至一 高電壓準位。每-階段的㈣長度可以視特定應用中的記 憶陣列及感測放大器的操作所需而調整。然而，這些代表 性時間長度顯示此處所描述之適合作為低電壓及高速記惊 體所需的電路。 〜 此陣列的預充電區間在此預充電區間之第二階段結束 或接近結束時完成’且此陣列中的資料線DL〇〜DLn可以準 備被感測。當存取一個例如是快閃記憶胞之典型非揮發記 憶胞結構中的-記憶胞時，使記憶胞資料影響感測節點 vCELL上的電壓，導致其快速地趨近一個高記憶胞臨界值 VCELL_HVT或低記憶胞臨界值Vcell_lvt。施加至感測放大器 109、110、m的參考電壓Vref，是設定在約為Vcell-贿 與Vcell lvt中間處。感測放大器1〇9、11〇、η!上的Vcm 和vREF的目標值邊界大到足夠消除雜訊的影響，但是又越 小越好以供快速感測之用。 —立第2圖顯不適用於p圖巾電路的兩階段偏壓電路的 不思圖。帛2圖中的偏壓電路僅需要在積體電路中佔用很 /的佈局面積，且可以有效率地操作以避免在記憶體陣列 中的感測郎點產生過大的電壓。 8 201248647 第2圖中的偏壓電路包括苐— 第一終端與電源供應節點VDD耦接，一级，其具有一 點轉接’及閘極與-控制信號轉接，此控= 中為SAEB。第二電晶體MN2具有一第一線总在此犯例 耦广第二終端與N2節點轉接，及閘極在點 偏壓電路的輸出耦接。一電阻元件4〇9， N4與此 元件’連接於N2節點與接收例如是vss的參== 考節點之間。此參考節點及其他參考節點在此: 角形作代表。此電阻元件409的阻值係根據所應 設計參數來設定’使得在Ν2節點的電壓落 VBIAS之電壓準位而言合適的操作範 娜2的電流適合偏壓之驅動能力。第三電 及間朽n N2搞接。笛與參考郎點耦接’ 及閘極與即點Ν2耦接帛四電晶體μν4具 在節點Ν4與此偏壓電路的輸出柄接， =壓= ΙΓΓ第節點轉接，及閘極與節= 接。第五電晶體具有一第一終端在筋黜 ::出耦接’-第二終端與節·點Ν3耦接，及閘 以2稱接。 一致能電路’在此實施例中係應用反或閘N〇R42〇及 二第六電晶體與節.點N3 _來實施。此致能電路係用來 於此預充電區間的第一階段時將節點N3盥一參 且於此預充電區間的第二階段時將節點、N;:夂考： 壓解除耦接。 第一電晶體Μ P1閘才亟的控制信號s A £ b也可以斑偏壓 耦接之記憶陣列中的預充電電晶體的間極耦接？且因 匕疋義出此預充電區間的開始及結束時點。 201248647 在此範例中的致能電路包括一邏輯閘，其具有至少一 輸入與至少—時序信號耦接。如同之前所提過的，此邏輯 閘是具有兩個輸入的反或閘NOR 420，其具有控制信號 CNTL1和CNTL2做為輸入。此反或閘NOR 420的輸出係 提供給第六電晶體MN6的閘極。此第六電晶體MN6具有 一第一終端與節點N3耦接，一第二終端與參考節點耦接， 及閘極與反或閘NOR 420的輸出耦接。在此範例中，控制 信號CNTL1和CNTL2決定此預充電區間的第一區間和第 一 h ^又之時序’其會於以下搭配第3圖的時序圖加以解釋。 第七電晶體MN7具有一第一終端與節點N2耦接，一 第二終端與參考節點耦接，及閘極與控制信號SAEB搞 接。第八電晶體MN8具有一第一終端在節點N4與此偏壓 電路的輸出耦接，一第二終端與參考節點耦接，及閘極與 控制信號SAEB耦接。此第七和第八電晶體在預充電區^ 以外被啟動以防止節點N2和N4的浮接。 第3圖顯示第2圖中偏壓電路的一實施例中之時序 圖’此偏壓電路係在包括第丨圖所示記憶陣列的積體電路 中。讀取操作所牽涉到的代表性控制信號舉例而言包括晶 片致能信號PCEB、位址正確信號PADVB、位址線ΡΑ[16·21] 及一位址變動偵測信號ATD。當一讀取操作被初始時，’控 制信號被施加以控制感測操作的時序，在此範例中包括一 感測放大器致能信號SAEB、感測信號SNEB、及第一和第 二控制信號CTSB和DCTS。在此範例中，第—和第二控制 信號CTSB和DCTS與第2圖中的控制信號CNTI/和 如第3圖所示，感測區間係由信號SENB自低準位轉 變至高準位的變動527與自高準位轉變至低準位的變動 528之間的間距而定義。而預充電區間係由信號ctsb自 201248647 轉變至低準位的變動523與自低準位轉變至高準位 ’文524之間的時間間距而定義。此預充電區間的第一 自信號CTSB的變動523開始直到控制信號DCTs =低準位轉變至高準位的變動525為止。此預充電區間的 一階段係自控制信號DCTS自低準位轉變至高準位的變 ，/25開始，而同時控制信號DCTSj呆持高準位直到控制 信號CTSB的變動524為止。控制信號saeb自轉變52ι 開始發出而在預充電區間及感測區間持續，此感測區間到 轉隻522結束’且此範例中信號senb同時在528轉變。 在此，時，控制信號DCTS於526轉變回到低準位狀態。 第2圖中的電路包括一預充電電晶體與第一電晶體 MP1對應’一疊接電晶體與第二電晶體MN2對應並和電阻 兀件490沿著與回授電路的疊接電晶體(MN幻閘極經由節 點N2串聯之，其是介於電阻元件49〇與疊接電晶體(mn2) 源極，間。此回授電路係響應控制信號CNTL1和cNTL2 以在^ ,卩自#又设疋一第一偏壓準位和在第二階段設定一第 二偏，準位，且其中第二偏壓準位係高於第一偏壓準位。 在此範例中的回授電路是兩級反向器。此反向器的輸入是 介於電阻元件490與疊接電晶體（MN2)源極之間的節點 N2。此反向器的輸出在節點N4提供此偏壓電路的輸出。 此反向器包括一拉升電晶體MP3，及第一和第二下拉電晶 體(MP4和MP5)與其輸入耦接。第六電晶體河^^操作作為 一切換開關以響應在反或閘N〇R 42〇輸出的控制信號，其 會於預充電區間的第一階段開啟第二下拉電晶體Mp5，並 且於預充電區間的第二階段關閉第二下拉電晶體MP5。其 結果是，節點N4之偏壓電路輸出的電壓準位會在第一階 段時略低。 201248647 因此，本發明描述了包括記憶體之積體電路的資料感 測方法。此方法包括於預充電區間施加一預充電電壓至記 憶陣列中的#料線，且使用制壓電路制壓個別資料線 感測節點於接近-預設目標值，以於預充電區間響應具有 兩個或更多階段的偏壓電壓。此方法包括產生偏壓電壓以 響應時序信號及回授’使得偏壓電壓在第一階段時具有一 第Γ偏壓準位和在第二階段具有一第二偏壓準位，且其中 第了偏壓準位係尚於第一偏壓準位。之後，開始於於預充 電，間的第亏階段或之後的感測區間内，與感測節點轉接 之感測放大器被致能。此方法可以使用如第2圖所示的小 ，積、高速極低電壓之電路實施。第2圖中如此的小體積、 南ΐ極低電壓之電路或是類似的電路，可以用來驅動一頁 ^核式記憶體中與例如是64、128條資料或更多的大量平 線對應的大量㈣電晶體。當然，實際被平行驅動 =料線數目必須由所使用特定讀取模式之設計來適當地 沾士 代實知例中’在兩個或以上階段中產生偏壓電壓 播μφ坚電路可以使用像是美國專利7982061中所示的根 據^較益之動態回授電路來實施，將其修改使得施加 直到參考節點上的電壓到達第一準位，且隨 ίη Γ 位的電墨直到此參考節點上的電壓到達 目軚準位或是此預充電區間結束為止。 偏壓= Ϊ = =準位的此預充電區間，且 地轉ί。柄Γ ^ i朗第二階段時快速 偏壓準彳 中，可以具有超過兩個階段。此外， ίίίΐΐ:以較快或較慢地轉變，端視特定應用 寸卩白奴和第二階段與預充電區間中第一準位 12 201248647 和苐一準位電壓到達的時間對應，而不是在偏壓電路的輸 出電壓準位產生快速地轉變。 ^ 第4圖顯示本發明使用如第2圖中偏壓電路於高速讀 取操作時之資料線電壓的模擬結果，其是對在感測節點上 的目標準位於預充電之後約在範圍800〜950亳伏特之間， 與傳統使用單一偏壓準位來控制資料線上疊接電晶體閘極 的比較。轨跡曲線501、502、503顯示此處所描述之兩階 段偏壓電路的模擬結果，因為圖中顯示這些軌跡幾乎沒有 超過目標值而展現本發明可以防止電壓過大的結果。相對 而5，執跡曲線511、512、513顯示使用單一偏壓準位所 產生的電壓過大現象。 第5圖顯示根據本發明一實施例之積體電路的簡化示意圖。 其中積體電路包括使用具有此處所描述的由一參考位元線所控制 之預充電及制壓電路。此積體電路包括一使用記憶胞實施之記憶 陣歹j 600’此s己憶胞可以例如是浮動閘極或是電荷捕捉之非揮發記 憶胞、唯讀記憶胞、或是其他型態的記憶胞。在一較佳應用中， ，憶陣列係組態為反或閘(NOR)架構。一頁面/列解碼$二！與沿 ^03與沿著記憶陣列600行方向安排之複數條位元線6〇4 =體二 笛，壓^偏壓結構623經由行解碼器6〇3及位元線6〇4導體以例 行扣上/It的之前所描述的方式與資料線(未示)在記憶陣列的 此外L預充電結構633也是經由行解碼器603及 r旳鉍妓…以之刖所描述的方式與記憶陣列的行方向上之4己 的方式與制壓/偏壓結構叫碰，且防止在= 低糖己憶體的預充電時在資料 :：連、 提供給行解碼器_、頁=解瑪器 A ㈣測放大n與資料輸人結構經由行解碼器 601 201248647 603、制壓/偏壓結構623及預充電結構633而與所選取的記憶胞麵 接。複數個參考假記憶胞640亦包含於此積體電路上，且用來產 生方塊606中感測放大器所使用的參考電壓，使得方塊6〇6中的 ΪΐΪί11使轉考籠來域記憶_ _中的實際記憶胞之 故界電壓改變。資料由積體電路上的輸人/輸出埠提供給 線611，或者由積體電路其他内部/外部的資、1 = ^資料輸入、_。資料由方請中的感測物 輸出線612，提供至積體電路上的輸入/輸出埠。 積體電路中。這些資源包含由方塊_所代表之讀取 ί除的/=壓6=產生或提供獅輸號時序嶋機構 電：；=:^施例中可以利用繼、 中，糊嶋嫌實施例 以執行-電腦程式而控制裝置ς =，可使，—積體電路， 器係由特殊目的邏輯電路與通用^在實施例中，該控制 於圖中緣示，第5圖中所’示 带處理盗組合而成。雖然並未 片所使_其他元件。因此、，’ _電^可以包括舉綱言於單晶 積體電路的代表性例示。’、’、g 3圮憶體或其他功能電路之 雖然本發明係已來昭訾 未受限於其詳㈣㈣容'彳來加以描述’然本發明創作並 述中所建議，且其他替換方、^及修改樣式係已於先前描 人士所思及。特別是 ^ =樣式將為熟習此項技藝之 I有於本發明之構件結 201248647 ^達成與本發明ff上相同結果者，皆4離本判之 於隨附在本發明 【圖式簡單說明】 本發明係由申請專利範圍 + 特徵，和實施例，會在j °這些和其它目的， 描述，其中·· 實轭方式的章節中搭配圖式被 第1圖顯示一個記恃雷* 上的制壓電路之兩階段偏虔電路、圖’其包括對資料線 電路對一疊接為基礎之制壓組態的兩階段偏壓 序圖第3圖顯示包括第2圖中偏壓電路的一記憶電路之時 第4圖顯示本發明使用一 壓變化之-記憶體的感測電壓的感測節點電 圖。第5_示根據本發明—實施例之積體電路的簡化示意 【主要元件符號說明】 100〜102 :記憶胞 〜105 :制壓電晶體 106〜108 :負載電晶體 109〜111 :感測放大器 120〜122 :預充電電晶體 130 :兩階段制壓偏壓電路 4〇9 :電阻元件 42〇 :反或閘 15 201248647 600 :記憶陣列(快閃記憶體） 601 :列解碼器 602 :字元線 603 :行解碼器 604 :位元線 605 :匯流排 606 :感測放大器/資料輸入結構 609 :讀取、抹除及程式化狀態機構 608 :讀取、抹除及程式化供應電壓 611 ·資料輸入線 612 :資料輸出線 623 :制壓/偏壓結構 624 :兩階段制壓偏壓電路 633 :預充電結構 640 :假參考記憶胞 16The prior U.S. Patent No. 7,028,061, entitled "MEMORY ARRAY WITH LOW POWER BIT LINE PRECHARGE", which is hereby incorporated by reference, is hereby incorporated by reference. As explained in U.S. Patent No. 7,082,061, a basic bias voltage used in a conventional memory device includes a piezoelectric crystal and a load transistor coupled to each of the bit lines. The piezoelectric crystal can comprise a stacked transistor having a gate coupled to an output of a respective feedback inverter. The input of the feedback inverter is coupled to the source of the piezoelectric crystal and the data line conductor. Therefore, a dynamic feedback circuit is provided which sets the equilibrium condition with a small current through the load cell. The voltage at the sense node will stabilize at the target level and the bit line is ready to be sensed. After allowing the voltage of the sensing node to stabilize for a period of time, the memory cell is sensed by applying a word line potential to the gate of the memory cell. Such a scheme requires a feedback inverter in each bit line. 201248647 In a conventional alternative embodiment, the dynamic feedback inverter can be replaced by a static bias voltage vbias. This circuit operates in a manner similar to that described above without dynamic feedback. When the voltage Vbl on the bit line reaches approximately the bias voltage minus the level of the threshold voltage through the piezoelectric crystal, the piezoelectric crystal begins to turn off and lower its current. Dynamic feedback can achieve the stabilization of the voltage of the sensing node at the target level. In this case, this pre-charging step is completed and the bit line is ready to be sensed. This saves layout area. However, it would rely on the use of an extra bit line and an additional bias voltage for the bias voltage regulator to use. Also. In order to pre-charge the low voltage bit line, a higher bias level must be applied first, and then a lower bias level is applied when the voltage of the dummy bit line approaches the target voltage. However, this comparative and then lower biasing method can only be driven and sensed at the same time because of the charge coupling of the bit line and the bias regulator output during the precharge operation, for example. A relatively small number of destination bit lines. While these traditional methods have been successfully applied to memory devices, the complexity required for each word line is increasing as memory access speeds increase, component sizes decrease, and more complex and highly parallel sensing structures are used. The sensing structure becomes a limiting factor in the size and manufacturing cost of the integrated circuit memory. In addition, as the magnitude of the supply voltage continues to decrease and the operating speed increases, the excessive voltage that occurs during pre-charging also reduces the boundary of the sensed data values in the memory array. It is therefore desirable to provide a sensing system that occupies a smaller area in an integrated circuit and that can operate faster and consume less power. SUMMARY OF THE INVENTION The present technology discloses an integrated circuit device including a memory cell array suitable for operation at a sustained speed and a low voltage. The bias circuit pre-charging the data line described herein can achieve fast pre-charging while preventing excessive voltage. Furthermore, the circuits described herein can also be implemented with a very small layout area of the device. 4 201248647 = One embodiment described includes the disclosure of an array of memory cells having a plurality of rows and columns. The complex number _= engages and the complex number of character lines minus the column of the array. Each of the voltage-carrying circuit strips is connected (4) and is adapted to prevent the sensing node at the respective 'data' from exceeding a target value. A biased Thunder, / Bessie 4 · Snowy cranial sputum, a production-to-semi-I circuit, providing a bias voltage at its output to use in the -phase - phase - the first voltage Turning on the voltage-pressing circuit 'and in the second stage of the pre-charging interval - the second circuit is used to start the circuit, and the second voltage level is greater than a voltage level. The bias circuit described herein includes a pre-charged transistor, a stacked electrical crystal, and a resistive component connected in series. And having a feedback circuit coupled to the node between the stacked transistor and the resistive element. In the bias circuit described herein, the feedback circuit is responsive to a timing signal to set the first bias level in the first phase and the second bias level in the second phase. In general, another embodiment of the present invention includes a method of sensing data in a device, wherein the memory device includes a memory cell array, a plurality of data lines coupled to the rows of the array, A plurality of word line lines are coupled to the columns of the array. The nodes on the respective data lines in the plurality of data lines are pressed to a near one standard level in response to a bias voltage applied in two stages or more, the second voltage level being greater than the first voltage level. The objects, features, and embodiments of the present invention will be described in conjunction with the drawings in the <RTIgt; [Embodiment] The following description of the embodiments of the present invention will be described with reference to Figs. Figure 1 shows a schematic diagram of a memory circuit that includes a sensing circuit, a pre-charge circuit, a voltage-suppression circuit, and a shared bias circuit for two-stage, 201248647 low-power pre-charging. A memory array is represented by memory cells 1 〇〇 〜 1 〇 2 ′ in the memory cell array along the bit line in the direction of the bit line, wherein the voltage VBL on the selected bit line is by the row decoding circuit (not Shown) and the data lines DL0, DL1 ._.DLn are consumed. These data lines DL0, DL1 ... DLn are connected to the sense amplifiers SA0, SA1 ... SAAn at respective nodes via respective data line circuits. In this example, the data line circuits are described in detail below. Precharge circuit, load circuit and voltage suppression circuit. The capacitor labeled CBL is also shown in the figure and is associated with each bit line. The capacitance indicated as Cbl represents the value of the overall bit line capacitance through a selected bit line. In the illustrated embodiment, the memory cell array has n+1 data lines DL0, DL1 ... DLn. The piezoelectric crystals 1〇3 to 105 and the load transistors 106 to 108 are included in the respective data lines DL0 to DLn, and are arranged to be identical in this exemplary embodiment. The piezoelectric crystal 1〇3 is used as a voltage-pressing circuit on the data line DL0. In this embodiment, the piezoelectric crystal 103 is a stacked N-channel MOS transistor having a source coupled to a conductor, which is then coupled to the selected memory cell via a decoding circuit. The pole is coupled to the sensing node VCELL, and the gate is coupled to the bias node VBIAS. The load transistor 106 acts as a load on the data line dl. The load transistor is an N-channel MOS transistor having a drain and a gate coupled to a supply potential VDD, and a source coupled to the sense node VCELL. The precharge transistors 12A to 122 are also coupled to the respective data lines DL0 to DLn. The precharged transistor is a p-channel M〇s transistor having a source coupled to a supply potential VDD, a drain coupled to a bias node VB1AS' and a gate coupled to a timing signal SAEB, which in some implementations It is also possible to apply to the sense amplifiers 109 to 111 as an enable signal in the example. The piezoelectric crystal 104, the load transistor 107, and the precharged electric crystal 121 on the data line DL1 are also arranged in a similar manner. Similarly, the piezoelectric crystal 105, the load transistor 1〇8, and the precharge transistor 122 on the data line DLn are also arranged in the same manner. As shown in the figure, the gates of the piezoelectric crystals 1(6) to 105 are coupled to a common node in a two-stage voltage-biasing bias circuit 13A, and the voltage-compression bias circuit 130 supplies a bias voltage. Vbias. Although, in this exemplary embodiment, the bias voltage biasing circuit 13 is operated in two stages, it may be more than two stages in the alternative embodiment. The sensing node vCELL on the negative line DL0 is lighter than the sense amplifier 1 〇9. Similarly, the sensing node Vcell on the data line DL1 is coupled to the sensing amplification 10, and the sensing node Vcell on the data line DLn is coupled to the sensing amplification state ill. Each sense amplifier 1〇9 in this example includes a second input coupled to a reference voltage Vref. These sense amplifiers =9 111 & are used to indicate the output data stored in the respective selected memory cells 1〇〇~1〇2. This reference voltage Vref can be generated using a pseudo memory cell or the like. The control signal is used to control the timing of the sensing operation including a pre-charge interval and a sensing interval. In the second diagram, control signals saeb, cntu cN 2 are coupled to a two-stage voltage-biasing bias circuit 13 0 to control the timing of the first and second phases of the pre-charge interval. In addition, the control signals saeb and SE NB are connected to the pre-charge transistors 12 0 12 12 and the sense amplifiers 109 to 111 f, respectively, to control the timing of applying the precharge voltage to the data line and sensing the 'on the sensing node. The timing of sensing data. Typically, this control signal is first applied to pre-charge the sense line on the sense node, and the two bias circuits 13 〇 generate a bias voltage (v) to prevent the sense period from being sensed. At the end of the pre-charge interval, the control signal turns off the pre-charge transistors (10)-122, and a control signal is issued to the temple sequence so that the electrical iterations on the sense node reflect the data values stored in the selected memory cells. In the case of the south p, the control signals SAEB, CNTL1, and CNTL2 are controlled in two stages to apply all of the data lines (10) to DLn in the array to the (4) electron crystal 201248647 body. The voltage on the gate of 103~105 is Vbias. It is of course also possible to use a combination of other control signals, which may comprise the same number or a different number of control signals. The target voltage value at the sensing node is based on the voltage vBIAS at the end or near the end of the pre-charging interval, and in this stacked configuration, the piezoelectric crystal 103~105 ό^ gate to source voltage Drop mosquitoes. As described in (v) herein, the voltage VBIAS is applied in at least two stages, in which the voltage VBIAS has a first voltage level and in the second phase the voltage Vbias has a second voltage level, It is higher than this first voltage level. That is, the VBIAS on this f-line transitions from a low voltage level to a high voltage level during pre-charging. The (four) length of each phase can be adjusted as needed for the operation of the memory array and sense amplifier in a particular application. However, these representative lengths of time show the circuitry described herein as suitable for low voltage and high speed shocks. ~ The precharge interval of this array is completed at or near the end of the second phase of this precharge interval' and the data lines DL?~DLn in this array are ready to be sensed. When accessing a memory cell in a typical non-volatile memory cell structure such as a flash memory cell, the memory cell data affects the voltage across the sensing node vCELL, causing it to rapidly approach a high memory cell threshold VCELL_HVT Or low memory cell threshold Vcell_lvt. The reference voltage Vref applied to the sense amplifiers 109, 110, m is set to be approximately midway between Vcell-Bile and Vcell lvt. The target values of Vcm and vREF on the sense amplifiers 1〇9, 11〇, η! are large enough to eliminate the effects of noise, but the smaller the better, for fast sensing. - Figure 2 is not applicable to the two-stage bias circuit of the p-ribbed circuit. The bias circuit in Figure 2 only needs to occupy a very large layout area in the integrated circuit and can operate efficiently to avoid excessive voltage generation in the sensing array in the memory array. 8 201248647 The bias circuit in Figure 2 includes 苐—the first terminal is coupled to the power supply node VDD, the first stage has a one-point transit' and gate-and-control signal transition. This control = SAEB . The second transistor MN2 has a first line which is always coupled to the second terminal and the N2 node, and the gate is coupled to the output of the point bias circuit. A resistive element 4〇9, N4 is connected to the element 2' between the N2 node and the reference node that receives, for example, vss. This reference node and other reference nodes are here: The angle is represented. The resistance of this resistive element 409 is set according to the design parameters so that the current of the operating mode 2 at the voltage level of the Ν2 node falls to the voltage level of VBIAS is suitable for the driving capability of the bias voltage. The third power and the dead n N2 are connected. The flute is coupled to the reference point and the gate is coupled to the point Ν2. The four transistors μν4 are connected to the output of the bias circuit at node Ν4, = voltage = ΙΓΓ node transfer, and gate Section = Connect. The fifth transistor has a first terminal coupled to the rib 黜 :: decoupling ─ the second terminal is coupled to the node Ν 3, and the gate is connected by 2 . The coincidence circuit 'in this embodiment is implemented by applying a reverse OR gate N〇R42〇 and a second sixth transistor to the node. Point N3_. The enabling circuit is used to decouple the node N3 during the first phase of the pre-charging interval and the node, N; in the second phase of the pre-charging interval; The control signal s A £ b of the first transistor Μ P1 gate can also be coupled to the interpole of the pre-charged transistor in the memory array coupled to the pixel array? And because of the meaning of the beginning and end of this pre-charge interval. 201248647 The enable circuit in this example includes a logic gate having at least one input coupled to at least a timing signal. As previously mentioned, this logic gate is an inverse OR gate NOR 420 with two inputs with control signals CNTL1 and CNTL2 as inputs. The output of this inverse OR gate NOR 420 is supplied to the gate of the sixth transistor MN6. The sixth transistor MN6 has a first terminal coupled to the node N3, a second terminal coupled to the reference node, and a gate coupled to the output of the inverse OR gate NOR 420. In this example, the control signals CNTL1 and CNTL2 determine the first interval of the precharge interval and the timing of the first h^ again, which will be explained below in conjunction with the timing diagram of Fig. 3. The seventh transistor MN7 has a first terminal coupled to the node N2, a second terminal coupled to the reference node, and the gate coupled to the control signal SAEB. The eighth transistor MN8 has a first terminal coupled to the output of the bias circuit at node N4, a second terminal coupled to the reference node, and a gate coupled to the control signal SAEB. This seventh and eighth transistors are activated outside the precharge area to prevent floating of the nodes N2 and N4. Fig. 3 is a timing chart showing an embodiment of the bias circuit of Fig. 2. The bias circuit is incorporated in an integrated circuit including the memory array shown in Fig. Representative control signals involved in the read operation include, for example, a wafer enable signal PCEB, an address correct signal PADVB, a address line ΡΑ [16·21], and an address change detection signal ATD. When a read operation is initiated, a 'control signal is applied to control the timing of the sensing operation, including a sense amplifier enable signal SAEB, a sense signal SNEB, and first and second control signals CTSB in this example. And DCTS. In this example, the first and second control signals CTSB and DCTS are compared with the control signal CNTI/ in FIG. 2, and as shown in FIG. 3, the sensing interval is changed from the low level of the signal SENB to the high level. 527 is defined as the spacing between the transitions 528 from the high level to the low level. The pre-charge interval is defined by the change 523 between the transition of the signal ctsb from 201248647 to the low level and the time interval between the transition from the low level to the high level 'text 524'. The first self-signal CTSB variation 523 of this pre-charge interval begins until the control signal DCTs = low level transitions to the high level change 525. The phase of this pre-charge interval begins with the control signal DCTS transitioning from the low level to the high level, /25, while the control signal DCTSj remains at the high level until the change 524 of the control signal CTSB. The control signal saeb starts from the transition 52ι and continues in the pre-charge interval and the sensing interval, and the sensing interval ends at 522. In this example, the signal senb is simultaneously transitioned at 528. Here, the control signal DCTS transitions back to the low level state at 526. The circuit in FIG. 2 includes a pre-charged transistor corresponding to the first transistor MP1, and a stack of transistors corresponding to the second transistor MN2 and a resistor element 490 along the stacked transistor with the feedback circuit ( The MN phantom gate is connected in series via node N2, which is interposed between the resistive element 49 〇 and the spliced transistor (mn2) source. This feedback circuit responds to the control signals CNTL1 and cNTL2 at ^, 卩 from #又a first biasing level is set and a second biasing level is set in the second phase, and wherein the second biasing level is higher than the first biasing level. The feedback circuit in this example is A two-stage inverter. The input of this inverter is a node N2 between the resistive element 490 and the source of the stacked transistor (MN2). The output of this inverter provides this bias circuit at node N4. The inverter includes a pull-up transistor MP3, and the first and second pull-down transistors (MP4 and MP5) are coupled to the input thereof. The sixth transistor operates as a switch in response to the inverse or a control signal output by the gate N〇R 42〇, which turns on the second pull-down transistor Mp5 in the first stage of the pre-charge interval, and The second pull-down transistor MP5 is turned off in the second phase of the pre-charge interval. As a result, the voltage level output by the bias circuit of the node N4 is slightly lower in the first phase. 201248647 Accordingly, the present invention describes the inclusion of memory. A data sensing method for a body integrated circuit. The method includes applying a precharge voltage to a #feed line in a memory array in a precharge interval, and using a pressure generating circuit to compress individual data line sensing nodes in a proximity-pre The target value is set such that the precharge interval is responsive to having two or more stages of bias voltage. The method includes generating a bias voltage in response to the timing signal and feedback 'making the bias voltage have a third phase in the first phase The biasing level has a second biasing level in the second phase, and wherein the first biasing level is still at the first biasing level. Thereafter, starting from the pre-charging phase, or In the subsequent sensing interval, the sense amplifier connected to the sensing node is enabled. This method can be implemented using a small, high-speed, low-voltage circuit as shown in Fig. 2. Small size, low voltage in the south A voltage circuit or the like can be used to drive a large number of (four) transistors in a one-core memory corresponding to a large number of flat lines such as 64, 128 data or more. Of course, the actual parallel drive = The number of feed lines must be appropriately designed by the design of the particular read mode used. 'The bias voltage is generated in two or more stages. The circuit can be used as shown in U.S. Patent 7,982,061. Implemented according to the dynamic feedback circuit of the benefit, modified to apply until the voltage on the reference node reaches the first level, and the ink with the ίη position reaches the target level or the voltage on the reference node reaches the target level or It is the end of this pre-charge interval. Bias = Ϊ = = this pre-charge interval of the level, and the ground is turned to ί. The handle Γ ^ i lang in the second stage of the fast bias 彳 , can have more than two stages. In addition, ίίίΐΐ: a faster or slower transition, depending on the specific application level and the second stage corresponds to the time of the first level 12 201248647 and the first level of the precharge interval, instead of The output voltage level of the bias circuit produces a rapid transition. ^ Figure 4 shows a simulation result of the data line voltage of the present invention using a bias circuit as in Figure 2 for a high speed read operation, which is about a range of 800 after the pre-charging on the sensing node. Between ~950 volts, compared to the traditional use of a single bias level to control the overlap of the gate of the data line. The trajectory curves 501, 502, 503 show the simulation results of the two-stage bias circuit described herein, since the figures show that these trajectories hardly exceed the target value to show that the present invention can prevent excessive voltage. In contrast, the traces 511, 512, and 513 show the excessive voltage generated by using a single bias level. Figure 5 shows a simplified schematic of an integrated circuit in accordance with an embodiment of the present invention. Wherein the integrated circuit includes the use of a precharge and voltage regulation circuit as described herein controlled by a reference bit line. The integrated circuit includes a memory array implemented using a memory cell, which can be, for example, a floating gate or a charge trapping non-volatile memory cell, a read-only memory cell, or other type of memory. Cell. In a preferred application, the memory array is configured as a reverse OR gate (NOR) architecture. One page/column decoding $2! With a plurality of bit lines 6〇4=body two flutes arranged along the line 03 and along the direction of the memory array 600, the voltage bias structure 623 is passed through the row decoder 6〇3 and the bit line 6〇4 conductor as an example. The previously described manner and data lines (not shown) on the line buckle /It are also in the memory array's further L pre-charge structure 633 also via the row decoder 603 and r旳铋妓... in the manner described with the memory array The direction of the four-way direction is called the voltage/biasing structure, and prevents the data in the pre-charging of the low-sugar memory::, connected to the row decoder_, page=solver A (four) The measurement amplification n and the data input structure are connected to the selected memory cell via the row decoder 601 201248647 603, the voltage/bias structure 623 and the pre-charge structure 633. A plurality of reference dummy cells 640 are also included in the integrated circuit, and are used to generate the reference voltage used by the sense amplifier in block 606, so that ΪΐΪί11 in block 6〇6 causes the transfer cage to be in the domain memory _ _ The voltage of the actual memory cell changes. The data is supplied to line 611 by the input/output 积 on the integrated circuit, or by other internal/external resources of the integrated circuit, 1 = ^ data input, _. The data is supplied to the input/output port on the integrated circuit by the sense output line 612 in the request. In the integrated circuit. These resources contain the /= pressure 6 = generated or provided by the block _ to generate or provide the lion record timing 嶋 mechanism power;; =: ^ can be used in the example, the implementation of the example, to implement - computer program and control device ς =, can, - the integrated circuit, the device is made up of special purpose logic circuit and general ^ in the embodiment, the control is shown in the figure, the figure shown in Figure 5 Combined. Although not made by the film _ other components. Therefore, ' _ electric ^ can include a representative example of a single crystal integrated circuit. ', ', g 3 圮 memory or other functional circuits, although the present invention has not been limited to its detailed (four) (four) 容 ' 彳 加以 然 然 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本 本, ^ and modified styles have been thought of by the previous people. In particular, the ^= pattern will be familiar to the skill of the art. I have the component of the present invention 201248647 ^Achieve the same result as the invention ff, all of which are attached to the present invention [simplified description] The invention is based on the scope of the patent application + features, and the embodiment, which will be described in the section of j ° and other purposes, wherein the conjugate mode is matched with the drawing, and the first figure shows a system on the 恃 * ** A two-stage bias circuit of a voltage circuit, FIG. 2 includes a two-stage bias sequence diagram for a data-line circuit-to-stack-based voltage regulation configuration. FIG. 3 shows a bias circuit including the second embodiment. Figure 4, when a memory circuit is shown, shows a sensing node electrical map of the present invention using a voltage-varying-memory sensing voltage. 5 - shows a simplified schematic of an integrated circuit according to the present invention - an embodiment of the main component symbol description 100 to 102: memory cell ~ 105: piezoelectric crystal 106 to 108: load transistor 109 to 111: sense amplifier 120 to 122: precharge transistor 130: two-stage voltage regulation bias circuit 4〇9: resistance element 42〇: reverse or gate 15 201248647 600: memory array (flash memory) 601: column decoder 602: word Line 603: Row Decoder 604: Bit Line 605: Bus 606: Sense Amplifier/Data Entry Structure 609: Read, Erase, and Stylize State Mechanism 608: Read, Erase, and Stylize Supply Voltage 611 Data input line 612: data output line 623: pressure/bias structure 624: two-stage voltage regulation bias circuit 633: pre-charge structure 640: dummy reference memory cell 16