TW201245948A - Decentralized power management distributed among multiple processor cores - Google Patents

Abstract

A multi-core processor provides a configurable resource shared by two or more cores, wherein configurations of the resource affect the power, speed, or efficiency with which the cores sharing the resource are able to operate. Internal core power state management logic configures each core to participate in a de-centralized inter-core power state discovery process to discover a composite target power state for the shared resource that is a most restrictive or power-conserving state that will not interfere with any of the corresponding target power states of each core sharing the resource. The internal core power state management logic determines whether the core is a master core authorized to configure the resource, and if so, configures that resource in the discovered composite power state. The de-centralized power state discovery process is carried out between the cores on sideband, non-system bus wires, without the assistance of centralized non-core logic. A multi-core processor including microcode distributed in each core enabling each core to participate in a de-centralized inter-core state discovery process is also disclosed.

Description

201245948 VI. INSTRUCTIONS: [References to Related Applications] The priority of this application is based on the US Patent Provisional Application, Case No.: 61/426, 47〇 'Application Date: 12/22/2010 'Name For the multi-core bypass bus (MULTI_C0RE INTERNAL BYPASS BUS), the case as a whole is included in this case. This application has the same filing date as the following US patent applications in the same application, and each application is incorporated into the case as a whole. Case Number TB Name TBD (CNTR.2503) 12/22/2010 Multi-Core Microprocessor Internal Bypass Bus TBD (CNTR.2527) 12/22/2010 Multi-Processor Core Decentralized Power Management Distributed Multiple Processor Cores TBD (CNTR.2528) 12/22/2010 Improved Reticle Set Modification to Producer Multi-core Dies TBD 12/22/2010 Multi-Core Micro Dynamic Configuration of the Processor 4 201245948 (CNTR.2533 ) Discovery Method Dynamic Multiple-Core Microprocessor Configuration Discovery TBD (CNTR.2534) 12/22/2010 Distributed Management of Shared Power for Multi-Core Microprocessors Distributed Management of a Shared Power Source to a Multi-Core Microprocessor TBD (CNTR.2536) 12/22/2010 Dynamically and selectively disables the core and resets a multi-core microprocessor. Dynamic and Selective Core Disablement and Reconfiguration in a Multi-Core Processor TECHNICAL FIELD OF THE INVENTION The present invention relates to multi-core microprocessing The field of device design, and in particular the management and implementation of multi-core domains (d〇main) for multi-core specific operations and multi-core processors. [Prior Art] Mouth. The main way in which modern microprocessors reduce their power consumption is to reduce the frequency and/or voltage of the micro _ 卞乍f. In addition, in some instances, the microprocessor may disable the private portion of portions of its circuitry. Finally, in some examples 201245948, the microprocessor may remove power from multiple parts of its circuitry. Furthermore, sometimes microprocessing n requires spike performance that requires operation at its highest voltage and frequency. The microprocessor takes power management actions to control the voltage and frequency levels of the microprocessor as well as the clock and power disable. Basically, the microprocessor should take the power management action from the direction of the operating system. The well-known χ86娜姐 "Let the system be a kind of simplification, implementation, and requirements to enter the person - an example of the optimal state related to the actual situation." The operation can use this state to perform advanced power supply. The optimalized cancer may be in the sleep or idle state. The well-known advanced configuration power interface (ACPI) specification is defined by the state of the defined operation or power management (eg "(:_) "Status" and "p•status") are convenient for operating system-directed power management. Because most modern processing systems are multi-core processing, many of the processing cores share one power supply. Management phase_resources, so the implementation of the power supply: The action is complex. For example, 'multiple cores may turn the voltage source and/or the clock source. Furthermore, the computing system containing the multi-core processor also basically contains— A chipset that includes a plurality of bridges that bridge the processor busbars to other busbars of the system (eg, to the peripheral I/O busbars), and includes one as a multicore processor plaque Interface memory The controller. The chipset can closely participate in various power management actions' and may require a mechanism between itself and the multi-core processor. More specifically, in a (four) system, with the permission of the multi-core processor, the chipset May be disabled - the clock signal on the processor bus, the processor receives and uses the money of the (10) day of the money card. In the case of the multi-core 201245948 processor, you The core of the bus that uses the busbar must be prepared to allow the chipset to disable its busbar clock. Also, until all the cores are ready, the chipset is allowed to block the bustling clock. In the shape of a sling, the chipset will snoop the processor's bus bar. It is a hidden body. For example, when a peripheral display is placed on a peripheral bus, it has a hidden access. The group will transfer this memory access to the processor sink. This allows the processing of the Snapshot Cache (4) to determine whether it holds the (_) peek address. For example, everyone Knowing that the device will periodically poll the body position to process the current limit Producing a tumultuous snoop cycle (sn〇〇p cycle) In some systems, a multi-core processor may enter a deep sleep state, which will clear the contents of its cache memory and disable the clock signal for the test. Save power. In this case, for multi-core processors, in order to respond to the sneak peeks on the processor bus (they are pure, the money will not return the hit ((8) message) Being quilted and then going back to sleep is undoubtedly a kind of wave, so the chipset can be authorized not to generate a snoop loop on the processing bus to achieve additional power savings, while reading and processing H. However, it must be reminded again.岐 '财 _ heart will be ready for the ^ group to find off the snooping function, that is, the crystal version of the _ ship, in addition to the nucleus (four) ready to go. U.S. Patent No. 451,333, issued to et al. (hereinafter referred to as Naveh), discloses a multi-core micro-processing crying containing multiple processing cores, each of which can be turned into an idle state command. . Multi-core 7 201245948 also includes Hardware Coordination Logic (HCL), which receives status from core inter-state and manages core power consumption based on command and core idle status. More specifically, the HCL decides whether all cores have detected a command that requires a transition to a common state. If not, the HCL selects the shallowest state (shall〇west) in the idle state of the command as the inter-core state. However, if ^^^ detects a command that requires conversion to a common state, the HCL can initiate a common power saving feature, such as perf〇rmance state reducti〇n, a shared phase-locked loop. (PLL) is turned off, or the processor is executed; the brother saves. Sinking can also prevent the external bfak event from reaching the core to make the dissidents look like a common state. In addition, the HCL can implement a handshake sequence with the chipset (handshake townships to turn the core into a common state. In the paper by Alon Naveh et al., the name is " Power in Intel Core Core Processors and Thermal management (P〇wer and Thermal Manag嶋t out of this Intel Core Duo Processor) "" published in the Intel Science and Technology Journal towel issued May 15, 2002, Naveh et al. - Viewing on the wafer or The compatible c_state control structure in the shared area of the platform is not like the hardware coordination logic (HCL), as the synchronic source on the job, the chip and the platform. The required cpUU state, (iv) the state of the shared resource, her imitation-the traditional (iegaey) single-core processor chip group to achieve the C-state entry agreement. In the Naveh reference button, the muscle system is concentrated in Nuclear 201245948's non-core logic 'Asian generation has core operations for power management. However, this centralized non-core logic solution has its drawbacks, especially when the muscles are expected to be contained in the core phase. size It will be difficult to connect, especially for the architecture that wants to include more cores on the chip. This drawback will be more obvious. [Invention] In an embodiment of the present invention, a multi-core processing is provided. , which includes a plurality of entities _ (four) and in the core of each health towel, the micro-code 'core-to-core state aging code can be related to the process of participating-distributed core (four) power state, A distributed microcode implementation method for discovering the power state of a multi-core processor comprising at least two cores participating in a decentralized inter-core state discovery process. The inter-core state discovery process is via each The implementation of the microcode executed on the core and the combination of signals exchanged between the cores by bypassing the non-system bus communication wiring. The discovery process is not through any centralized non-core logic. In addition, in most embodiments The inter-core state discovery process is implemented in accordance with an appropriate or selected hierarchical coordination system using chain-locked inter-core communication. The inter-core state discovery process provides a microprocessor configuration that includes the utilization and distribution of resources that cause core boot and how many cores are started, and the hierarchical coordination of systems and systems, including domain and domain masters. 201245948 In another aspect of the present invention, a multi-core processor is provided, a dynamic processing core and a transmission and sharing rate shared by two or more cores are provided for the parent core. In other words, the processor further includes setting the internal core power state management logic of each of the cores to participate in the core: a kind of decentralized nuclear-powered state discovery, which is assisted by Chinese non-core logic. In order to set the shared resource

The target power state is determined by the branching of the W H / 电 电 电 电 电 的 的 的 电 电 电 电 电 电 电 电 电 电 , , 内部 内部 内部 内部 内部 内部 内部 内部 内部 内部 内部 内部 内部 内部 内部 内部 内部 内部 内部 内部 内部 内部 内部 内部 内部 内部For shared resources, the composite target power: two; 实 power state of the real state, it will not interfere with the sharing of resources is considered to be the most energy-efficient power state. ’, any corresponding target power management of the parent core =:::rr—the kind of power supply. The power state definition will affect the shared power state, where the target degree or effect (4) is the source domain. Nuclear = the power supply of its lining operation, the speed of its inclusion does not pass through any 隼 式 非 non-nuclear, ^ power state discovery process, his core power status:: and the sharing of the resource at least one of its composite target The power supply secret is distributed: it is designated as the -Manager 2 core power state discovery process for the purpose of setting the configuration of the common source, and the core drive is used to set the composite of the configuration of the 201245948 resource. The implementation of the target power state. mouth. = Heart Sorrow' The present invention provides a multi-core processor. Multi-core: Rational: Each core contains power state management microcode to set the core group, and (10) decentralized and inter-composite power state discovery process. Power State Management: Micro 1 enables the parent core to read and receive requests for any of the predetermined power states (including - active operating states and one or more progressively less sensitive states) One of the goals is set to be its own configuration. When the core reception request is transformed into a restricted power state (for example, it will interfere with the power source of the other cores), then its power state management microcode starts: the distributed core inter-composite The process, _ decides whether all other affected, such as the power state of the _ has been prepared. If participating in the discovery of the difficult core to confirm that the restricted power is _ is the composite power state, then the authorized person in the core implements or activates the restricted_electrical state via the #power state management microcode. In particular, the drain core will implement the most restrictive or energy efficient operating state' which can be implemented by the core without interfering with the corresponding target operating states of other cores. In another embodiment, the core of each of the cores, the power management microcode, or the normal system is synchronized, and the group is designed to exchange power states with other nodes that are connected to each other. Information to determine the state of the hybrid power supply. Each invoked instance of the synchronization logic is designed to be at least conditionally connected to the core of the node that has not been synchronized (it is connected to the core of itself by the node, and one of the synchronization logics has not yet been synchronized Arouse the generation of the subordinate instance of the 201245948 synchronization logic as part of the composite Wei state. In the implementation of the financial, the nuclear source source is not required to enable its synchronization logic - the local instance can be achieved - the target power state, if the core target power state is not - need to be coordinated with other cores, Power state core ~. Otherwise, the 'power management logic sets the core's untargeted implementation state of the target power state or the non-limiting implementation of the power state (eg, local power save action on the core) and evokes one of its synchronization logics locally. For example, the power state that is restricted by the text should be closed. The maximum domain of the heart begins the composite power state discovery process. In the case of a composite power supply that is found to correspond to a target-restricted power state, it is authorized to implement one of the composite power states, core power management microcode startup (typically the manager core with the greatest impact range) and/or The implementation of the composite power state. In another embodiment, the present invention provides a method of decentralizing a management power supply for use with a multi-core processor, such as the processor described above. The method includes receiving a state transition request for any of the cores to set the configuration of the core ("local core,") according to a target power state. If the target power state is a restricted power state, then executing The power management logic on the local core implements a local instance of the synchronization logic to initiate a decentralized inter-core composite power state discovery process to allow this core to exchange power states with other cores. This method also includes evaluating the discovered power state' and Conditionally responding to the implementation or initiation of a restricted power state. Each local instance of the synchronization logic generates one or more slave instances of the synchronization logic on the connected core at one or more nodes, which are sequentially operated 201245948 As an additional slave instance to generate their synchronization logic. Each instance of the synchronization logic determines at least the state of the hybrid power supply, and recursively (unless by the termination condition, if any) in the synchronization logic Step by step (four) point on the far core of the core is more t-step (four) from (four) instance (four), Lang may be scaled Each of the cores has a synchronous synchronization of synchronization logic. When the composite power state is found to be equal to the restricted power state, the power management logic is executed on the -authorized core to start and/or be implemented. In the female aspect, the present invention provides microcode, which is encoded in a computer readable storage medium comprising a decentralized core and a physical core of the above-described Wei wei zhizhi processor. Illustrated is a system for coordinating, synchronizing, managing, and implementing power, sleep, or operational state on a multi-core processor by using intrinsic force-allocation logic that is replicated on each core. Embodiments of the method. Before describing each of the drawings of the detailed embodiments, a more general applicable concept of the present invention will be described below. I. Multilayer multi-core processor concept as used herein, one more A core processor typically represents a processor that contains multiple activated physical cores, each of which is designed to be extracted, decoded, and executed to follow an instruction set. In general, the multi-core processor is coupled to a 13 201245948 chipset by a system bus (which is ultimately shared by all cores), and is used by the turtles and the miscellaneous faces. In some embodiments t, (4) the busbar is the front-end busbar, which is the external interface from the disciplinary to the rest of the computer system. In some embodiments t, the chipset also uses the main memory for 4. The core and the common-off graphics control are centralized access. The core of the multi-core processing may be encapsulated in one or more chips containing multiple cores, as described in the paragraph _26 of the application, the filing date For 2010] February 22, the name is "Multi-CoreProcessorlnby Busy Bus" (Formal (n) rovisionai order request (CNTR25〇3), which is incorporated into the gray As suggested by the shot, a typical "was a wafer semiconductor wafer that has been domaind or cut into an early physical entity, and typically has at least a group of physical 1/〇妾 touch pads, for example, some dual cores. The wafer has two sets of I/O contacts, each for its Nuclear, mother - one use. Other dual core wafers have a single set of (10) contact turns that are flipped between their dual cores. Some of the squirts have two sets of W-contact 塾, 、, and 仏 two sets of dual-core each. Multiple configurations are possible. Furthermore, a multi-core processor may also provide a one-of-a-kind multi-chip. —The package|body" is a substrate on which the wafer is placed or mounted, and the package can be supplied with a single-group pin for connection to the domain board and associated handler bus. The substrate of the body contains wire nets or traces that connect the pads to the common pins of the package. Further layering levels are possible. For example, in the package and located An additional laminate (hereinafter referred to as ping 14 201245948 D (platform)) can be provided between the lower motherboards, and multiple packaging systems are provided on the platform. The platform can be-like the package described above. a substrate having a wiring network or wiring connecting the legs of each package. The core uses the above concept. In one embodiment, a multi-package processor can be regarded as / (4) 2 The package is disposed on a platform, each package has N1 wafers, and each wafer has N0 cores. The numbers N2, N1, and N0 are greater than or equal to and at least N2, N1, and N0 are greater than Or equal to 2. Π. Inter-core transmission structure such as The use of 'non-core but on-wafer hardware coordination logic (HCL) to achieve the requirements of inter-core coordination activities, including more complex, more asymmetrical and lower yield wafer designs And the scaling challenge (scalling anllenge) #代方式 is to use the crystal # group itself to perform all such coordination, but the XI way is likely to need to transfer between each core and the system bus on the system bus, so that Passing the appropriate value to the chipset. This coordination basically needs to be implemented via a system software such as the BIOS, but this approach is limited or impossible to control for the manufacturer. To overcome the two conventional methods Disadvantages, some embodiments of the present invention utilize bypass connections between the cores of the multi-core processors. These bypass connections are not connected to the physical pins of the package; therefore, they do not transmit signals to the outside of the package. Communication via them will also not require a corresponding transmission on the system bus. For example, as illustrated in CNTR.2503 'Each wafer may provide one in [3 核 nucleus] The bypass busbar between the cores, the bypass busbar is not connected to the physical connection of the chip to the 201245948 touchpad, so its sub-transmission is not transmitted (4) from the light core (9). The bypass busbar also provides the balance between the cores. Good, and can make the nuclear transfer or coordination without using the system bus. Multiple changes are also considered. For example, as explained in CNTR.25G3 - the needle '- kinds of four core chips may provide - two in two a set of bypass busbars between the two cores. Alternatively, as described in an embodiment, a four core chip may provide a bypass bus between each of the two cores of the chip, and An additional bypass busbar is provided between the two selected cores. In another embodiment, a quad core wafer may be provided with a bypass bus between the cores of each of the cores (four) as described in Figure 16 below. Moreover, in another embodiment, a quad core chip may provide pure convergence between the first and second cores, the second core and the third core, the third and fourth cores, and the core (four) between the first and the thin The row does not need to provide a core, inter-bypass busbar between the first and third cores or between the second and fourth cores. - face-like; f-path (even if the system is distributed between the cores on two dual-core wafers) is disclosed in the paragraph number 61/426, 47 of the application, the application is December 22, 2010 Named "Distributed Management of a Shared Power Source to a

Multi-Core Microprocessor ", and its non-provisional application (CNTR 2534), which is also filed concurrently, is hereby incorporated by reference. Moreover, the present invention contemplates a less extensive inter-core communication wiring set than the bypass busbar of CNTR.2503, such as the alternative example illustrated in the paragraphs of application Serial No. 61/426, 47, Shen Qingyi December 22, 2010, the name "Photomask is set to change to produce multi-core chips (Reticle Set Modification to pr〇ciUce 16 201245948

Multi-CoreDies)", and its non-provisional (n〇npr〇visi〇nai) application (CNTR.2528) are also incorporated herein by reference. One of the communication wiring between the cores is not a huge liver CNTR.2^4, Green Lin field reference. The core communication wiring group should be as small as possible in terms of the number of wirings included, as long as it can be used to initiate coordinated activities as described herein. The inter-core communication wiring built between the cores may also be designed or arranged between the cores in a manner similar to the following (9) communication lines. Furthermore, the '-package may provide an inter-chip communication line between the blocks - and the platform may provide an inter-package communication line between the seals (4) of the platform. As will be more fully explained below, the implementation of the inter-communication line may require at least one external output contact pad on each wafer. The implementation of the inter-county communication line may require on each side of the body. At least - the extra entity outputs the contact pads. Again, as further advanced, some embodiments provide a (four) output test that exceeds - a minimum number of output contacts to provide a larger Resilience. In order to allow all kinds of possible nuclear communication to be implemented, it is better that they do not need any core external active logic (on e & (4). Thus, various embodiments of the present invention can be used through non-core Rainbow or other active non-core logic provides the advantages of the invention as described herein in a coordinated core d implementation. 阶层. Hierarchical concept re-personality' The description of the invention is not limited unless otherwise specified In the multi-core multi-processing H, several real-times, which provide bypass through-line and through the system bus, lie in the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The implementation of the financial, (4) entity implementation and the hierarchical coordination system to coordinate the implementation of the hardware coordination of the f. Some of the hierarchical associations described here are very complex. For example, Figure 2, u, ^, 14, 15, 16, 18, 19, 20, 2! and 22 describe multi-core administrative embodiments of various hierarchical coordination systems that are structured to facilitate inter-core coordination activities such as power state management. This manual also provides several examples of a more in-depth and poetic (4) characterization of hierarchical associations, and even more detailed and complex hierarchical coordination systems. S1 is used to initiate-construct or close activities. Before describing the specific examples of the inter-core coordination process, it is beneficial to describe the various implementations of the various hierarchical coordination systems that have been examined here. As used herein, the -layer protocol (10)' a system for the coordination of certain appropriate or pre-emptive or purpose's in a hierarchical manner that is at least partially restricted or organized. This architecture is an equal peer-to-peer ) Coordination system has a district Because each of these cores has the same privileges and can coordinate directly with any other core (and with the chipset) to perform an appropriate activity. For example, the core of the node tree architecture is limited in certain Under the activity, only the upper or lower node connection core is coordinated, and only one single path exists between any two nodes, so the node tree architecture can form a strict hierarchical coordination system. Unless defined more rigorously, a hierarchical coordination system also includes a loosely hierarchical hierarchical coordination system, such as a system that allows point-to-point coordination within the core of at least one group, which is tied to at least two core groups. Hierarchical coordination between groups. This presents an example of both the rigorous and loosely ordered 201245948 layered coordination system. In one embodiment, a hierarchical coordination system corresponds to one of the cores in a microprocessor, the microprocessor has a plurality of packages, each package has multiple/wafers, and each wafer has multiple core. It is useful to treat each layer as a "domain". For example, a dual-core dual-core package that can be considered to be composed of its core can be considered to be composed of; the domain, and the package platform or microprocessor can be considered It is also useful for the package to consist of a particle that nucleates itself into a domain. In this way, the concept of "domain" is related to, for example, - cache, - voltage source or - the source of the clock - the dragon is also related. This resource is overturned by the domain - but this resource is otherwise The method records the near end of the domain (ie, 'not shared by the external core of the domain). Of course, the depth of the domain suitable for any given nucleus and the number of components of each domain (for example, 曰曰; UT' is - domain 'encapsulation system is - domain', etc.) can be based on the core The number, our knives, and various resources are changed and enlarged or reduced in a way that is shared by the core. Naming the ride between different types of fields is also useful. As used herein, all activated physical core systems on a multi-core wafer are considered to be the "C_tituents" of the wafer, and each other, and the constituents ((4). Her ^. The same All activated physical U-systems on the 'multi-chip package' are considered to be the same as the package and the other components. In addition, all the entities in the multi-package are activated as above. Be regarded as the constituent of the processor and the members of each other. Again, this way may extend to

S 19 201245948 has the same level of domain depth as multi-core processors. In general, each non-terminal domain layer is defined by one or more constituents, each of which contains a lower domain level below the hierarchical structure. In the case of the core processing, for each multi-core domain (for example, for each wafer, for each package, for each platform, etc.), the only core system is designated as There is also a function to check or coordinate the role for one of the "masters" used by the domain. For example, a single core (if any) of each multi-core wafer is designated as one of the wafers, and the wafer manager ", a single core of each package is designated as one of the packages" The package manager "(pM> and (for such a layer-processor) a single core system for each platform is designated as the "platform manager" for the platform, etc. - in general, The top-level manager core of this class is the only "bus service processor core of the multi-core processor, of which only the BSP is authorized to coordinate certain types of activities with the chipset. We can note that Convenience, in this _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ In each of the cores and cores, the target axis is called (for its mark), the core 2::=:,, the pair of _1 ==: the chip manager crystal (10) of the seed chip. In other words, the fine of the same day is regarded as any one of the other cores of the _^4, A core system is regarded as a partner. In the description of the substitution characteristics, Xia Qianren, the partner 20 201245948 designation system is reduced to the "affiliation between the tubes. This kind of _ sex == other core crystal moon management of the heart chip The core will have three gangs to a four-core chip, only with a grass-partner (wafer manager core). The mother of one will be treated as the other manager (_y)"-hi The core of the shore may be regarded as a "companion", a body of the body, a core of the manager, and a core of the second is regarded as - but in the case of - replacement, he manages _ _ _ (4) The package is a four-part series. This alternative feature description is applied to the species: the chip package, the core will have three partners, and the conversion will be only a single partner (four) nuclear and another kind of In the FIG. 11), for each of its cores in the processor (including the management core W on a different dragon body of the processor), a manager core system is regarded as a "companion" , '. Seven to the next domain level (for example, with this depth - a multi-core processor level ), for each of the other PM cores of the platform, the coffee (or platform manager (maSter)) core is considered a "chum". - Generally speaking, for each PM core of the same platform, each A PM core system is about - friends. But in the 1st generation, you can hide the towel, so you can decide on the ___ of the other cores of the Bsp dragon body manager and the platform. Apply this feature description to - Kawasaki is expected to have three materials, but each of the other 21 201245948 PM cores will be considered to have only a single partner (8) p). The above-mentioned partner/companion/friend relationship is generally regarded as a "same attribute" relationship. Each, • Partner " core belongs to a group of the same attribute, each "companion" core belongs to the same attribute group of the higher level, and each π-friend m core belongs to the same attribute group of the higher level In other words, the various domain definitions of the hierarchical coordination system described above correspond to the "same attribute" group (for example, a group of one or more groups of partners and a group of friends). In addition, each of the "partners" of the specific core and the ||friends|, the core (if any) can be more regarded as the family (five) 丨' core. As used here, the same attribute group The concept of a group is slightly different from the concept of a domain. As mentioned above, a domain is composed of all the cores in its domain. For example, the -package domain-(d) consists of all the cores on the package. In contrast, the same attribute group is generally composed of the core selected by the corresponding domain. For example, the corresponding attribute group of a package domain is only the manager core on the package (and one of them is also The package manager is composed of, instead of any partner cores on the package. In general, only the terminal multi-core domain (that is, the domain without the constituent domain) will be defined - one containing all cores. The same attribute group. For example, - dual core; - will define - terminal multi-core domain, which has a pair of wafers and two cores of the play attribute battle. I pay attention to each of the H-shirts are included in their own Near-end itself and not in other batches The resource 'can be set by various operations (4). We will understand that in the above-mentioned partner/companion/friend level, any non-manager core 22 201245948 is a - partner and belongs to only _ day The single-same attribute group formed by the core of the daily film. Each chip manager core, the first, belongs to the lowest level of the same attribute group composed of the partner cores on the same wafer; the second, belongs to the same: The companion core on the package consists of the same attribute group. Each block manager, the core 'the-' belongs to the partner of the _ day and day 0, such as Shuncheng, the lowest level with the same attribute group; 'Belongs to the same attribute group that is touched by the peer core on the same package; and third, belongs to the same attribute group composed of the friend cores on the same platform. In short, 'each core belongs to the same attribute Group, where w equals the number of the same attribute group (the core is a manager core) plus!. ^ In order to further rescue the hierarchical nature of the same attribute group, any ::::: Low-level multicore In the case of a case, regardless of a specific:, the film manager specifies the core 'its most direct same attribute group contains its group, which is contained in the same - close to the same attribute. The core companion. mi: the core of the rationale will also have a one-third close to the same pair of crying, strong, and the other) will be semi-exclusive. That is, there is a core. 5 'There is no established group of the same attribute that will contain the above-mentioned concept of the same attribute group of the processor. Even further, the different coordination model 23 201245948 and the secret ambiguity will be fined between its domain private. For example, in this case, in the same attribute group, the direct coordination between the cores is limited to the coordination of the core of the manager and the core of the controller. (10) The core of the theologians cannot directly coordinate with each other, and can only be indirectly through the core of the manager. In the peer cooperation (peer_e. brain. on e) "with the attribute group t, in contrast, any two sides of the 'closed group may directly agree with each other * without the arbitration of the core of the official. In the group, the = manager's kind-competitive term will be "delegation" because it is a coordinator of the week~, in order to coordinate with the higher-level domain, not for the same organization _ _ tune. My face is that this domain is in the "" manager's secondary activities (10) sex group has 4 meanings. - Generally speaking, for some predetermined members into the core can only be It is 5 weeks for the members or common groups of the same attribute group, and for the same attribute group arbitrated by any manager, only the preferred "common component" or poorer component can be applied. The point of view of the connection between the node and the node is also appropriate. 〃 The white layer is the multi-core processing private button, and the 阶层 point hierarchy is the core of each node. The system is root =: 2 one, one of them Core (such as Na Tune) path, (including the middle door:! There is a - between the nodes Continued coordination, to at least another / point, if appropriate.) Each node is connected to the activity used - the destination node and not all other nodes, and only for the coordination system, only Coordination with the "node-connected" core. In order to go further - step 24 201245948 area = some node connection 'here will be, the core _ _ ground _ core, or as a subsidiary family, 'nuclear ~ 'Ming 'If the system is connected to the core of the core node, the core of the constituents, the difference between the ugly and the core of the constituents is the core that is not attached to the node itself. More: One point and the bottom of the heart The Yang Shi nu and its fine-grained core of any Saki class (for example, H is coordinating with the same attribute group 'core system is part--). It is also a family member of the 观 、, (10) or "terminal" As far as the eyesight is concerned, '卩$ layered coordination Wei has clearly explained the different nesting configurations of these domains to the charm core (for example, the domain of the body does not correspond to each suitable," day, package And the platform). For example, the map does not The entity of the core of the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ However, it is consistent with the real-world coordination of the package core. 'Bypass wiring definition-corresponding three levels of hierarchy: === 友封封者, related as the same 3 and related as the partner's chip core However, according to the core doubling line of a processor (such as the butterfly), the ♦, 靡 and 咖 bypass settings are established, and the core system may be installed between the processing and the ringing system. In terms of nested entity configuration, it has 25 201245948 with different depths and layers, and several such examples are set in (4), Μ, Μ, and ^. Figure 1 shows an eight-core processor with two packages, each of which has two ", and each wafer has a _ core. In Figure n, a second-order hierarchical __ multi-link wiring is set.核心 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财 财It has four cores of "double core". In Fig. 14, = the desired lobes, and the red tiers of the three layers of 靖 细. Figure 15 shows a processor with two quad-core chips, where the wiring between the cores of each =b曰=-the second-order hierarchical coordination line, and at each L ratio= (ie, buddy) A plurality of inter-wafer wirings are provided as a coordination of the first level. Figure 21 shows a similar package 22 with two asymmetric packages, where the asymmetric package has three dual cores and the other has a single dual core wafer. However, as shown in Figure 11, the inter-wafer system, '^ Μ bypass wiring system is provided to assist the second-order hierarchical coordination between the cores. All the manager core systems of the two seals are the same homogeneous group, 'I part . Hope to be accepted. The hierarchical coordination system of different depths and coordination models can be applied according to the period of time. If it is suitable for providing the distribution of the common (four) source as the multi-core processing 11, the construction ability and limit of the multi-core processor are consistent with the limit. if. ☆ More in-depth chipset Set up enough bypass communication wiring to assist the processor of the peer coordination model of all cores of each quad-core. However, in Figure 26 201245948, the core is created for the core of each ton of heart chips: =, as shown in Figure 15, there are two groups (four) with the same attribute group - multi-level coordination level, if needed It can also be established for the core of the core microprocessor of Figure 16 by using (in order to coordinate the activities applied by the system) less than all of the core W wiring that can be passed. Since each of the quad core chips in Figure 6 provides bypass wiring between each of its cores, the wafers are capable of assisting all three types of hierarchical coordination. In general, 'regardless of the domain, the singularity group, and the multi-core △, the nature and number of processing H nodes', only the only core in each domain can be designated as the domain and the management of the corresponding >1 sex group By. The domain may have a constituent domain, and then each domain and only one core of the corresponding homogeneous group will be designated as the administrator of the domain. The most advanced core of the coordination system is also called a "root node n 〇 IV. Power State Management After introducing various concepts about multi-core configuration, bypass communication capabilities, and hierarchical relationships, this manual now describes power state management. Certain concepts of particular contemplated embodiments of the system. However, it should be understood that the present invention is applicable to the coordination of diverse activities other than power state management. In the distributed multi-core power management embodiment described herein, 'Each core of a multi-core processor includes decentralized and distributed meterable power management logic' that replicates in one or more microcode resident routines on each core. Power management logic is operable to receive a target The power state determines whether it is a restricted power supply state, and initiates a composite power state discovery process that includes coordination between cores and reacts appropriately. In general, a target state is any demand or desired schedule. One of the operational states (such as c-state, P_state, voltage ID (VID) value, or clock ratio value) In general, the operational state definition of a predetermined group includes multiple processor operational states 'based on one or more power, electrical grind, frequency, performance, operation, responsiveness, shared resources, or restricted implementation features. Relative to - processing: other desired (four) depends, the operating state can provide the most money to manage the power. In the example, the predetermined operating state includes a valid operating state (such as (3) state) and multiple progressive The ground is less effective or sensitive (4) (for example, Ch C2, 〇 〇 )). As such, (4) '- progressively less sensitive or effective state indicates a saving relative to a more efficient or sensitive state. Or operational state, or relatively less sensitive (eg, slower, less fully activated, unable to perform, for example, access, such as caching memory resources, or easier to sleep, and more difficult to wake up). In some embodiments, Based on derived or compatible with ACPI specifications, the predetermined operational state constitutes, but is not limited to, the C. state or the dormant secret. In other implementations, the operational state of the service constitutes or contains various voltages and frequencies. State (eg, progressively lower voltage and/or lower frequency state) 'or both. Again' a set of predetermined operational states may include (or consist of) a variety of programmable configurations, such as forcing instructions The program sequence is called to force the parent time cycle to only issue one command, only format=instruction per clock cycle, only convert a single microinstruction per clock cycle, and only retire the order per clock cycle—instruction, and/or tree column Form access to various cache memories, such as the technology of 28 201245948 5 children in the United States application number 61/469, 515 'applications for March 30, 2011, the name is "reduced instructions per clock operation Running State Power Saving Via Reduced Instructions Per Clock, Operation I (CNTR.2550), which is incorporated herein by reference. ···, as we understand, the microprocessor may be configured according to different, and independent or partially independent sets of operational states. Various operational configurations that affect power consumption, performance, and/or responsiveness can be divided into different levels of power states, each level can be implemented independently based on the corresponding hierarchical association (4), *each (10) has its Its own independently defined domain, domain manager and coordinating model of the same attribute group. Generally speaking, the level of a predetermined operational state can be divided into at least two categories: (1) the main local operational state (pred (10) (five) qing 叩 叩 〜 ~ her s), its Qi _ cake core resources, or in general In practice, 'mainly affects only the performance of a particular core; and (2) the restricted operating state (restncted 〇perating states), which will impact one or more resources shared by other cores' or in the actual application τ, It is relatively more likely to interfere with other cores. The state of knowledge of the common source is related to the relatively large possibility of interference with the power, performance, efficiency or responsiveness of the thin core sharing the resource. Near = red realization - in general (4) to coordinate with their miscellaneous, or to obtain the debt 1 Γ 歇 允许 allow. In contrast to the implementation of the restricted operating state, it is more important to coordinate and license with other cores. =Into the gram, the paste can be divided into (four) hierarchical class J How the various poor sources are shared and shared. For example, - first

S 29 201245948 The operational state may define the configuration of a local resource located in a core, a second set of operational states may be defined by a core of a chip but not located in the local resource configuration of the chip. The second set of operational states may be defined by a package. The configuration of resources shared by the core...etc. The implementation of an operational state requires coordination with and approval of the core of the shared resources under the operational state configuration of the application. In general, a composite operational state for any given domain is an extreme value (i.e., maximum or minimum) of the operational state of the application belonging to the core of each of the activated entities of the domain. The status of the job-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Or the operational state of the demand, the application operating state of the core is some preset value. The preset value may be zero (e.g., a condition in which the composite operational state is calculated to be the minimum value), a maximum value of the predetermined operational state (e.g., a condition in which the composite operational state is calculated as the maximum value), or an operational state of the core currently implemented. In an embodiment, a core application operating state is a power or operational state, such as a voltage ID (VID) or clock ratio value desired or required by the core. In the other-real complement, the “professional state” is the most recent valid c_ state that the core has received from the applied system software. In another embodiment, the application operational state of an entity core is the extreme value of the most recent still correct target or required operational state of the core (if any), and will affect the highest pie domain (if any). The most extreme operational state of the local resource for which the highest domain has the administrator credentials. Therefore, the overall operational state of the processor will appear to be the lowest value of all the startup entities of the processor. The composite power state of an enclosure will be the maximum or minimum value of the power state applied to the core of all the startup entities of the package. The composite power state of a wafer will be the maximum or minimum value of the active source state of all of the startup entities of the wafer. ~ Describes the implementation of the decentralized electric secret, the power management logic of each face, or the part of the Randy logic, which is designed to be at least conditionally connected to the other nodes ^ (ie, the same - Other cores of the same attribute group) ^Change the power supply to determine the status of the hybrid power supply. The hybrid power state is the value of the application power state corresponding to at least the node of the local simple step logic. In some non-essential situations, a simultaneous suspension calculation and a fine-hybrid power state will accurately correspond to the composite power state for an application domain. A wake-up instance of each side-step logic (inv〇ked test (10)) is designed to generate synchronization logic at least conditionally for cores 4 connected at points ii that have not yet been synchronized. The nodes of the same attribute group are connected to the core, and the nodes of the higher-level affinity group are continuously connected to the core (if any, to the core to which the synchronous logic instance belongs). The nodes that are not synchronized are connected to the core of the node, and the synchronization logic synchronization instance has not been implemented as part of a composite power state discovery process. , b, in each instance of the synchronization 26 series; see the process, will recursively to the remote core of the node that has not been synchronized, further step by step (at least conditionally) 5 series 彳A pervasive example, until every core of the potentially impact domain 31 201245948 potentially impact domain), there is an instance of synchronization logic synchronization being executed. In the discovery process for the composite power state of the applied domain, an instance of the power management logic executing on the core is authorized to initiate or execute the implementation of the composite power state for the domain, and can be activated. ability. μ V. DETAILED DESCRIPTION OF THE INVENTION Turning now to the particular embodiment shown in the figures. In one embodiment, each instance of the synchronization logic passes through a bypass rail or a bypass busbar (inter-core communication wiring 112, inter-chip communication wiring 118, and inter-package communication wiring 1133) different from the system bus and other cores. The synchronization of the logic on the example of the dragon's use of Xiang - a kind of decentralized distribution of money and electric riding. This allows the core to be physically placed on multiple wafers or in multiple packages = Lv error to potentially lower the wafer size and improve yield, and to provide the high degree of seamability of the core number of the wire towel, without the modern The contact pads and pin restrictions of the wafer and the package of the processor are affected. Referring now to the block diagram shown in FIG. 1, there is shown a practical implementation of a computer power line 1GG for distributed power supply between multiple processing cores in accordance with the present invention. The system includes a single chipset 114 that is moved to the multi-core microprocessor by -116. The multi-core microprocessor 102 package contains two dual core wafers 104, which are represented by wafer cassettes and wafers 1. The film is printed on one of the substrates of the package. The substrate comprises a wiring net (or simply referred to as ''wiring") or a face that connects the "1") to the pin of the package 32 201245948 102. The pins may be connected to other reasons Busbar 116. The substrate wiring also includes inter-wafer communication wiring 丨丨8 (discussed below) connected between the wafers 104 to facilitate communication between them. The rib implementation is distributed at the core of the township core (10). Decentralized power management of 106. Each dual core wafer 104 contains two processing cores 1 , 6 , which contain core 0 and core 1 , and wafer 1 contains core 2 and core 3. Each wafer has 1 - 4 The designated manager is responsible for the implementation. In the embodiment of the figure, the core and the system are the manager core 106' of the chip and the core 2 is the manager of the chip! The core 1〇6. In an embodiment 'Each core 106 contains a configuration fuse ((: 〇11£^11 plus 1〇11613), the manufacturer of the wafer 104 may blow the configuration fuse to indicate the core 〇6 which is the manager core of the wafer 104 In addition, the manufacturer of the wafer 1〇4 may blow off the configuration of the Hyun to each The cores 106 specify their instances, that is, which of the cores 1〇6 is core 0, core 1, core 2, or core 3. As described above, the terminology "partner" is not on the same wafer 104 and each other The core of communication is 1〇6; therefore, in this embodiment of Figure 〖, core 0 and core 为 are partners, while core 2 and core 3 are partners. The term "companion" is used in different chips. The manager core 106 on the 4th and communicating with each other; therefore, in the embodiment of Fig. 1, the core and core 2 are companions. In one embodiment, the even cores 106 are 1 per crystal. The manager core of 4. In one embodiment, the core system is labeled as a boot service processor (BSP) of the multi-core microprocessor 1200, which is separately authorized to coordinate with the chipset 114. These limiting activities include enabling the implementation of certain composite power bears. In one embodiment, the BSP core 106 notifies the chipset 114 and asks it to remove the U6 clock to reduce power consumption, and / or avoid creating a snooping week on the bus n6 The period, as discussed later in block 322 of Figure 3. In the case of a real palladium, the 'BSP system is the core 1〇6, and its bus bar requires the output system to be bound to the BREQ0 signal on the bus bar 116. The two cores 1〇6 within 104 communicate via the inter-core communication wiring 112 located inside the chip 104. More specifically, the inter-core communication wiring 112 allows the core and hall within the wafer 1()4. Interrupted with each other and communicated with each other to perform distributed power management between the cores 1 1G6 allocated for pure read processing. In one embodiment, the core and inter-communication wiring 112 includes parallel bus bars. In one embodiment, the inter-core communication wiring 112 is similar to that described in CNTR2528. Further, the core 106 communicates via the inter-chip communication wiring 118. More specifically, the inter-wafer communication wiring 118 allows the manager cores 106 on the individual wafers 104 to communicate with each other and transfer messages to each other to perform core (10) distributed power management distributed among the multi-core microprocessors. In the embodiment, the inter-wafer communication wiring 118 is executed at a clock rate of the bus bar 116. In one embodiment, 'core 1 〇 6 transmits 32-bit messages to each other. During transmission or broadcast, the cores 1-6 are arranged on a single wire of the inter-wafer communication wiring 118 during the bus cycle to indicate that it is about to transmit a message, and then on the next 31 bus cycles 116. A sequence of 31 bits is transmitted. At the end of the mother-to-wafer communication wiring η8 is a _ & bit shift register, which accumulates a single bit received to form a 32-bit message. In a real case, the 32-bit afl contains multiple information fields (fieid). An information interception uses the VI〇 value of one of the 7-bit requirements of 34 201245948, according to the VRM allocation management mechanism shared in CNTR.2534. Other information blocks contain messages about synchronization of power states (eg, C-states), such as c-state request values and acknowledgments, which are exchanged between cores 1-6, as discussed herein. In addition, a special message value causes a core 106 that transmits its value to interrupt a core 106 that receives its value. In the embodiment of Figure 1, each wafer 104 includes four contact pads 1 〇 8 that are respectively stalked to four pins (represented by "ΡΓ," P2 ", P3", and "P4"). With respect to the four contact pads 108, one of them is an output contact pad (indicated by 〃〇υτ") and the other three are input contact pads (indicated by IN 1, IN 2, and IN 3). The inter-wafer communication wiring 118 is the same as the following. The contact pad of the wafer 塾 and the contact pad of the chip J are coupled to the pin P1 via a single-wiring net; the contact of the crystal m ουτ with the 03 of the wafer 0 is coupled via a single „ghex wire mesh, connected to the connection Ankle 2; the IN 2 contact pad of the wafer 与 and the wafer 1 接触 3 contact pad is connected to the pin P3 via a single wiring network; and the IN 1 contact pad of the wafer 0 is in contact with the wafer, and is connected to the pin P4 via a single wiring _ In the embodiment, the core intestine is contained in each of the messages transmitted from the 〇υτ contact pad 108 to the inter-wafer communication wiring 118 (or the inter-package via line 1133 as illustrated in Figure u below). - Reward code. This identification code uniquely identifies the target core to which the message is scheduled to arrive, 1-6, which is useful in the embodiment described herein (where this message is broadcast up to $receiver core, 1Q6). In the embodiment, 'each wafer 104 is set according to the configuration that is blown during the manufacture of the multi-core microprocessor 1〇2, and the four contact pads are designated as the output contact pads (OUT). The manager of the chip 0 core ^ 0 wants to communicate with the manager of the 丨 核心 core 2 35 201245948 Transmitting the information on the OUT contact pad to the wafer contact pad; similarly, when the manager core 2 of the chip 1 wants to communicate with the manager core 0 of the chip G, it will be on its 0UT contact pad. The information is transmitted to the ^ 3 contact pads of the wafer. So, in the picture! In the embodiment, only one input contact pad 108 is required per wafer 1 4 instead of three. However, the advantage of fabricating the die 104 having three input contact pads 1 为其 8 is that it allows for the core multi-core microprocessor of Figure 1 and the eight-core multi-core microprocessor of Figure 9, for example. The same wafer 1 〇 4 in 2 was designed. Furthermore, in the embodiment of the figure, two pins ρ are not required. However, the advantage of making a wafer with four pins is that it allows the same quad core microprocessor 102 in Figure 1 to be designed as a single quad core microprocessor 1 2, for example as shown in FIG. The four-core microprocessor 11〇2 can be designed as an eight-core system Π00. However, as shown in the core yoke examples of Figures 12 and 14 to 16, it is contemplated to remove unused pins and contact pads 108 to reduce > contact 塾 and pin count as needed. In addition, for example, in the embodiment shown in FIGS. 19 and 2, as in the embodiment, the unused pins ρ - and 塾 1 〇 8 may be removed as needed to reduce the number of contacts and the number of pins. Or deployed for other purposes. In one embodiment, busbar 116 includes a number of signals that allow chipset 114 and multi-core microprocessor 102 to communicate via a busbar protocol similar to the well-known Pentium 4 busbar protocol. The bus bar 116 includes a bus clock signal provided by the chip set 114 to the multi-core microprocessor 102, and the core, 1 〇 6 uses it to generate an internal core "clock signal, the frequency of which is generally the bus block frequency. Ratio. Bus 116 ''匕έ STPCLK k (set by the chipset 1 μ)' to require the core 1 〇6 to allow the 2012 clock to remove the bus clock signal, that is, to allow the bus to be stopped. Signal. The multi-core microprocessor 102 performs an I/O read transfer on the bus 116 from a predetermined 1/〇 connection address (only one of the core offices executes it) to indicate that the chipset 114 can The STPCLK is set. As discussed below, the multiple cores 106 communicate with each other via the inter-core communication wiring m and the inter-chip communication wiring ι 8 to determine when the single-core 106 can perform a 1/〇 read transmission. In one embodiment, after the STpcLK is set in the wafer set 114, each core (10) issues a STOP GRANT message to the chipset 114; once each core ship has issued an S10P GRANT message, the chipset 114 can remove the busbars. Pulse. In another In one embodiment, the chipset m has a configuration option such that it only expects a single sT〇p G read message from the multi-core microprocessor 1〇2 before it removes the busbar clock. ® 2 is shown in detail, which details one of the typical examples of the core 106 of the present invention. According to one embodiment, the core rigid microstructure contains a function of single politics - super pure amount (King brewing heart), meaning The instruction execution pipeline - the instruction cache 202 caches the instruction extracted from the system memory (not shown). An instruction translation device 204 is subtracted to receive an instruction from the instruction cache (eg, an edge instruction set architecture instruction). A registration alias table (RAT) 212 receives the decoding microinstructions from the instruction decoder 204 and from the -microsequencer, and generates dependency information for the decoding microinstruction. The reservation station 214 is used to receive the information from the button. The decoding unit executes the decoding microinstruction and the dependency information. The executing unit 216 is configured to receive the decoding flip from the reservation station 214 and receive the instruction operand used for decoding the micro age. 37 201245948 .i From the nuclear ~1Q6 temporary Memory (such as general temporary storage n· and The read and writable module register (_238, and the __ to the execution unit block 222. - the retiring unit 2 丨 8 is wired to receive the & Let the wire be executed, and the structure of the wire will be mixed (4). The data is taken from the 222 system to the bus interface unit (BIU) 224, which is connected to the interface of the figure (10). (The call receives the bus clock signal from the bus bar 116 and generates a core clock signal 242 to the core, 106 various functional units. The rainbow 226 can be controlled via the execution unit 216, for example, disabled. Execution unit 2!6 receives - BSP indicator code and a manager indicator code 232, which respectively indicate whether the core office is the manager core of the chip collapse and the BSP core of the multi-core microprocessor 102. As noted above, the BSp# code entry and manager indicator code 232 may contain a programmable melt. In one embodiment, the clerk indicator code 228 and the manager indicator code 232 are stored in a special module register (10) phantom top. 'It is first fetched by the programmable melt value, but it may be written by software. It was updated to shun 238. Execution unit 216 also reads and writes control and status registers (CSR) 234 and 236 for communication with other cores. In particular, the core 1 〇 6 uses the CSR 236 for communicating with the core 106 on the same wafer via the inter-core communication wiring 112, and the core uses the CSR 234 for communicating with the 塾 108 via the inter-wafer communication wiring ns. The core 1〇6 on the wafer 1〇4 communicates as detailed below. The micro-sequencer 206 includes a micro-code memory 2〇7, which is designed to store the purpose of the main a-way 包含 包含 包含 包含 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 2012 The 〇 ) ) ) 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 6 (For example, the Nata instruction > that is, the instance of the "state transition instruction" is unique to the core 1G0, and the microcode system executed by the transition instruction instance is executed on the core 106. ^ = 062 = fine 'cause each shot __There is a user program from the instruction set architecture instruction. In addition to the core 106, the microprocessor may contain an auxiliary or service processor (not shown), which does not have The same instruction set architecture is the core 106. However, in the present invention, the core (10) itself (not an affiliate or service processor and not any other non-core logic component) executes the multiple processing cores allocated in the multi-core microprocessor 102. Decentralized power management Therefore, it is advantageous to provide more _ (size) capability, recombinability, yield characteristics, power supply reduction, and/or W real area reduction advantages. The power management logic microcode fine instruction is implemented in response to at least two conditions. First, the power management logic microcode 208 can be invoked to implement one of the core, one of the instructions of the instruction architecture. In one embodiment, Χ86 job order and m instruction, etc.;: in the microcode 208. That is, when the command decoder 2〇4 encounters -_娜八汀 or sink instruction, the instruction decoder 2〇4 stops extracting the currently executed The user program instruction, and the control is sent to the micro (four) H 2 〇 6 _ to extract the implementation of the power management logic microcode in the MWait or 39 201245948 command. Second, the power management logic microcode 208 may respond - interrupt The event is aroused. That is, when an interrupt event occurs, the core ~106 stops extracting the current user program instruction and transfers control to the microsequence $206 to begin extracting the power management logic microcode that controls the interrupt event. 208 Hanging. Interrupt events include architectural interrupts, exceptions, errors, or traps, as defined by the 指令86 instruction set architecture. An example of an interrupt event is one of the sinks 116 for the power supply tube __^ stomach The I/O read transmission detection. The interrupt event also contains non-architectural defined events. The non-architectural definition of the wipe-off event includes: inter-core communication wiring 118 via the diagram (eg Figure 5 The connection described in 6) sends a signal or through the inter-wafer cage of the diagram, the line 118 sends a signal (or via the inter-package communication wiring 1133 of FIG. u, the following discussion) core, interrupt Requirements (as illustrated in connection with Figures 5 and 6); and the side set or unset by one of the chipset STpcLK. In the implementation of the financial, f source management sugar microcode 208 years of age as the core touch microarchitecture instruction group instructions. In another embodiment, the microcodes are of different ages, which will be converted into instructions of the microarchitecture instruction set of the core. System 100 of Figure 1 performs distributed power management distributed between multiple processing cores 1-6. It is more clear that 1?i3t•’s each implements its local Wei management logic microcode 208 in response to the state transition requirement and transitions to the target power state. The target power state is required by any of a plurality of predetermined power states (e.g., C-state). The pre-power state includes a reference or active operating state (e.g., ACpi2 bear) and a plurality of progressively and relatively less sensitive states (e.g., ACn, c2, 201245948 C3, etc.). Referring now to FIG. 3, the flow chart of the present invention is shown in FIG. 3, which shows the operation of the system 100 of FIG. 1 in a decentralized manner in a multi-core microprocessor. Processing: Power supply management. Specifically, the flowchart shows one of the power management and logic microcodes 208.仏 · _ Knife work, in response to a MWAIT command 戍 令 令 缚 缚 缚 — — — — — — — — — — — — 新 新 新 新 新 新 新 新To be clearer, the part of the power supply 5 that is displayed in the ® 3 is the power management logic-state transition demand processing logic (STRHL) routine. ~ For the better understanding of Figure 3, the implementation of the MWAIT instruction and the C_state architecture is in the box. The MWAIT instruction can be included in the f__, for example, job d_, Lin_, Ma_) or 统 software. For example, if the system software knows the amount of work on the system, is low or forested, _, the record can be recorded - MWAIT age to allow core 106 to enter - low power state until an event (eg from one The interruption of the peripheral device is required to be served by the core 1〇6. Another example is that the software that is executed on the core 1-6 may share data with the software executed on the other core 1-6, so that, for example, when accessing the data shared by the two cores 106, for example, - the number (synchronized by s brewing; if the storage of another core 1 〇 6 jins is executed to the money U〇ret〇s嶋ph〇re) has passed a significant amount of time, then at the current core The software executed on 106 will cause the current core 1 to enter the low power state via the mwait command until the store signal is generated. The MWAIT Directive is described in detail in the IntdR 64 and iA々41 201245948 Architecture Software Developer's Manual (Architectures 3 Manual D (4) Manual) in Volume 2A: Volume 2A: Instruction Set Reference (A_M), pages 3_761 to 3_764. The monitoring (MONITOR) command is described in detail in the third document of the same document, the entire disclosure of which is incorporated herein by reference. MWAIT is ordered to specify the target c-state. According to an embodiment, c_state 0 is the -execution state, and c is greater than the c; the secret is the dormant state; and the c-state of the south is the stop state, in which the core 1〇6 is not extracted and executed. The instructions, while 2 and the souther C-state core 1〇6 may perform additional actions to reduce their power consumption, such as disabling their cache memory and reducing its power and/or frequency state. According to a real customs, the secret of 2 filaments is considered and pre-determined to become a restricted power state. In the 2 or higher state, the chipset ι 4 may remove the bus 116 clock, thereby effectively disabling the core 1Q6 clock to greatly reduce the power consumption by the core office. Regarding the higher c· state of each subsequent segment, the core 106 will be allowed to perform more aggressive power saving actions, and __ will take longer to return to the execution state. An example of a component that may cause the core to exit the low power state is a cap and a bribe to another specified address range (specified by the previously performed monitoring (M〇NIT〇R) instruction) ). Obviously, the AC-numbering mechanism for the C-state uses a higher c-number to indicate a progressively less sensitive, deeper sleep state. By using this numbering mechanism, the composite power supply of the group (ie, ", body, platform") will be the application c_state minimum of all the cores of the group. The minimum C-state minimum for each core is the most recent valid requirement c_state (if there are 42 201245948 words) = is zero (if the core does not have a valid recent request to apply the c_ state. However, other 敎The power state uses a progressively higher number to indicate a progressively more sensitive state. For example, CNTR.2534 illustrates a type of indication—desired electrical power, and a coordination system for a voltage identification horse (VID) to a voltage regulator module. The higher VID is higher for the drum, and the _ corresponds to the _ (and therefore more sensitive) performance state. However, the coordination-composite VID involves determining the maximum value of the core request because the source state numbering mechanism can be raised or The descending order is referred to as 'so the part of this specification defines the composite power state as “"extreme value", which is the minimum or maximum value of the application m嗤. However, I understand that even the second request VID in time The ratio value is changed to 3| knowing the direction of the annihilation" orderable n (for example, using a negative count from the original value); therefore, regardless of the direction of the traditional boundary, the description is based on the definition of the county. The hierarchical coordination system usually also applies to these power states. Although Figure 3 illustrates the embodiment, the response to the core of the towel 106-MWAIT refers to the implementation of distributed power management, but the core office may also respond to other forms of transmission. Core 1〇6 may enter a low power state. For example, the bus " 224 may generate a signal to detect the transmission of a 1/〇 item on the bus 116 to a predetermined one. In the range of ί/〇4, the core 1〇6 is used to perform the trapping (4) 208. Furthermore, the embodiment in which the core touches the other external letter 7 received and executes the microcode is also adopted by the present invention. Considered, and the embodiment is not limited to the x86 instruction set architecture embodiment or to the system embodiment including the one (four) type 4 processor bus. Further, the established target of the core 106 43 201245948 1 is hereby incorporated. Squatting The situation with the desired voltage and clock values appears. Now focus on the individual function blocks of Figure 3, the flow begins at block 3〇2. At block 302, the instruction decoder 204 of Figure 2 encounters _ Μ · ΙΤ instruction and enter p£3 spelling to execute the power s logic microcode 骂, and the STRHL routine that does not implement the instruction. The MWAIT instruction states that the target c_ state is represented by "X", and is in core 1 ()6 Waiting--the event is notified that it may enter an optimized state. Specifically, the optimized state may be a low power state in which the core 1〇6 will consume the MWAIT command than the core 106. Less power in the execution state. Flow continues to block 303. Microcode will store "X" as the core application or the most recent required power state, expressed as "Y." We can note that if Core 1〇6 has not yet encountered -MWAIT age, or if the target is It is expected that the age has been replaced or become stale (for example, by a later STPCLK release) and the core is in a normal execution state, then stored as the value of the core application or the most recent valid required power state "Y" The flow is continued to block 304. At block 304 'microcode 208 (more in detail STRHL routine) check "X" 'which is a value corresponding to one of the target c_states. If •'X" is less than 2 (ie, 'the target C_ state is 〇, the flow continues to block 3〇6; and, if the target C-state is greater than or equal to 2 (ie, "χ" corresponds to one The restricted power state is then passed to block 308. At block 306, the microcode 208 puts the core 106 to sleep. That is, the STRHL routine of the microcode 2〇8 writes the control register to the core 106. Internal 'used to stop extracting and execute instructions. Therefore, core 201245948 consumes less power than it is in the execution state. Best of all, when core 106 is sleeping, microsequence 206 is not extracted and executed. The code 2 〇 8 instruction. The flow ends at block 306. Figure 5 illustrates the operation of the core ι 6 in response to wake-up from sleep. Block 308 represents a path, which is "乂, which corresponds to 2 or more The operation performed by the STRHL routine of the microcode 208 in a limited power state. As noted above, in a consistent embodiment, one or more of the c. states involve removing the busbar 116 clock. 116 clocks are shared by the core 1〇6, so When a core has 2 high-targets (in the state), the preferred method is that the cores 1〇6 communicate with each other through the age-matched financial model to confirm that each core 106 has been notified. It may be converted to a C-state of 2 or greater prior to notifying the Crystal's group 114 (which may remove the busbar 116 clock). In block 308, the STRHL routine of the microcode 208 is based on the block 3〇2 The target C-state specified by the MWAIT age is encountered, and the associated power save action (PSA) is performed. In general, the psA & taken by the core 1〇6 contains actions independent of the other cores~106. For example, each core 1 〇 6 contains its own cache memory 'which is located near the core ship itself (eg, command cache and data cache 222), while psA includes refresh local cache, The clocks are removed and powered down. In another embodiment, the multi-core microprocessor may contain caches shared by the multiple cores 106. In this embodiment, the shared cache cannot. Being refreshed, their clocks removed, or powered down until the cores communicate with each other Decide that all cores 106 have been received to specify an appropriate target C-state - 45 201245948 MWAIT So far, in this case, they may be informing the chipset ιΐ4 that it can greedy the need to remove the busbar U6a and/or Suppressing the common caches, removing their clocks, and powering them off before allowing the snooping on the busbar 116 (see block 322). In the embodiment, the cores 1〇6 share a voltage. Regulator Module (VRM). CNTR.2534 illustrates the use of a distributed approach to managing the devices and methods shared by multiple cores. In one embodiment, the core 106 has its own PLL 226, as in the embodiment of FIG. 2, such that the core 106 can reduce its frequency or disable the PLL 226 to conserve power without affecting other cores 106. . However, in other embodiments, the core on a wafer 1〇4 may share a -PLL. CNTR.2534 describes an apparatus and method for managing a PLL shared by multiple cores using a distributed dispersion scheme. Embodiments of the power state management and associated synchronization logic described herein may also (or alternatively) be applied to manage the PLL ° flow shared by the multiple cores to a block using a distributed approach. 312. At block 312, the STRHL t-type call of the power state management microcode 2〇8 is represented by the syne_c state, the power state management microcode 208* (which is described in detail with respect to FIG. 4) for use with other Nodes connect core 106 to communicate and obtain a composite c_ state for multi-core microprocessor 1 , 2, which is represented by Z in FIG. Relative to the instance being executed on the core, each of the c_state routines is exemplified by the syne-c_state routine - 〃 local „ instance. The STRHL routine of the micro horse 208 evokes an input parameter Or detect (pr〇be) the power state value of the syncLC• state routine, the value of the probe money state is equal to the core of the 46 201245948 application power state (8) 卩, its most recent valid target power state), which is specially specified by the MWAIT directive Specify the value of τ received in block 302. Arouse the C-state routine to start a composite power state discovery process, as shown in Figure 4, which is further explained. • The parent is awakened sync — (:_ state routine calculates a "mix"c_ state and returns the "mixed π state to any program that calls or implements it (here is strhl). 1 "[Status is detected C The minimum value in the _ state value, and the detected & state value is the C-state of the application that is received by the wake-up program, executes the state routine on the core, and is triggered by the correlation with the sync_c-state routine. Example office The C-state value is received. In some cases, the mixed c_ state is related to the composite power state common to both the local SynC_C-state routine and the synchronized sync_c_state routine. Note that in other cases, the mixed state may be just one of the domains to locally synthesize the C-state.

- Generally speaking, a composite power supply of a domain is the extreme value of the power state of the application (the minimum value in the AOT power state mechanism). For example, - the synthesis C of the wafer 104, the state is the core of all of the wafers, applying the minimum value of the c_ state (e.g., the most recently required C-state, if all cores have such values). Overall, the multi-core microprocessor moves to the composite C state for all cores of the multi-core microprocessor 102 to receive the minimum value of the c_ state. However, the hybrid state may be a composite power state of the thief, or a partial composite state. - The partial composite power state will be the extreme value of the core application power states of the two application domains on 47 201245948. In some parts, this specification refers to a mixed power state that includes a "at least partially synthesized power state" to include any variation. The potential between a hybrid power state and a composite power state (even if it is subtle) The differences will become more apparent through the description of Figures 4C, 10 and 17. It is noted in advance that a non-zero composite c-state of one of the multi-core microprocessors 102 indicates that each core 106 has seen a non-executive The M_IT of the C_ state (i.e., C-like sadness with a value of work or greater), and the synthetic C-likeness of a zero value indicates that not every core 106 has seen MWAIT. Again, greater than or equal to The value table of 2 is not the core of all cores 102 of the core microprocessor 102 has received a larger C-state MWAIT instruction. The flow continues to decision block 314. In decision block 314, the microcode 2〇8 The STRHL routine checks the mixed c-state "z&quot; determined at block 312. If, z, is greater than or equal to 2, then flow continues to decision block 318. Otherwise, flow continues to block 316. At block 316, the STRHL routine of microcode 208 places core 1〇6 to sleep. The decision is made in decision block 318 'The STRHL routine of microcode 208 determines if core 1〇6 is a BSP. If yes, then flow continues to block 322; otherwise, the flow continues to block 324. At block 322 'BSP 106 notifies the chipset 114 it may be required to remove the busbar 116 clock and/or to inhibit the creation of a snooping shield ring on the busbar 116. 48 201245948 In the embodiment - the only authorized to allow under the well-known Pentium 4 busbar agreement The BSP age of the higher power management state will inform the chipset that it may request to remove the bus 116 by applying one of the 1/〇 reads on the initialization bus 116 to a predetermined ι/〇埠. And/or inhibiting the creation of a snoop cycle on the busbar 116. The chipset 114 then sets the stpclk signal on the busbar 116 to request removal of the busbar 116 clock. In one embodiment, at notification b曰After group 114 can set STPCLK at block 322 (or block 608), the STRHL routine of microcode 208 executing on BSP core 1 〇6 will wait for chipset i to set STPCLK instead of going to sleep state (in Block 324 or block 614), and then notify other cores 106 about the setting of the STPCLK to 'publish its STOP GRANT message, and then go to sleep. The predetermined I/O is specially based on the read transmission by 1/〇. The port group 114 can then inhibit the generation of a snoop cycle on the bus 116. Flow continues to block 324. At block 324, the microcode 208 places the core 106 in a sleep state. Flow ends at block 324. 4' a flow chart showing the operation of another component of the system of FIG. 1 'which performs distributed power management distributed among the multiple processing cores 1 - 6 of the multi-core microprocessor 1 。 2. More specifically That is, the flowchart shows the operation of one example of the Sync_C-state routine of the power state management microcode 208 of Figure 3 (and Figure 6). Although Figure 4 is a single example of the sync_c-state routine showing the microcode 208. Functional flow chart 'but We will understand below that it implements a synthetic C-state discovery process via multiple instances of this routine. The flow begins at block 4〇 4. 49 201245948 At block 402, a microcode 208 on a core 106 ( &quot;sync_C - One instance of the sync_C-state routine of the state micro mom 208") is woken up and receives an input probe C-state 'indicated by &quot;A" in FIG. An instance of the sync_C-state routine may be awakened from where the MWAIT instruction microcode 208 is executed, as explained in relation to Figure 3, in which case the sync_C-state routine forms an initial instance of the sync_C-state routine. . In addition, one instance of the sync_C-state routine may be generated by a synchronization request originating from one of the other cores (herein referred to as an externally generated synchronization requirement), in which case sync-C-like sorrow The routine constitutes a dependent instance of the sync_C-sense routine. In particular, when performing a local instance of one of the sync-c-state routines on the core connected to another node, it is possible to generate a local instance of the sync-C-state routine by transmitting an appropriate inter-core interrupt to the local core. . As explained in more detail with respect to Figure 6, an inter-core interrupt handling routine (ICIH) of the power state management microcode 208 will process the inter-core interrupts received by the node-connected cores 1-6. Flow continues to decision block 404. At decision block 404, if the instance of the sync c_state routine (ie, "local instance") is an initial instance, that is, if it is awakened from the MWAIT instruction microcode 208 of FIG. 3, the flow continues. To block 406. Otherwise, the local instance is generated by executing the external or local real-time of the sync-C state f-type on the node connected to the node, and the flow proceeds to decision block 432. The block 406 'Sync_C-state microcode 208 is generated by the CSR 236 of the programmed circle 2 to generate a "subordinate" at its core, and (4) the value of the "A" received at block 402 is transmitted to Its partner is used to interrupt the partner ^ This will require the partner 50 201245948 to calculate the current c-state and pass it back to the local core 1〇6, which will be explained in more detail below. The process continues to block. In the block, the sync-c_ state microcode is programmed (10) 236 to detect that the partner has returned a mixed c_ state to the core full, such as the silk 'cluster's hybrid (four) state, rhyme 4, (four), the table (d) Note that if the partner is in its most active execution state (_face 吆 _), then the value of &quot;B" will be zero. In one embodiment, the microcode latrine waits for the partner to respond in a loop. In the request made by the square, the loop is a pre-determined value to poll the CSR 236 for the side partner to have a mixed c_ state. In the case of the case towel, the loop contains - timeout If the timeout counter expires, the microcode 208 assumes that the partner core 1〇6 is no longer activated and can be used, does not include an application for the partner in any subsequent sync-C-state calculations or Assume that the state of the embarrassment, and subsequently did not attempt to communicate with the partner cores 1. In addition, in the communication with other core offices (that is, the companion core and the friend core), the microcodes are operated in a similar manner. Whether it is via the inter-core communication wiring 112 or the inter-chip communication wiring 118 (or The inter-worker communication wiring 1133) is in communication with another core 106. Flow continues to block 412. At block 412, the sync_c-state microcode 208 is the wafer 1〇4 to which the core 106 belongs, by calculating "A&quot; The minimum value of the "B" value is different from a mixed C-state and is represented by &quot;c&quot;. In a pair of core chips, c&quot; will necessarily be a composite C· state because the values of “&quot;a” and “B” indicate the C-like sense of application of all (two) cores on the wafer. 201245948 Flow continues Decision block 414. At decision block 414, if the "C&quot; value is less than 2' calculated at block 412 or the local core, hall is not the manager core 1-6, then flow continues to block 416. Otherwise, the C&quot; value is at least 2 and the local core 1〇6 is the manager core, and the flow continues to block 422. At block 416, the routine replies to the calling procedure that evokes (at this routine) at block 412 to calculate the &quot;c&quot; value. The flow ends at block 416. At block 422 'Sync_C-state microcode 208 by program CSR 234 of Figure 2 generates a dependent instance of the sync_C| state routine on its companion core for transmitting the "C" value calculated at block 412 to its companion and for interrupting the companion. This would require peer computing And return _ mixed c_ state, and provide its rewards such as ι〇6, as described in more detail below. At this point, it should be noted that the sync-C-state microcode 208 is not in the companion core. The slave instance of the sync_C-state routine is generated until it has determined the synthesis 0 of its own chip itself. In fact, all the sync-C-state routines of the day and month mentioned in this specification are The operation is performed according to a compatible nested domain access sequence. That is, each sync-C-state routine progressively and conditionally discovers the synthesized c_state, first in the lowest domain of which is a part (eg, a wafer). Start, then, if it is the domain The controller then proceeds to the next higher level domain in a nested manner (for example, the processor itself in the case of Figure 1). Figure 13, which is discussed later, will further show this search order, which The towel syneJ:H|t^ conditionally and progressively first discovers the core, the crystal _ state of the granules, and then searches for it as part of the encapsulation (if the core is also the manager of the wafer) Finally, the entire processor or system is accessed (if the core is also the BSP of the processor). The flow continues to block 424. At block 424, the sync_c-state microcode 208 programs the CSR 234 to detect that the companion has been transmitted back. A mixed c_ state is obtained and a mixed €_ state is obtained, which is indicated by "D&quot; in FIG. In some cases, &quot;D&quot;, in some cases, will not necessarily require all (as described below in relation to the value "L" in Figure C) to form a companion wafer synthesis C-state. . Flow continues to block 426. At block 426, the sync_C-state microcode 208 calculates a mixed state of the multi-core microprocessor 1〇2 by the minimum value of the &quot;C&quot; and &quot;D&quot; values, which is represented by Έ. "D" is the companion wafer synthesis c_ state, then, Ε, will constitute the synthetic C-state of the processor, because &quot;ΕΜ will be "C" (as mentioned above, we know the wafer The minimum value of the synthesized C-state) and &quot;D·, (companion wafer synthesis c_state), and no core on the processor is omitted from the calculation. If not, then &quot;E&quot; may constitute processing Only a portion of the synthesis state (ie, the minimum of the application c·state of the core and companion cores on this wafer, rather than the minimum of the application C-state of the companion partner) continues. Decision block 428. The constant &quot;E&quot; value calculated at block 426 is passed back to its caller at block 428. The flow ends at block 428. At decision block 432, if the inter-core interrupt processing routine of Figure 6 Wake up the sync_c_ state routine to respond to the core An interrupt (ie, a partner wakes up the routine), the flow continues to block 434. Otherwise, the inter-core interrupt handler routine wakes up the sync_C-like % routine to respond to an interrupt from the core companion (ie, The companion generates this routine, and the flow continues to block 466. 53 201245948 At block 434, the core]06 is interrupted by its partner, so the mouth-& state microcode 208 stylized CSR 236' is used by the partner and The detected C-state delivered by the generated routine is represented by nF&quot; in 圊 4. The flow continues to block phantom 6. At block 436, the sync_C-state microcode 208 is calculated by its own application c_state "Y" The minimum value of the "detected C-state" F" (received by its partner) is used to calculate a mixed C-state for its wafer 104 itself, the result of which is indicated by "G&quot;. In a dual core chip, the "G" will be the composite c_ state of the wafer 104 containing the core 106, because in that case, Ύ" and "F·' will be assigned to show the chip's wealth (two The core application C-state. Flow continues to decision block 438. At decision block 438, if the &quot;G&quot; value calculated at block 436 is less than 2 or the core 106 is not the manager core 1-6, the flow continues to block 442. Otherwise, if &quot;G&quot; is at least 2 and the core For the administrator core, the flow continues to block 446. At block 442', in response to an interrupt request from its partner core, the status microcode 208 stylizes the CSR 236 for transmitting the &quot;G&quot; value calculated at block 436 to its partner. Flow continues to block 444. At block 444, the sync_c-state microcode 208 returns the &quot;G&quot; value calculated at block 436 to the program that wakes it up. Flow ends at block 444. Block 446 'sync_C-state microcode 208 generates a dependent instance of the state-of-the-art state on its companion core by programming CSR 234 of FIG. 2 for the "G" calculated at block 436. The value is passed to its companion' and used to interrupt the companion. This will require the companion to calculate a mixed C-state and pass it back to this core; [〇6, which will be explained in more detail in 54 201245948. Flow continues to block 448. At block 448, the sync-C-state microcode 208 stylized the coffee 2 rectifies that the companion has passed back the mixed C-state to the core 1〇6 and obtains the mixed c_state, which is represented by 'Ή' in FIG. In at least some, but not all, cases (as described in the corresponding &quot;L&quot; corresponding to Figure 4C) &quot;H&quot; will constitute the composite state of the companion wafer. Flow continues to block 452. At block 452 'sync_C-like cancer microcode 208, a multi-core microprocessor 102 calculates a mixed C-state by computing a "g" and a minimum value of Ή&quot; and is represented by "j&quot;. Assuming that &quot;H&quot; is the companion's wafer synthesis C-state, then "J&quot; will constitute the composite c_ state of the processor, because 'T will be nG'. (As mentioned above, we know that this is the synthesis of the chip C· . state) and &quot;H" (companion wafer synthesis C-state) the minimum value, and no core on the processor is omitted from the calculation. If not, then "j&quot; may constitute only a portion of the processor's composite C-state (ie, the minimum C-state of the core and companion cores on the die, not the partner of the companion) The minimum value of the C-state. Therefore, &quot;H" constitutes the &quot;at least partial synthesis&quot; C. state of the processor. Flow continues to block 454. At block 454, the CSR 236 is programmed to transmit the "J" value calculated at block 452 to its partner in response to requesting the 'sync_C-state microcode 208' from its core interrupt request. Flow continues to block 456. The "J" value calculated at block 452 is returned to the program that wakes it up at block 456'. Flow ends at block 456. At block 466, the core 106 is interrupted by its companion, so the sync_C-state micro 55 201245948 code 2〇8 stylizes the CSR to obtain the input probe C-state of the routine delivery generated by the companion, in FIG. Expressed by "K〃." Due to the hierarchical search sequence of the sync-C-state routine, the companion will not interrupt the core unless it has found the composite c_ state of its wafer, so "κ" will be the companion produced. Synthetic C-state. Also, it should be noted that because it is interrupted by a companion, this means that the core 106 is the manager core 1〇6 of the chip 1〇4. The machine continues to block 468. At block 468, the sync-C-state microcode 208 counts at least the minimum value of the C-state &quot;K&quot; value of the received companion by calculating its own application C-state, The partial synthesis of the c_ state, the result of which is denoted by , if L" is the same, then i'l" cannot be the composite c_ state of the processor because it is not. And its partner applies the C-state. If the application c_ state of the partner is 〇, then the synthetic C-state for the processor (which is not accurately discovered) will be 〇. However, even if it is not required to be accurately discovered, the composition of the processing 也不 is not greater than "L&quot;. In the power management logic disclosed in this particular threshold triggering embodiment, once a mixed C-state is found to be less than two, we know that the combined C-state of the processor is also less than two. The implementation of the C-state less than 2 has only a partial effect, so a more accurate decision to synthesize c_state is not necessary. Thus the synthetic C-state discovery process may gradually relax and terminate, as shown here. , and < If L is 〇 ', it must be the synthesized C-state of the processor, because (as described above) the synthesized C-state of the processor cannot exceed any of the mixed σ c states of the processor. It is advantageous to mention in the specification that the sync_c_state routine is a subtle point of calculating a "composite value of at least the office 56 201245948." Flow continues to decision block 472. At decision block 472, if calculated at block 468 If the L&quot; value is less than 2, the flow continues to block 474. Otherwise, the flow continues to block 478. It should be noted that other embodiments of the present invention may omit such threshold conditions (e.g., L &lt; 2?) To continue a synthetic C-state discovery process. In such an embodiment, each of the boot cores of the processor will unconditionally determine the composite C-state of the processor. At block 474' is the core between the companions The interrupt request, Sync_c-state microcode 208, stylizes CSR 234 for transmitting the &quot;L' value calculated in block 468 to its companion. Again, 'we should pay attention to when the companion receives the L&quot; The reception may constitute a local composite value of the processor. However, since &quot;L&quot; is less than 2, the synthesized value of the processor must also be less than 2, and any action to further determine the synthesized value of the processor (if 'L' is 1) will be excluded. The flow continues to block 476 &lt; 3 At block 476, the command returns the &quot;L&quot; value calculated at block 468 to its caller. The process ends at block 476. At block 478, the Sync-C-state microcode 208 wakes up a dependent sync_c-state routine on its partner core by the stylized CSR 236 to pass the nL&quot; value calculated at block 468 to its partner and Interrupt partner. This will require the partner to calculate a mixed C-state and provide it to core 1〇6. We may note that in the architecture of the core embodiment of Figure 4 and illustrated by the sync_C-state DM 208 of Figure 4, this would be equivalent to the requesting partner providing its most recent request c_state (if any). The flow continues to block 48^ at block 482, the synC-C_state microcode 2〇8 stylized CSR 236 has returned a mixed C-state to the core I% by the debt test partner, and obtains a mix of 57 201245948 partners C- The state 'is indicated by 'Μ' in Figure 4. We can note that if the partner is in its most active execution state, the value of &quot;Μ&quot; will be zero. Flow continues to block 484. At block 484, sync The C-state microcode 208 calculates a mixed c_state for the multi-core microprocessor 102 by computing the minimum of &quot;L&quot; and &quot;&quot; values, denoted by &quot;N&quot;. It may be noted that in the architecture of the core embodiment of FIG. 1 and illustrated by the sync-c_state microcode 208 of FIG. 4, &quot;N&quot; must be the synthesized c_ state of the processor because it contains companions The wafer synthesis C-state K, the core's own application c_state A, and the application's application C-state (the latter is incorporated into the hybrid power state M returned by the partner), the three states together The application c_ state of all four cores. Flow continues to block 486. At block 486, the inter-core interrupt request 'sync_C-state microcode 2〇8' is programmed to pass the &quot;N&quot; value calculated by block 484 to its companion. Flow continues to block 488. The value of n&quot; calculated by block 488 'normally calculated at block 484 is passed back to its caller. Flow ends at block 488. Referring now to the flowchart shown in Figure 5, a system 100 in accordance with the present invention is shown. 'Operation to perform distributed power management assignments between multiple processing cores of the multi-core microprocessor 110. More specifically, this flowchart shows the arousal and restart of the microcode 208 by power state management. (wake-and-resuine) The core of the routine 'has the operation after the core 106 is awakened by an event from a sleep state (e.g., from block 306, 316 or 324 of Figure 3, or from block 614 of Figure 6). Flow begins at block 502. 58 201245948 At block 502 'core 106 wakes up from its sleep state in response to an event and resumes by extracting and executing an instruction handler for microcode 208. The event may include but is not affected Limited to: an inter-core interrupt', that is, an interruption from another core 106 via the inter-core communication wiring 112 or the inter-chip communication wiring 118 (or the inter-package communication wiring 1133 of the embodiment of FIG. 11); The STPCLK h 5 on the bus 116 of the group 114 is not set, and the STPCLK signal is deasserted on the bus bank 116 by the chip set 1]. 4, and another type of interrupt, such as an external interrupt. The setting of the request signal may be generated, for example, by a peripheral device (e.g., a USB device). Flow continues to decision block 5〇4. At decision block 504, arouses and restarts the routine to determine if core 1〇6 is being used by another core. The interruption of 106 is invoked. If yes, the flow continues to block; otherwise, the flow continues to decision block 508. At block 506, an inter-core interrupt routine controls the inter-core interrupt, as described in detail with respect to Figure 6. </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> </ RTI> Otherwise, the flow continues to decision block 516. At block 512, the STPCLK request has been set for the I/O read transfer that is performed in response to block 322 of FIG. 3 or block 608 of FIG. In addition to the bus 116 permission, in response to this 'core 〇 6 microcode 2 〇 8 on the bus 116 to issue a STOP GRANT message to inform the chipset η * which may remove the bus 116 pulse. In an embodiment, the chipset m will continue to wait, 59 201245948

The bus 116 is not removed until all cores 106 have issued a STOP GRANT message. In yet another embodiment, the busbar 116 clock may be removed by the die set 114 after the single core 106 has issued the STOP GRANT message. Flow continues to block 514. At block 514' core 106 returns to sleep. The chipset 114 will remove the bus 116 clock to reduce power consumption due to the multi-core microprocessor 1 , 2, as described above. Finally, the chipset 114 will resume the bus 116 clock and then de-set the STPCLK to return the core 106 to their execution state so that they can execute user commands. Flow ends at block 514. Whether or not the decision block 516' evokes and restarts the normal mode determination core 1 〇 6 is aroused by the de-setting of the STPCLK signal on the bus bar 116 by the chip set 114. If so, the flow continues to block 518; otherwise, the flow continues to block 526. In the block ‘ is a response-event (e.g., Wei timing or peripheral interrupt) ’. The bank 114 has resumed the busbar 116 and re-sets the STpcLK to cause the core 106 to resume execution. In response to this, the "power up" action initiated by the block 308 is lifted and restarted. For example, the microcode pass may cause the power supply to recover to the core 106 local cache, the 4 core plus the core 106 day clock frequency, or the core 106 fine voltage. In addition, Core 1() 6 may restore power to the shared cache, for example, if the core 106 is a coffee. Flow continues to block 522. The block 522 'Arouses and restarts the routine reading and writes the CSR saying disk move' to notify all other cores 1 〇 6 that the core hall has woken up and re-lighted. Arouse and restart the normal storage, Q&quot; as a core application or the latest 201245948 effective requirement C-state. Flow continues to block 524. The block 524' evokes and restarts the routine termination and returns control to the command decoder 204 to resume decoding the extracted user program instructions (e.g., full instructions). In particular, a typical user instruction fetch and execution will restart the instruction following the "instruction." The process concludes at block 524. At block 526, the evoke and restart routines are processed for other interrupt events, such as those described above. Block 502. The flow ends at block 526. Referring now to the flow chart shown in Figure 6, the system 1 of Figure 1 of the present invention is shown for performing the processing of multiple processing cores 1-6 of the multi-core microprocessor 102. Decentralized power supply operation. More specifically, this flow chart shows the operation of the inter-core interrupt processing routine (ICIHR) of microcode 2〇8, which is based on receiving an inter-core interrupt, that is, via the core. Operation performed by communication interconnect 112 or inter-wafer communication wiring 118 (e.g., as may be generated by blocks 406, 422, 446, or 478 of Figure 4) from the interruption of another core 1-6. Microcode 208 may be polled (If microcode 2〇8 has been executed) take an inter-core interrupt, or microcode 2〇8 may take an inter-core interrupt as a real interrupt between user program instructions, or an interrupt may cause The code 208 wakes up from the state in which the core 106 is sleeping. Flow begins at block 604. At block 604, the ICIHR of the interrupt core 1-6 calls a local Sync_C-state routine according to Figure 4 to continue synchronization with another core. In response to this, it obtains at least a partial synthesis C-state for the multi-core microprocessor 102, represented by &quot;PC&quot; in Figure 6. The ICIHR call has an input value "Y〃 sync_C- State microcode 208, which is the probe C-state delivered by the external sync_c- 61 201245948 state routine, and the local sync-C-state routine will depend on the external sync_C-state routine. Moreover, a value greater than or equal to 2 indicates that TC&quot; is a complete and not only a partial synthetic c-state of all cores 1〇6 of a multi-core microprocessor 1〇2, and represents all cores of the processor. 6 has received the MWAIT instruction specifying one of the &quot;PC&quot; or larger C-state values. What?|_ Private continues to block 606. At block 606, the microcode 208 determines whether the value of the PC obtained at block 604 is greater than or equal to 2, and whether the core is authorized to perform or allow the execution of the &quot;pc&quot;c-state (eg, Core 1〇) The 6 series is BSp). If so, the flow continues to block 608; otherwise, the flow continues to decision block 612. At block 608, the core, 106 (e.g., when the BSp core 1-6 is authorized to do so), notifies the chipset m that it may require permission to remove the bus 116, as in block 322 above. The flow continues to the decision block μ]. At decision block 612, the microcode determines that it is touching the sleep touch. If yes, the flow continues to block 614; no%, the flow continues to block (10).

2〇4, and restart the interpretation of the extracted user program instructions. . The process ends at block 204 and ends at block 616.

In contrast, in the example of Fig. 8, a case is made. In the example of Figure 7, the 'users execute, each executing an MWAIT instruction. The user program effectively executes 62 201245948 lines on the core 106. Each time a different time is executed, _mwait refers to eight executions of an MWAIT instruction and enters eight sleeps. In the other, the core has the characteristics of the microcode 208 of the core 106, and some examples are shown, one for each of the four cores 106. For example, as shown in Fig. 1, the core 2 is the manager of their wafers 1, and the BSP of the microprocessor 102. Each row of Figure 7 is a spear, and the core is the action taken by the multi-core master without the cores. Figure 7 shows the passage of time for each touchdown. First, each core touch encounters a MWAIT instruction specified by various C states (at block 302). In the example of FIG. 7, the & command sent to the core and core 3 is 4 (:·_, and sent to the core and the core, and the 2's instruction specifies the C-state of 5. Each core 106 Responsively performing its associated power saving actions (in the block period), _ the received target c. state (,, χ&quot;) is stored for its applied and most recent valid request c_state" γ„ ^ Next, each The core 106 transmits its application c_state &quot;[gamma&quot; as a probe c_ state to its partner (at block 4〇6), as indicated by the arrow with the value of A, A. Each core 106 It then receives its partner's probe c_state (at block 4〇8) and calculates its wafer 104's synthesized C-state &quot;C&quot; (at block 412). In this example, calculated by each core 106&quot; The C&quot; value is 4. Since Core 1 and Core 3 are not the manager cores, they both go to sleep (at block 324); because Core 0 and Core 2 are the manager cores, they are each other (ie, they The companion) transmits the respective "C&quot; value to the other party (at block 422), such as to have &quot;C 63 201245948 The indicated value is represented by the arrow. Each of them receives its companion's wafer synthesis c_state (at block 424) and calculates the multi-core microprocessor 1〇2 to synthesize the c_state "E" (at block 426). In this example, the value of "quote" calculated by each core and core 2 is 4. Since core 2 is not the BSP core 106, it goes to sleep (at block 324). It is a BSP, so its notification chipset 114 may request permission to remove the sink&quot;iL row 116 clock (at block 322), for example, to set up a PC pclk. More specifically, the core UI notifies the chipset 114_multicore The microprocessor 〇2 synthesizes the C-state to 4' and then the core 〇 proceeds to sleep (at block 324). The predetermined ι/〇 connection address is specified according to the 1/0 read transfer initialized by block 322. The wafer, group 114 can then inhibit the generation of a snoop cycle on the bus bar 116. - When all of the core halls are dormant, the chipset 114 sets STpCLK to wake each core to 106 (at block 502). Post an ST〇p grant message to the chipset 114 (in Block 512) then returns to sleep (at block 514). Core 106 may sleep for an ambiguous amount of time 'without the power, ie, the benefits of both action and sleep, still consume less power than they would normally operate. Finally, a wake-up event occurs. In this example, chipset m de-asserts STPCLK, which wakes up each core, (10) (at block 5〇2). Each core contact should undo its previous power-saving action ( At block 518), and leaving its microcode 208 and reverting to extracting and executing the user code (in Box. See the flow chart shown in reference to Figure 8, which shows a second example of the operational flow of the system (10) of Figure 1 in accordance with the present invention in accordance with Figures 3 through 6. Flowchart of Figure 8 201245948 years old Figure 7 'However' In the example of Figure 8, each user who effectively performs the execution on the core touches the execution of the day-------------------- The heart is in the age-MWAIT^M face record _ only executed.乜3 first encounters a specific target & state &quot;X&quot; is * difficult ^ τ 曰 7 (at block 3 〇 2). Core 3 responsively performs its associated power saving action (at block 308) 'and stores τ as its application c-state, the following more steps - τ not nucleus u 3 then apply its c_ state as a system [The status is passed to the partner 'core 2' (at block 406), as indicated by the arrow with the &quot;A&quot; tag value, which will interrupt core 2. Core 2 is interrupted by its partner core 3 (at block 6〇4). Since Core 2 is still in the -execution state, its own fine c_ state is Q, expressed as &quot;γ&quot; (at block 604 + ). Core 2 receives the detected c_ state of core 3 (in block 4), is represented by &quot;F" and has a value of 4. Core 2 then computes its ^1Q4 synthetic c_state&quot;G&quot; (at block 436), and The "G" value is passed back to its partner core 3 (at block 442). Then 'core 2 leaves its microcode 2〇8 and reverts to the user code (at block 616). Core 3 receives its partner core 2 Thereafter, the c-state is synchronized, ΊΒΠ (at block 408). Core 3 then calculates its wafer 104 to synthesize c_state "c" (at block 412). Since the value of C is zero, core 3 proceeds to sleep (at block 316). Core 2 then encounters a MWAIT instruction with a specific target c_. state χ&quot; 5 (at block 302). Core 2 responsively performs the associated power save action (at block 308) 'and stores &quot;X&quot; as It applies the c-state, and then to Core 2 with &quot;Y" 65 201245948. Core 2 then passes 'Ύ〃 (which is 5) as a probe c_ state to its partner 'core 3' (at block 406) ' as indicated by the arrow with the &quot;A&quot; tag value, which will Interrupt core 3. The core 3 is interrupted by its partner core 2 of wake-up core 3 (at block 5〇2). Since core 3 is preceded by a MWAIT instruction of 4 and the value is still correct, its applied C-state is 4, expressed as &quot;[gamma]&quot; (in block 6〇4). Core 3 receives the probe C-state of core 2 (at block 434), is represented by &quot;F&quot; and has a value of 5. Core 3 then computes its wafer 1〇4 synthesis c_state "G&quot; (at block 436) as the minimum of the detected C-state (ie, 5), and its own application C-state (ie, '5) And pass the 4 "G" value back to its partner core 2 as a mixed state (at block 442). Core 3 then returns to sleep (at block 444). Core 2 receives its partner core 3 mix c_ State (at block 4〇8), denoted by &quot;B„ and have a value of 4, and then calculate its wafer 1〇4 synthetic c_state&quot;c" value (at block 412) as one of the smallest mixed C-states The value (ie, 4), and its own application C-state (ie, 4). Because Core 2 has found that the synthetic C-state of its lowest hierarchical domain is at least 2, as the administrator of the domain Core 2 belongs to a higher-level group of the same attribute, so its (Core 2) then passes its own "c," value (for 4) to its companion core (at block 422), which will break the core. Hey. The core system is interrupted by its peer core 2 (at block 604). Since the core 〇 is in an execution state, its application c_ state is 〇, denoted by &quot;γ&quot; (in block 6.4). The core 〇 receives the probe C-state of core 2 (at block 466), Κ', which means that it has a value of 4. The core then computes its mixed c-state &quot;l&quot; (at block 66 201245948 468) and transmits the L value of 0 to its companion core 2 (at block 474). Core 0 then leaves its microcode view and reverts to the user code (at block (10)). Core 2 receives the mixed state of its peer core (indicated by: and represents the value of G', calculates its own corpse C-state (at block 426), and: it is represented by E. Since the E, 'value is G, the core, 2 goes to sleep (at block 316). Core 0 then encounters a specific target C-state &quot;X&quot; is the MWAIT instruction of 4 (at block 3〇2). The core responsively performs the associated power save action (at block 308) and stores the &quot;X as its application C. state, expressed as &quot;[gamma&quot;. Then, the kernel will, Τ (the system is 4) As a probe C-state is transmitted to its partner, core i, (at block 406) 'is indicated by the arrow with the A&quot; tag value, which will interrupt core i. Core 1 is interrupted by its partner core 0 ( At block 604), since core i is still in the -execution state, its application c_ state is 〇, ύ&quot; indicates (in block 604). Core i receives the core c probe c state (at block 434) , with "F" and with a value of 4. Core! Then calculate its wafer service synthesis c_ state G (at block 436) 'Return the G&quot value to its partner core 〇 (at block 442). Then 'core 1 leaves its microcode hire and replies to the user code (at block 616) 0 core~ 〇 Receive the value of its partner core 1 as a mixed c_state" (at block 408). Core 0 then calculates its wafer 1〇4 synthesis [state" c&quot; (at block 4(1). Because the value of &quot;C" is () 'So the core 〇 goes to sleep (at block 316). Core 1 then encounters a specific target c. state &quot;χ,, is 3 mwait 67 201245948 instruction (at block 302). Core 1 responds Save “χ” as its application power state' and perform the associated power save action (at block 3〇8). Then, the core worker sends its application C-state 'Ύ' (for 3) to its partner, core〇 , (at block 4〇6), as indicated by the arrow with the value of “Α”, it will interrupt the core 〇. Core 0 is interrupted by the buddy core 1 of wake-up core 0 (at block 5〇2). Core 0 previously encountered a target C-state 4 MWAIT instruction, so its application C-state is 4' to 1Ύ "Representation (in block 604). Core 0 receives the probe C-state of core 1 (at block 434), is represented by &quot;F" and has a value of 3. The core 〇 then computes its wafer 104 synthesized C-state&quot;G&quot; (at block 436), and pass the 3&quot;G&quot; value to its companion core 2 (at block 446), which will interrupt core 2. The core 2 is interrupted by its companion core (at block 604) The companion core 〇 wakes up core 2 (at block 502). Since Core 2 previously encountered an MWAIT instruction with a C-state of 5, its applied C-state is 5, denoted by ηΥ&quot; (in block 604). Core 2 receives the probe 〇 state of core 0 (at block 466), denoted by Κ&quot; and has a value of 3. Core 2 then computes a "mixed" C-state &quot;L&quot; (at block 468), and 3 The &quot;L&quot; value is passed to its partner core 3 (at block 474), which will interrupt core 3. The core 3 is interrupted by the buddy core 2 of wake-up core 3 (at block 502). Because core 3 encountered C before - A MWAIT instruction with a status of 4, so its application C-state is 4, indicated by &quot;Υ&quot; (in block 604). Core 3 receives the C-state of core 2 (at block 434) to 'Τ&quot; Represents and has a value of 3. Core 3 then computes a mixed C-state &quot;G&quot; (at block 436) and passes the value of 3 "G" to its partner 68 201245948 core 2 (at block 442). G&quot; is now responsible for each core application "state, so &quot;G" constitutes a multi-core processor 1〇2 synthesis c_ state. However, since core 3 is not a BSP and is evoked from sleep, core 3 returns to sleep (at block 614). Core 2 receives a mixed c_state &quot;M&quot; of its partner core 3 value of 3 (at block 482). Core 2 then computes a mixed C-state &quot;N&quot; (at block 484). Then 'core 2 passes the value of 3&quot;N' to its companion core 〇 (at block 486). Again, 'because 'C' is responsible for the c_ state of each core application, so &quot;N&quot; also needs to be constructed The multi-core processor 102 synthesizes the C-state. However, since core 2 is not a BSP and is evoked from sleep, core 2 returns to sleep (at block 614). Core 0 receives the C-state "H&quot; of its companion core 2 of 3 (at block 448). Core 0 then computes the mixed c_state" (valued at block 452) and passes it to the partner core. 1 (at block 454). Furthermore, since &quot;J&quot; is responsible for the application C-state of each core, it is also necessary to form a multi-core processor 102 to synthesize the C-state. Also because the core port is BSp, it notifies the chipset 114 that it is required to remove the bus bar 6-day suffix (at block 608). More specifically, the core 〇 notification chipset 114 multi-core microprocessor ι〇2 synthesizes the c_state system to three. The core 进行 then proceeds to sleep (at block 614). Core receives a C-state &quot;B&quot; of its partner core value of 3 (at block 408). Core 1 also computes a mixed c_state &quot;C&quot; (at block 412), which is 3 and its It also constitutes the C-state synthesized by the multi-core processor 102. Since the core 1 is not a BSP, the core 1 goes to sleep (at block 3) 6) 69 201245948 Now all H6s are like they are in the example of Figure 7. The sleep state, and the event pair also touches the pair made in Figure 7, that is, the chipset 114 sets STPCLK and wakes up the core 1〇6, etc. Obviously, this final synchronization power state discovery process is completed. During the period, all cores have separately calculated the multi-core processor 1〇2 to synthesize the c_ state. In one embodiment, the microcode 208 is designed to be uninterruptible. Thus, in the example of Figure 7, when each The microcode 208 of the core 106 is woken up to process its various MWAIT instructions. 'When another core 1〇6 tries to interrupt the microcode 2〇8, the temple is not interrupted. Instead, 'for example, the core looks The core i has sent its c_ state and obtained at block 408 from the core The c-state assumes that the core sends its C-state at block 406 to respond to the core interrupt core. Similarly, core 1 sees that core 0 has sent its C-state, and at block 408, it obtains c_ from the core. State, core 0 is considered to have sent its C_ state at block 406 to accommodate core interrupt interrupt core 0. Because each of core 0 and core 1 incorporates the C-state of the other core 106 when calculating the at least partially synthesized c_ state Consider, so each core 1〇6 will calculate at least a partially synthesized C-state. Thus, for example, the core 丨 will calculate at least a partially synthesized C-state, regardless of whether the core 送 sends its c_ state to the core In response to receiving an interrupt from one of the cores 1 or in response to an instruction, in this case, the two C-states can simultaneously span the inter-core communication wiring 112 (or across the inter-chip communication wiring 118, or across inter-package communication) Wiring 1133 is transmitted in the present embodiment of Figure u. Accordingly, advantageously, microcode 2〇8 is suitably operative to perform decentralized power management between cores 6 of multi-core microprocessor 102, 2012 45948 regardless of the sequence of events received by the various cores 106 for the MWAIT instructions.

As can be observed in the text, broadly speaking, when a core 106 encounters a MWAIT instruction, it first exchanges C-state information with its partner, and the two cores 106 are based on the C-states of the two cores 106. Wafer 111 calculates an at least partially synthesized c-state, but for example in the case of a dual core wafer, it will be the same value. The manager core 106 only converts the c-states after the compute wafer 104 is synthesized, and then exchanges C-state information with their companions, and the two are calculated based on the composite 匸_ state of the two wafers 04 for the multi-core microprocessor 102. The composite c_ state will be the same value. According to this approach, the benefit is that all cores 106 calculate the same composite c_ state regardless of the order in which the core 106 receives their MWAIT instructions. Moreover, preferably, regardless of the order in which the cores 106 receive their MWAIT instructions, they are coordinated with each other in a distributed manner such that the multi-core microprocessor 110 can communicate with the chipset 114 as a single entity. Participate in the licensing of power-saving actions relative to the multi-core microprocessor i's globally, such as removing the bus 116 clock. It is advantageous that 'this type of distributed C·state synchronization is used to achieve the implementation of the power supply, in the case where there is no need to make the secret crystal 1〇4 but the dedicated hardware for performing power management outside the 1G6. It is performed, which may provide the following advantages: adjustable (size) capability, arbitrability, yield miscellaneous, power reduction, and actual size reduction of the domain wafer. It may be noted that each core 1G6 of other multi-core microprocessor embodiments having different numbers and configurations may employ similar microcode employment, as explained with respect to Figures 3-6. For example, a core of a dual-core microprocessor that does not have two cores 106 in a single chip 1 (eg, Figure 201245948) 8 may employ a similar micro-mamm, as relevant Each core 106 has only a companion and no _ of Figures 3 through 6. Similarly, a dual core microprocessor embodiment with two single core ~ chip collapse (such as shown in Figure 19) The core (10) may make similar microcode. As illustrated in Figures 3 through 6 of each core, which has one companion and no partner (or reassign core 106 as a companion). Similarly, a dual core microprocessor having a single core single chip package 104 (e.g., as shown in FIG. 20) may have a similar microcode 2〇8 for each core of the embodiment. Each core (10) has only - friends and no companions or partners (or reassigns the core, as illustrated by Figures 3 through 6 of the same. Again, other asymmetric configurations with core 106 (eg, Figures 21 and 22) Each of the cores 1-6 of the plurality of core microprocessor embodiments of the display may employ a similar microcode 208 that is altered relative to Figures 3 through 6, for example as described below with respect to Figures 1, 以及, 13 and 17. The operation of the core 〇6 and/or the package having different numbers and configurations as described herein (which employs the following microcode 208 of the core 106 described with respect to FIGS. 3 to 6 and 10, 13 and 17) The system embodiment and the like other than the combination are also considered by the present invention and can be equivalently modified according to the actual application. Referring now to the block diagram shown in Fig. 9, which shows the computer system of the present invention Multiple processing in a multi-core microprocessor 902 An alternative embodiment of decentralized power management between the cores 106. The system 900 is similar to the system of Figure 1, and the multi-core microprocessor 902 is similar to the multi-core microprocessor 102 of Figure 1; however, the multiple 72 201245948 core micro Processor 902 is an eight core microprocessor 9A2 that includes four dual core wafers 104 organized on a single microprocessor package, represented by a wafer cassette, a wafer 2, and a wafer 3. The wafer cassette contains a core 〇 and core j, and the chip core 2 and core 3, similar to the figure; in addition, the wafer 2 contains the core 4 and the core /, and the wafer 3 contains the core 6 and the core 7. Within each chip, the core For each other's partners, but each chip selects a core labeled as the manager of the wafer. The wafer manager on the package has multiple inter-wafer communication wirings that connect each wafer to every other wafer. This allows one The implementation of the coordination system, in which the wafer official includes a peer-collab〇rative member of the same attribute group; that is, 'each wafer; the I* manager is able to interact with any other wafer manager on the package. Association The inter-wafer communication distribution line 118 is designed as follows: the 〇τ contact 〇 of the wafer IN, the IN i of the wafer 1 ; the 妾 pad, the m 2 pin of the wafer 2, and the 3 pin of the wafer 3 are via a single- Wiring _ is connected to pin P1; QIT contact 晶片 of wafer 1, IN 1 contact pad of wafer 2, 4 2 contact pads of wafer 3, and pad contact pads of wafer 系 are connected to pin p2 via single-wiring: wafer 2 〇υ 塾 contact 塾, wafer 3 IN i #妾 contact pad, wafer 〇 m 2 contact 塾 and wafer 〗 〖 3 contact 塾 she from a single - g pass 峨 charm pin P3; "3 contact 塾, The contact of the IN 1 contact 塾, the wafer] and the 2 3 of the wafer 2 are coupled to the pin p4 via a single wiring network. § When each manager core 1〇6 wants to communicate with other chips1〇4, it will transmit the information of its OUT contact pad 1〇8, and this information will be broadcast to other wafers just after the appropriate IN contact.塾108 is received by the respective manager core, 〇6. As seen in Figure 73 201245948, it can be seen that 'the advantage is the number of contact pads (10) on each wafer i〇4 and the number of pins P on the package 902 (i.e., regarding the multiple cores allocated as described herein). The contact pads and pins of the decentralized power management; however, the multi-core microprocessor 102 may of course contain other contacts and pins for other purposes, such as data, address and control busbars, which are not greater than The number of wafers 1〇4, which is a relatively small number. This is particularly advantageous in the design of the finite (4) finite and domain pin, which may be common, since the number of contact 塾/pins on the package is standard, for microprocessor manufacturers. In other words, f tries to follow these "quasi-values have their own benefits" and most of the contact pads/pins may have been made in this shop. In addition, the following alternative embodiments, each of which is on the wafer The number of contact ports 108 is or may be less than the number of wafers. _ Referring to the flow chart shown in FIG. 10, which shows the system 9 of FIG. 9 in accordance with the present invention, the distribution is performed in the eight core microprocessor 9〇2. Multi-processing core operation of the sub-type power management. More specifically, the flow chart of Tuchuan shows the operation of Figure 2, ?)_-C marriage microcode 2. 8. Similar to the flowchart of Figure 4. , - the heart is similar 'and the same number of squares are similar. : The core of the description shows the state of the _ state micro _ = there is a (10) to explain the difference. In particular, the wafer just each manager core 106 and 1 Two steel with core 1G6, _ with (10). In addition, the manager Bu =:::: one The same two phase is arbitrated by the package manager or BSP. 201245948 The process begins at block 402 in Figure 10 and continues through block 416 as explained in relation to Figure 4. However, Figure 10 does not include block 422. 424, 426, or 428. Conversely, flow continues from decision block 414 to &quot;NO'' branch to decision block 1018. At decision block 1018, sync_C-state microcode 208 determines whether all of its peers have been visited, i.e., Whether the core 106 has exchanged C-states with each of the peers by blocks 1022 and 1024. If so, the flow continues to block 416; otherwise, the flow continues to block 1022. At block 1022, the sync_c-state microcode 208 is stylized. Figure 2, CSR234, generates a new instance of the sync_C-state on its next companion to pass the &quot;C&quot; value to its next companion and to interrupt the companion. In the case of the first companion, the nC&quote sent The value is calculated at block 412; in the case of the remaining companions, the "c" value is calculated at block 1026. In the loop containing blocks 414, 1018, 1022, 1024, and 1026, the microcode 208 chase The companions have been visited to ensure that they have visited each of them (unless the decision block 414 was found to be a real condition). Flow continues to block 1024. At block 1024, the sync-C-state microcode 208 stylizes the CSR 234. Detecting that the next companion has passed back a mixed C-state and obtaining a mixed C-state, indicated by nD&quot;. Flow continues to block 1026. At block 1026, the sync_c-state microcode 208 is calculated by &quot;C&quot; The minimum value of the "D" value is used to calculate a recently calculated local mixed c_state 'in nC&quot;. The process returns to decision block 414. Flow continues from block 434 in Figure 1 and continues through block 444 as illustrated in Figure 75 201245948 with respect to Figure 4. However, FIG. 10 does not include blocks 446, 448, 452, 454, or 456. Conversely, the flow continues from decision block 438 to the &quot;NO&quot; branch to decision block 1045. At decision block 1045, the 'sync_C-state microcode 208 determines whether all of its companions have been visited', i.e., whether the core 106 has been blocked by block 1 46 and 1048 exchange the C-state with each of the peers. If so, the flow continues to block 442; otherwise, the flow continues to block 1046. At block 1046, the sync_c-state microcode 208 is programmed by the CSR 234 in its next companion. A new instance of the sync_C state routine is generated to pass the &quot;g" value to its next companion and to interrupt the companion. In the case of the first companion, the &quot;G&quot; value sent is calculated at block 436; in the case of the remaining companions, "G," the value is calculated at block 1052. Flow continues to block 1048. At block 1048, the microcode 208 programs the CSR 234 to detect that the next companion has returned a mixed C-state to the core 1〇6 and obtains a mixed C-state, indicated by "H&quot;. Flow continues to block 1052. At block 1052, the sync_c-state microcode 208 calculates a most recently calculated local blending state by calculating the minimum value of the &quot;H&quot; value, denoted by &quot;Gn. The flow returns to decision block 438. The flow continues from Figure 10 Block 466, and continues via block 476, as explained in relation to Figure 4. We can note that in block 474, the companion (core 1〇6 transmits the L&quot; value to it) is the interrupt core 1〇6 companion. In addition, the flow continues from the decision block 472 in Figure 1 离开 to the "NO&quot; branch and continues through block 484, as described in relation to 76 201245948 in Figure 4. However, Figure ι does not include blocks 486 or 488. The flow continues from block 484 to decision block 1085. At decision block 1085, if the &quot;L&quot; value is less than 2, the flow continues to block 474; otherwise, the flow continues to decision block 1087. The flow continues from block 484 to the decision block. In the case of 1085, the &quot;L&quot; value is calculated at block 484; in the case where the flow continues from block 1093 to decision block 〇85, the &quot;L&quot; value is spurred out at block 1〇93. . Flow continues to decision block 1087. The decision block 1087&apos; synch_C-state microcode 208 determines if all of the peers have been visited, i.e., whether the core 106 has exchanged the c_state with each of the peers or received the C-state from each of the peers. In the event of a break with the peer, the c_state is received via block 466 (and will be sent via block 474); therefore, the interrupted companion is considered to have been visited; in the remaining companions, the c_state is via Blocks 1〇89 and 1091 are exchanged. If all of the companions have been visited, the flow continues to block 474; otherwise the process continues to block 1089. At block 1089, the microcode 208 generates a new instance of the sync-C-state routine on the next companion by the stylized CSR 234 for transmitting the &quot;L&quot; value to its next companion and for interrupting the companion . In the case of the first companion, the "L," value sent is calculated at block 484; in the case of the remaining companions, the &quot;L&quot; value is calculated at block 1093. Go to block 1091. At block 1〇91, the microcode 208 is programmed to CSR 234 to make a companion that has been passed back to the hybrid core lG6 and obtain a mixed C-state, indicated by &quot;M&quot;. 77 201245948 Flow continues Block 1093. At block 1093, the sync_c-state microcode 208 calculates the most recently calculated value of the local mixed C-state by calculating the minimum of the "L&quot; and "M," values, expressed as &quot;L&quot;. To decision block 1085. Referring now to the block diagram shown in FIG. 11, an alternate embodiment of the distributed power management of the computer system 1100 of the present invention for distributing between the multiple processing cores 106 of two multi-core microprocessors 102 is shown. System 1100 is similar to system 100 of FIG. 1, and two multi-core microprocessors 102 are each similar to multi-core processor 102 of FIG. 1; however, this system includes two multi-cores coupled together Microprocessing state to provide a The eight-core system is 11〇〇. Therefore, the system of FIG. 2(8) is also similar to the system 9〇〇 of FIG. 9 , which includes four dual-core chips 1〇4, with a chip 〇, a Japanese film, a Japanese film 2, and Wafer 3 is indicated. Wafer 0 contains core 〇 and core i, wafer 1 contains core 2 and core 3, wafer 2 contains core 4 and core 5, and wafer 3 includes s core 6 and core 7. However, the wafer cassette and the chip j are included in the first multi-core microprocessor package, and the wafer 2 and the wafer 3 are included in the second multi-core unit. Therefore, although the core I% is allocated among the multiple multi-core microprocessor packages 102 in the present embodiment of the present embodiment, the core 106 has certain power management related resources, that is, by the chipset. The m and the chipset 114 are used to snoop or not to snoop the bus. The clock is cached on the processor bus: slightly, so the chipset 114 can be pre-determined by a 1/〇 connection address. And the single-1/0 read transmission on the destination bank 116 is expected. In addition, the cores 106 of the two packages H 102 potentially share a VRM, and the core c of the chip collapse may share - PLL ' as described above. Advantageously, the core of the system of Figure 11, 106 (especially the microcode 208 of the 2012 2012 948 core 106) is designed to communicate with each other, as such and CNTR. As explained in 2534, the control of the resources related to the shared power management is coordinated in a decentralized manner by using the inter-core communication wiring ιι2, the inter-chip communication wiring 118, and the inter-fab communication wiring 1133. The inter-chip communication wiring 118 of the first multi-core microprocessor 102 is designed as shown in FIG. However, the pins of the second multi-core microprocessor 1〇2 are represented by &quot;, &quot;p6„, "P7" and "P8", and the inter-chip communication wiring of the second multi-core micro-processing stomach 1〇2 The 118 series is set as follows: the contact pads of the wafer 2 and the contact pads of the wafer 3 are coupled to the pin 5 via a single wiring net; the contact pads of the wafer 2 and the IN 2 contact pads of the wafer 3 are via a single wiring. The net is coupled to the pin p6; the 〇υτ contact pad of the chip 2 and the IN 1 contact pad of the chip 3 are coupled to the pin p7 via a single wiring net; the OUT 3 of the wafer 3 contacts the 3U 2 of the IN 3 contact pad via a single _ The wiring network is coupled to the pin P8. Further, the pin P1 of the first multi-core microprocessor 102 is coupled to the second multi-core microprocessor 102 via the inter-package communication wiring 1133 of the motherboard of the system U00. The pins P7' are such that the out contact pads of the wafer, the sink contact pads of the wafer, the IN 2 contact pads of the wafer, and the IN 3 contact pads of the wafer 3 are all coupled together via a single wiring network; A pin p2 of a multi-core microprocessor 1 耦 2 is coupled to a pin P8 of the first multi-core 〇 processor 1 , 2 to enable the wafer 1 The out contact, the IN 1 contact of the wafer 2, the IN 2 contact of the wafer 3, and the IN 3 contact pads of the wafer are all coupled together via a single wiring network; the first multi-core micro-processing is 102 The pin P3 is coupled to the pin P5 of the second multi-core microprocessor ι2 to make the OUT contact pad of the wafer 0, the j contact pad of the wafer 1, the IN2 contact pad of the wafer 2 201245948, and the wafer The IN3 contact pads of the three are all coupled together via a single wiring network; the pin P4 of the first multi-core microprocessor 102 is coupled to the pin P6 of the second multi-core microprocessor 1〇2 to enable the chip The OUT contact pad of 0, the IN 1 contact pad of the wafer 1, the 2 contact pad of the wafer 2, and the 3 contact contacts of the wafer 3 are all coupled together via a single wiring net. The CSR 234 of FIG. 2 is also connected. The inter-package communication wiring 1133 is used to activate the microcode 208 to program the CSR 234 to communicate with other cores 106 via the inter-package communication wiring 1133. Therefore, the manager core 106 of each wafer 104 is activated to be packaged. Inter-body communication wiring Π33 and inter-wafer communication wiring 118 and other wafers ι管理者4 manager core 1〇6 (ie, its companion) communicates. When each manager core 1〇6 wants to communicate with other chips 104, it transmits the information just on its ουτ contact pad, and this The information is broadcast to other wafers 1 4 and received by respective manager cores 106 via appropriate access ports (10). As may be observed from Figure u, advantageously, relative to each multi-core microprocessor The number of contacts (10) on each wafer ship and the number of pins P on the package 102 are not greater than the number of wafers, which is a relatively small number. 'More' Please note that for one of the wafers 104, the established manager core is 1〇6, and the manager of the core is the core of the established manager.” With the core office, we can observe the core from Figure 11. g, core 2, core 4, and core 6 are companions similar to those configured in Figure 9, even though the Figure 9 chip collapses are included in the single-eight-core micro-drive package_, and: Figure 4 The defragmentation system is included in two separate quad core microprocessor packages 201245948 body 102. Thus, the microcode 2 〇 8 system described with respect to Figure ι is designed to operate as in system 1100 of Figure 11. All four companion cores 1〇6 form a co-operating attribute group together, in which each companion core 1〇6 system is activated without arbitration, so that no matter which companion core 1〇6 is designated as The Bsp core can be directly coordinated with any other companion cores 1. I further note that although the pin P is required in a multiprocessor embodiment (such as those shown in Figures 11 and 12), But if necessary, the pin can be in a single month. The multi-core microprocessors 1 2 are omitted in the embodiment, although they are beneficial for debugging purposes. Referring now to the block diagram shown in Figure 12, the computer system 1200 is shown to perform the allocation in two multi-core micros in accordance with the present invention. An alternative embodiment of decentralized power management between multiple processing cores of processor 12〇2. System 12 is similar to system 1100 of Figure u, and multi-core microprocessor 12〇2 is similar to Figure u. The core micro-processing state 102. However, the eight cores of the system 1200 are organized and physically connected by a deep hierarchical hierarchical coordination system by bypass wiring. Each wafer 104 has only three contact pads 108 ( OUT, IN1 and IN2) for coupling to the inter-wafer communication wiring 118; each package 12〇2 has only two pins, represented by Ρ^_Ρ2 on the first multi-core microprocessor 1202, and The two-core microprocessor 1202 is represented by P3 and P4; and the inter-chip communication wiring 118 and the inter-package communication wiring 1133 connected to the two multi-core microprocessors of FIG. 12 have different configurations from the corresponding elements in FIG. In the system of Figure 12〇 , The core and the core 4 square of their respective designated multi-core microprocessor 1202 81 201 245 948 The "package manager &quot; or" p manager. " Furthermore, unless otherwise (four) 'no specific terms &quot; friends &quot; this system to represent the manager core, i06 on different packages 1202 communicating with each other; therefore, in the embodiment of Figure 2, Core 0 and Core 4 are friends. The inter-wafer communication wiring 118 of the first multi-core microprocessor 12A is designed as follows. Within the first package body 12〇2, the OUT contact pad of the wafer defect and the “contact contact pad of the chip” are extinguished to the pin P1 via the single-wiring net, and the OUT contact pad of the wafer 1 and the IN of the wafer 0 are 1 The contact pads are coupled via a single wiring network; and the IN2 contact pads of the wafer 0 are coupled to the pins P2. Within the second package 1201, the contact pads of the 0UT contact pads of the wafer 2 and the wafer 3 are passed through a single- The wiring net is coupled to the pin P3; the contact pad of the wafer 3 is in contact with the chip 2 via the single-wiring net; and the IN2 contact of the chip 2 is connected to the pin P4. Uo's motherboard inter-package communication wiring 1133, pin P1 is coupled to pin P4, so that the wafer 0 接触τ contact pad, the wafer IN 1 contacts 塾 ' and the wafer 2 ΓΝ 2 contacts 塾 via a single distribution network And all the contacts are connected to each other; and the pin P2 is connected to the pin P3' to make the wafer 2^〇υτ contact the whole, the IN 1 contact pad of the wafer 3, and the sink 2 contact pad of the wafer via the single wiring net And all come together. Therefore, unlike in the system 900 of Figure 9 and in the system of g η, each of the tubes For example, 1G6 can communicate with other managers, and in the system 1200 of Figure 12, only the manager core and the manager core 4 can communicate with each other (i.e., via the bypass wiring as described herein). An advantage of the embodiment over graph u is that with respect to each multi-core microprocessor 12〇2, the contact 塾108 S mesh (1) of each wafer 1 〇 4 on 82 201245948 is smaller than the number of wafers, and each The number of pins p (2) on the body 1202 is smaller than the number of the wafers 104, which is a relatively small number. In addition, the number of C-state exchanges between the cores 1 and 6 may be less. For the purpose of debugging, the first multi-core processor 1 also includes a third pin that is connected to the WT connector (10) of the chip 1, and the second multi-core microprocessor 1202 also includes a surface-to-wafer 3 〇υτ接难1〇8 one of the third pins. See the flowchart shown in the multi-test I3, which shows the system 1200 according to the present invention for performing distribution on the dual quad core microprocessor (10) (eight The core system is the "distributed power management operation" of "the first (four) eve of the night, the core, and the 〇6. More specifically, the private graph of σ diagram I3 shows FIG. 3 (the operation of “c_state microcode 2〇8” is similar to the flowcharts of FIGS. 4 and 1G, which are similar in many respects, and The blocks of the same number are similar. However, the configuration of the inter-chip communication wiring 118 and the inter-package 1-hole wiring 1133 which are responsible for the sync_C-state microcode application of the core touch described in the flowchart of Fig. 13 is shown in Fig. 12. The system 12〇〇 is different from the system of Figure n, especially some of the manager cores (ie Core 2 and Core 4) are not designed to be with the system. (10) Direct communication 'But instead a friend (core 核心 and core 4) is passed down to it in a hierarchical way (4) chew (core 2 and heart 6 respectively), which are then passed down to their partners in sequence. Eagle. Now let's make these differences. The flow starts at block 4〇2 in the figure and proceeds to block 424, as explained in relation to Figure 4. However, Figure 1〇 does not contain block gamma or similar. Proceeding from block 424 to block 1326. Additionally, in decision block 4 , 83 201245948 If the interrupted core i 6 is a friend rather than a partner or companion, the flow continues to block 1301. At block 1326, the sync_C-state microcode 208 is calculated by &quot;C&quot; The minimum value of £) is used to calculate the value of one of the (local) mixed C-states, as indicated by &quot;c&quot;. Flow continues to decision block 1327. At decision block 1327, if calculated at block 1326 If the &quot;C&quot; value is less than 2 or the core 106 is not the package manager core 106, then flow continues to block 416; otherwise, the flow continues to block 1329. At block 1329, the sync_c-state microcode 208 is programmed by CSR 234. A new instance of the sync_C-state is generated on its buddy to pass the X" value calculated at block 1326 to its buddy and to interrupt the buddy. This requires the friend to calculate and return a mixed C-state (this situation is similar to the description above in connection with Figure 4, which may constitute the composite C-state of the entire processor) and ask the friend to provide it back to this core. . Flow continues to block 1331. At block 1331, sync_C-state microcode 208 programs CSR 234 to detect that the friend has returned a mixed state to core 1〇6 and obtains a mixed C-state, indicated by &quot;D." Flow continues to block 1333 At block 1333, the sync_C-state microcode 208 calculates a most recently calculated mixed c_ state by computing the minimum of the &quot;C&quot; and &quot;D&quot; values, denoted by ''C'. We may notice' Assuming D is at least 2, then once the flow continues to block 1333, in block 1333, at the C-state calculation of the 'combination of CM values', the c_state of each core 1 〇6 in the system 1200 is considered. Thus, the synthesized c-state is referred to herein as the c_ state synthesized by system 1200. Flow continues to block 416. Flow continues from block 434 in Figure 13 and proceeds to block 444 and 84 201245948 448 'as relevant This is illustrated in Figure 4. However, Figure 13 does not include blocks 452, 454 or 456. Conversely, the flow continues from block 448 to block 1352. At block 1352 'sync_C• state microcode 208 by calculating "G', The minimum value of the &quot;H&quot; value to calculate a most recent calculation The local mixed C-state is indicated by "G&quot;. Flow continues to decision block 1353. At decision block 1353, if the fG&quot; value calculated at block 1352 is less than 2 or the core 106 is not the package manager core 106, then the flow continues. To block 442; otherwise, the flow continues to block 1355. At block 1355, the sync_C-state microcode 208 generates a new instance of the sync_C-state on its buddy by the stylized CSR 234 for the nG to be calculated at block 1352. The value is passed to its friend and used to interrupt the friend. This requires the friend to calculate and return a mixed C-state to the core 106. Flow continues to block 1357. At block 1357, sync_C-state microcode 208 stylizes CSR 234 To detect that the friend has returned a mixed C-state to core 1〇6 and obtain a mixed C-state, indicated by &quot;H&quot;. The flow continues to block 1359. At block 1359, the sync_C-state microcode 208 is Calculate the minimum value of the &quot;G" and &quot;H&quot; values to calculate a recently calculated local mixed C-state, expressed as &quot;G." We can note that assuming Η is at least 2, once the process continues to the block 135 9, in block 1359, the C-state of each core 106 in system 1200 is considered in the composite C-state calculation of the &quot;G" value; thus, the synthesized C-state is referred to herein as system 1200. Synthesize the C-state. Flow continues to block 442. Flow continues from block 466' in Figure 13 and continues through blocks 476 and 482, as explained in relation to Figure 4. However, Figure 13 does not include blocks 484, 486 or 85 201245948 488. Conversely, flow continues from block 482 to block 1381. At block 1381, the sync_C-state microcode 208 calculates a recently calculated local mixed C-state by computing the minimum of the "L&quot; and &quot;M&quot; values, as indicated by &quot;L&quot;. Flow continues to decision block 1383. At decision block 1383, if the "L&quot; value calculated at block 1381 is less than 2 or the core 106 is not the package manager core 106, then flow continues to block 474; otherwise, flow continues to block 1385. At block 1385, the sync_C-state microcode 208 generates a new instance of the sync_C-state on its buddy by the stylized CSR 234 to transmit the &quot;L&quot; value calculated at block 1381 to its buddy' and to interrupt Friends. This requires the friend to calculate and pass back a mixed C-state to this core 106. Flow continues to block 1387. In block 1387, sync_c·state microcode 2〇8 stylizes CSR 234 to detect that the friend has returned a mixed C_ state to core 1〇6 and obtains a mixed C-state, indicated by “M&quot;. Flow continues To block 389. At block 1389, the sync_C-state microcode 208 calculates the locally-synchronized locally synchronized C-state by calculating the minimum of the &quot;L&quot; and the &quot;M&quot; value, &quot;L,' Representation. We may note that, assuming at least 2, once the process continues to block ι389, each of the system 12〇〇 is considered in the composite C-state calculation of the 'in&quot;L value in block 1389. The C-state of core 106, therefore, the synthesized c_state is referred to herein as system 12 〇〇 synthesized C-state. Flow continues to block 474. As discussed above, in decision block 432, if the core 106 of the emotion is a friend rather than a partner or companion, then flow continues to block 1301. At block 1301, the core 106 is interrupted by its friends, so the microcode 2〇8 program 86 201245948 converts the CSR 234 to obtain the synthesized C-state of the friend from its friends, represented by nQ&quot; in FIG. It should be noted that the buddy does not wake up the instance of the synch_C-state if it has not confirmed for its encapsulation that the composite C-state is at least 2. The flow continues to block 1303. At block 1303, the sync_C-state is slightly drinking 2〇8.  A local mixed C-state (represented by MR) is calculated as the minimum value of the C-state &quot;Y&quot; value and the &quot;Q&quot; value it is applied to at block 13: The flow continues to decision block 1305. Block 1305, if the "R" value calculated at block 1303 is less than 2, the flow continues to block 1307; otherwise, the flow continues to block 1311. At block 1307, in response to an inter-core interrupt from its friend request, the microcode 2程式8 The stylized CSR 234 transmits the &quot;R&quot; value calculated at block 1303 to its friend. Flow continues to block 1309. In block 1309, the routine will calculate the &quot;R&quot; value passed at block 1303. Returning to its caller, flow ends at block 1309. At block 1311, the Sync-C-state microcode 208 generates a new instance of the sync_C-state on its partner by the stylized CSR 236 for use in block 1303. The "R" value is passed to its partner and used to interrupt the partner. This requires the partner to calculate and return a mixed C-state to core 1〇 6. Flow continues to block 1313. In block 1313, 'sync_C-state microcode 208 Stylized CSR 236 to detect The test partner has returned a mixed C-state to core 1〇6 and obtained the partner mixed C-state, indicated by &quot;S, in Figure 13. Flow continues to block 1315. At block 1315 'sync-C- The state microcode 208 calculates a most recently calculated local mix by calculating the minimum of the "R&quot; and "S" values (: _form 87 201245948 state, indicated by &quot;R&quot;. Flow continues to decision block 1317. In block 1317, if the &quot;R&quot; value calculated at block 1315 is less than 2, then flow continues to block 1307; otherwise, flow continues to block 1319. At block 1319, sync_C-state microcode 208 is programmed by CSR 234 A new instance of the sync_C-state is generated on its companion to pass the &quot;R&quot; value calculated at block 1315 to its companion and to interrupt the companion. This requires the companion to calculate and return a mixed C-state to this Core 1〇 6. Flow continues to block 1321. At block 1321, sync_C-state microcode 208 stylizes CSR 234 to detect that the companion has returned a mixed c-state to core 106 and obtains a mixed C-state to &quot ;S” indicates. The process continues To block 1323. At block 1323, the sync_c-state microcode 208 calculates a recently calculated local mix state by calculating the minimum of the "R" and "s" values as &quot;R&quot;. We can note that it is assumed that s is at least 2, so once the process proceeds to block 323 ', it will be in block Π23, and the c_ state of each core 1〇6 in system 12〇0 is taken into account in the calculation of τ value. Therefore, 'τ will form a simplified synthesis of the system to the block 13〇7. Referring to the block diagram shown in the reference figure, it is shown that the computer system of the present invention is replaced by one of the multi-processing power cores of the multi-processing core 1〇6 of the core core microprocessor 1402. Example. The system has just been similar in some respects to Figure =i=9GQ' because it consists of a single eight-core microprocessor with four dual-core wafers that are connected together via inter-wafer communication. 1402. However, the eight cores of system 1400 are organized and physically connected by bypass wiring in accordance with a deeper three-layer hierarchical coordination system. First, the arrangement of the inter-wafer communication wiring 118 is different from that of Fig. 9, as follows. The system 1400 is similar in some respects to the system 12 of Figure 12, in which the core is organized and physically connected in accordance with a three-tier hierarchical coordination system. Each of the four wafers 104 includes two contact pads 108' for coupling to the inter-wafer communication wires 118, namely an OUT contact pad, an in 1 contact port, and an in 2 contact port. The multi-core microprocessor 1402 of Fig. 14 includes four pins which are represented by &quot;ρι&quot;, ''ρ2', &quot;ρ3&quot;, and &quot;p4&quot;. The core microprocessor of Figure 14 is 14〇2 The inter-wafer communication wiring 118 is configured as follows: the out contact pads of the wafer, the contact pads of the wafer 1, and the IN 2 contact pads of the wafer 2 are all coupled together via a single wiring network coupled to the _P1 The wafer contact pad and the wafer contact pad are coupled together via a single wire mesh coupled to the pin P2; the pad 2 of the wafer 2 contacts the pad 1 of the wafer 3 and the wafer 0 The 接触2 contact pads are all coupled together via a single wiring net coupled to the pin 3; the 〇υτ contact pads of the wafer 3 and the IN contact pads of the wafer 2 are coupled via a single distribution network coupled to the pins The cores 106 of Figure 14 are designed to operate in accordance with the teachings of Figure 13, for cores and cores 4, even if they are located in the same package 14〇2 (as described above in relation to Figure 12) The specific term, the opposite of the friend" is still considered good In the embodiment of Fig. 14, the two friends communicate with each other via the inter-chip communication wiring 118 instead of the inter-package communication wiring 1133 of Fig. 12. In this case, in addition to the physical model of the processor, the core is designed according to a deep hierarchical coordination system with three levels of domain. Referring now to the block diagram shown in FIG. 15, an alternate embodiment of distributed power management distributed between a multi-processing core of a multi-core microprocessor 15A2 is performed in accordance with the computer system 1500 of the present invention. System 丨5〇〇 is similar in some respects to system 1400 of Figure 14, as it includes a single eight-core microprocessor 15〇2 having eight cores 〇6 represented by cores 0 through 7. However, multi-core microprocessor 1502 includes two quad-core wafers 1504 that are secretly coupled via wafer μ communication wiring 118. Each of the two wafers 1504 includes two contact pads 108 for engaging the inter-wafer communication harness 118, i.e., a contact pad and a sinking pad 2 and a padding pad. The multi-core microprocessor 15 〇 2 includes two pins indicated by "卩"" and |, 1 &gt; 2". The configuration of the inter-month communication wiring 118 of the multi-core microprocessor 1502 is as follows. The contact pad and the wafer contact pad are consumed by the single-wiring net coupled to the pin - and the wafer is (5) the contact pad is in contact with the IN 1 of the wafer, and the single-wiring is connected to the pin P1. The network is connected together. In addition, the core communication between the four core chips 1504 _ 112 will be lightly connected to each core 1 〇 6! 5 〇 4 other core just to promote distribution in a multi-core microprocessor 1502 The decentralized power management of multiple locations is difficult. The core 106 of Figure 15 is designed to operate according to the description of Figure 13, and is understood by the following description. Wei, the core of each wafer itself is based on The layers of the layers are coordinated and pure, and are organized by the bypass wiring* and physically connected to the day and day. There are two partners with the same attribute group (core and core workers; core 2 201245948 and core 3) and a companion Attribute group (core 〇 and core 2). Similarly, wafer 1 has two Partners with the same attribute group (Core 4 and Core 5; Core 6 and Core 7) and a companion with the same attribute group (Core 4 and Core 6). Here we can note the same: Companion core ~ Even if we are on the same chip Upper (as described above in relation to Figure 1).  The opposite of the characteristics of the companion is still considered a companion. Further, the companion communicates with each other via the inter-core communication wiring U 2 instead of the inter-wafer communication wiring 118 of Fig. 12 in the example of Fig. 15 . Second, the package itself defines a third hierarchical range and a corresponding buddy group. For the core of the core and the core 4 even if they are located on the same package 1502 (as opposed to the above-mentioned terminology specified in Figure 12, the meaning of 'friends') is still considered a friend. And 'friends in Figure 15 In the embodiment, communication is performed with each other via the inter-wafer communication wiring 118 instead of the inter-package communication wiring 1133 of Fig. 12. Referring now to the block diagram shown in Fig. 16, the computer system 1600 according to the present invention performs the allocation in a An alternative embodiment of decentralized power management between multiple processing cores 1 and 6 of multi-core microprocessors 16 。 2. System 1600 is similar in some respects to system 15 图 of Figure 15 because it includes a single eight core The microprocessor 16〇2 has eight cores 106 represented by core 0 to core 7. However, each wafer 104 includes a plurality of inter-core communication wires η) between each core 1〇6, To allow the parent core 106 to communicate with other cores 106 in the wafer 104. Thus, to illustrate the operation of the microcode 208 for each core 1-6 of Figure 16, (1) core 〇, core 1, core 2, and core 3 Considered as a partner Core 4, Core 5, Core 6 and Core 7 are considered partners; (2) Core and Core 4 are considered as companions. Therefore, 91 201245948 System (10) is based on the same attribute group of partners and peers. One of the two-level hierarchical coordination system domains is connected and physically connected. In addition, the inter-core communication wiring 112 existing in each core of the chip can facilitate the supply; the defined partner is the same attribute group. One of the peer cooperation coordination models. Although it is possible to coordinate the operation according to the peer cooperation, Figure 17 (4) - the manager cooperation coordination model used for distributed power management between the heart. Now refer to the flowchart shown in Figure 17 The system 1600 of Figure 16 in accordance with the present invention is shown for performing the operation of distributed power management distributed between multiple processing cores of a multi-core microprocessor 1 。 2. More specifically, the flowchart of Figure 17 is not shown in Figure 3. The operation of the sync_〇' state microcode 2〇8 (with Figure 6) is similar to the flowchart of Figure *, which is her in many respects and the squares of the (four) number are similar. However, in Figure 17 Illustrated in the flowchart The microcode 2〇8 of the core 1〇6 is responsible for the case where there are eight cores 106, instead of the four cores 1〇6 in the embodiment of the figure, specifically four cores 1〇6 series two dual wafers 1 The method of 〇4 exists, but now the difference is explained. In particular, each manager core 〇6 of a wafer 1-4 has three buddy cores 106 instead of one buddy core 〇6. The flow begins in Figure 17. Block 402 continues and passes through decision block 404 and leaves the 1 'NO' branch of decision block 404 to decision block 432 as explained in relation to FIG. However, Figure 17 does not include blocks 406 through 418. Conversely, flow continues from decision block 404 to the &quot;YES&quot; branch to block 1706. At block 1706, sync_C-state microcode 208 generates a sync_C-state routine on a partner by programming CSR 236 of FIG. An example, to be received at block 402 92 201245948 or generated at block Π12 (discussed below), the ά&quot; value is passed to its next partner and used to interrupt the partner. This requires the partner to calculate and return a hybrid C. _ state to core 106. In the loop containing blocks 1706, 1708, 1712, 414, and 1717, the microcode 208 keeps a record of its visited partners to ensure that they visit each of them (unless the decision block 414 is The process is found to be a real condition. The flow continues to block 1708. At block 1708 'sync-C-state microcode 208, the CSR 236 is programmed to test that the next partner has returned a mixed C-state to the core 106 and obtained the partner. The mixed C_ state is represented by &quot;Βπ in Figure 17. Flow continues to block 1712. At block 1712, the sync_C-state microcode 208 calculates a recent count by calculating the minimum of &quot;Α&quot; and "Β" values. The local mixed C-state of the calculation, which is represented by &quot;A". Flow continues to decision block 1714. At decision block 1714, if the "Απ value is less than 2 or the core 106 is not the manager core 106' as calculated at block 1712, then flow continues to block 1716; otherwise, the flow continues to decision block 1717. At block 1716 'sync_C-state The microcode 208 passes the &quot;A&quot; value calculated at block 1712 back to its caller. Flow ends at block 1716. {^Decision block 1717, sync_C-state microcode 208 determines whether all of its partners have been visited. That is, whether core 106 has exchanged C-states with each of its partners by blocks Π 06 and 1708. If so, the flow continues to block 1719; otherwise, the flow returns to block Π 06. At block 1719, sync_C-state microcode 208 determines that the &quot;A&quot; value of 93 201245948 calculated at block 1712 becomes its wafer synthesis c_ state, which is represented by "c", and the flow continues to block 422 and proceeds to block 428, as described above in relation to FIG. The flow continues from the &quot;NO&quot; branch of decision block 438 to decision block 1739. At decision block 1739, the sync_c-state microcode 208 determines whether all of its partners have been visited, i.e., whether the core 106 has exchanged a mixed C-state with each of its partners via blocks 1741 and 1743 (discussed below). If so, the flow continues to block 446 and proceeds to block 456 as described above in relation to FIG. 4; otherwise, flow continues to block 1741. At block 1741, the sync_C-state microcode 208 generates a new instance of the Sync_C-state routine on its next buddy by programming the CSR 236 of FIG. 2 for use at block 436 or at block Π 45 (discussed below) Calculated, the 'G' value is passed to its next partner and used to interrupt the partner. This requires the partner to calculate and return a mixed state to core 106. Including blocks 438, 1739 '174: 1, 1743, and 1745 In the loop, the microcode 208 keeps a record of the partners it has visited to ensure that it visits each of them (unless the decision block 438 is found to be a real condition). Flow continues to block 1743. At block 1743, sync_C- The status microcode 208 stylizes the CSR 236 to detect that the next partner has returned a mixed C-state to the core 1 〇 6 and obtains the partner's mixed &amp; status, indicated by "F" in Figure 17. Flow continues to block 1745. At block 1745, the synC_C-state microcode 2〇8 is calculated by calculating the minimum value of the F, and %" values - the most recently calculated handle is mixed with the c state, which is represented by the "center". Flow returns to decision block 438. 94 201245948 Figure 17 does not include blocks 478 through 488. Instead, the flow continues to exit the decision block 472 "ΝΟπ branch to decision block 1777. At decision block 1777 'sync_C-state microcode 208 determines whether all of its partners have been visited', ie, whether core 106 has passed block 1778 and 1782 (discussed below) exchanges a mixed C-state with each of the partners. If so, the flow continues to block 474 and proceeds to block 476 as described above in relation to FIG. 4; otherwise, the flow continues to block 1778. At block 1778, the sync_c-state microcode 208 generates a new instance of the sync-C-state routine on the next buddy by programming the CSR 236 of FIG. 2 for use at block 468 or at block 1784 (discussed below) The calculated value is passed to its next partner and used to interrupt the partner. This requires the partner to calculate and return a mixed heart state to core 106. In the loop containing blocks 472, 1777, 1778, 1782, and 1784, the microcode 208 keep track of the records of the partners they have visited to ensure that they visit each of them (unless the decision is found to be true in decision block 472). Flow continues to block 1782. At block 1782, the sync-C-state microcode 208 programs the CSR 236 to detect that the next zebra has passed back a mixed C-state to the core 1 〇 6 and obtains the partner's 匸 匸 state. "M&quot; said. Flow continues to block 1784. At block 1784, the Sync_C-state microcode 2〇8 is calculated by calculating the minimum value of the L" and "M&quot; values - the most recently calculated local blend "weave, its fine" &quot;L&quot; Representation. The process reverts to decision block 472. As stated earlier, 'as applied to the diagram showing a hierarchical coordination model of a manager arbitration 95 201245948 to a microprocessor 1602 application, its bypass wiring facilitates At least some of the core co-attribute groups cooperate with the coordination model. This combination provides various advantages. On the other hand, the physical architecture of the microprocessor 1602 provides defining and redefining hierarchy. The domain and the resiliency of the designating and redesignating domain manager, as described in the paragraphs of Application No. 61/426,470, the application for the aforementioned application is December 22, 2010, entitled " Dynamic and Selective Core Disablement in a multi-core processor, and its non-provisional application (CNTR. 2536), which is incorporated herein by reference. In addition, on a microprocessor that provides such inter-core coordination flexibility, one of the hierarchical coordination systems can be actuated in a manner similar to the predetermined situation or configuration settings. For example, '--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- The same attribute group uses one of the temporary stalkers, or switches to a model that is used by the same-identity group. Examples of possible model switching conditions include the search for the management phase 2 = disable, the reduced manager if based on their (four) or urgency, only the source state (for example, from (4)), the next tt composite power state A brother's power state composite power state discovery process can operate before the implementation of the restricted power supply state of each core in 96 201245948 to be responsible for processor state 0.  However, the configuration and rating of the earlier narrators are also considered by the present invention. In addition, this issue = the restricted domain of the specific domain level, which is a very advanced setting of the power state, in the domain. The restricted power state of the class will be applied to the progressive higher of the processor: for example, in a multi-core multiprocessor with multiple multi-core chips, the ΓγΓ core is shared by -pll, but by micro The single-job shared by one of the processors, as explained in the C-Board, the power state hierarchy of the restricted domain can be defined to include, among other things, a core 4 (and not externally shared). The first set of power states of the resource is particularly suitable for the resources that are not shared by the outside of the wafer (for example, rainbow ', taken) (4) source type 15 and are suitable for the whole The microprocessor also has a group power state (such as a voltage health bus). Thus, in each embodiment, each domain has its own composite power state. For the mother, there is a single-appropriate authorization, such as (for example, the domain's clerk), which has the implementation or activation of the restricted power state, such as the power state hierarchy of the corresponding The definition of Rui County is the domain of Wei’s name. The advanced configuration is particularly suitable for including the A example shown in cntr·(5)4, in which the processor cores of the subgroup share the cache, pLL, and the like. The present invention also contemplates several embodiments in which the decentralized synchronization process utilizes 97 201245948, which does not require waking up all cores to not only manage the implementation of the restricted power state, but also selectively implements a restricted power state. One evokes the state or revokes. This advanced embodiment contrasts with a system similar to that of Figure 5 in which the de-setting of one of the chipsets STPCLK can completely wake up all cores. Referring now to Figure 23, an embodiment of the sync_state logic is depicted to show, for example, the conditional implementation of the selective contact-restricted operational state in the microcode. As described below, the syne-state logic 2 supports the implementation of the power state hierarchy coordination system of the domain-differentiated (d〇main-differentiated). The good news is that the sync-state logic 2300 is quite measurable because it can be extended to the hierarchical coordination system of the D_in_levd & handsome. Moreover, the logic 2300 can be used not only as a way for the microprocessor to appear to be global, but also for a particular group core of the microprocessor (eg, only for the core of a wafer, as explained below with respect to block 2342). More restrictions are implemented. In addition, the sync_state logic 2300 can be independently applied to groups of different operational states using different hierarchically coordinated systems with associated definitions, operational states of the applications, and domain level thresholds. In an implementation of an embodiment similar to the earlier display of the sync-C-state microcode 208, the sync-state logic 2300 may be generated locally or externally and in the routine of transmitting a detected state value. carried out. For example, a power state management microcode routine can receive a target operational state transmitted by an MWAIT instruction, or associated with CNTR 2534, using a local core logic for the core to generate a target operational state (eg, a request) VID or frequency ratio value). Then, the power supply bearer 98 201245948 microcode routine can store the target value as the core target operating state 〇 TARGET, and then wake up the sync-gamma logic 2300 by transmitting the 0TARGET to the probe state value 〃p. 'The * page is similar to the implementation discussed in the previous embodiment. —Curry Logic, 230() may be awakened by the externally generated (four) step requirement. For simplicity, this example is called an external wakeup instance of sync-state logic. Before moving on further, we should note that, for the sake of simplicity, Figure 23 shows that in a form suitable for managing the operational state, her logic 23 〇〇 'operational secrets are required to be progressively greater Coordination between the cores to progressively higher demand verification (for example, as in c. The way lg) is defined or arranged. It will be understood that a person skilled in the art can utilize the lying logic to modify the sync-state logic 2300 to support an operational state hierarchy (e.g., VID or frequency ratio state) in which the operational state is defined in the opposite direction. Alternatively, operational states that are defined in one direction by tradition or selection may be arranged in the opposite direction by definition. Thus the 'sync-her logic' can be applied to the operational state (e.g., the VID and frequency ratio states of the demand) only by rearranging them&apos; and applying a reference value of the opposite indication (e.g., a negative original value). We also pay attention to the fact that the marriage 23 shows that the syn-state logic 2 is designed as a strictly hierarchical association (10), and its all-inclusive group is based on a manager arbitration agreement. As evidenced by the previously described synchronous logic embodiments that may coordinate some degree of peer-to-peer cooperation, the present invention should not be construed as being limited to strictly hierarchical side secrets (except for the degree of face-to-face). 99 201245948 The flow begins at block 2302, where the sync_state logic 2300 receives the probe status value 'T&quot;. Flow continues to block 2304 where the sync_state logic 2300 also obtains the target operational state of the local core, TARGET, the maximum operational state 〇MAX that can be implemented by the local core, the largest domain level DmaX controlled by the local core, and is not involved. Or the maximum available domain-specific state MD of the external resource of a particular domain D. It should be noted that the manner in which sync_state logic 2300 obtains or calculates the value of block 2304 or the chronology is not important. Block 2304 in the flow diagram is only used to introduce the important variables that apply to the sync_state logic 2300. Other core coordination on his package, if any, and so on. The maximum applicable domain-specific state Md is: m = In an exemplary but non-limiting embodiment, the domain level D is defined as follows: single core is 〇; multi-core wafer is]; multi-chip package For 2, and so on. The operational states of 〇 and 1 are unrestricted (meaning that a core can implement them without coordination with other cores), and the operational states of 2 and 3 are limited by the core of the same chip (think they may be - The core of the crystal is implemented on the other cores, but not in coordination with other cores on other crystals, and the operating states of 4 and $ are related to the phase. Limited at the core of the body (meaning that they may be implemented on the body after d weeks of the core of the package, but need not

〇max; wafer manager core 100 201245948 The heart will have a Dmx of 1 and a corresponding maximum self-executable operating state 〇max; and the package manager or BSP core will have a maximum of 2 DMAX and 5 Self-executing operational status. Flow continues to block 2306 where the Sync_state logic 2300 calculates an initial collocation value &quot;B&quot; which is equal to the detection value 叩" and the minimum value of the target operating state OTARGEt of the local core. And 'if P is received by a subsidiary family core and its value is less than or equal to the maximum applicable domain-specific operational state (the family core is implemented as credentials accordingly)' based on the logic described here, This generally means that an affiliated family core seeks to revoke any potential interference sleepier state imposed by the core of a local or higher class. This is because in the general configuration, the affiliated family core has been implemented with a more sober p-like L relative to its ability, and it cannot be unilaterally revoked without a higher level of coordination. The interference performed by the controlled domain is easier to sleep. Flow continues to block 2308 where the d or hierarchical variable 〇 is initialized to zero. In the example shown above, a D of 0 represents a core. Flow continues to decision block 2310. If D is equal to Dmax, then flow _ to block 2340. Otherwise, the flow continues to decision block 2312. For example, in a non-official core, syne-_f 2: wins without the need for a machine (four) paper_any__ to = 1 for the logic displayed between blocks 2312-2320 is provided A manager's core conditionally synchronizes the core of the affiliated family. Regarding the other example, if the chip manager core does not have other manager credentials, then its D_x is equal to 丨. Initial: Heart 101 201245948 is 0, so a conditional synchronization process may be implemented on other cores of the wafer in accordance with blocks 2312-2320. However, upon completion of any such synchronization (assuming that it is prematurely terminated according to decision block 2312) and D has been incremented by one (block 2316), the flow will continue (via decision block 2310) to block 2340. . Moving to decision block 2312, if B&gt; MD, the flow continues to decision block 2314. Otherwise, the flow continues to block 2340. Stated another way, if the mixed value B currently calculated by the local core does not involve or interfere with the external resources of the domain defined by the variable D, then there is no need to synchronize with any more affiliated family cores. For example, if the currently calculated mixed value B is 1, such a value indicates that it only impacts local resources located in a given core, so there is no need to synchronize with more affiliated family cores. In another example, the local core is assumed to be a friend core with sufficient credentials to close or impact resources common to multiple chips. It is also assumed that the currently calculated mixed value B of the friend is 3, which is a value that will only impact the local resources of the other wafers managed by the friend's wafer rather than the friend. Also assume that the buddy has completed synchronization with each of the cores on its own wafer in accordance with blocks 2314'2318 and 2320, thereby increasing the variable D to one (block 2316) and taking the new Md = Mi = 3 into consideration (block 2312). ). Under these circumstances, the buddy does not need to be further synchronized with the core of the affiliated family (such as a companion) on other crystal moons, since the implementation of friends of 3 or less values will not affect other chips anyway. Moving now to decision block 2314, the sync_state logic 23 evaluates whether there are any (more) affiliated cores that have not been synchronized in the domain defined by D+i. If there is any such core, then flow continues to block 2318. If not, then 102 201245948 The flow first proceeds to block 2316 (where D is incremented), and then to decision block 2310, where again the value of the currently added D is evaluated again, as described above. Now move to block 2318, because an unsynchronized dependent family core has been sided (block 2318), so it may be affected by the currently calculated blend value "B·, the implementation (block, 2312)' because it will affect A resource shared by the core of the attached family, so the local instance of the synC_face logic 2300 wakes up a new slave instance of sync_state logic 2300 on the unsynchronized dependent family core. The local instance transmits its currently mixed mixed value ''B "As a dependent instance of the sync_state logic a · - the detected value. As seen by the logic of the sync-state logic, the dependent instance will eventually return - not greater than the original, 'B' (block 23〇6), and not less than the largest applicable domain of the attached family core. a value of a particular state Md (block 2346) that does not interfere with the maximum value of any resources shared between the local and the attached family core. Thus, when the flow continues to block 2320, a local instance of the sync-state logic 2300 The value returned by the dependent instance is taken as its own "^, value. Until now, the focus has been directed to one of the sync-state logic 2300 that conditionally synchronizes the core of the affiliated family. Now, focusing on blocks 2340-2348, which illustrate the logic for performing a target and/or synchronization state, including conditional coordination with the more advanced steroid cores (i.e., higher level managers) . Moving now to block 2340, the local core executes its current blend value "B" to the extent that it is acceptable. In particular, it performs the minimum of B and is executed by the local core. We may note that, in relation to the core of the domain manager, block 2340 103 201245948 design this _ 仙 纽 纽 — — 复合 复合 复合 复合 复合 复合 复合 复合 复合 复合 复合 复合 复合 复合 复合 复合 复合 复合 复合 复合 复合 复合 复合 复合 复合 复合 复合 复合 复合 复合 复合 复合The implementation of the power state (ie 〇MAX). The flow continues to decision block 2342, where the __ logic 23 〇〇 evaluates whether the local core is the BSp of the microprocessor. If so, there is no more advanced core to coordinate, and the flow continues to block. If the shirt, Lin Cheng continues to decision block 2344. We should note that 'in her embodiment, 5 her logic is used to control the operation in a way that is less than a gbbal way. 4 'block 2342 is in a predetermined group. The operating state is related to the "highest application domain official" &quot;replacement''BSP&quot; and changes. For example, if the sync_state logic 23〇〇 is only applied to the desired frequency of the pLL shared by the chip as explained in CNTR.2534 Among the clock ratios, it will be replaced by &quot;chip manager," BSpi. In decision block 2344, the Sync_state logic 2300 evaluates whether the sync__state local instance is awakened by a manager core. If so, the local core is synchronized with its manager by definition&apos; so the flow continues to block 2348. If no, the process continues to block 2346. Moving now to block 2346, sync_state logic 2300 wakes up a slave instance of sync_state on its manager core. It transmits the maximum value of the core's final blend value B and the core's maximum applicable domain-specific state MD as the last detected value p. Two examples are provided here to illustrate the choice of the detected value P. In the first example, it is assumed that B is higher than the maximum self-executable operating state 0MAX of the local core (block 2340). In other words, in the absence of higher level coordination 104 201245948

Under the circumstance, the local core cannot unilaterally lead to the singularity of B. In such cases, Box Li represents the local core's request for its manager's core, requiring it to be implemented more fully, if possible. We will use the logical set proposed by _ _ _ 23 if the request is not with the manager as its own target status and with other potential influences of the state of the state (four), (four) the core will refuse this please The ruler will implement this request and reach the extent to which it corresponds to those states, the maximum value of the straightforward tree's maximum self-determination g Q_ (block 2340). According to the square 2346, the value of the BU (which can be equal to the B value of the original kernel) of the beginning of the core of the city is to request its own higher core (if any). In this way, if the application conditions are met, the sync_state logic 2300 will fully implement the final blend value B of the local core. In the second example, it is assumed that B is less than the maximum self-executable operational state 〇max of the local core (block 2340). Assuming that there is no higher interfering operational state other than the resources controlled by the local core, then in block 2340, the local core can fully follow B. However, if the higher interference operation state is in effect, the local core will not be able to unilaterally revoke the interference operation state. In this case, block 2346 represents the local core requesting one of its manager cores to require it to revoke an existing interfering operation state to a level that no longer interferes with the full implementation of B (ie, the local core's largest applicable domain) - Specific status MD). As will be appreciated, in accordance with the logical set proposed in Figure 23, the manager core will comply with the request to implement a state of MD that is no larger than and possibly less than the local core. We should note that block 2346 may or request 105 201245948 The administrator only implements B. But if B&lt;MD, this may allow the manager core to perform a more awake state than the local core needs to fully implement B. Therefore, it is preferred to use a detection value that is equal to the maximum value of the final mixed value B of the local core and the maximum applicable domain-specific state MD of the local core. Therefore, we will understand that sync-state 2302 supports a minimalist approach to both dormant and evoked states. Moving now to block 2348, sync_state logic 2300 passes a value back to the call or executes a procedure equal to the maximum of the core's final blend value 3 and the core's maximum applicable domain_specific state md. As illustrated by block 2346, we have noted that block 2348 may or may just return the value of b. But if Β &lt; Μ〇, then this may cause a awake core (block 2318) to perform a more awake L than is needed. Therefore, it is a better choice to return the final mixed value B of the core and the maximum applicable domain-specific state Md of the core. Furthermore, we will understand that in this manner sync-state 2302 supports a minimalist method for implementing both the sleep state and the evoked state. In another embodiment, one or more additional decision blocks are interposed between squares 2344 sk. * 2 and 6 to further set the condition of block 2346 for dependent synC-State and %. For example, under a suitable condition, if =, the process will continue to block 2346. Under another suitable condition, if only one of the interference states can be applied to the local core, then the flow will continue to block 2346. If both of the applied conditions are applied, then the flow will continue to block 2346. In this way, sync—she fiber 106 1064545945 supports a method for implementing the brewing state. In detail, we should observe that this alternative embodiment assumes that the local core can be applied to an embodiment of the local core non-energy side-interference operation state, as depicted in Figure 23. A lesser implementation method is preferred. . It will also be understood that in Figure 23, when it is necessary to implement a deeper operating state ^ or its _ type), the composite operating state is _ domain dependent - the species is as low as the most (or close to the most The order of the same attribute group that is far away is to search for the core level of the highest level domain (which contains its nested domain) in a progressively and more frequently-seeking order, and does not require financial correction. Affected by the target operating state. In addition, when the s Wei line - the _ operation state, the composite operation status _ process only needs to continue to search for a higher manager. Moreover, in the alternative embodiment described above, this extension of the search is to the state of the interfering operation currently implemented (if needed). Therefore, in applying the earlier example to Figure 23, the target 2 or 3 restricted power state will only trigger the core process in the application chip. (4) The target will only be the _ (four) composite power state discovery process. Figure 23 can further describe its features in a domain-specific (except core-specific) manner. Continuing the above illustrated example, - (9) can have an adaptation of 2 and 3 - a look-a-source state. For example, if the 电源(5)f face is found to be difficult through a local or external singular composite electric state, it is found that the composite power state of the crystal moon itself is only 1 because i is not a versatile domain. State, 107 201245948 It is expected to implement it. If the w management face is found to be connected to the core, the green state is 5 (or the composite state of the wafer and the state of the node = = = the state of the mixed state is equal to 5) as an alternative example and if the S is the core of the official Does not have any higher manager's credentials, then (assuming it does not do so) 曰h total strength can be the heart of the core # ^理者 core will be the real side of the power of 3 /, the system is 3 (the largest field of the chip • The minimum value of the specific power state) phantom (the composite power state of the wafer or its mixed state). Furthermore, I I noticed that in this solution, "manager nuclear" Jing _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ ) What is the actual or partial composite power state (for example, 4 or 5). Continue with the above _ 'The controller found that the wafer composite power state or its mixed state is 5, "the manager will start with the system - The composite power state discovery process, which will need to include the search for the next higher level domain (eg, the package or the entire processor), which is side-by-side (9) intermediate implementation of the manager (if any) In addition to the electrical state of the wafer. This is because 5 is greater than 3 ("Maximum Range_Specific Power State"), so the implementation of a higher restricted power state needs to depend on the power state applied to one or more higher-level domains. In addition, down-her High-level domain-specific—highly enforced _ power state implementations may only be initiated and/or implemented by the domain administrator (eg, multi-package processor package manager or single-packet processing) It is worth reminding that the chip manager may also maintain the relevant package manager or 108 201245948 BSP certificate. Therefore, in the above example t, at some point in the discovery of the financial, the chip manager core will Exchange with the peers the composite electrical status (or its age). Under certain conditions, this discovery process will pass the higher-level (eg, package)-at least partial composite power state (which is less than 2) Going back to the chip manager core. Again, this will not cause the power state of 3 to be revoked, which is the chip manager core that has been implemented for the chip. Under other conditions, this discovery process will be on the package or micro Shame-composite power state (eg 4 or more), which corresponds to 4 or more restricted power states. If it is ' then the domain manager (eg package manager) will implement - compare A highly restricted power state, which is the minimum of the composite power state (age 4 or n5) of the higher level domain and the maximum restricted power state (here 5) applied to the higher level domain. The discovery of the application _ is testing a more advanced restricted power state' then this conditional domain_specific power_state implementation process will extend to a more advanced domain level (if any). As mentioned above, Figure 23 shows a hierarchical domain that is operable to incorporate domain-dependent embedding power states and associated thresholds. _Specific Restricted Powers, Responsibility, and Threads, which are appropriate for side cores and groups. Fine-timed domain-specific decentralized approach 〇 人 注意到 图 图 注意到 注意到 注意到 注意到 注意到 注意到 注意到 注意到 注意到 注意到 注意到 注意到 注意到 注意到 注意到 注意到 注意到 注意到 注意到 注意到 注意到 注意到 注意到 注意到 注意到 注意到 注意到 注意到 注意到 注意到 注意到 注意到 注意到 注意到 注意到 注意到 注意到 注意到 注意到 注意到 注意到 注意到 注意到 注意到 注意到Logic. However, we will understand that some power state embodiments contain several power states, and in the absence of a chipset or other core, the "power" can not be powered from this power supply. The state is evoked. For example, in the above c_state structure, the state of 2 or higher may be removed from the tree, and the command may be transmitted through the system bus. , _ Wei Wei - clearer _ consumption. Power supply or clock source optional miscellaneous from the - the nuclear film is removed its recording processor configuration is also considered. ® 5 Gangjue series - the real customs to take care of these flights , by waking up all core switches STPCLK release settings. However, more selective embodiments of Weiluohong can be considered. In the case of an example, consider the (4) awakening logic implemented by the software (such as the operating system or the BIOS), where (4) the software will be released first - evoke or rush to ask for pleasure, and if within the time interval of the ship Not receiving - responding or if not complying, then will release the caller awakening request to the higher manager and chipset (possibly) as needed, until an expected response or detection is received Until appropriate compliance. This awakening logic executed by the software system coordinates the power-mode of the flip-flop 23, and the priority is the dispersion mode (where the core of each target starts to transform by using its own microcode). To achieve a clearer state, to reach the extent that it is operational, to do this, and when the core is prohibited from doing so, the embodiment of the awakening logic is done in a centrally coordinated manner only to selectively evoke the inability to evoke Description and illustration of several possible embodiments of their own core. VI. Extended Embodiments and Applications Although it has been said that there is a specific number of private 106s, it can be considered as "other embodiments of the number of cores 106. For example, although Figures 1 and 13 are 201245948 and 17 The illustrated microcode 208 is designed to perform distributed power management between the eight cores, but the microcode 208 has a more inclusive by including the presence or absence of the check core ι 6 Appropriate utility in systems with fewer cores, such as those described in paragraphs 61/426, 47 of the application, the application for the aforementioned application is December 22, 2010, the name is • Dynamic Multi-Core Microprocessor Configuration π, and its non-provisional application (CNTR2533), which is applied at the same time, reveals that the book is affiliated with it. That is, if a core 106 is absent, then micro Code 2〇8 does not exchange C-state information with absent core 106, and effectively assumes that the state of the absent core is the highest possible C-state (eg, c. state of 5, therefore, in order to achieve manufacturing efficiency) 'Core 1 () 6 can Can be manufactured with microcode passes, which is designed to perform distributed power management between the eight cores, even though the core should probably be included in a system with fewer cores 106. Again, considering that the system contains eight The above nucleus. The microcode system described here is extended to communicate with those methods similar to those already mentioned (10). Through the foregoing description, the systems of Figures 9 and η can be Amplification to include 16 cores 106 with eight companions, and the system of Figure (1) can be augmented to include π cores 106 with four friends, similar to the systems of Figures 9 and U in four companions A method of synchronizing c-like w between, and the system of Figure 16 can be by having 16 partners (two wafers and each wafer having eight cores, or four wafers and each wafer having four cores) The features associated with the method of augmenting 16 cores, _ 4, 1G, 13 and 17 can also be integrated. ΙΠ 201245948 Independently implement different levels of power state (eg, C-state, p_state, demand) VID, frequency axis rate of demand, etc.) Embodiments are also contemplated. For example, 5' each core may have different application power states for each level of power state (eg, respective application VID frequency ratios, c_states, and p_states). , having a fixed (4) localization, and a rib-calculated mixed state sub-discovery composite state (eg, the minimum value of the C-state to the minimum of the requested VID maximum). Different hierarchical coordination systems ( For example, different domain depths, different domain members (d〇main c〇nstituencies), different designated domain managers, and/or different homogeneous group coordination models may be established for different levels of power state. In addition, some power states may only require more than one of the other cores on the -domain (e. g., wafer), which contains only a subset of all cores w on the microprocessor. The hierarchical association (10) considered for this type of electromorphism may be that only nodes are connected to the 5 domain, coordinated with the core within the domain, and found to be applied to or within the domain. Composite power state. - Generally speaking, 'all operational states indicated by the implementation of the scarf are progressively ascending or descending' and are the basis of the strict and linear sequence of the domain, that is, the operational states are arranged in a foed and in sequence Other embodiments of the mine ((4) which can be ordered by ascending or descending type (the embodiment in which the number of layers is independent of the other layers) are also considered by the present invention. The power state of the predetermined group can be The composite form of different levels AB ' ABC ', etc. describes the succession, where each layer A, B, C is related to a different feature or feature level. For example, a power state may be a composite form of CP or PC. Describe the characteristics, where p denotes - Π 2 201245948 AO ^ - state ' and C denotes - Accic• state. Furthermore, the level of the restricted power state may be the specific composition of the Wei state (eg a or b) Or (7) is defined by the link, and the off-source H-class can be defined by the value of the hybrid definition power supply h. In addition, in any given restricted power state, each layer corresponds. In the mixed definition of the power state - one of the components Values (such as CP), except for the limits imposed on this layer, for a given core, the value of another component (such as P in CP) may be unrestricted or subject to different levels. For example The core of a target power state with Cp may be subject to the respective restrictions and coordination requirements for the implementation of the C and P parts of its target power state, where P represents its p_ state and c represents the c• state of its demand. In a composite power state embodiment, for a given core of a calculated extreme value, the "extreme value" of any two power states may represent a composite state of one of the extreme values of the components of the composite f' source state, or The composite power state is less than one of the extreme values of all components, and is selected or determined by other methods (and for other components). Also, multiple cores 100 perform allocation in a system. Embodiments of decentralized power management to explicitly perform the power evaluation (p〇wer credit) functionality are also contemplated, as illustrated in U.S. Application Serial No. 13/157,436 (CNTR.2517), the application of It is incorporated herein by reference in its entirety, the entire disclosure of which is incorporated herein by reference in its entirety in its entirety in the in the in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in in A shared memory area. The advantage of this embodiment is that it is for the system firmware (such as BIOS) and the system software is 113 201245948 = and does not require the body or software to provide a shared memory. = Because the microprocessor manufacturer may not necessarily have the control to make this force, it is popular. A synchronous logic embodiment that transfers other values in addition to the * is also considered. In one embodiment, with respect to any other simultaneous operation discovery process, the time-of-day transmission may (4) confirm that the discovery has been recorded (which is part of the discovery process). In another implementation, the synchronous routine transmits a value by which the synchronized or unsynchronized core can be identified. For example, the (10) heart embodiment may describe an 8-bit value, where each record element "core-specific core, = bit indicates whether the lake step or the ship is still One part of the process. The synchronization routine may also transmit a value that confirms the beginning of the instant discovery process. 0 曰 Promote the implementation of the additional embodiment of the synchronization of the Wei-Touch, which is also used in the example, each The core store confirms that the member's bit masks the same attribute group (it is part of it). For example, in the three levels of deep hierarchical _ construction of the eight-core shouting towel, every heart Store three octets &quot; the same as ^ occlusion, - "closest, sexual occlusion, - the second layer of smear occlusion and the top layer with the same attribute occlusion" where the value of each occlusion bit is confirmed to belong to the occlusion table The core family (if any) in the same attribute group. In another example, each; L stores a map, a (10) e丨 number, or a combination thereof, which can correctly and uniquely determine the core, the node level, including the confirmation of each domain manager. In yet another example, the core store identifies shared resources (e.g., power__, clock source with 114 201245948 and cache), and information about the particular core or corresponding domain to which they belong and share. In addition, we are expected to use the above-mentioned order (10), each of the bribes, and other types of (4) and restricted activities, rather than just status information related to power status or power supply. For example (4), in some implementations, the above-mentioned various hierarchical cooperatives use the decentralized logic on each core to coordinate with the dynamic discovery, such as in CNTR.2533 - multi-core microprocessor configuration, For example, as described above. In addition, it should be noted that the invention does not require the use of any of the above-mentioned methods of mineralization (10) and the predetermined limits of movements unless specifically stated otherwise. In fact, the invention is suitable for purely peer-to-peer coordination between cores unless there is some other degree of special provision. However, as is apparent from this description, the use of a hierarchical coordination system can provide several advantages, especially when relying on bypass communication, because the structure of the microprocessor bypass communication line is not Allow a fully equal peer-to-peer coordination system. As can be observed from the above, compared to, for example, the above-mentioned Naveh continuation including centralized non-core hardware coordination logic (HCL), the crane function is equally distributed among the distributed implementations of the core 106 described herein. For example, the benefit is that no additional non-core logic is required. Although non-core logic can be included in a wafer 1 〇 4, what is required in the illustrated embodiment is the implementation of a decentralized distributed power management mechanism 硬 hardware and microcode system and multi-core _ per wafer ( Multi_c〇re_per_die) inter-core communication wiring in the embodiment, inter-chip communication wiring i丨8 in the multi-wafer embodiment, and inter-package communication wiring 1133 in the multi-package embodiment together, completely 115 201245948 entity Up and logically within their own core 1〇6. Because of the results of the distributed embodiments of power management assigned between the multiple processing cores 1-6, the cores 106 may be located on individual wafers or individual packages. This potentially reduces the size of the beta wafer and improves yield, provides more configuration flexibility, and provides the ability to adjust the size of the core in a high-level system. In still other embodiments, the cores 1-6 differ from the representative embodiment of FIG. 2 in various implementations and provide a highly parallel configuration that is superimposed, such as applied to a GPU. The coordination system used for various operations (such as power state management, core configuration discovery, and core re-planning) can also be applied. Although various embodiments of the invention have been described herein, it should be understood that Familiarity _ Computer Technician will make various changes in form and detail without departing from the scope of the present invention. For example, the software may permit functions, manufacturing, simulation tests, simulations, instructions, and/or defects of the devices and methods described herein. This can be achieved by using a general programming language (e.g., C, C++)&apos; containing Verik)g HDL, VHDL, etc., hardware descriptions (HDL) or other cloakable programs. Such software can be deployed in any known computer usable medium, such as a semiconductor, disk or optical disc (e.g., CD-ROM 'DVD-ROM, etc.). Embodiments of the apparatus and methods described herein may be included, for example, in the semiconductor intellectual property core of the microprocessor core (e.g., embodied in the HDL) and changed to hardware in the product of the integrated circuit. In addition, the devices and devices described herein may be embodied as a combination of hardware and software. 116 201245948 The present invention should not be limited by any of the illustrative embodiments described herein, but should only be applied to the domain and the quilt. And the body f, this hair can be used in the micro-processing H device that may be used in the computer. Finally, the applicants should understand that they can easily use the disclosed concepts and specific examples as the basis for designing other structures of miscellaneous changes, so as to solve the problem without turning away from the (four) towns. The same purpose. F7G into a simple description of the figure ^ Figure 1 is a block diagram of an embodiment of a computer system, computer system: Ding knife is placed between the multi-processing core of the - dual-chip quad-core microprocessor Figure 2 is a block diagram showing the core of the figure represented by Figure 1. Figure 3 is the management of the core of the multi-core (four) period. Figure 4 is a flow chart showing the operation of the composite power state discovery process of the integrated power of 3, which is the embodiment of the power state synchronization routine. - The core operation flow wave ^5 tr - evoke and restart the normal formula should be from - sleep state will wake up - view - a fine m called the flow chart. 圏 6 is the display - core interrupt processing routine In response to receiving a core room 117 2012459 Figure 48 is a flow chart showing an example of the operation of the composite power state discovery process according to the description of ® 3 to 6. Figure 8 is a diagram showing the operation according to Figure 3 6 is a flow chart of another example of the operation of the composite power state discovery process. FIG. 9 is a block diagram showing another embodiment of the electronic system, and the computer system performs the allocation in the i-core (10) processing ^ ( Decentralized power management between multiple processing cores with four dual-core chips on a single body. Figure 10 shows the power state synchronization routine for the composite Wei state discovery process integrated into the system of Figure 9. Figure 1 is a block diagram showing another embodiment of a computer system that is distributed between multiple processing cores of an eight core microprocessor. The distributed power supply principle, the eight core microprocessor has four dual core chips, which are distributed on the two packages using the power state synchronization routine of Figure 10. Figure 12 is another display of a computer system In the block diagram of the embodiment, the computer system performs distributed power processing disposed between multiple processing cores of an eight core microprocessor, according to a deep hierarchical coordination system, the eight core microprocessor has four as shown in FIG. Dual core chips, but the cores are not related to each other as in Figure 11. Figure 13 is a diagram showing one embodiment of a power state synchronization routine for one of the composite power state discovery processes integrated into the system of Figure 12. Flowchart of operation by a core. 118 201245948 FIG. 14 is a block diagram showing another embodiment of a computer system that performs distributed power management distributed between multiple processing cores of an eight-core microprocessor. According to a deep hierarchical coordination system, the eight core microprocessor has four dual core chips on a single-package like Figure 9, but the cores are not related to each other like Figure 9. Figure 15 is a block diagram showing another embodiment of a computer system that executes between multiple processing cores of a human core microprocessor (which has two quad core chips on a single-county) Decentralized power management. Figure 16 is a block diagram showing yet another embodiment of a computer system that performs distributed power management distributed between multiple processing cores of an eight core microprocessor. Figure 17 is a flow diagram showing the operation of the core-integrated power state synchronization routine of one of the systems of Figure 16 - a core state operation. The diagram is a block diagram showing another embodiment of a computer system in which the computer system and the money are distributed among the cores of the dual-core and single-chip microprocessors. Knife Figure 19 is a block diagram showing yet another embodiment of a computer system for dispensing a split electric raft between two dual core micro-chips having two single core chips. The core diagram 20 is shown as another embodiment of a computer system. The implementation of the distribution of the right eye + the electrical display shows that there is two single core, one of the single chip packages, the core of the dual core 119 201245948 Decentralized power management. Figure 21 is a block diagram showing still another embodiment of a computer system. The computer is a distributed power management between the core of the eight-core microprocessor and the eight-core read processing. The device has two packages, one with three dual core wafers and the other with a single dual core wafer. Figure 22 is a block diagram showing yet another embodiment of a computer system that performs distributed power management distributed between the cores of an eight core microprocessor, the eight core microprocessor being similar to Figure 21, but Having a deep hierarchical coordination system 0 FIG. 23 is a flow diagram showing another embodiment of operational state synchronization logic implemented on a core that supports a domain-differentiated operational state hierarchy coordination system And it is measurable for different domain depths. [Description of main component symbols] P, P1-P8: pins 100, 900, 1100, 1200, 1400, 15〇〇, 1600: computer systems 102, 902, 1202, 1402, 1502: multi-core microprocessor/package 104. Wafer 106: Core 108: Contact Pad 112: Intercore Communication Wiring 114: Chipset 120 201245948 116: Busbar 118: Communication Wiring 202: Instruction Cache 204: Command Decoder 206: Micro Sequencer 207: Microcode Memory 208: Microcode 212: Registration Alias Table (RAT) 214: Reservation Station 216: Execution Unit 218: Retirement Unit 222: Data Cache 224: Bus Interface Unit (BIU) 226: Phase Locked Loop (PLL) 228: BSP indicator 232: manager indicator

234 ' 236 : CSR 238 : Special Module Register ( MSR ) 242 : Core Clock Signal 1102 : Four Cores : Processor 1133 : Inter-Package Communication Wiring 1201 : Second Package 121 201245948 1504 : Wafer 1602 : Multi-core microprocessors 1802, 1902, 2002: dual core microprocessor 2202: eight core processor 2300: logic 2302: sync-state 122

Claims (1)

201245948 VII. Scope of application for patents: 1. A multi-core processor, comprising: a plurality of activated entity processing cores; 〇 shared, the shared resources of the towel can utilize the electricity-configurable resources that can be operated by the two The configuration of such core sources affects the core source, speed or efficiency of sharing the resource, and for each core, the internal core power state management logic two tree is implemented between the cores Shape t found face, and money needle _ heart logic assistance: ', where 'the core power management of the domain is in the core. Among them, if the core is set for the purpose of setting the configuration of the shared resource - The core of the administrator, and the composite target power state is discovered through the inter-divided power state discovery process, the job power management logic = setting the core configuration to drive the implementation of the target power state of the configuration setting the shared resource; Let 5 set the 'complex target power state' as the most energy-efficient power state for the shared resource, which will not interfere with each core sharing the resource. Ho ^ corresponding target power state. For example, the multi-core processor described in claim 1 of the patent scope further includes a plurality of bypass communication wirings that do not connect the core to the group-system bus bar and are in the heterogeneous core, and the shirts thereof The decentralized nuclear source state process passes through these bypass pass-through lines, and carries a number of power state values that are exchanged for the cores to be exchanged for 2012. The multi-core processor of claim 1, wherein the target power states are C-states; the shared resources are shared by all cores to the wafer bus; and the system The manager core obtains exclusive rights in coordination with the chipset to perform one of the C-states of the streamer operation. The multi-core processor of claim 1, wherein: the shared source is a voltage source shared by at least some of the cores; the target power state is determined by 1 ·Change the commonality of the family (four) heart - _ quasi 5 of the multi-core processor as described in claim 1 of the patent scope, Yizhong. At least some of the cores are shared,; The clock ratio signal representation; and the official core exclusive of the plurality of clock ratio demand signals, which are sent to: cause a change in the pulse frequency provided by the clock source; -h U at time 6, as claimed in the multi-core processor described in the patent Na, and in the total: f only single - one is designed to drive the purpose of the composite power supply is specified as The core of the manager; and 124 201245948 These cores contain programmable logic, which can be set by the first software to be used: 增加 to increase or remove the purpose of setting the shared _'_孑日疋0 7 If you apply for the multi-core processor described in item 6 of the patent scope, (4) within (10): the source of the official logic is arbitrarily, and the correction is shown as the manager. The multi-core processor as described in the patent application scope w: the state is one of a plurality of predetermined power states, the power supply tube = the top of the predetermined power supply The state is contained in the internal influence of the second and second - at least the unshared resources - the unrestricted power supply = mother na (four) Well, the phase wheel lion domain is used in the case of adjustment - the local core target power state, if the eight systems are - If it is not the power state of the system. 9, := Γ range of the multi-core processor described in item 1, wherein the power state == turn_frequency (four) fine money such as the power supply of the heart ^ to respond to the transition into one of the configurations that will set the shared resource Target power state - demand. 10, (4) Please refer to the multi-cores described in the patent lang ^ item = rational: set each core configuration Qin type external = type core power state discovery _. Shenyue Patent|&A multi-core processor as described in item 1, wherein - decentralized 125 201245948 inter-cardiac power state discovers the process of micro-powered cancer and contains the same core code in the core m-state process An instance of side money, which participates in the exchange of multiple cores is executed. 12. The multi-core processing n as described in item 11 of the (4) patent scope, each instance of the microcode of a given core and f-wire, and another core-to-core-power state; Wherein the local instance is calculated according to at least two of the following values - the hybrid power state: the local core target power state, if any, - received by the implementation process - the detected power state value; and the inter-core power supply The state discovery microcode - the slave real instance returns a power state value. 13 A multi-core processor as claimed in item n of the patent scope, wherein the decentralized inter-core electrical status discovery touches a Pu (4) power supply, and the _-type path in the (four)-cylinder listening core == "Using: other cores of Beiyuan, recursively implement and synchronize the subordinate instances of the microcode between the core power states. 14. Distributing methods for managing power states of the multi-core processing (4), the multicore The processor has a multi-tilted physical core (four) and a resource shared by at least some of the cores, the method comprising: - the core receiving affects a configurable resource shared between itself and at least one other core - Local, such as the target power state, its local core target power state definition will be shared with the resource. The cores are configured with one of the resources of the power, speed or efficiency in which they can operate; 126 201245948 , &gt The process of discovering the core with the core, including the non-nuclear non-nuclear, not sharing the resources of at least _ other cores of electricity = sorrow - exchange; and = core system for the purpose of (four) sharing The purpose of the configuration of the source is designated as an official core 'and the composite target power state is found through the decentralized core power supply tree, then the fourth (four) set the purpose of the shared resource Driven - the realization of the composite target power state; its ▲ medium (4) source, the composite target power supply is the most power state in the month b, it will not interfere with each core sharing the resource Any corresponding target power state. The method of claim 14, wherein the method of participating in the inter-core power state discovery process is carried out via the eve of the core gates of the core gates, wherein The bypass communication wirings are connected to the cores of the cores, and the busbars are different, and wherein a plurality of power supply systems exchanged between the cores are exchanged through the bypass communication wirings. For example, the method described in the patent application is as follows: wherein: the target power states are C-states; &quot;, using the source system, all cores, sharing and connecting to one of the H groups of system busses ; and »hai g The core is deducted from the exclusive right of the chipset to perform a C-state that affects one of the operations of the sink. 17. The method of claim 14, wherein: 127 201245948 the share I Originally represented by at least some of the cores - a voltage source; a target electrical state - a demanding electrical variable; and a plurality of voltage change demand signals of the manager's core age, which are sent to the A method of claiming a change to a level of one of the cores of the source. 18. The method of claim 14, wherein: the shared resource is At least some of the cores are shared by the clock source, a target power state is represented by a - demand (four) pulse ratio signal; and the manager core monopolizes more money, which is sent to the clock source' It will result in a change in the clock frequency provided by the clock source to the cores sharing the clock source. 19. The method of claim 2, further comprising: discovering the private state by participating in the power state between the cores implemented by the other core, and verifying that the core is found and driven to set the shared resource. The configuration of one of the composite target power states is implemented. One of the physical cores of the processing core is encoded in the computer readable storage medium _ 'The m contains (4) executes the following code. Receives a set of configurable resources shared by more than two of these cores And multiple configurations of the East &lt;&gt; shared resources affect the power, speed, or efficiency with which the cores sharing the resource can operate; participate in the distributed core power supply of the core implementations State discovery process without the assistance of centralized non-core logic; and 128 201245948 If the "Xuan core" is designated as an official core for the purpose of setting the configuration of the shared resource, and the composite target power state is via The decentralized inter-core power state discovery process was discovered, and the configuration of the core was designed to drive the configuration of the composite target power state for the sigh of the configuration of the shared resource, which: 'for the co-time source In other words, the composite target power state is a power state of the ready-to-use type that will not interfere with any corresponding target power state of each core sharing the resource. 21. A multi-core processor, comprising: a plurality of processing cores; and a core-to-core status gambling code, in each of the _ heart towels, for not traversing any centralized non-core logic, and The core receives or communicates to other cores to participate in the distributed inter-core state discovery process. 22. The multi-core processor described in item 21 of the patent scope, wherein: The inter-core state discovers the microcode, exchanging signals with other cores via multiple bypass communication wires independent of the multi-core, processor-to-wafer-system bus; and the inter-core state discovery microcode Judging with the assistance of any centralized non-core logic - the available state value, its system-function, at least one state of the other core. 2:3. The multi-core processor as described in claim 21 of the patent scope, wherein: the inter-core state discovery micro-matrix includes synchronization logic provided to each core thereof 129 201245948 has a synchronization example for a core room A plurality of purposes of the state discovery process are operable to be implemented on multiple cores; and wherein each local real___ implements a plurality of new instances of the synchronization logic on its heartbeat, and the response is implemented on the local instance Any previous instance of the synchronization logic on another core. The multi-core processor of claim 23, wherein: each core has a target operational state; The processor includes a field that includes at least one of the cores of the microprocessor - I&quot;*, the processor provides - resources to the field, the resources of which are shared by the cores of the field; the synchronization logic Is configured to discover whether the field is ready to implement a limited power-saving operational state for the resource to limit the power, speed, or efficiency with which the cores sharing the resource can operate; and wherein the field is prepared In the case of a real-life limited power save operation state, if it is for each start core that shares the resource in the field, there is at least a restrictive target operating state as the restricted operational state. 25. The multi-core processor of claim 24, wherein: the _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The core; and the restricted operational state is a C-state that disables the system from sinking one of the bus clocks. 130 201245948 26. The multi-core processor of claim 24, wherein: the shared resource is a phase-locked loop on a guest of the microprocessor; the field includes all startups The core, the clock signal is supplied by the phase locked loop; and 受限 the limited operation mode H can share a lower than maximum performance frequency ratio used by the core such as the phase locked loop (4). 27. The multi-core processor of claim 24, wherein: the shared resource is a voltage resource; the field includes all and is limited to a total (10) voltage #_ the startup core of the microprocessor; and the limited The operational state is a level below the maximum performance voltage level that can be used by the core of the pie resource. 28. The multi-core processor of claim 24, wherein: each instance of the synchronization logic is configured to 'unless terminated by a termination condition to recursively implement the synchronization on other cores Multiple instances of logic until a synchronized instance of the synchronization logic has been implemented on all cores of an available domain of the processor; and wherein the synchronization logic is configured to stop on other unsynchronized cores with a termination condition Implementation of an instance of synchronization logic if it finds that a core has a target operational state that is less restrictive to the limited power-saving operational state; 131 201245948 where the synchronization logic (4) is coordinated - the other core of the minimum thief It is used to discover that the Lai (4) field is ready to implement the _ limited power saving operation state. 29. A multi-core processor as described in paragraph 23, wherein: each core has a target operational state; 4 processor includes a 'domain, which includes at least the second of the core of the microprocessor; The processor provides the f source to the field, and its resources are shared by the cores in the field; the synchronization logic is configured to: discover whether the domain shares the boot core of the resource, Having a target operating state is lower than the current state of the power saving state; if it is the fine side of the system, to cancel the power saving operation state of the resource, if the synchronization logic has found one of the fields The startup core, the -target operation state is less restrictive than the current implementation of the power-saving operation state. 3〇, "Please refer to the multi-core processor described in the 23rd patent, wherein each instance of the synchronization encounter 2 The state is organized according to a hierarchical way. The hierarchical coordination system is used to apply the synchronization logic to other cores of the multi-correction processor. The multi-core processor of claim 23, wherein the order coordination system aggregates the $132 201245948 core into the fields based on resources shared by the cores in the fields, wherein each field For the purpose of a five-week configuration of the resources, a single core system is designated as the administrator of the domain. 32. The multi-core processor as described in claim 23, wherein: The hierarchical hierarchical coordination system aggregates the cores into a plurality of domain levels, including at least: a top-level domain of the highest status, having all of the cores; and a second-level domain of two or more peer-to-peer positions , most immediately adjacent to the most prominent position, which is composed of the members of the primary level domain, each of which includes a sub-group of the cores; The field miscellaneous, the solution-nuclear (four) concept is defined as a manager in the field; each multi-core field of the lowest-level multi-core field material defines a genus! The group is the most closely related to the town. The core of the manager of the adult domain; 〆&gt; The lowest layer, and the core domain define the same attribute group, which is composed of all its cores, · each core belongs to at least one attribute group; ^The logic of each financial field _ is limited by the new instance of Lai Shi &amp; to non-belonging to the core of the local core of the same attribute group. Declaring the special plum _ 23 items of the rural private processor The heart of the bean is designated by the core of a sea eve as a manager of each multi-core field of the hierarchical coordination system 133 201245948. 34 such as the multi-core processing described in the 23rd article of the patent appearance Each core group 4 has its decentralized core-line code to find out if the other cores of the multi-core processor are disabled. 35, Shen: The multi-core processor described in Item 23 of the patent scope, wherein each core group cancer is a 帛 秘 分散 分散 ^ 四 四 四 四 四 四 四 四 四 四 四 四 发现 发现 发现 发现 发现 发现 发现 发现 发现 发现 发现 发现 发现 发现 发现 发现 发现 发现36. The multi-core processor described in claim (4) (4) of the claim, wherein each core group complains of the hierarchical inter-core state discovery to discover the multi-core processor-hierarchical coordination system. A method for implementing a distributed microcode of a discovery state of 37 multi-core processors, the multi-core processor comprising a plurality of entity processing cores, the method comprising: at least two cores exchanged by the core without passing through any centralized non-core logic The signal comes to the process of decentralized nuclear state discovery. The method of claim 37, wherein the method is performed by at least one of the following states: a composite power state for the processor; a composite power source for the H-domain of the process State, the job includes a group of multiple cores, which is a configurable resource that is operatively configured according to one of a plurality of configurations for the purpose of power saving; another core A target power state; a minimum limit of any one of a plurality of cores of the comorable resources; 201245948 Sexual target power state; a maximum target power state, which does not interfere with the correspondence of other cores A core of the target operating state is implemented; whether a core is started or disabled; how many cores of the multi-core processor have startup; a shared resource and an identification of multiple core domains, among which various configurable resources Department is shared; 5 Hi-core core hierarchical coordination system for operating shared resources; multiple bypass communication wiring in multi-core processors to coordinate core-utilization The bypass communication wiring is independent of a system bus that connects the multi-core processor to a chipset; and the core-hierarchical coordination system performs inter-core communication on the bypass communication wiring, The road communication wiring is independent of a system bus that connects the multi-core processor to a chip set. 39. The method of claim 38, wherein each of the participating cores uses a bypass communication wiring and another participating core exchange state related signal, and the bypass communication wiring is independent of the multi-core processor. Connected to a system bus of the chipset. 40. The method of claim 38, further comprising participating in the decentralized core state discovery process to discover a target power state of another core. 41. The method of claim 38, further comprising participating in the decentralized core state discovery process to discover a composite power state of the core group. 135 201245948 42. The method described in item 38 of Zhongli Liwei, including the section on the restriction of the resource (IV) affecting the Wei, speed, or effective reporting of shared resources - The decentralized inter-core state finds that the implementation of the wire-limited operating state for configuration-shared resources to an operational state is no longer restricted to co-drying. Any nuclear call is called the minimum restricted target operational state. 43. The method of claim 38, further comprising: each core receiving a target operational state; each core, in response to receiving the target operational state, implementing a local instance of synchronization logic embodied in s The core code of the core is used to discover a usable state; wherein the (4) state is not greater than a most restrictive operational state of the target operating state of the miscellaneous, which is not hindered by the corresponding target operating state of other cores. The core instance of the synchronization logic implements the synchronization logic to read at least one new slave instance at another core, and deliver the target operational state of the local core to the other core; and the slave instance compute-mix operation The state is at least a function that the target operational state can use for itself and the target operational state received from other local cores' and return the hybrid operational state to the local core. 44. The method of claim 43, further comprising: each instance of the synchronization logic, wherein the synchronization logic is recursively implemented on other cores that are still unsynchronized unless previously terminated by the termination condition Example, 136 201245948 Until the synchronized instance of the synchronization logic has been implemented in all cores of an available field of the processor. 45. The method of claim 44, further comprising: each instance of the synchronization logic conditionally preventing a dependent instance of the synchronization logic from being implemented on other unsynchronized cores, if its instance finds a core having The status is not limited to the minimum restricted operational state of the resource; wherein the synchronization logic is configured to coordinate - a minimum sufficient number of other cores - discovery shirt - restricted operational state can implement shared resources . 6, i microcode routine is encoded in the - multi-core surface - the entity processing core, computer readable storage ship towel, the code routine includes code for the non-transparent ^ any centralized non-core logic A decentralized inter-core state discovery_ is used by the core-switched signal to discover an available state of the multi-core processor; wherein the available state is one of: a state of the processor Composite power state; for the numeracy of the n-collection _-composite electric service, the lie includes a multi-health-group" which is operatively shared according to one of a plurality of configurations for power saving purposes Configurable-configurable resource; a target power state of another core; a minimum restricted target power state of any one of a plurality of cores of a configurable source; 137 5? 201245948 A most restrictive target power state, which is implemented by a core that does not interfere with the corresponding target operating state of other cores; whether a core is activated or disabled; how many cores of the multi-core processor are activated; Gt; identification of the source and multiple core domains in which various configurable resources are shared; such core-hierarchical coordination systems for operating shared resources; multiple pieces within a multi-core processor Bypassing the communication wiring to coordinate the utilization of the core, the bypass communication wiring is independent of a system bus that connects the multi-core processor to a chip set; and the hierarchical coordination of the cores The inter-core communication on the bypass communication wiring 'bypass communication wiring is independent of a system bus that connects the processor to a chip set. 138