201244379 六、發明說明： 【發明所屬之技術領域】 本發明係指一種脈寬調變（pUlse width modulation，pWM )驅 動晶片及其脈寬調變輸出訊號產生方法，尤指-種可棚較少輸入 腳位’達_時具有-直接輸人脈寬機轉速控麵式及—非直接 輸入脈寬觸概控賴摘减調變鶴晶狀其脈寬調變輸出 机號產生方法。 【先前技術】 近年來隨著電腦技術的發展，中央處理器（centralpr_sing 刪’ CPU)的處理時脈大幅度的增加，中央處理器所發出的熱量也 ，來越高’因此在散熱上的需求也越顯重要，在目前所使用的眾多 政熱方式巾仍崎熱風扇為主。在巾央處刻所使_散熱風扇中 (pulse width modulation » PWM) m 速兩種調速方式，其中，脈波寬度·調速又分為直接輸入脈寬調 變轉速控麵纽敍赌人减·轉触麵0麵式。 ▲詳細來說，請參考第1Affl，第1A圖為f知具有—直接輸入脈 寬調變轉速控麵式之—脈寬調變驅動晶片1()之示意^如第认 圖所示，脈寬調變驅動晶片1G包含—脈波寬度調變腳位⑽，用來 接收-脈寬調變訊號PWM，使得脈寬調變驅動晶片ι〇可以脈寬調 變訊號PWM直接做為一脈寬調變輸出訊號PWM⑽來控制輸出以 201244379 驅動風扇。 舉例來說，請參考第出圖，第1B圖為第1A1中脈寬調變驅 動晶片ίο之一驅動電路104之示意圖。如第1B圖所示，脈寬調變 驅動晶片10可以脈寬調變輸出訊號PWM〇ut控制驅動電路1〇4中 -上橋開關1G6及-下橋關之開啟與_，以改變驅動風扇 之一驅動電流IL，進而改變風扇轉速。在此情況下，請參考第ic 圖’第1C圖為第1A圖中脈寬調變驅動晶片1〇之脈寬調變訊號 PWM及脈寬調變輸出訊號pwM〇ut之示意圖。如第丨匸圖所示，由 於脈寬調變輸出訊號pWMGUtm脈寬調變訊號PWM，因此可藉由 控制所輸人之脈寬調變峨PWM之脈絲㈣脈寬霞輸出訊號 PWMom之脈寬及相對應風扇轉速。 二而由於直接脈波寬度調變控制模式所產生的轉速曲線會與 脈寬調變簡PWM之脈寬成正比，目此若需要縣哺速應用， 例如脈寬調變輸出訊號具有最低或最高操作脈寬（如施或8〇%之 最低或最R3操作脈寬），則必彡貞細非直接脈波寬度調變訊號控制模 式。 。月參考第2A圖，第2A圖為習知具有一非直接輸入脈寬調變轉 速控制模式之一脈寬調變驅動晶片2〇之示意圖。如第2入圖所示， 脈寬調變驅動晶片20包含一設定腳位2〇2、一振⑽位2〇4以及一 比較器206。設定腳位2〇2及振盪腳位2〇4分別用來接收一設定訊 201244379 號SET及一三角波〇sc，比較器2〇6用來比較設定訊號SET及三 角波OSC以產生一脈寬調變輸出訊號pwMout’ ，其中，設定訊號 SET係相關於所輸入之脈寬調變訊號PWM之脈寬。在此情況下， 脈寬調變驅動晶片20可根據脈寬調變訊號PWM，以非直接方式透 過脈寬調變輸出訊號PWMout，控制輸出以驅動風扇（其驅動方式 與第1B圖相似）。 舉例來說，可透過輸入脈寬調變訊號PWM切換一雙載子電晶 體（bipolar junction transistor，BJT) Q1 之開啟與關閉，再透過一分 壓電路208以及一濾波電路210產生與所輸入之脈寬調變訊號PWM 之脈寬呈負相關之直流設定訊號SET (於脈寬調變訊號PWM之開 啟時間時，雙載子電晶體Q1開啟且電阻R2〜R3並聯，因此電阻 R3之跨壓較小）。 在此情況下，請參考第2B圖’第2B圖為第2A圖中設定訊號 SET、三角波OSC以及脈寬調變輸出訊號PWMom，之示意圖。如 第2B圖所示’比較器206可比較直流設定訊號SET與一振盪器212 所產生之三角波OSC，以得到脈寬調變輸出訊號PWMout，。如此 一來，可藉由調整分壓電路208中電阻R1〜R3來決定設定訊號set 與所輸入之脈寬調變訊號PWM之脈寬之間的關係，進而決定脈寬 調變輸出訊號PWMout’之最低或最高操作脈寬及相對應最低或最 高轉速。 201244379 舉例來說，當脈寬調變訊號PWM之脈寬為0%時，設定訊號 SET之電壓等於並聯電阻R2〜R3之跨壓，此時若電阻幻〜之 電阻值較大則設定訊號SET最大值較大，使得脈寬調變輸出訊號 PWMout’之最低操作脈寬及相對應最低轉速較小，可依此調整脈 寬調變輸出訊號PWMout’之最低操作脈寬及相對應最低轉速。依 此類推，亦可調整脈寬調變輸出訊號PWM〇ut’之最高操作脈寬及 相對應最高轉速。 須庄意’為了使脈寬調變輸出訊號p\yM〇ut’之脈寬以及頻率 皆可調整，第2A圖所示用來產生設定訊號SET之電路以及震盪器 212所接之電容都是位於脈寬調變驅動晶片2〇外部，因此脈寬調變 驅動晶片20需有設定腳位202及振盪腳位204。 另一方面，請參考第3圖，第3圖為習知同時具有一直接輸入 脈寬調變轉速控制模式及一非直接輸入脈寬調變轉速控制模式之一 脈寬調變驅動晶片30之示意圖。如第3圖所示，在習知技術中，若 S人同時包g直接輸入脈寬调變轉速控制模式及非直接輸入脈寬調變 轉速控制模式，則必須如脈寬調變驅動晶片3〇包含三個輸入腳位 302〜306 ’分別用來接收脈寬調變訊號pwm、設定訊號SET以及 三角波OSC，以分別進行如脈寬調變驅動晶片1〇 ' 20之操作。 然而，由於一般脈寬調變驅動晶片腳位有限，因此習知以三個 輸入腳位來同時實現直接輸入脈寬調變轉速控制模式及非直接輸入 201244379 ===::=_變一功能受限 【發明内容】 匕本發月之主要目的即在於提供一種可以較少腳位同時具 有-直接輸人脈__速控麵式及_非直接輸人脈寬調變轉速 控制模式的脈寬調變驅動晶片及其脈寬調變輸出訊號產生方法。 本發明揭露-種脈寬調變驅動晶片，包含有一第一腳位，用來 接收第一成號’一第二腳位，用來接收一第二訊號丨一比較單元， 用來將該第-訊號與-參考電壓進行比較，以產生—比較結果指示 雜寬調變驅動晶片之—操作模式；以及—輸出單元，用來根據該 第一汛號、該第二訊號以及該比較結果，輸出一脈寬調變輸出訊號。 本發明另揭露一種脈寬調變輸出訊號產生方法，用於一脈寬調 變驅動晶片。該脈寬調變輸出訊號產生方法包含有接收一第一訊號 與一第二訊號；比較該第一訊號與一參考電壓’以產生一比較結果 指示該脈寬調變驅動晶片之一操作模式；以及根據該第一訊號、該 第二訊號以及該比較結果，輸出一脈寬調變輸出訊號。 【實施方式】 請參考第4圖，第4圖為本發明實施例同時具有一直接輸入脈 寬調變轉速控制模式DPWMM及一非直接輸入脈寬調變轉速控制 201244379 模式IDPWMM之-脈寬調變駆動晶片4〇之示意圖。如第4圖所 示，脈寬调變驅動晶片40包含有腳位4〇2、4〇4、一比較單元4〇6 以及一輸出單元408，其亦可另包含如第1B圖所示之驅動電路1〇4 以驅動風扇，而不限於此。 簡單來說，腳位402、404可分別接收訊號sig卜SIG2，其中， sfl號SIG1可以係一電壓訊號，而訊號siG2可以係一三角波〇sc 或一脈寬調變訊號PWM’ 。接著’比較單元406可將訊號SIG1 與一參考電壓VREF進行比較’以判斷訊號SIG1是否為一設定訊 號SET，，再據以產生一比較結果SEL指示脈寬調變驅動晶片40 之一操作模式〇p為直接輸入脈寬調變轉速控制模式DPWMM或非 直接輸入脈寬調變轉速控制模式IDPWMM。最後，輸出單元408 可根據訊號SIG1、SIG2以及比較結果SEL，輸出一脈寬調變輸出 §扎號PWMout “控制輸出以驅動風扇（其驅動方式之實現可與第iB 圖相似）。 在此情形下’脈寬調變驅動晶片40可偵測訊號SIG1之準位而 決定訊號SIG2為三角波OSC’或脈寬調變訊號PWM，，再據以輸 出脈寬調變輸出訊號PWMout “，因此可將三角波OSC，及脈寬調 變§孔5虎PWM之輸入腳位合併於腳位404。如此一來，相較於習知 需要三個輸入腳位，脈寬調變驅動晶片40僅需兩個腳位4〇2、404 即可同時具有直接輸入脈寬調變轉速控制模式DPWMM及非直接 輸入脈寬調變轉速控制模式IDPWMM，因此可於有限腳位的情況 201244379 下實現更多功能。 詳細來說，比較單元406係將訊號SIG1與參考電壓VREF進 行比較，於訊號SIG1小於參考電壓VREF時，判斷訊號SIG1不為 設定訊號SET’，因此比較結果SEL指示脈寬觀鶴晶片仙之 操作模式op為直接輸入脈寬調變轉速控制模式DPWMM。在此情 形下，訊號SIG2為脈寬調變訊號PWM，，因此輸出單元4〇8會以 脈寬调變訊號PWM，直接做為脈寬調變輸出訊號pWM〇ut “輸出。 另一方面，比較單元406於訊號SIG1大於參考電壓VREF時， 判斷訊號SIG1為設定訊號SET，’因此比較結果SEL指示脈寬調 變驅動晶片40之操作模式〇p為非直接輸入脈寬調變轉速控制模式 IDPWMM。在此情形下，訊號SIG2為三角波〇sc’ ，因此輸出單 元408會比較設定訊號SET，與三角波0SC，，以產生一非直接脈 寬調變訊號IDPWM做為脈寬調變輸出訊號PWM〇m “輸出。其中， 非直接脈寬調變訊號IDPWM之產生方式與第2B圖所示相似。 具體而言，輸出單元408包含有一比較器410以及一多工器 412。比較器410之一負輸入端與一正輸入端分別用來接收訊號 SIG1、SIG2 ’比較器410可比較訊號SIG1、SIG2，以於其一輸出 立而輸出非直接脈寬調變訊號IDPWM。多工器412之一輸入端用來 接收非直接脈寬調變訊號IDPWM而另一輸入端用來接收訊號 SIG2，可根據比較結果SEL對非直接脈寬調變訊號IDPWM與訊號 201244379 SIG2進行選取’以輸出脈寬調變輸出訊號pWM〇ut “。 在此情形下，若訊號SIG1小於參考電壓VREF，則多工器412 選取訊號SIG2做為脈寬調變輸出訊號pwM〇ut “輪出，表示脈寬調 變驅動晶片40之操作模式〇p為直接輸入脈寬調變轉速控制模式 DPWMM且訊號SIG2為脈寬調變訊號PWM’。另一方面，若訊號 SKH大於參考電壓聰F，則多工器412選取非直接脈寬調變訊;虎 IDPWM做為脈寬輕輸出贿pWMQut “輸出，麵脈寬調變驅 動晶片4〇之操作模式〇p為非直接輸入脈寬調變轉速控制模式 ①PWMM且訊號SIG2為三角波〇sc，。如此一來，輸出單元偏 可根據訊號SKH、SIG2以及比較結果孤，輸出適當脈寬調變輸 出訊號PWMout “控制輸出以驅動風扇。 值得注意的是，本發明之主要精神在於脈寬調變驅動晶片奶 可偵測腳位4G2之訊號SIG1之準位而決定腳位撕之訊號舰為 三角波osc’或脈寬霞訊號PWM，，再據以輸出脈寬調變輸出 訊號PWMout “’因此可將三角波〇sc，及脈寬調變訊號歸从 之輸入腳位合併於腳位404。本領域具通常知識者當可依此進行修 飾或變化，而不限於此。舉触說，參考賴v跡較佳為三角波 OSC，之波谷值與訊號SIG1為非設定訊號啦，日夺準位之間一準 位，以避免比較單it 406誤判脈寬調變驅動晶片4〇之操作模式〇p. 此外’用來產生設定訊號SET，與三角波〇sc，之電路可與第从 圖所示電路相似，但不限於此；再者，比較單元概與輸出單元權 201244379 之具體電路實現方式並不限於第4圖所示之電路，只要能達到其各 別作用即可。 因此’脈寬調變驅動晶片40關於脈寬調變輸出訊號pwMout 之輸出操作’可歸納為一脈寬調變輸出訊號產生流程5〇，如第5 圖所示’其包含以下步驟： 步驟500 :開始。 步驟502 :接收訊號SIG1、SIG2。 步驟504 :比較訊號SIG1與參考電壓VREF，以產生比較結果 SEL指示脈寬調變驅動晶片40之操作模式〇p。 步驟506 ··根據訊號SI(H、SIG2以及比較結果SEL，輸出脈寬 調變輸出訊號PWMout “。 步驟508 :結束。 脈寬調變輸出訊號產生流程50之詳細内容，可參考脈寬調變驅 動晶片40之相關敘述，於此不再贅述。 在習知技術中，以三個輸人腳位來同時實現直接輸人脈寬調變 轉速控制模纽非直接輸讀寬輕觀控趣式之对，會因此 般脈寬調變驅動晶片腳位有限，造成脈寬調變驅動晶片功能受 限。相較之下，本發明之脈寬調變驅動晶片4〇可偵測腳位4〇2 2訊 銳SIG1之準位而決定腳位4〇4之訊號啦2為三角波〇sc，或脈寬 調變訊號PWM’，再據以輸嫌寬機輸出職pWM⑽“，因此 201244379 可將MSGSC’及脈寬調變峨卩觀’續續位合併於腳位 404’進而僅需較少聽即可_具有直接輸人脈㈣變轉速控制模 式及非直罐人脈寬調贿魅趣式，耻可於魏腳位的情況 下實現更多功能。 示上所述本發明之脈寬調變驅動晶片可以較少腳位同時具有 直接輸入脈寬霞槪控繼歧非赌人脈__速控麵 式。 以上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍 所做之均等變化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 第1A圖為習知具有一直接輸入脈寬調變轉速控制模式之一脈 寬調變驅動晶片之示意圖。 第1B圖為第ία圖中脈寬調變驅動晶片之一驅動電路之示意 圖。 第1C圖為第1A圖中脈寬調變驅動晶片之一脈寬調變訊號及一 脈寬調變輸出訊號之示意圖。 第2A圖為習知具有一非直接輸入脈寬調變轉速控制模式之一 脈寬調變驅動晶片之示意圖。 第2B圖為第2A圖中一設定訊號、一三角波以一及脈寬調變輸 出訊號之示意圖。 12 201244379 第3圖為習知同時具有一直接輸入脈寬調變轉速控制模式及一 非直接輸入脈寬調變轉速控制模式之一脈寬調變驅動晶片之示竟 圖。 …第4圖為本發明實施綱時具有一直接輸人脈寬靖轉速控制 模式及-非直接輸人脈寬調變轉迷控讎式之H賤驅動晶片 之示意圖。 第5圖為本發明實施例一脈寬調變輸出訊號產生流程之示意 圖。 脈寬調變驅動晶片 脈波寬度調變腳位 驅動電路 上橋開關 下橋開關 設定腳位 振盪腳位 比較器 分壓電路 濾波電路 振盪器 腳位 比較單元 【主要元件符號說明】 】〇、20、30、40 102 104 106 108 202 204 206 208 210 212 302〜306、402、404 406 201244379 408 輸出單元 410 比較器 412 多工器 50 流程 500〜508 步驟 PWM、PWM’ 脈寬調變訊號 PWMout、PWMout’ ' PWMout 脈寬調變輸出訊號 IL 驅動電流 SET、SET’ 設定訊號 OSC、OSC’ 三角波 Qi 雙載子電晶體 R1 〜R3 電阻 SIG1 > SIG2 訊號 VREF 參考電壓 SEL 比較結果 IDPWM 非直接脈寬調變訊號201244379 VI. Description of the Invention: [Technical Field] The present invention relates to a pulse width modulation (pWM) driving chip and a pulse width modulation output signal generating method thereof, and more particularly The input pin 'has _ when there is - direct input pulse width machine speed control surface type and - non-direct input pulse width touch control 赖 减 减 鹤 鹤 鹤 鹤 鹤 其 其 其 其 其 其 其 其 其 其 其 其 其 其 其 其 其 其 其 其 其 其 其 其[Prior Art] In recent years, with the development of computer technology, the processing clock of the central processor (centralpr_sing deleted 'CPU) has increased greatly, and the heat generated by the central processing unit has also increased, so the demand for heat dissipation The more important it is, the many hot-selling methods used in the current are still hot fans. At the center of the towel, the _ cooling fan (pulse width modulation » PWM) m speed two speed control modes, wherein the pulse width and speed regulation are further divided into direct input pulse width modulation speed control surface Reduced and turned to face 0. ▲ In detail, please refer to 1Affl, and Figure 1A shows that there is a direct input pulse width modulation speed control surface type - the pulse width modulation drive chip 1 () is shown as the first picture, pulse The wide-variation-variable driving chip 1G includes a pulse width modulation pin (10) for receiving the pulse width modulation signal PWM, so that the pulse width modulation driving chip ι can directly use the pulse width modulation signal PWM as a pulse width. The output signal PWM (10) is modulated to control the output to drive the fan at 201244379. For example, please refer to the first figure, and FIG. 1B is a schematic diagram of a driving circuit 104 of the pulse width modulation driving chip ί1 of the first embodiment. As shown in FIG. 1B, the pulse width modulation driving chip 10 can control the driving circuit 1〇4-upper bridge switch 1G6 and the lower bridge switch opening and closing _ to change the driving fan. One drives the current IL, which in turn changes the fan speed. In this case, please refer to the first ic diagram. FIG. 1C is a schematic diagram of the pulse width modulation signal PWM and the pulse width modulation output signal pwM〇ut of the pulse width modulation driving chip 1A in FIG. As shown in the figure, because the pulse width modulation output signal pWMGUtm pulse width modulation signal PWM, it can be controlled by the pulse width modulation of the input pulse 峨 PWM pulse (four) pulse width Xia output signal PWMom pulse Width and corresponding fan speed. Second, since the speed curve generated by the direct pulse width modulation control mode is proportional to the pulse width of the pulse width modulation PWM, if the county speed application is required, for example, the pulse width modulation output signal has the lowest or highest The operating pulse width (such as the minimum of the application or 8〇% or the most R3 operating pulse width) must be in the non-direct pulse width modulation signal control mode. . Referring to FIG. 2A, FIG. 2A is a schematic diagram of a pulse width modulation driving chip 2 习 having a non-direct input pulse width modulation speed control mode. As shown in the second figure, the pulse width modulation driving chip 20 includes a set pin 2〇2, a ring (10) bit 2〇4, and a comparator 206. The setting pin 2〇2 and the oscillating pin position 2〇4 are respectively used to receive a setting signal 201244379 SET and a triangular wave 〇sc, and the comparator 2〇6 is used to compare the setting signal SET and the triangular wave OSC to generate a pulse width modulation. The output signal pwMout', wherein the setting signal SET is related to the pulse width of the input pulse width modulation signal PWM. In this case, the pulse width modulation driving chip 20 can pass the pulse width modulation output signal PWMout in an indirect manner according to the pulse width modulation signal PWM, and control the output to drive the fan (the driving method is similar to that of Fig. 1B). For example, a bipolar junction transistor (BJT) Q1 can be switched on and off by an input pulse width modulation signal PWM, and then generated and input through a voltage dividing circuit 208 and a filter circuit 210. The pulse width of the pulse width modulation signal PWM is negatively correlated with the DC setting signal SET (when the pulse width modulation signal PWM is turned on, the bipolar transistor Q1 is turned on and the resistors R2 to R3 are connected in parallel, so the crossover of the resistor R3 The pressure is small). In this case, please refer to FIG. 2B'. FIG. 2B is a schematic diagram of the setting signal SET, the triangular wave OSC, and the pulse width modulation output signal PWMom in FIG. 2A. As shown in FIG. 2B, the comparator 206 compares the DC setting signal SET with the triangular wave OSC generated by an oscillator 212 to obtain a pulse width modulated output signal PWMout. In this way, the relationship between the set signal set and the pulse width of the input pulse width modulation signal PWM can be determined by adjusting the resistors R1 R R3 in the voltage dividing circuit 208, thereby determining the pulse width modulation output signal PWMout. 'The lowest or highest operating pulse width and the corresponding minimum or maximum speed. 201244379 For example, when the pulse width of the pulse width modulation signal PWM is 0%, the voltage of the setting signal SET is equal to the voltage across the parallel resistors R2 to R3. At this time, if the resistance value of the resistor is large, the signal SET is set. The maximum value is large, so that the minimum operating pulse width and the corresponding minimum rotational speed of the pulse width modulation output signal PWMout' are small, and the minimum operating pulse width and the corresponding minimum rotational speed of the pulse width modulated output signal PWMout' can be adjusted accordingly. By analogy, the maximum operating pulse width and the corresponding maximum rotational speed of the pulse width modulated output signal PWM〇ut' can also be adjusted. In order to make the pulse width modulation output signal p\yM〇ut' pulse width and frequency can be adjusted, the circuit used to generate the setting signal SET and the capacitor connected to the oscillator 212 are shown in FIG. 2A. Located outside the pulse width modulation driving chip 2, the pulse width modulation driving chip 20 needs to have a setting pin 202 and an oscillating pin 204. On the other hand, please refer to FIG. 3, which is a pulse width modulation driving chip 30 which has a direct input pulse width modulation speed control mode and a non-direct input pulse width modulation speed control mode. schematic diagram. As shown in FIG. 3, in the prior art, if the S person directly inputs the pulse width modulation speed control mode and the indirect input pulse width modulation speed control mode, the chip 3 must be driven as the pulse width modulation. The 〇 includes three input pins 302 to 306' for receiving the pulse width modulation signal pwm, the setting signal SET, and the triangular wave OSC, respectively, to perform operations such as pulse width modulation driving the chip 1 〇 '20. However, due to the limited pulse width of the general pulse width modulation driver, it is conventional to realize the direct input pulse width modulation speed control mode and the indirect input with three input pins. 201244379 ===::=_ Restricted [Invention] The main purpose of this month is to provide a pulse width that can have fewer feet at the same time - direct input pulse __ speed control surface and _ non-direct input pulse width modulation speed control mode The modulation drive chip and its pulse width modulation output signal generation method. The invention discloses a pulse width modulation driving chip, comprising a first pin for receiving a first number 'a second pin' for receiving a second signal, a comparing unit, for using the first - the signal is compared with a reference voltage to generate - the comparison result indicates the operation mode of the hetero-wide modulation driving chip; and - the output unit is configured to output according to the first apostrophe, the second signal, and the comparison result A pulse width modulation output signal. The invention further discloses a pulse width modulation output signal generating method for a pulse width modulation driving chip. The pulse width modulation output signal generating method includes: receiving a first signal and a second signal; comparing the first signal with a reference voltage to generate a comparison result indicating an operation mode of the pulse width modulation driving chip; And outputting a pulse width modulation output signal according to the first signal, the second signal, and the comparison result. [Embodiment] Please refer to FIG. 4, which shows a direct input pulse width modulation speed control mode DPWMM and an indirect input pulse width modulation speed control 201244379 mode IDPWMM-pulse width adjustment according to an embodiment of the present invention. A schematic diagram of the flip chip 4〇. As shown in FIG. 4, the pulse width modulation driving chip 40 includes pins 4〇2, 4〇4, a comparing unit 4〇6, and an output unit 408, which may further include as shown in FIG. 1B. The drive circuit 1〇4 drives the fan without being limited thereto. Briefly, the pins 402 and 404 can respectively receive the signal sig SIG2, wherein the sfl number SIG1 can be a voltage signal, and the signal siG2 can be a triangular wave 〇sc or a pulse width modulation signal PWM'. Then, the comparison unit 406 can compare the signal SIG1 with a reference voltage VREF to determine whether the signal SIG1 is a set signal SET, and then generate a comparison result SEL indicating the operation mode of the pulse width modulation drive chip 40. p is the direct input pulse width modulation speed control mode DPWMM or the indirect input pulse width modulation speed control mode IDPWMM. Finally, the output unit 408 can output a pulse width modulation output according to the signals SIG1, SIG2 and the comparison result SEL, and the PWM output "controls the output to drive the fan (the implementation of the driving mode can be similar to the iB diagram). The lower pulse width modulation driving chip 40 can detect the level of the signal SIG1 and determine that the signal SIG2 is a triangular wave OSC' or a pulse width modulation signal PWM, and then output a pulse width modulation output signal PWMout ", so The triangular wave OSC, and the pulse width modulation § hole 5 tiger PWM input pin are combined in the foot position 404. In this way, compared with the conventional three input pins, the pulse width modulation driving chip 40 only needs two pins 4〇2, 404, and can have a direct input pulse width modulation speed control mode DPWMM and non- The pulse width modulation speed control mode IDPWMM is directly input, so more functions can be realized under the limited pin position 201244379. In detail, the comparison unit 406 compares the signal SIG1 with the reference voltage VREF. When the signal SIG1 is smaller than the reference voltage VREF, the determination signal SIG1 is not the set signal SET', so the comparison result SEL indicates the operation of the pulse width The mode op is a direct input pulse width modulation speed control mode DPWMM. In this case, the signal SIG2 is the pulse width modulation signal PWM, so the output unit 4〇8 will use the pulse width modulation signal PWM as the pulse width modulation output signal pWM〇ut "output. On the other hand, When the signal SIG1 is greater than the reference voltage VREF, the comparison unit 406 determines that the signal SIG1 is the set signal SET, so the comparison result SEL indicates that the operation mode 脉p of the pulse width modulation driving chip 40 is an indirect input pulse width modulation speed control mode IDPWMM. In this case, the signal SIG2 is a triangular wave 〇sc', so the output unit 408 compares the set signal SET with the triangular wave OSC to generate an indirect pulse width modulation signal IDPWM as the pulse width modulation output signal PWM〇. m "Output. Among them, the non-direct pulse width modulation signal IDPWM is generated in a similar manner to that shown in FIG. 2B. Specifically, the output unit 408 includes a comparator 410 and a multiplexer 412. The negative input terminal and the positive input terminal of the comparator 410 are respectively used for receiving signals SIG1, SIG2'. The comparator 410 can compare the signals SIG1 and SIG2 to output an indirect pulse width modulation signal IDPWM on an output thereof. One input end of the multiplexer 412 is used to receive the non-direct pulse width modulation signal IDPWM and the other input end is used to receive the signal SIG2, and the non-direct pulse width modulation signal IDPWM and the signal 201244379 SIG2 can be selected according to the comparison result SEL. 'The output pulse width modulation output signal pWM〇ut". In this case, if the signal SIG1 is smaller than the reference voltage VREF, the multiplexer 412 selects the signal SIG2 as the pulse width modulation output signal pwM〇ut "rounds, The operation mode 脉p indicating the pulse width modulation driving chip 40 is the direct input pulse width modulation speed control mode DPWMM and the signal SIG2 is the pulse width modulation signal PWM'. On the other hand, if the signal SKH is greater than the reference voltage Sin F, the multiplexer 412 selects the non-direct pulse width modulation; the tiger IDPWM serves as the pulse width and light output bribe pWMQut "output, surface pulse width modulation drive chip 4" The operation mode 〇p is the non-direct input pulse width modulation speed control mode 1PWMM and the signal SIG2 is the triangle wave 〇sc, so that the output unit bias can output the appropriate pulse width modulation output according to the signals SKH, SIG2 and the comparison result. Signal PWMout "Controls the output to drive the fan. It should be noted that the main spirit of the present invention is that the pulse width modulation drive chip milk can detect the level of the signal SIG1 of the foot 4G2 and determine that the signal ship is a triangular wave osc' or a pulse width signal PWM, According to the output pulse width modulation output signal PWMout "', the triangular wave 〇sc, and the pulse width modulation signal can be combined with the input pin to be integrated into the pin 404. Those skilled in the art can modify it accordingly. Or change, not limited to this. In terms of the touch, the reference ray trace is preferably a triangular wave OSC, the trough value and the signal SIG1 are non-set signals, and the level is between the daily positions to avoid comparing the single it 406 The operation mode of erroneously judging the pulse width modulation driving chip 〇p. In addition, the circuit for generating the setting signal SET and the triangular wave 〇sc can be similar to the circuit shown in the figure, but is not limited thereto; The specific circuit implementation of the unit outline and the output unit right 201244379 is not limited to the circuit shown in Fig. 4, as long as the respective functions can be achieved. Therefore, the pulse width modulation drive chip 40 is about the pulse width modulation output signal pwMout. Output operation 'It can be summarized into a pulse width modulation output signal generation process 5〇, as shown in FIG. 5', which includes the following steps: Step 500: Start. Step 502: Receive signals SIG1, SIG2. Step 504: Compare signal SIG1 with reference The voltage VREF is used to generate the comparison result SEL indicating the operation mode 〇p of the pulse width modulation driving chip 40. Step 506 · Output the pulse width modulation output signal PWMout according to the signal SI (H, SIG2 and the comparison result SEL). For the details of the pulse width modulation output signal generation process 50, reference may be made to the related description of the pulse width modulation driving chip 40, which will not be described herein. In the prior art, three input pins are simultaneously used. The direct input of the pulse width modulation speed control module is not directly input to the wide and light control and control, so the pulse width modulation drive chip pin position is limited, resulting in limited pulse width modulation drive chip function. In contrast, the pulse width modulation driving chip 4 of the present invention can detect the level of the pin 4 〇 2 2 SIG SIG1 and determine the signal of the pin 4 〇 4 2 is a triangular wave 〇 sc, or a pulse width modulation Change signal PWM', and then according to the loss of wide machine Job pWM (10) ", so 201244379 can be combined with MSGSC' and pulse width modulation 'continuation' in the foot 404' and then only need to listen less _ with direct input pulse (four) variable speed control mode and non-straight tank The pulse width of the bribe is fascinating, and the shame can achieve more functions in the case of the Wei foot. The pulse width modulation driving chip of the present invention can be used with fewer feet and direct input pulse width control. The above description is only the preferred embodiment of the present invention, and all the equivalent changes and modifications made by the scope of the present invention should be within the scope of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1A is a schematic diagram of a pulse width modulation driving chip which is known as a direct input pulse width modulation speed control mode. Fig. 1B is a schematic view showing a driving circuit of a pulse width modulation driving chip in the Fig. Fig. 1C is a schematic diagram showing a pulse width modulation signal and a pulse width modulation output signal of the pulse width modulation driving chip in Fig. 1A. Figure 2A is a schematic diagram of a pulse width modulated drive chip having a non-direct input pulse width modulation speed control mode. Figure 2B is a schematic diagram of a set signal, a triangular wave, and a pulse width modulated output signal in Fig. 2A. 12 201244379 Figure 3 is a schematic diagram of a pulse width modulation driver chip with a direct input pulse width modulation speed control mode and a non-direct input pulse width modulation speed control mode. ... Figure 4 is a schematic diagram of a H贱 drive wafer having a direct input pulse width control mode and a non-direct input pulse width modulation control mode. FIG. 5 is a schematic diagram of a pulse width modulation output signal generation process according to an embodiment of the present invention. Pulse width modulation drive chip pulse width modulation pin drive circuit upper bridge switch lower bridge switch setting pin oscillating pin comparator voltage divider circuit filter circuit oscillator pin comparison unit [main component symbol description] 】 〇, 20, 30, 40 102 104 106 108 202 204 206 208 210 212 302~306, 402, 404 406 201244379 408 Output unit 410 Comparator 412 multiplexer 50 Flow 500~508 Step PWM, PWM' pulse width modulation signal PWMout , PWMout' ' PWMout pulse width modulation output signal IL drive current SET, SET' setting signal OSC, OSC' triangle wave Qi dual carrier transistor R1 ~ R3 resistance SIG1 > SIG2 signal VREF reference voltage SEL comparison result IDPWM non-direct pulse Wide tone signal