201244086201244086
1 I 六、發明說明： 【發明所屬之技術領域】 本發明係有關於-種高壓錄铸體元件，更朗地是利用 多段式隔離7G件設置在閘極結構下方，使得崩潰賴提高時，可 以改善尚壓金氧半導體元件内之導通電阻值。 【先前技術】 常見的半導體元件即為金氧半導體電晶體(M〇S transistor， metal oxide semkondiutotmnsistor)，這些金氧半導體電晶體係以 高密度來製作於積體電路中。 其中側向擴散金氧半導體(LDMOS，lateral diffusion metal oxide semiconductor)為一種製作在積體電路中的高壓元件，而高壓 元件往往被要求能夠承受較高的崩潰電壓扣^此^仰丨吨十並 且可以在較低的源/汲極導通電阻值(Rdson)下操作。但較高的崩潰 電壓通常需要較大的元件尺寸，如此將會同時提高源/汲極導通電 阻值(Rdson) 〇 【發明内容】 有蓉於發明背景中所述之提高崩潰電壓(breakdown voltage) 時，其源/沒極導通電阻值(Rdson)也會隨之提高的問題，本發明的 主要目的在於提供一種具有低導通電阻值之高壓金氧半導體元件 (HVMOS，high voltage metal oxide semiconductor)，係在閘極結構下 方、且鄰近於漂移區形成多段式之隔離元件，以藉由多段式隔離 元件(multiple isolation device)來阻擋電流直接進入漂移區，且可以 增加本體區至漂移區之間的長度，使得提高高壓金氧半導體元件 之崩潰電壓提高時，其高壓金氧半導體元件基板内導通電阻值可 以降低。 3 201244086 根據以上所述之目的，本發明揭露一種高壓金氧半導體元 件，其包括：一基板；一多段式第一隔離元件，設置在基板内， 且包含複數個段結構；一源極區及一汲極區，分別設置在多段式 第一隔離元件之兩側；以及一閘極結構’設置在至少部份之多段 式第一隔離元件之上方；藉由多段式第一隔離元件可以增加在閘 極結構下方電流的流通路徑，使得在增加閘極結構之崩潰電壓 時，在此區域之間的導通電阻值可以降低。 本發明還揭露一種半導體元件’其包括：一基板；一多段式 第一隔離元件，設置在一閘極結構下方，且包含複數個段結構， 其中部份多段式第一隔離元件與閘極結構重疊；及複數個第二隔 離元件，設置在基板之兩侧邊；藉由多段式第一隔離元件可以增 加在閘極結構下方電⑽麵賴，使得在增加_結構之崩潰 電壓時，在此通道之間的導通電阻值可以降低。 為讓本發明之上述和其他目的、特徵和優點能更明顯易 僅’下文特舉較佳實施例’並配合所附圖式，作詳細說明如下。 【實施方式】 本發明在此所探討的方向為—種高壓金氧半導體元件。為了 ，徹底地瞭解本發明，將在下_贿巾提出詳錢高壓金氧 構及其製造步驟。地，本發明的實行並未限定 =金神導體兀件之技藝者所熟習的特殊細節，細，對於 =發，的較佳實施例，則會詳細描述如下。除了這些詳細描述之 可以廣泛地施行在其他的實施财’林發明的範 又限疋，在视縣㈣之精神和範_，當 動與潤飾’因此本發明之專利保護範 —f之更 專利範圍所界定者為準。純圍舰本說明書所附之申請 4 201244086 圖1至圖6备根據本發明所揭 之方法之各步驟流程示意圖；圖7係:=餘半導體元件 :示具有較厚之閘氧化層之高壓金氧半導：露=術， 有雙間極結構之賴錢轉紅件 離元件與崩溃電;之=^ 係表不具有不同區段之多 口久回 圖。 Μ _轉與電流之關係示意 首先請參考圖卜係提供一基板u，在此1 I. Description of the Invention: [Technical Field] The present invention relates to a high-voltage recording and casting body component, and more particularly, a multi-segment isolation 7G member is disposed under the gate structure, so that when the collapse is improved, It is possible to improve the on-resistance value in the MOS device. [Prior Art] A common semiconductor element is a metal oxide semiconductor crystal (M?S transistor, metal oxide semkondiutotmnsistor), which is fabricated in a bulk circuit at a high density. Wherein, a lateral diffusion metal oxide semiconductor (LDMOS) is a high-voltage component fabricated in an integrated circuit, and a high-voltage component is often required to withstand a high breakdown voltage buckle. It can be operated at a lower source/drain on-resistance value (Rdson). However, a higher breakdown voltage usually requires a larger component size, which will simultaneously increase the source/drain on-resistance value (Rdson). [Inventive content] There is a breakdown voltage as described in the background of the invention. When the source/no-pole on-resistance value (Rdson) is also increased, the main object of the present invention is to provide a high voltage metal oxide device (HVMOS) having a low on-resistance value. Semiconductor) is formed below the gate structure and adjacent to the drift region to form a multi-segment isolation element to block current directly into the drift region by a multiple isolation device, and can increase the body region to the drift region The length between them makes it possible to increase the on-resistance value of the high-voltage MOS device substrate when the breakdown voltage of the high-voltage MOS device is increased. 3 201244086 According to the above, the present invention discloses a high voltage MOS device comprising: a substrate; a multi-segment first isolation element disposed in the substrate and comprising a plurality of segment structures; a source region And a drain region respectively disposed on two sides of the multi-segment first isolation element; and a gate structure ' disposed over at least a portion of the multi-segment first isolation element; the multi-segment first isolation element may be added The flow path of the current under the gate structure allows the on-resistance value between the regions to be reduced when the breakdown voltage of the gate structure is increased. The invention further discloses a semiconductor device comprising: a substrate; a multi-segment first isolation element disposed under a gate structure and comprising a plurality of segment structures, wherein the plurality of segments of the first isolation device and the gate The structure overlaps; and a plurality of second isolation elements are disposed on both sides of the substrate; the multi-segment first isolation element can increase the electric (10) surface under the gate structure, so that when the breakdown voltage of the structure is increased, The on-resistance value between this channel can be reduced. The above and other objects, features, and advantages of the present invention will become more apparent. [Embodiment] The invention is directed to a high voltage MOS device. In order to thoroughly understand the present invention, a detailed high-pressure gold oxide structure and its manufacturing steps will be proposed in the next. The implementation of the present invention is not limited to the specific details familiar to those skilled in the art of the Golden God, and the preferred embodiment of the invention will be described in detail below. In addition to these detailed descriptions, it can be widely implemented in other implementations of the invention of the invention, and in the spirit and scope of the county (four), when moving and retouching, the patent protection scope of the invention is therefore more patented. The definition is final. Appendices attached to the present specification 4 201244086 FIG. 1 to FIG. 6 are schematic diagrams showing the steps of the steps of the method according to the present invention; FIG. 7 is: = residual semiconductor component: high voltage gold showing a thick gate oxide layer Oxygen semi-conducting: dew = surgery, there is a double-pole structure to turn the red pieces away from the component and crash electricity; the =^ system does not have multiple sections of the long-term back map. Μ _ Turn relationship with current indication First, please refer to the diagram to provide a substrate u, here
Tnfl' ； ^ ;光學二i在氧可以是二氧化_2)。接著，利 緊基區一 · 荖，力Man /先在乳化層12上形成一 I化層14 ;接 後以_^+上形成具ί贿化之光阻層(未在®巾表示），然 11，/· I ’移除部份氮化層14、氧化層12以及部份的基板 -、、聋準二爐^内形成複數個第一溝渠結構16a、16b及複數個第 其中第二溝渠結構18a、18b形成在 芬Γ ΐ溝細冓16a、16b之兩側邊。第一溝渠結構16a、16b 溝渠結構18a、18b可能會因為橫向的尺寸不同而造成深度 、5目+溝雜為讀、’並*代表真實的尺寸或深度。 接著，將介電材料(dielectric material)填入複數個第—溝渠結 構6a、16b及複數個第二溝渠結構版、 Η表面。縣，域㈣14做騎域製雖在 止層^用平坦化製程將多餘的介電材料移除；接著，再將氮化 層14及氧化層12移除，使得在基板u内形成一個具有第一段結 構+⑹a及第一段結構161b之第一隔離元件⑹以及複數個第二 Pw離元件⑻a、1’。另外，如圖3所示，在此實施例中第一 201244086 隔離元^ 161及第二隔離元件181a、mb可以是淺溝渠隔離元件 (STI，shallow trench isolation)。要說明的是，在另一個可選擇的 施例中’可以在基板η _成第—隔離元件⑹及第二隔離元件 181a、181b之後，再形成Ν_井區8〇。 在此要說明的是，第-隔離元件⑹之每一段結構腿、祕 的南寬比係大於每-第二隔離元件⑻a、腿的高寬比，而第一 隔離元件⑹之每-段結構⑹a、⑽之高寬比可以相同或是不 同。第-隔離元件⑹係以多段方式形成在基板u内，為了簡化， 在本案中以具有二個段結構第—隔離元件161進行制。另外， 如圖4A〜4D所示，可依多種方式配置第一隔離元件i6i之段结構 騎、祕在基板n内。如圖4八戶斤表示，兩段結構均為連續結 構，而圖4Β及圖4C係表示非連續之段結構與連續之段結構交互、 且彼此電性分離的形成在基板u内；或是如圖4D所示，多段式 第-隔離το狀段結構均為非連續之段結構，而這些非連續之段 結構彼此交錯排列，但是彼此電性分離以形成在基板u内。在此， 將第-隔離元件⑹之段結構161a、祕以連續或非連續交互或 交錯設置的目的在於:在增加閘極崩潰電壓時，可以藉由多段式隔 離兀件的結構來增加電流的流通路徑，避免電流直接由本體區(未 在圖中表句直魏人漂㈣(未顧巾麵），可 電阻值。 · 接著’請參考圖5，_半導體製程技術，於基板u上 閘極結構30，其形成閘極結構30之步驟包含：在基板η上形成 -閘氧化層(gate Gxide la㈣3Ga、且覆蓋多段式第—隔離元件⑹ 及複數個第二隔離元件181a、職；接著，一多晶梦層㈣^出咖 layer)30b形成在閘氧化層3〇a上。在此實施例中閘氧化層咖 的材料可以是二氧切。接著，執行另—次半導體之微影、钮刻 201244086 I f 製程··首先係在多晶石夕層30b上方形成具有間極結構30圖案 案化光阻層(未在圖中表示）；接著，進行钱刻步驟，由上而下 移除部份多晶石M 30b及閘氧化層30a，移除該圖案化光阻層之後 2基板11上方形成—閘極結構3G。其中，閘極結構“與在 基板11内部份多段式第一隔離元件161重疊。 且右圖5，利用閘極結構30為遮罩(義k)，係摻雜 /、有第一導電性之離子在基板u内以形成具有第二電性之源極 /汲極區(贿ce/drain) 40a、40b。接著， 化 氮化物層(未在圖中表示），例如，二氧化㈣氧化層或 結構3。及基板η之表)面二著:在閘極 ^層以糊隙壁(spa⑽）32在閘極結構3G之側壁上m 遮罩t __ __ 32做為 内之源極區40a與第二隔離元件⑻ 在基^ 之第-本體區(body) 50。接著，關⑽/场成具有第一電性 做為遮罩，再利用離子植!:方:樣==間隙壁-在基板11内分別形成具有較高離 1有第一電性之離子， 且環繞部份多段式第—隔離元件⑹=成下方， 二隔離元件181b。 弟一段、，，《構161b與部份第 緊接著，同樣參考圖6，再一 内較深的位置，植入具有第子植入步驟在基板11 職之離子，以形成-井區(well 201244086 region)80 ’該井區80環繞多段式第一隔離元件16卜第二隔離元 件181a、181b、且包覆第二本體區60以及漂移區70，以完成一 高壓金氧半導體元件10。然後，再將一金屬層3〇c形成在閘極結 構30之多晶矽層30b上，其形成步驟包括··先沉積一層金屬層(未 在圖中表示)在閘極結構30之多晶矽層30b上以及在源極區/沒極 區(S〇urce/drain)40a、40b上所曝露的矽基板1〇表面上；執行一退 火步驟使得金屬層與閘極結構30之多晶矽層30b所曝露之表面以 及與源極區/汲極區(source/drain) 40a、40b上所曝露的矽基板1〇 表面進行反絲形成金射化物；接著，移除未反應的金屬層； 以及最後，再進行退火製程使得矽化物相轉變為具有低阻值之 相。在此，石夕化金屬層30c的材料可以是石夕化鶴、石夕化始、 矽化鎳、矽化鈦等。 从2道為了要在基板U上形成較厚的閘氧化層在形成側向擴 金乳+導體元件賴程中，必需要藉由額相製程才能達到。、 =體的另―實施财，在基板U上所形成之高壓金氧 側向擴散金氧半導體元件及完全空乏型金 在圖中表- )。因此，基板U係分成兩個區域(未 而二個區域係形用以形成侧向擴散金氧半導體元件’ :逆=====Tnfl'; ^; optical two i in oxygen can be dioxide_2). Then, tightening the base area 一, force Man / first form an I-layer 14 on the emulsion layer 12; and then forming a photoresist layer (not indicated by the ® towel) on the _^+, 11, 11, I remove a portion of the nitride layer 14, the oxide layer 12, and a portion of the substrate -, and a plurality of first trench structures 16a, 16b and a plurality of second trenches The structures 18a, 18b are formed on both sides of the sulcus ridges 16a, 16b. The first trench structure 16a, 16b trench structures 18a, 18b may be depth due to different lateral dimensions, 5 mesh + trenches are read, 'and * represents true size or depth. Next, a dielectric material is filled into the plurality of first-ditch structures 6a, 16b and a plurality of second trench structure plates and ruthenium surfaces. County, domain (four) 14 do the riding system, although in the stop layer ^ use the flattening process to remove excess dielectric material; then, remove the nitride layer 14 and the oxide layer 12, so that a formation in the substrate u A segment of structure + (6) a and a first isolation element (6) of the first segment structure 161b and a plurality of second Pw isolation elements (8) a, 1'. In addition, as shown in FIG. 3, in this embodiment, the first 201244086 isolation element 161 and the second isolation elements 181a, mb may be shallow trench isolation (STI). It is to be noted that, in another alternative embodiment, the Ν_well region 8〇 may be formed after the substrate η_to the first isolation element (6) and the second isolation element 181a, 181b. It is to be noted that each of the structural legs of the first spacer element (6) has a larger aspect ratio than the height ratio of each of the second spacer elements (8) a and the legs, and the structure of each of the first spacer elements (6) (6) The aspect ratios of a and (10) may be the same or different. The first spacer element (6) is formed in the substrate u in a plurality of stages. For the sake of simplicity, the spacer element 161 having the two-segment structure is used in the present invention. In addition, as shown in FIGS. 4A to 4D, the segment structure of the first isolation element i6i can be configured to ride in the substrate n in a plurality of ways. As shown in Fig. 4, the household structure is a continuous structure, and FIG. 4A and FIG. 4C show that the discontinuous segment structure interacts with the continuous segment structure and is electrically separated from each other in the substrate u; As shown in FIG. 4D, the multi-stage first-isolated τ-like segment structures are all discontinuous segment structures, and the discontinuous segment structures are staggered with each other, but are electrically separated from each other to be formed in the substrate u. Here, the segment structure 161a of the first isolation element (6) is configured to be continuously or discontinuously or alternately arranged to increase the current by increasing the gate breakdown voltage by the structure of the multi-section isolation element. The circulation path avoids the current directly from the body area (not in the figure, the direct Wei people drift (four) (not considering the towel surface), the resistance value. · Next 'Please refer to Figure 5, _ semiconductor process technology, the gate structure on the substrate u 30. The step of forming the gate structure 30 includes: forming a gate oxide layer (gate Gxide la (4) 3Ga, and covering the multi-segment-type isolation element (6) and the plurality of second isolation elements 181a, and then; The crystal dream layer (4) is formed on the gate oxide layer 3〇a. In this embodiment, the material of the gate oxide layer may be dioxent. Then, the lithography and the button of the other semiconductor are performed. 201244086 I f process · Firstly, a patterned photoresist layer having an interpolar structure 30 (not shown) is formed over the polycrystalline layer 30b; then, a money engraving step is performed, and the top and bottom portions are removed. Part of polycrystalline stone M 30b and gate oxide layer 30a After the patterned photoresist layer is removed, a gate structure 3G is formed over the substrate 11. The gate structure "overlaps the multi-segment first isolation element 161 in the substrate 11 and the gate 5 is used. The pole structure 30 is a mask (meaning k), which is doped/the first conductive ion in the substrate u to form a source/drain region (a bribe ce/drain) 40a, 40b having a second electrical property. Next, a nitride layer (not shown), for example, a (4) oxide layer or structure 3, and a surface of the substrate η) are surfaced: at the gate layer with a gap wall (spa(10)) 32 On the sidewall of the gate structure 3G, m mask t __ __ 32 is used as the inner source region 40a and the second isolation element (8) in the first body-body 50. Then, the (10)/field has the first An electrical function as a mask, and then use ion implantation!: square: sample = = spacer - in the substrate 11 respectively formed with a higher ion from the first electrical, and surrounded by a multi-segment - isolation Element (6) = down, two isolation element 181b. A section, ", 161b and part of the second, followed by Figure 6, and a deeper position, implanted with The sub-implantation step is performed on the substrate 11 to form a well region (well 201244086 region) 80'. The well region 80 surrounds the multi-segment first isolation member 16 and the second isolation member 181a, 181b and covers the second body The region 60 and the drift region 70 are used to complete a high voltage MOS device 10. Then, a metal layer 3〇c is formed on the polysilicon layer 30b of the gate structure 30, and the forming step includes: depositing a metal layer first. (not shown) on the polysilicon layer 30b of the gate structure 30 and on the surface of the germanium substrate 1 exposed on the source/demagnet regions 40a, 40b; performing an annealing The step of causing the metal layer to be exposed to the surface of the polysilicon layer 30b of the gate structure 30 and the surface of the germanium substrate 1b exposed on the source/drain regions 40a, 40b to form a gold emitter. Next, the unreacted metal layer is removed; and finally, an annealing process is performed to convert the telluride phase into a phase having a low resistance. Here, the material of the Shihua chemical metal layer 30c may be Shi Xihua crane, Shi Xihua, nickel, titanium telluride, and the like. In order to form a thick gate oxide layer on the substrate U in order to form a laterally expanding gold + conductor component, it is necessary to achieve this by a phase process. The other is the implementation of the high-voltage gold-oxygen side-diffused MOS device formed on the substrate U and the completely depleted gold in the figure -). Therefore, the substrate U is divided into two regions (there are two regions to form a laterally diffused MOS device): inverse =====
St力 為了要有較厚的_二 氧化層時，也^時^ 空乏型金氧半導體製程形成閘 此閘氧化層31^厂二板❺區域上形成閑氧化層31a，且 U的厚度比利用側向擴散金氧半導體製程所形成的 201244086 閘氧層30a的厚度要厚，如圄 氧化層犯也有助於改麵因此，具有較厚厚度的閘 片儿a…· 吾原、Λ及極導通電阻值(Rdson) 〇此外，此蘭 巩化層31a也同時形成在多段式第一 161a與第二段結構161b之間。 f之第K構 根據以上所叙步驟可崎到—高壓 或圖7所示，由於本案在第一隔離元 :： = ===崩潰電壓(一 St 通電阻值。在本發明中，高壓而此區域之間的導 金氧半導體元件。门塾金料導體讀10可以是側向擴散 1 中’係在基板11上_成雙閘極結構 將主動ί 件，纽錢錢半導體元件中，係 region)設置在汲極區4〇b及通道烛_1)之 ^使H、有較向的崩潰電壓時，藉由在第二本體區⑼盘漂移 19Ga〜19Gf之多段式第一隔離元 阻信"二有益於在局的崩潰電壓的條件下有較低的導通電 =述 步驟以及元件之功能均與前述相同，不= ^制的是，在本發明所揭露之多段式第—隔離元件 ^僅以兩個段結構做為說明，但是在本發明在以下將針對具有 =段第:隔離元件、分成二個段結構之多段式第一隔離 牛、/刀成二個段結構之多段式第—隔離元件及分成四個段 7隔離元件的崩潰電壓及電流做比較，俾說明段:構 請參考圖9A，在圖9A中菱形符號是表示在第二本體區的與 201244086 二之間之隔離兀件為單—段結構時，其崩潰電壓只能在 戸弓认-寺以下’矩形符號是表示當第二本體區60與漂移區70之 =隔離元件具有三個段結構時，其崩潰輕可以提高到接近43 s相對於在第二本體區6〇與漂雜％之間僅有單—段結構 件之同壓金氧半導體元件而言其崩潰電壓已經可以提 二伏特’接著’二角形符號是表示當第二本體區⑼與漂移區 处^間的隔離疋件具有四個段結構時，其崩潰電壓可以提高到43 伙特左右；以及圓形符號是表示當第二本體區6〇與漂移區7〇之 間的隔離元件具有五個段結構時，其崩親壓可以提高到Μ伏特 以上。 因此，很明顯的可以得到，當設置在第二本體區6〇與漂移區 =之間的隔離元件分成愈多區段時，可以提高其崩潰電壓，因此， 间壓金氧半導體7〇件可以承受較高㈣潰電壓，而可以廣泛應用 於需要高壓的電子產品。 另外，請參考K 9B，菱形符號是表示當第二本體區60與漂 移區7=之間之隔離元件為單—段結構時’其電流值是接近 2.55xl〇女培(a),正方形符號是表示當第二本體區⑼與漂移區 70之=隔離，件是具有三個段結構時，其電流值是大於 2.55Χ10安培，二角形符號是表示當第二本體區60與漂移區70 之間的隔離兀件具有四個段結構時，其電流值是接近 2.6x10·4 安 培:以及圓形符號是表示當第二本體區6〇與漂移區7〇之間的隔 離元件具有五個段結構時’其魏值是大於2 63前4安培。 _因此，很明顯的可以制，當第二本體區60與漂移區70之間 的隔離70件分成愈多區段時，其電流愈高相對地該在第二本體區 60與漂移區70之間的電阻值也愈低。而藉由改變第二本體區6〇 與漂移區7G之元件的結構，可以達龍高㈣電壓而降低 201244086 導通電阻值，不需要改變製程，僅 阻上改變隔離元件_案，即可元件時，在光 件的製程來完成。 彻絲的高㈣氧半導體元 雖然本發明已以較佳實施例揭露如上，然其 本發明，任何熟習此技蓺者，在 i、，、卜用乂限疋 内，告可作此❹审Λ 在離本發明之精神和範圍 附之申請專利制所界定者鱗。料月之保―圍當視後 【圖式簡單說明】 表示在基板上具有氧化層之 圖1係根據本發明所揭露之技術， 示意圖； 細應物在基板内 根據本發騎揭露之技術，絲將介錄料填充在溝渠 =構内’以形成多段式第—隔離元件及複數個第二隔離元件； 圖仏至圖4D係根據本發明所揭露之技術，表示多 隔離元件各種排列配置之俯視圖； ^ f根據本發明紅撕，縣基板上形成_結構及 在土板内形成源極/没極區之示意圖； 圖;6係根據本發明露之技術，係在基板内崎子植入方式 立成第本體區及漂移區以完成一馬壓金氧半導體元件之示 意圖； 圖7係根據本發明所揭露之技術，表示具有較 高壓金氧铸航叙雜ffl; W化層之 ^ f係根據本發明所揭露之技術，表示具有雙閘極結構之高壓 ，氧半導體元件之示意圖； 201244086 圖9A係根據本發明所揭露之技術，表示具有不同區段之多段 式第一隔離元件與崩潰電壓之關係示意圖；及 圖9B係根據本發明所揭露之技術，表示具有不同區段之多段 式第一隔離元件與電流之關係示意圖。 【主要元件符號說明】 10 高壓金氧半導體元件 1 基板 12 氧化層 14 氮化層 16a、16b 第一溝渠結構 18a、18b 第二溝渠結構 161第一隔離元件 161a、161b第一隔離元件之段結構 181a、181b第二隔離元件 30、90 閘極結構 30a、31a 閘氧化層 30b 多晶層 3〇c 矽化金屬層 32 間隙壁 40a 源極區 40b 汲極區 50 第一本體區 60 第二本體區 70 漂移區 80 井區 12 201244086In order to have a thicker _2 oxide layer, the St ^ ^ 空 金 金 金 金 金 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 此 闲 闲 闲 闲 闲 闲 闲 闲 闲 闲 闲 闲 闲 闲The thickness of the 201244086 thyristor layer 30a formed by the lateral diffusion MOS process is thick. For example, the ruthenium oxide layer also contributes to the modification. Therefore, the gate with a thick thickness a...· 吾原, Λ and polar guide Through resistance value (Rdson) 〇 In addition, the blue-skinning layer 31a is also formed between the multi-segment first 161a and the second-segment structure 161b. The Kth structure of f can be as follows according to the above-mentioned steps - high voltage or as shown in Fig. 7, since the present case is in the first isolation element:: = === breakdown voltage (a value of St resistance). In the present invention, high voltage The gold-oxide semiconductor component between the regions. The threshold metal conductor read 10 can be laterally diffused 1 in the 'on the substrate 11 _ into a double-gate structure will be active ί, Region) is set in the drain region 4〇b and the channel candle_1) to make H, when there is a relatively large breakdown voltage, by the second body region (9) disc drift 19Ga~19Gf multi-segment first isolation element resistance The letter "2 is beneficial to have a lower conduction current under the condition of the breakdown voltage of the board. The steps and the functions of the elements are the same as the foregoing, and the multi-section type-isolation disclosed in the present invention is not The component ^ is only described by two segment structures, but in the following, the segment will be directed to the segmented segment having the segment segment: the spacer element, the segmented segmentation of the segmented segment, and the segmentation into two segments. Comparison of the breakdown voltage and current of the isolation component and the isolation component俾Description section: Please refer to FIG. 9A. In FIG. 9A, the diamond symbol indicates that the isolation voltage between the second body region and the 201244086 two is a single-segment structure, and the breakdown voltage can only be recognized in the 戸 bow- The 'rectangular symbol' below the temple means that when the second body region 60 and the drift region 70 have three segment structures, the collapse light can be increased to nearly 43 s relative to the second body region 6 漂 and drift %. The breakdown voltage of the same-voltage MOS device with only a single-segment structure can be increased by two volts. 'Then' the 'digonal symbol' indicates the isolation between the second body region (9) and the drift region. When there are four segment structures, the breakdown voltage can be increased to about 43 laps; and the circular symbol means that when the isolation element between the second body region 6 〇 and the drift region 7 具有 has five segment structures, it collapses. The pressure can be increased to more than volts. Therefore, it is obvious that when the isolation element disposed between the second body region 6〇 and the drift region= is divided into more sections, the breakdown voltage thereof can be increased, and therefore, the intervening MOS semiconductor can be Withstand high (four) collapse voltage, and can be widely used in electronic products that require high voltage. In addition, please refer to K 9B, the diamond symbol means that when the isolation element between the second body region 60 and the drift region 7 = is a single-segment structure, its current value is close to 2.55xl 〇 female ( (a), square symbol It means that when the second body region (9) is separated from the drift region 70, and the member has a three-segment structure, the current value is greater than 2.55 Χ 10 amps, and the binary symbol indicates that the second body region 60 and the drift region 70 are When the spacer element has a four-segment structure, the current value is close to 2.6x10·4 amps: and the circular symbol indicates that the spacer element between the second body region 6〇 and the drift region 7〇 has five segments. When the structure is 'the value of its value is greater than 2 63 before 4 amps. Therefore, it is obvious that when the isolation 70 between the second body region 60 and the drift region 70 is divided into more sections, the higher the current is, the opposite is the second body region 60 and the drift region 70. The lower the resistance value between them. By changing the structure of the components of the second body region 6〇 and the drift region 7G, it is possible to lower the voltage of the 201244086 on-resistance by the voltage of the high (four) voltage, without changing the process, and only changing the isolation component _ case, the component When the process of the light piece is completed. The present invention has been disclosed in the preferred embodiments as described above, but the present invention, anyone skilled in the art, is allowed to make such a trial within the limits of i,, and者 The scale defined by the patent application system attached to the spirit and scope of the present invention. FIG. 1 is a schematic view showing an oxide layer on a substrate. FIG. 1 is a schematic view showing a technique according to the present invention; The wire fills the trench material in the trench = in-frame to form a multi-segment-type isolation element and a plurality of second isolation elements; FIG. 4D shows a top view of various arrangement configurations of the plurality of isolation elements according to the technology disclosed in the present invention. ^ f According to the red tear of the present invention, the formation of a structure on the substrate of the county and the formation of a source/no-polar region in the soil plate; Figure; 6 is a technique according to the present invention, the method of sagging in the substrate A schematic diagram of forming a body region and a drift region to complete a horse-voltage MOS device; FIG. 7 is a technique according to the present invention, showing a higher pressure metal oxide casting argon; The technology disclosed in the present invention is a schematic diagram showing a high voltage, oxygen semiconductor device having a double gate structure; 201244086 FIG. 9A is a multi-segment first having different segments according to the disclosed technology. Showing the relationship of the elements from breakdown voltage; and 9B of the system according to the present invention is disclosed art, many different sections of the graph showing a relationship-type segments of a first spacer member having current. [Main component symbol description] 10 high voltage MOS device 1 substrate 12 oxide layer 14 nitride layer 16a, 16b first trench structure 18a, 18b second trench structure 161 first isolation element 161a, 161b first isolation element segment structure 181a, 181b second isolation element 30, 90 gate structure 30a, 31a gate oxide layer 30b poly layer 3〇c deuterated metal layer 32 spacer 40a source region 40b drain region 50 first body region 60 second body region 70 drift zone 80 well zone 12 201244086
I I 190 隔離元件 190a〜190f 隔離元件之段結構I I 190 isolation element 190a~190f segment structure of isolation element
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