201240472 六、發明說明： 【發明所屬之技術領域】 本揭露是有關於一種自動校正影像之方法，特別是有 關於一種藉由自動同步類比至數位轉換器之輸入訊號，以 達到自動校正影像功校之方法。 【先前技術】 由於訊號的數位化有助於訊號的處理、分析與儲存， 因此數位與類比訊號的轉換技術越來越受到重視。類比至 數位轉換器（Analog to Digital ; ADC)是一種用來將類比訊 號轉換為數位訊號的裝置。由於自然界中的訊號大多以類 比方式存在，因此需要類比至數位轉換器來將類比訊 換成數位訊號。 二現今的電子產品，例如液晶電視、個人電腦、行動電 活等，大多使用了類比至數位轉換器來進行色彩訊號的轉 ::例如’以三原色(RGB)型態來輸入的色彩訊號通常會 破分為紅色訊號、藍色訊號和綠色訊號來分別處理。紅色 =號、藍色訊號和綠色訊號會被送人相應的類比至 換器中’时別轉換出紅色、藍色和綠色的數位灰階訊號。 在類比至數位的轉換過程中，通常需要 來對輪入資料(例如RGB等三輸入訊:二 右輸入資料受到影響（例如，傳輪路徑不同_ 、、:而， RGB不同步），時脈訊號可能無法 认訊號 而 導致影像的顏色便會出現異常。 取樣輪入資料 其可對輸 因此，需要一種自動校正螢幕影像之方法， 201240472 入 資料進行同步校正， 以避免影像顏色出現異常 【發明内容】 本發明之一 + 此自動校正面是在提供一種自動校正影像之方法。 換器的類比法，可自動地校正輸入至類比至數位轉 類比至數位轉振^的相位，並挑選出適當的工作時脈給 比色彩訊號。、°以使類比至數位轉換器正確地取樣類 根據本發明夕 中，首先根據則加施例’在此自動校正影像之方法 比色彩訊號以及二來提供第一類比色彩訊號、第二類 以使類比至數办絲二類比色彩訊號至類比至數位轉換器， 色彩訊號以及輸出第一數位色彩訊號、第二數位 不同之候選時脈了—位色彩訊號。然後，提供複數個相位 器來取樣第1 :候選時脈係用以供類比至數位轉換 類比色彩訊號。接彩錢、第二類比色彩訊號以及第三 後，從候_脈+設順序來排列候選時脈。然 換器利用基準時脈來：二：脈’其中當類比至數位轉 出之數位色采^考 ’，類比至數位轉換器所輪 試=率:脈作為搜尋起點來從候選時脈二 時脈為候選時脈令最先使第-數脈，f中第一測試 之時脈，繼第-測試時脈決定後，第號轉態(A咖） 脈中最先使第二數位色彩訊號轉離之時脈為候選時 脈决定後，笫_ 。夺脈，繼第二測試時 第二測试時脈為該些候選時脈中最先使第三數 5 201240472 位色彩訊號轉態之眭晰 ^ 時脈。然後，計算第一測試時脈和第二 測试時脈之一第一如a μ -延遲時間H 並根據第—相位差來計算出第 之第二相位差，並根 =二測試時脈和該第三測試時脈 „ ^么%〜兀根據第二相位差來計算出第二延遲時 二：U丁訊號延遲步驟，以根據第-延遲時間、第 a使第一數位色彩訊號、第二數位色彩訊號以 彩訊號同步。接著，進行工作時腻計算步驟， ^ 7 °式時脈或該第三測試時脈來計算出工作時 2楚以广時脈來取樣已被延遲之該第，類比色彩訊 第貞色彩訊號以及第三類比色彩訊號。 【實施方式】 C # J圖，其係緣示根據本發明實施例之影像校 、^構不意圖。影像校正裝置110係用以根據 類比至數位轉換器所輸出之數位色彩訊號⑽UT、GOUT 和BOUT來权正所輸入之類比色彩訊號rin、〇ΐΝ和bin 的相位’並根據校正後的類比色彩訊號RIN、GIN和bin 來選擇出適當的取樣時脈SCLK，以使類比至數位轉換器 120可輸出正確的數位色彩訊號R〇UT、G〇UT和Β〇υτ。 在本實施例中，類比色彩訊號RIN、GIN和BIN分別為紅 色類比訊號、綠色類比訊號以及藍色類比訊號，而數位色 彩訊號ROUT、GOUT和BOUT則分別為紅色數位灰階訊 號、綠色數位灰階訊號以及藍色數位灰階訊號。 影像校正裝置110包含延遲控制器111、延遲器 112a〜112c以及時脈選擇器113。延遲控制器111係用以接 201240472 收數位色彩訊號ROUT、GOUT和BOUT，並根據數位色 彩訊號ROUT、GOUT和BOUT來控制延遲器U2a〜112c， 以使延遲器112a〜112c分別延遲類比色彩訊號RIN、GIN 和BIN。另外，延遲控制器ill亦根據數位色彩訊號 ROUT、GOUT和BOUT來控制時脈選擇II n3輸出工作時 脈SCLK來取樣經過延遲後的類比色彩訊號尺爪、gin和 BIN。在以下的說明中，將詳細介紹本實施例所採用的影 像校正方法。 請參照第2圖，其係繪示根據本發明實施例之自動影 像校正方法200的流程示意圖。在影像校正方法2〇〇中， 首先進行圖案輸入步驟210，以根據測試圖案來提供類比 色彩訊號RIN、GIN和BIN至類比至數位轉換器12〇。在 本實施例中’測δ式圖案為點圖案(D〇t Pattern)，而類比至數 位轉換器120輸出數位色彩訊號rout、GOUT和BOUT 係對應至此點圖案。接著，進行候選時脈提供步驟220， 以提供多個同頻率但相位不同之候選時脈，其中後選時脈 的頻率等於類比色彩訊號的資料傳輸率。在本實施例中， 共有64個相位不同的時脈CLK1〜CLK64被提供來做為候 選時脈，其中CLK64的相位最大，CLK1的相位最小且時 脈CLK1〜CLK64的頻率與點圖案(D〇t PaWern)的資料傳輪 率相同。 然後’進行排列步驟230，以根據預設順序來排列這 些候選時脈。在本實施例中，候選時脈的排列係以相位的 大小來進行，因此CLK1為第一個候選時脈，而CLK64為 最後一個候選時脈。值得注意的是，雖然本實施例之候選 201240472 時脈係由小排到大’但在本發明之其他實施射亦可由大 排到小。 接著，進行基準時脈選定步驟240，以從候選時脈 CLK1 CLK64中選出—基準時脈。在進行基準時脈選定步 驟240中’係將候選時脈輸人至類比至數位轉換器12〇， 並撿測數位㈣織R〇UT、G()UT和Β·的值是皆相 同（皆為0或皆為1)。例如，若將候選時脈CLK1輸入至類 比至數位轉換器12G後，數位色彩訊號R〇UT、G〇UT和 BOUT的值皆相同時，則賴選時脈clki為基準時脈。 值得注意的是，對於64個候選時脈而言，可能會有多個候 選時脈可被挑選為基準時脈，但在本實施例中，只需要找 出一個即可。 然後，進行搜尋步驟250，以利用基準時脈作為搜尋 起點來從候選時脈中決定出第一測試時脈、第二測試時脈 以及第二測試時脈，其中第一測試時脈為候選時脈中最先 使某一個數位色彩訊號(例如ROUT)轉態（Assert)之時脈； 第二測試時脈為繼第一測試時脈決定後，候選時脈中最先 使另一數位色彩訊號(例如G0UT)轉態之時脈；第三測試時 脈為繼第二測試時脈決定後，候選時脈中最先使最後一個 色彩訊號(例如BOUT)轉態之時脈。此處所謂的轉態係指訊 號的邏輯由0轉變至1或是由i轉變至〇的現象，以8bit 的ADC為例則由〇〇〇〇〇〇〇〇轉變至丨丨丨丨丨丨丨丨或是由 11111111轉變至〇〇〇〇〇〇〇〇的現象。搜尋步驟25〇係進行多 個子搜尋步驟來分別搜尋（或決定）第一測試時脈、第二測 試時脈和第三測試時脈，以下將以一範例來具體說明搜尋 201240472 步驟250。 以CL在驟250中，若CLK1被挑選為基準時脈，則 以CLK1為起點依序將CLK1〜CLK64 換器120,直馳㈣數位色彩⑽發生料轉 =:生輪入至類比至數位轉換器 琥ROUT發生轉態，則以CLK1 i為第—測試時脈 再從CLK12開始，繼續將候選時脈輸人至類比 器120’直到檢測出其他的另一數位色彩訊號發生轉：現 象。例如，若CLK24被輸入至類比至數位轉換器12〇後， 數位色彩訊號GOUT發生轉態，則以CLK24為第二測試時 脈。然後，再從CLK25開始，繼續依序將候選時脈輸^至 類比至數位轉換器120，直到檢測出最後的數位色彩訊號 發生轉態現象。例如，若CLK31被輸入至類比至數位轉換 器120後，數位色彩訊號BOUT發生轉態，則以CLK31 為第^測試時脈。當第一測試時脈、第二測試時脈和第三 測試時脈都被找到以後，便跳至下一個步驟。 值得注意的是，在本發明之其他實施例中，當使用其 他候選時脈來作為基準時脈時，例如CLK3，若搜尋步驟 250搜尋至CLK64之後，還未決定出所有的測試時脈，則 需返回至CLK1以搜尋尚未被搜尋的候選時脈CLK1和 CLIC2 〇 搜尋步驟250完成後，接著進行延遲時間計算步驟 2 60 ’以根據第一測試時脈和第二測試時脈間的相位差來計 算出延遲時間Tdl以及根據第二測試時脈和第三測試時脈 間的相位差來計算出延遲時間Td2。然後，進行訊號延遲 201240472 步驟270，以利用根據延遲時間Tdl、Td2來利用延遲器 112a〜112c使數位色彩訊號R〇UT、GOUT和BOUT同步。 請參照第3圖，其係繪示根據本發明實施例之測試時 脈與數位色彩訊號的關係示意圖。在本實施例中，CLK1 被挑選為基準時脈，CLK11為第一測試時脈，CLK24為第 二測試時脈，CLK31為第三測試時脈’而延遲時間Tdl和201240472 VI. Description of the Invention: [Technical Field] The present disclosure relates to a method for automatically correcting images, and more particularly to an automatic synchronization analog image power meter by automatically synchronizing analog input signals to analog converters The method. [Prior Art] Since the digitization of signals contributes to the processing, analysis and storage of signals, digital and analog signal conversion techniques are receiving more and more attention. Analog to Digital (ADC) is a device used to convert analog signals into digital signals. Since most of the signals in nature exist in analogy, analog to digital converters are needed to convert analog signals into digital signals. Secondly, today's electronic products, such as LCD TVs, personal computers, mobile computers, etc., mostly use analog-to-digital converters for color signal conversion: for example, 'color signals input in the three primary colors (RGB) type usually Divided into red signal, blue signal and green signal to deal with separately. The red =, blue, and green signals will be sent to the corresponding analog to the 'replacer' and the red, blue, and green digital grayscale signals will be converted. In the analog to digital conversion process, it is usually necessary to input data (such as RGB and other three input signals: two right input data is affected (for example, the different paths are _, , :, RGB is not synchronized), the clock The signal may not be recognized by the signal and the color of the image will be abnormal. Sampling the wheeled data can be converted. Therefore, a method for automatically correcting the screen image is needed. 201240472 Incoming data for synchronization correction to avoid abnormal color of the image. One of the inventions + This automatic correction surface is a method for automatically correcting an image. The analogy of the converter can automatically correct the phase of the input to the analog to digital analogy to the digital transfer ^ and select the appropriate The working clock gives a color signal, and the analogy to the digital converter is correctly sampled. According to the present invention, firstly, according to the embodiment, the method of automatically correcting the image here is more than the color signal and the second. Analog color signal, the second type is to make the analog to the analogy of the color analog to the analog to digital converter, the color signal is And outputting the first digital color signal and the second digit different candidate clocks to the bit color signal. Then, providing a plurality of phasers to sample the first 1: candidate clock system for analog to digital conversion analog color signal. After the color money, the second analog color signal, and the third, the candidate clocks are arranged from the order of the _ pulse + set. The converter uses the reference clock: two: the pulse 'where the analogy to the digital digits ^考', analog to digital converter round test = rate: pulse as the starting point of the search from the candidate clock two clocks as the candidate clock to make the first number of pulses, the first test of f, followed by After the first-test clock is determined, the first time in the first transition state (A coffee), the clock that turns the second digit color signal away is determined as the candidate clock, 笫_. The second test clock is the first of the candidate clocks to make the third number 5 201240472 color signal transition state ^ clock. Then, calculate the first test clock and the second test clock Like a μ - delay time H and calculate the second phase according to the first phase difference , root = two test clocks and the third test clock „ ^ % % 兀 兀 according to the second phase difference to calculate the second delay two: U 讯 signal delay step, according to the first delay time, the first The first digital color signal and the second digital color signal are synchronized by the color signal. Then, the working time calculation step, the ^7° clock or the third test clock is used to calculate the working time. The sample is delayed, the analog color signal, and the third analog color signal. [Embodiment] The C #J diagram, which is based on the image of the embodiment of the present invention, is not intended. The image correcting device 110 is configured to correct the phase of the analog color signals rin, 〇ΐΝ, and bin input according to the digital color signals (10) UT, GOUT, and BOUT output from the analog to digital converter and according to the corrected analog color signal. RIN, GIN, and bin select the appropriate sampling clock SCLK so that the analog to digital converter 120 can output the correct digital color signals R〇UT, G〇UT, and Β〇υτ. In this embodiment, the analog color signals RIN, GIN, and BIN are red analog signals, green analog signals, and blue analog signals, respectively, and the digital color signals ROUT, GOUT, and BOUT are red digital gray signals, green digital gray, respectively. Order signal and blue digit gray scale signal. The image correcting device 110 includes a delay controller 111, delays 112a to 112c, and a clock selector 113. The delay controller 111 is configured to receive the 201240472 digital color signals ROUT, GOUT and BOUT, and control the delay devices U2a to 112c according to the digital color signals ROUT, GOUT and BOUT, so that the delay devices 112a to 112c are respectively delayed by the analog color signal RIN. , GIN and BIN. In addition, the delay controller ill also controls the clock-selected II n3 output operating clock SCLK according to the digital color signals ROUT, GOUT and BOUT to sample the delayed analog color signal finger, gin and BIN. In the following description, the image correction method employed in the embodiment will be described in detail. Referring to FIG. 2, a schematic flowchart of an automatic image correction method 200 according to an embodiment of the present invention is shown. In the image correction method 2, a pattern input step 210 is first performed to provide the analog color signals RIN, GIN, and BIN to analog to the digital converter 12A according to the test pattern. In the present embodiment, the delta pattern is a dot pattern, and the analog to digital converter 120 outputs digital color signals rout, GOUT, and BOUT corresponding to the dot pattern. Next, a candidate clock providing step 220 is performed to provide a plurality of candidate clocks of the same frequency but different phases, wherein the frequency of the selected clock is equal to the data transmission rate of the analog color signal. In this embodiment, a total of 64 clocks CLK1 to CLK64 having different phases are provided as candidate clocks, wherein the phase of CLK64 is the largest, the phase of CLK1 is the smallest, and the frequency and dot pattern of the clocks CLK1 to CLK64 (D〇) t PaWern) has the same data transfer rate. Then, an arranging step 230 is performed to arrange the candidate clocks according to a preset order. In this embodiment, the arrangement of candidate clocks is performed in phase, so CLK1 is the first candidate clock and CLK64 is the last candidate clock. It should be noted that although the candidate 201240472 of the present embodiment is from small to large, the other implementations of the present invention may range from large to small. Next, a reference clock selection step 240 is performed to select a reference clock from the candidate clocks CLK1 CLK64. In the reference clock selection step 240, the candidate clock is input to analog to the digital converter 12〇, and the values of the digital (four) woven R〇UT, G()UT, and Β· are the same (both 0 or both are 1). For example, if the candidate clock CLK1 is input to the analog-to-digital converter 12G and the values of the digital color signals R〇UT, G〇UT, and BOUT are the same, then the clock clki is selected as the reference clock. It is worth noting that for 64 candidate clocks, there may be multiple candidate clocks that can be selected as the reference clock, but in this embodiment, only one can be found. Then, a searching step 250 is performed to determine the first test clock, the second test clock, and the second test clock from the candidate clocks by using the reference clock as the search starting point, wherein the first test clock is a candidate The first pulse of a digital color signal (such as ROUT) is turned into a pulse; the second test clock is determined by the first test clock, and the other candidate color signal first makes another digital color signal. (For example, G0UT) The clock of the transition state; the third test clock is the clock that first shifts the last color signal (such as BOUT) in the candidate clock after the second test clock is determined. The so-called transition state here refers to the phenomenon that the logic of the signal changes from 0 to 1 or from i to 〇. Taking an 8-bit ADC as an example, the transition from 〇〇〇〇〇〇〇〇 to 丨丨丨丨丨丨丨丨 or the phenomenon of transition from 11111111 to 〇〇〇〇〇〇〇〇. The search step 25 performs a plurality of sub-search steps to separately search (or decide) the first test clock, the second test clock, and the third test clock. The following will specifically describe the search 201240472 step 250. With CL in step 250, if CLK1 is selected as the reference clock, CLK1~CLK64 converter 120 is sequentially sequenced starting from CLK1, and the direct (four) digital color (10) is turned on =: raw round to analog to digital conversion If the switch A is in the state of ROUT, then CLK1 i is the first—the test clock starts from CLK12 and continues to input the candidate clock to the analogizer 120' until another color signal is detected: For example, if CLK24 is input to the analog-to-digital converter 12〇 and the digital color signal GOUT transitions, CLK24 is used as the second test pulse. Then, starting from CLK25, the candidate clock is continued to be sequentially analogized to the digital converter 120 until the last digital color signal is detected to be in a transition state. For example, if CLK31 is input to analog to digital converter 120 and the digital color signal BOUT transitions, CLK31 is used as the test clock. When the first test clock, the second test clock, and the third test clock are all found, skip to the next step. It should be noted that in other embodiments of the present invention, when other candidate clocks are used as the reference clock, for example, CLK3, if all the test clocks have not been determined after the search step 250 searches for CLK64, Returning to CLK1 to search for candidate clocks CLK1 and CLIC2 that have not yet been searched. After the search step 250 is completed, a delay time calculation step 2 60 ' is then performed to determine the phase difference between the first test clock and the second test clock. The delay time Td1 is calculated and the delay time Td2 is calculated from the phase difference between the second test clock and the third test clock. Then, signal delay 201240472 is performed to synchronize the digital color signals R〇UT, GOUT, and BOUT by the delays 112a to 112c according to the delay times Td1, Td2. Please refer to FIG. 3, which is a schematic diagram showing the relationship between a test clock and a digital color signal according to an embodiment of the present invention. In this embodiment, CLK1 is selected as the reference clock, CLK11 is the first test clock, CLK24 is the second test clock, CLK31 is the third test clock' and the delay time Tdl and
Td2則分別根據CLK11和CLK24間的相位差以及CLK24 和CLK31間的相位差計算而得。得到延遲時間Tdl和Tcj2 後’分別將類比色彩訊號RIN、GIN延遲Tdl+Td2以及Td2 的時間’如此即可使數位色彩訊號ROUT、GOUT和BOUT 同步。 在數位色彩訊號ROUT、G0UT和Β〇υτ同步後，進 2作時脈計算步驟，以根據第-測試時脈或第三測 =時脈計算出類比至數位轉換器m實際進行取樣工作所 驟:脈。4參照第4圖，其鱗示工作時脈計算步 的流程示意圖。在本實施例之工作時脈計算步驟彻 cuult?行排序步· 282，以排序候選時脈 序步驟282中，係以第三職《為 時脈。接著，進行二=個時脈為終點’依序排列候選 _、_丁和=:::找出使數位色彩訊號 依排序步驟282之排序來輸:候;==了脈。例如’ 器⑶，直到數位色彩贿^時脈至類比至數位轉換 為止，而類比至數付赖/ 0UT、G0UT和B0UT轉態 決定為第四測試時脈(例如=所=之帥 ⑴如CLK63)。然後，進行工作時脈 201240472 286 ’以從位於第四測試時脈和第三測試時脈間 的候選時脈中，挑選—者作為卫作時脈，例如取位於第四 測試時脈和第三測試時脈正中間的候選時脈。 請回到第3圖。由第3圖可看出，第三測試時脈^^ 和第四測試時脈CLK63係分別對應至已延遲 號_、⑽和歷的上升邊緣和下降邊緣，因員= 測试時脈CLK31和第四測試時脈63中間挑選一者來作為 工作時脈，對於提高取樣的正確性和對訊的容忍度有相當 的幫助。然而，若不需要較大的容忍度來進行取^，工作 時脈計算步驟細亦可直接蚊第三測試時脈來做為工作 時脈。 由上述說明可知，本發明實施例之自動影像校正裝置 100與自動影像校正方法120係藉由延遲類比色彩訊號 RIN、GIN和BIN以及適當選擇取樣的工作訊號來校正類 比至數位轉換器120所輸出的數位色彩訊號R〇UT、BOUT 和GOUT，避免類比至數位轉換器120進行錯誤的取樣而 輸出錯誤的數位色彩訊號。 另外，對於搜尋步驟250而言，由於數位色彩訊號 ROUT、BOUT以及GOUT可能全部或部分同時轉態，因 此在本發明之其他實施例中，搜尋步驟250中可加入判斷 步驟來幫助判斷數位色彩訊號ROUT、BOUT以及GOUT 是否同時轉態。例如，當CLK5被輸入至類比至數位轉換 器120後，數位色彩訊號ROUT發生轉態時，可同時判斷 數位色彩訊號GOUT和BOUT是否轉態。若數位色彩訊號 GOUT和BOUT全部轉態了，則表示CLK5可同時取樣到 201240472 數位色彩訊號ROUT'GOUT和BOUT，故將CLK5決定為 第三測試訊號。若數位色彩訊號GOUT和BOUT中僅有一 者與數位色彩訊號ROUT同時轉態，則表示CLK5可同時 取樣到數位色彩訊號ROUT以及另一個數位色彩訊號，故 將CLK5決定為第二測試訊號，然後再接著搜尋第三測試 訊號。 請同時參照第5圖和第6圖，第5圖係繪示根據本發 明另一實施例之自動影像校正方法5〇〇的流程示意圖，第 6圖係繪示根據本實施例之測試時脈與數位色彩訊號的關 係示意圖。自動影像校正方法5〇〇係類似於自動影像校正 方法200，但不同之處在於自動影像校正方法5〇〇之搜尋 步驟550、延遲步驟570以及工作時脈計算步驟58〇與自 動影像校正方法200的搜尋步驟250、延遲步驟270以及 工作時脈計算步驟280不同。 時’搜尋的起點則為CLK1，ff 尋方向係由CLK1至CLK64， 此類推直到CLK2。以下再以一 正方法500。 在本實施例中，搜尋步驟550的搜尋方向係與搜尋步 驟250的方向相反。舉例而言，若基準時脈被決定為江幻 而終點則為CLK2。意即，搜 ’再由CLK64至CLK63，如 -範例來具體介紹自動影像校Td2 is calculated based on the phase difference between CLK11 and CLK24 and the phase difference between CLK24 and CLK31, respectively. The delay time Tdl and Tcj2 are obtained, and the analog color signals RIN and GIN are delayed by Tdl+Td2 and Td2, respectively, to synchronize the digital color signals ROUT, GOUT and BOUT. After the digital color signals ROUT, G0UT and Β〇υτ are synchronized, the clock calculation step is performed to calculate the analogy to the digital converter m according to the first test clock or the third test = clock. :pulse. 4 Referring to Fig. 4, the scale shows the flow chart of the working clock calculation step. In the working clock calculation step of the embodiment, the step 282 is sorted to sort the candidate time sequence in step 282, and the third job is the clock. Then, the two = clocks are used as the end point. The candidates _, _, and =:: are sequentially arranged to find that the digital color signals are sorted according to the sorting step 282: *; For example, '3', until the digital color bribes to the analog to digital conversion, and the analogy to the number / 0UT, G0UT and B0UT transition is determined as the fourth test clock (for example = = = handsome (1) such as CLK63 ). Then, the working clock 201240472 286 ' is selected from the candidate clocks located between the fourth test clock and the third test clock as the guard clock, for example, in the fourth test clock and the third Test the candidate clock in the middle of the clock. Please return to Figure 3. As can be seen from Fig. 3, the third test clock and the fourth test clock CLK63 correspond to the rising edge and the falling edge of the delayed number _, (10) and the calendar respectively, the factor = test clock CLK31 and The middle of the fourth test clock 63 is selected as the working clock, which is quite helpful for improving the correctness of the sampling and the tolerance of the communication. However, if a large tolerance is not required for the acquisition, the working clock calculation step can also be used as the working clock directly. It can be seen from the above description that the automatic image correcting device 100 and the automatic image correcting method 120 of the embodiment of the present invention correct the analog output to the digital converter 120 by delaying the analog color signals RIN, GIN and BIN and appropriately selecting the sampling working signals. The digital color signals R〇UT, BOUT, and GOUT prevent the analog to digital converter 120 from erroneously sampling and output an erroneous digital color signal. In addition, for the searching step 250, since the digital color signals ROUT, BOUT, and GOUT may be all or partially rotated at the same time, in other embodiments of the present invention, a determining step may be added in the searching step 250 to help determine the digital color signal. Whether ROUT, BOUT, and GOUT are in the same state. For example, when CLK5 is input to the analog-to-digital converter 120, when the digital color signal ROUT transitions, it can simultaneously determine whether the digital color signals GOUT and BOUT are in a transition state. If the digital color signals GOUT and BOUT are all transitioned, it means that CLK5 can simultaneously sample the 201240472 digital color signals ROUT'GOUT and BOUT, so CLK5 is determined as the third test signal. If only one of the digital color signals GOUT and BOUT is simultaneously rotated with the digital color signal ROUT, it means that CLK5 can simultaneously sample the digital color signal ROUT and another digital color signal, so CLK5 is determined as the second test signal, and then Then search for the third test signal. Please refer to FIG. 5 and FIG. 6 simultaneously. FIG. 5 is a schematic flow chart of an automatic image correction method 5〇〇 according to another embodiment of the present invention, and FIG. 6 is a diagram showing a test clock according to the embodiment. Schematic diagram of the relationship with digital color signals. The automatic image correction method 5 is similar to the automatic image correction method 200, but differs in the automatic image correction method 5, the search step 550, the delay step 570, and the working clock calculation step 58 and the automatic image correction method 200. The search step 250, the delay step 270, and the work clock calculation step 280 are different. The starting point of the search is CLK1, and the ff direction is from CLK1 to CLK64, and so on until CLK2. The following method is again followed by a positive method 500. In the present embodiment, the search direction of the search step 550 is opposite to the search step 250. For example, if the reference clock is determined to be Jiangyue and the end point is CLK2. That is to say, search 'from CLK64 to CLK63, such as - example to introduce the automatic image school
。接著 出弟一測試時脈為CLK56, 第三測試時脈為CLK38。 在本例中’搜尋步 ，第一測試時脈為 ’延遲時間Tdl和 12 201240472. Then the test clock is CLK56, and the third test clock is CLK38. In this example 'search step, the first test clock is' delay time Tdl and 12 201240472
Td2可分別根據CLK56和CLK50間的相位差以及CLK50 和CLK38間的相位差計算而得。得到延遲時間Tdl和Td2 後，延遲步驟570分別將類比色彩訊號RIN、GIN延遲 Tdl+Td2以及Tdl的時間’如此即可使數位色彩訊號RIN、 GIN和BIN同步。當數位色彩訊號RIN、GIN和BIN同步 後，便進行工作時脈計算步驟580。 请參照第7圖，其係繪示工作時脈計算步驟58〇的流 私示思圖。在本實施例之工作時脈計算步驟58〇中，首先 進行排序步驟582，以排序候選時脈CLK1〜CLK64。在排 序步驟582中’係以第—測試時脈為起點，第—測試時脈 之上一個時脈為終點，依序排列候選時脈。值得注意的是， 由於搜尋步驟550係由CLK1往回搜尋CLK64、CLK63等， 因此第一測試時脈CLK56的上—時脈為CLK55而非 CLK57。接著，進行搜尋步驟564,以找出使數位色彩訊號 ROUT、GOUT和BOUT轉態之一第四測試時脈。例如， 依排序步驟562之排序來輸入候選時脈至類比至數位轉換 器120，直到數位色彩訊號R〇uT、GOUT和BOUT轉態 為止，而類比至數位轉換器於此時所採用之候選時脈即被 決定為第四測試時脈(例如CLK30)。然後，進行工作時脈 挑選步驟566，以位於從第四測試時脈CLK3〇和第一測$ 時脈CLK50間的候選時脈中，挑選—者作為工作時脈:例 如取位於第四測試時脈和第一測試時脈正中間的候 脈。 雖然本發明已以數個實施例揭露如上，然其並非用以 限定本發明，在本發明所屬技術領域中任何具有通常知識 201240472 者，在不脫離本發明之精神和範圍内，當可作各種之更動 與潤飾，因此本發明之保護範圍當視後附之申請專利範圍 所界定者為準。 【圖式簡單說明】 為讓本發明之上述和其他目的、特徵、和優點能更明 顯易懂，上文特舉數個較佳實施例，並配合所附圖式，作 詳細說明如下： 第1圖係繪示根據本發明一實施例之影像校正裝置的 架構不意圖。 第2圖係繪示根據本發明一實施例之自動影像校正方 法的流程示意圖。 第3圖係繪示根據本發明一實施例之測試時脈與數位 色彩訊號的關係示意圖。 第4圖係繪示根據本發明一實施例之工作時脈計算步 驟的流程示意圖。 第5圖係繪示根據本發明另一實施例之自動影像校正 方法的流程示意圖。 第6圖係繪示根據本發明另一實施例之測試時脈與數 位色彩訊號的關係示意圖。 第7圖係繪示根據本發明另一實施例之工作時脈計算 步驟的流程示意圖。 【主要元件符號說明】 14 201240472 110 :影像校正裝置 112a〜112c :延遲器 120 :類比至數位轉換器 200 :自動影像校正方法 220 :候選時脈提供步驟 240 :基準時脈選定步驟 260 :延遲時間計算步驟 280 :工作時脈計算步驟 284 :搜尋步驟 550 :搜尋步驟 580 :工作時脈計算步驟 584 :搜尋步驟 RIN :類比色彩訊號 BIN :類比色彩訊號 GOUT :數位色彩訊號 CLK1〜CLK64 :候選時脈 Td2 :延遲時間 111 :延遲控制器 113 :時脈選擇器 210 :圖案輸入步驟 230 :排列步驟 250 :搜尋步驟 270 :訊號延遲步驟 282 :排序步驟 286 :工作時脈挑選步驟 570 :訊號延遲步驟 582 :排序步驟 586 :工作時脈挑選步驟 GIN :類比色彩訊號 ROUT :數位色彩訊號 BOUT :數位色彩訊號Td2 can be calculated from the phase difference between CLK56 and CLK50 and the phase difference between CLK50 and CLK38, respectively. After the delay times Tdl and Td2 are obtained, the delay step 570 delays the analog color signals RIN, GIN by Tdl + Td2 and Tdl, respectively, to synchronize the digital color signals RIN, GIN and BIN. When the digital color signals RIN, GIN, and BIN are synchronized, the working clock calculation step 580 is performed. Please refer to Fig. 7, which is a flow chart showing the working clock calculation step 58〇. In the working clock calculation step 58 of the present embodiment, the sorting step 582 is first performed to sort the candidate clocks CLK1 to CLK64. In the sequence step 582, the first test clock is used as the starting point, and the first clock above the test clock is the end point, and the candidate clocks are sequentially arranged. It is worth noting that since the search step 550 searches for CLK64, CLK63, etc. by CLK1, the upper-clock of the first test clock CLK56 is CLK55 instead of CLK57. Next, a search step 564 is performed to find a fourth test clock that causes the digital color signals ROUT, GOUT, and BOUT to transition. For example, the candidate clock is input to analog to digital converter 120 in accordance with the ordering of sorting step 562 until the digital color signals R〇uT, GOUT, and BOUT transition, and the analog to digital converter is used at this time. The pulse is determined as the fourth test clock (eg CLK30). Then, a working clock selection step 566 is performed to select one of the candidate clocks from the fourth test clock CLK3 〇 and the first measured $ clock CLK 50 as the working clock: for example, when the fourth test is taken The vein and the waiting pulse in the middle of the first test clock. While the invention has been described above in terms of several embodiments, it is not intended to limit the invention, and any of the ordinary skill in the art to which the present invention pertains can be used in various embodiments without departing from the spirit and scope of the invention. The scope of protection of the present invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS The above and other objects, features, and advantages of the present invention will become more apparent and understood. 1 is a schematic diagram showing the architecture of an image correcting apparatus according to an embodiment of the present invention. 2 is a flow chart showing an automatic image correction method according to an embodiment of the present invention. FIG. 3 is a schematic diagram showing the relationship between a test clock and a digital color signal according to an embodiment of the invention. Figure 4 is a flow chart showing the operation clock calculation step according to an embodiment of the present invention. Figure 5 is a flow chart showing an automatic image correction method according to another embodiment of the present invention. Figure 6 is a diagram showing the relationship between a test clock and a digital color signal according to another embodiment of the present invention. Figure 7 is a flow chart showing the steps of calculating the working clock according to another embodiment of the present invention. [Main component symbol description] 14 201240472 110 : Image correction device 112a to 112c: delay device 120: analog to digital converter 200: automatic image correction method 220: candidate clock supply step 240: reference clock selection step 260: delay time Calculation step 280: Working clock calculation step 284: Search step 550: Search step 580: Working clock calculation step 584: Search step RIN: Analog color signal BIN: Analog color signal GOUT: Digital color signal CLK1 to CLK64: Candidate clock Td2: delay time 111: delay controller 113: clock selector 210: pattern input step 230: arrangement step 250: search step 270: signal delay step 282: ordering step 286: working clock selection step 570: signal delay step 582 : Sorting step 586: Working clock selection step GIN: analog color signal ROUT: digital color signal BOUT: digital color signal
Tdl :延遲時間 15Tdl: delay time 15