2012404504TW 37242twf.doc/n 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種影像感測器，且特別是有關於一 種影像感測器的像素電路。 【先前技術】 以光二極體(Photo Diode，PD)所實現的影像感測器 (Image Sensor)像素電路’尤其是互補式金屬氧化物半導體 (Complementary Metal-Oxide Semiconductor, CMOS)影像 感測器（簡稱CIS)，逐漸朝向高感光密度的趨勢發展。為了 辨識彩色影像，一般在不同的光二極體上配置不同顏色的 遽光片’再將接收到特定光波長的這些光二極體所產生的 汛號經由後端電路作訊號的運算與處理，但如此做法顯得 需耗費相當的晶片面積與成本。 另一作法是將三個光二極體垂直疊置於晶片而形成多 接面光二極體。藉由不同深度的多層光二極體來接收不同 波長之光源，如此就能有效降低面積需求且不需使用濾光 片來降低成本。然而，多接面光二極體不論在元件設計、 製程架構以及峨讀At路皆相對於單接面光二極體來得 複雜。再者，Μ接面光二極酬實現的像素電路在操作 過程中容易遭受大量雜訊。 【發明内容】 201240450,. TW 37242twf.doc/n 訊的=明提供一種影像感測器的像素電路，改善内部雜 本發明實施例提出-種影像感 第一開關、第二開關、第三開關、/的像素電路’包括 第-光二極體、第二光二極體以及：：關、第五開關、 關的第一端接收一第一參考電壓。_ “ 一極體。第一開 第一端輕接至第一開關的第二端。第:開關與第三開關的 耦接至第三開關的第二端。第二 光一極體的第一端 第二開關的第二端。第二光^體=體的第一端輕接至 一光二極體的第二端。第三光二 ^端直接連接至第 第二光二極體的第一端。第四開 端直接連接至 二《的第二端。第五開關的第—端耦至第三光 = 端。第，與第五開關 光感測i 感:器：素:路，包括 及第五開關。光感測器包含第一換雜四開關以 第二與第鳴區為第-導 四摻雜區之間，其中=虚第而第二^雜區配置於第二與第 三掺雜區相鄰接，且第三雜區相鄰接，第二與第 的第-端接收第—參考;壓第：摻雜區相鄰接。第一開關 端耦接至第-開關的第一開關與第三開關的第一 第-、。第二開關的第二端•接至第 4 201240450、 W 3 7242twf. doc/n ，區。第三開關的第二端輕 關的第-端耦接至第四掺雜區 =。第四開 :電=細開關與第五開關的第二端麵接至第二參 為讓本之上述特徵和優點能更明顯易懂 舉貫施例，並配合所附圖式作詳細說明如下。 ’ 【實施方式】 是2本發明的實施例說明—種影像感_統的 力月匕方塊不思圖。此影像感測系統包括影像感測器剛、 輸出放大器(output amplifier) 1〇1、類比數位轉換 to digital Converter，ADC) 1〇2與影像處理器（丨脱明 processor) 103。影像感測器100包括列驅動器（r〇wdriver) 110、像素陣列(pixel array) U0 與行驅動器(c〇lumn driver) 130。列驅動器lio連接像素陣列12〇的多條定址線，例如 定址線Ri。行驅動器130連接像素陣列12〇的多條讀出 線’例如讀出線Ci。在這些定址線與這些讀出線的交會處 分別配置一個像素電路，例如在定址線Ri與讀出線Ci的 交會處配置一個像素電路200。 配合列驅動器110對這些定址線的驅動時序，行驅動 器130可以經由這些讀出線讀取位於被驅動定址線上像素 電路的感測電壓訊號，然後將感測結果傳送給輸出放大器 101。輸出放大器1〇1將行驅動器130所讀出的感測結果加 以放大，然後將放大後的感測結果傳送給類比數位轉換器 201240450 W 37242twf.doc/n 102。類比數位轉換器102將類比的感測結果轉換為數位 值。影像處理器接收並處理此數位值。 圖2是依照本發明的實施例說明圖丨所示像素電路 200的等效電路示意圖。像素電路2〇〇包括第一開關、 第一開關M2、第三開關M3、第四開關M4、第五開關M5、 第一光二極體PD1、第二光二極體PD2以及第三光二極體 PD3。上述開關Ml〜M5可以用N通道金屬氧化物半導體 (N-channel metal oxide semiconductor, NMOS)電晶體實現 之。第一開關Ml的第一端接收第一參考電壓。於本實施 例中，所述第一參考電壓可以是重置電壓VRESET或是其 他固定的電壓。第一開關Ml受控於控制信號巾尺而決定 是否將重置電壓VRESET導引至第一開關！^^的第二端。 第二開關M2與第三開關M3的第一端耦接至第一開關M1 的第二端。 第一光二極體PD1的第一端耦接至第三開關M3的第 二端。第二光二極體PD2的第一端耦接至第二開關M2的 第二端。第二光二極體PD2的第二端直接連接至第一光二 極體PD1的第二端。第三光二極體PD3的第一端直接連 接至第二光二極體PD2的第一端。第四開關M4的第一端 耦接至第三光二極體PD3的第二端。第五開關M5的第一 端耦接至第一光二極體PD1與第二光二極體pD2的第二 端。第四開關M4與第五開關M5的第二端耦筮一务 考電壓。於本實施例中，所述第二參考電== 壓GND、共同電壓(common v〇itage)或是其他固定的電壓。 6 201240450 χ ji^^wij4TW 37242twf.doc/n 於本實施例中，重置電壓VRESET的準位被設定為高 於接地電壓GND，因此上述第一光二極體pD1、第二光二 極體PD2與第二光二極體PD3的第一端為陰極，而上述 第一光二極體PD1、第二光二極體PD2與第三光二極體 PD3的弟二端為極，如圖2所示。在其他實施例中，若 重置電壓VRESET的準位被設定為低於接地電壓gnd， 則上述第一光一極體PD1、第二光二極體與第三光二 極體PD3的第一 h為陽極，而上述第一光二極體PD1、第 二光二極體PD2與第三光二極體PD3的第二端為陰極。 上述第一開關M2、第三開關M3、第四開關M4與第 五開關M5分別受控於控制信號、〇c與φ(1。圖3 是依照本發明的實施例說_ 2所示控制的 圖。請參照圖2與圖3。於第—重置期關' Ml、第三開關M3與第五開關Μ5為導通(tum 〇η)，而第 一開關M2與第四開關Μ4為截止(turn off)。因此，第一光 二極體FD1、的陽極被接地，而第一光二極體削的陰極 可以被重置為約略重置電壓VRESET的準位。 於第-積分期間T2，第五開關M5為導通，而第一開 關Ml、第二開關M2、第三開關M3與第四開關M4為戴 止。因此於第一積分期間T2，第一光二極體則的陽極 被接地’而第-光二極體PD1的陰極電壓準位會以塑應於 光照量的速率降壓。第三開關M3能夠於第—積分^丁2 將第-光二極體ΗΜ隔開於第一開關⑷，也就是說能夠 將充電路徑與儲存電荷分離。如此一來，第三開關奶可 201240450 rw 37242twf.doc/n 將第-M Ml切換時產生之切換雜訊做有效的 以整體雜訊能降低。 所 於第-讀出期間T3,第三開關奶與第五開關M 導通，而第一開關Μ卜第二開關M2與第四開關M4為截 止。因此，行驅動器130可以於第一讀出期間T3透過 二開關M3直接或間接地讀出第一光二極體PD1的光照積 分結果(即第一光二極體PD1的陰極電壓準位）。在讀出第 一光二極體PD1的過程中，第二開關M2與第四開關 會持續被關閉著而不會干擾第一光二極體PD1的訊號。 於本實施例中，像素電路200更配置電晶體M6作為 源極隨耦器（source follower)。此電晶體M6的控制端(例如 閘極)耦接至第二開關M3與第三開關M3的第一端。電晶 體M6的第一端(例如汲極)耦接至第三參考電壓。於本^ 施例中’所述第三參考電壓可以是電源電壓VDD或是其 他固定參考電壓。於第一讀出期間T3，電晶體M6可以^ 據第一光二極體PD1的陰極電壓準位而從電晶體M6的第 二端(例如源極)輸出感測電壓。開關M7於第一讀出期間 T3被對應地導通，使得感測電壓可以經由讀出線Ci被傳 送至行驅動器130。電晶體M6可以將第一光二極體PD1 阻絕於像素陣列120中其它像素負載與導線負載，因此能 有良好的雜訊隔離效果。電晶體M6亦能提供足夠的推 力’將信號忠實且快速的反應到後端讀出電路(例如行驅動 器 130)。 8 201240450 37242twf.doc/n 请繼續參照圖2與圖3。於第二重置期間丁4，第一開 關Μ卜第二開關M2與第五開關M5為導通，而第三開關 M3與第四開關M4為戴止。因此，第二光二極體ρ〇2的 陽極被接地，而第二光二極體PD2的陰極可以被重置為約 略重置電壓VRESET的準位。於第二積分期間τ5，第五 開關Μ5為導通，而第一開關Ml、第二開關Μ2、第三開 關MS與第四開關Μ4為截止。因此於第二積分期間τ5， 第二光二極體PD2的陽極被接地，而第二光二極體pD2 的陰極電壓準位會時應於光照量的速率降壓。與第三開 關M3相似，第二開關M2能夠於第二積分期間τ5將第二 光二極體PD2隔開於第-開關Μ卜如此—來，第二開關 M2可將第-開關M1切換時產生之切換雜訊做有效的抑 制，所以整體雜訊能降低。 於第二讀出期間T6,第二開關奶與第五開關奶為 導通，而第-開關m、第三開關M3與第四開關M4為截 止。電晶體M6可以依據第二光二極體PD2的陰極電 位而從電晶體Μό的源極輸出感測電壓。因此，行驅 130可以於第二讀出期間Τ6透過讀出線α、開關奶# = 第二光二極體PD2的光照積分結果（即於第 貝 的感測電壓）。 π ^間T6 於第三重置期間Τ7，第一開關Μ卜第二 第四開關Μ4為導通，而第三開關Μ3與第五^ 與 截止。於第三積分顧Τ8，第四開關_為導& = 開關Ml、第一開關M2、第三開關M3與第五門關 5為 201240450 TW 37242twf.doc/n 截止。因此於第三積分期間T8，第三光二極體pD3的陽 極被接地’㈣三光二極體PD3的陰極電壓準位會以變鹿 於光照量的速率降壓。第二開關M2能夠於第 ^ T8將第二光二極體PD3隔開於第一開關M卜如此一來， ^開關M2可將第—開關M1切換時產生之切換雜訊做 有效的抑制，所以整體雜訊能降低。 於第二讀出期間T9,第二開_M2與第四開關⑽為 導通’而第-開關⑷、第三關M3與第五開關奶為截 止。電晶體M6可以依據第三光二極體咖的陰極電壓準 位而從電晶體M6的源極輸出感測電壓。因此，行驅動器 13^可以於第二·|賈出期間T9透過讀出線〇、開關讀出 第三光二極體PD3的光照積分結果(即於第三讀出期間T9 的感測電壓）。 —上述三個光二極體Pm、pD2、pD3可以被設定來接 收一原色，例如分別接收紅色光、綠色光以及藍色光。依 照圖3的說明來操作像素電路200内部的開關，可以改善 内部雜訊的干擾。 本發明不限制上述光二極體pD1、pD2、PD3的佈局 方式’例如可以將光二極體pD1、pD2、並排地配置 於曰曰片基底上，或是沿基底的垂直方向將光二極體pD1、 PD2、PD3疊置於該基底。 舉例來說，圖4是依照本發明的實施例說明圖2所示 ，二極體PD1、PD2、PD3的佈局結構剖面示意圖。本實 施例將以光感測器4〇〇的三接面(Triple_Juncti〇n)所形成的 201240450 4TW 37242twf.doc/n 寄生二極體來實現圖2所示光二極體PDi、pD2、pD3。 圖5是依照本發明的另一實施例說明圖1所示像素電路 200的電路示意圖。圖5所示實施範例可以參照圖2的相 關說明。 請參照圖5,像素電路2〇〇包括光感測器4〇〇、第一開 關Ml、第二開關M2、第三開關M3、第四開關M4與第 五，關M5。請參照圖4與圖5，光感測器4〇〇包含第一摻 雜，聰、第三掺雜區DR2、第三#雜區DR3與第四摻 雜區DR4。第-摻雜區聰與第三掺雜【肥為第一導 電^(例如N型摻雜}，第二掺雜區腿與第四摻雜區腿 為第二導電型(例如p型摻雜）。第二掺雜區脆配置於第 ，雜區DR1與第四摻雜gDR4L且第—摻雜區㈣ 與第二掺雜區DR2相鄰接而形成一個pN接面(相當於第一 光-極體I>D1)。帛-摻雜區DR1、第二掺雜&贈、第 三摻雜區DR3與第四摻雜區刪是沿基底_直方向疊 $該基底中。於本實施例中，是以p型基底實現第四摻 雜區DR4，如圖4所示。2012404504TW 37242twf.doc/n VI. Description of the Invention: [Technical Field] The present invention relates to an image sensor, and more particularly to a pixel circuit of an image sensor. [Prior Art] Image Sensor pixel circuit implemented by Photo Diode (PD), especially Complementary Metal-Oxide Semiconductor (CMOS) image sensor ( Referred to as CIS), it is gradually moving toward a trend of high photosensitive density. In order to recognize the color image, the phosphors of different colors are generally disposed on different photodiodes, and the nicks generated by the photodiodes receiving the specific wavelengths of light are processed and processed by the back-end circuit, but This approach appears to require considerable wafer area and cost. Alternatively, three photodiodes are vertically stacked on the wafer to form a multi-sided photodiode. By receiving multi-layer photodiodes of different depths to receive light sources of different wavelengths, the area requirement can be effectively reduced and the filter can be used to reduce the cost. However, multi-junction photodiodes are complicated in terms of component design, process architecture, and strobe At roads relative to single junction photodiodes. Moreover, the pixel circuit realized by the junction light dipole is susceptible to a large amount of noise during operation. SUMMARY OF THE INVENTION 201240450,. TW 37242twf.doc/n _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The pixel circuit 'including the first photodiode, the second photodiode, and the first terminal of the off, fifth switch, and off receives a first reference voltage. _ "One pole body. The first open first end is lightly connected to the second end of the first switch. The first switch is coupled to the third switch to the second end of the third switch. The second light first body is first a second end of the second switch. The first end of the second optical body is lightly connected to the second end of the photodiode. The third optical end is directly connected to the first end of the second optical diode The fourth opening is directly connected to the second end of the second. The first end of the fifth switch is coupled to the third light=end. The first and the fifth switch light sensing i sense: device: prime: road, including and a fifth switch. The photo sensor includes a first four-switch switch, wherein the second and the first sound zone are between the first and fourth doped regions, wherein the virtual region and the second region are disposed in the second and third regions The doped regions are adjacent to each other, and the third miscellaneous regions are adjacent to each other, and the second and the first end terminals receive the first reference; the pressed: doped regions are adjacent to each other. The first switch end is coupled to the first switch The first switch of the first switch and the third switch, and the second end of the second switch are connected to the fourth 201240450, W 3 7242twf. doc/n, the area. The second end of the third switch is lightly closed - End coupled to fourth Miscellaneous zone =. Fourth opening: electric = fine switch and the second end face of the fifth switch are connected to the second reference to make the above features and advantages of the present invention more obvious and easy to understand, and cooperate with the drawing The detailed description is as follows. 'Embodiment】 It is an embodiment of the present invention, which illustrates an image sensing system including an image sensor, an output amplifier (output amplifier). 1〇1, analog digital conversion to digital converter, ADC) 1〇2 and image processor (丨明明处理器) 103. Image sensor 100 includes a column driver (r〇wdriver) 110, pixel array (pixel array) U0 and a row driver (c〇lumn driver) 130. The column driver lio is connected to a plurality of address lines of the pixel array 12A, such as an address line Ri. The row driver 130 is connected to a plurality of readout lines of the pixel array 12A, such as readout lines. Ci. A pixel circuit is respectively disposed at the intersection of the address lines and the readout lines, for example, a pixel circuit 200 is disposed at the intersection of the address line Ri and the read line Ci. The timing of driving the column driver 110 to the address lines is matched. Line drive The actuator 130 can read the sensing voltage signal of the pixel circuit located on the driven address line via the readout lines, and then transmit the sensing result to the output amplifier 101. The output amplifier 1〇1 senses the readout by the row driver 130. The result is amplified and the amplified sensed result is passed to an analog to digital converter 201240450 W 37242twf.doc/n 102. The analog to digital converter 102 converts the analog sensed result into a digital value. The image processor receives and processes this Digital value. 2 is a schematic diagram showing an equivalent circuit of the pixel circuit 200 shown in FIG. 2 in accordance with an embodiment of the present invention. The pixel circuit 2 includes a first switch, a first switch M2, a third switch M3, a fourth switch M4, a fifth switch M5, a first photodiode PD1, a second photodiode PD2, and a third photodiode PD3. The above switches M1 to M5 can be realized by an N-channel metal oxide semiconductor (NMOS) transistor. The first end of the first switch M1 receives the first reference voltage. In this embodiment, the first reference voltage may be a reset voltage VRESET or other fixed voltage. The first switch M1 is controlled by the control signal towel to determine whether to direct the reset voltage VRESET to the first switch! The second end of ^^. The first end of the second switch M2 and the third switch M3 are coupled to the second end of the first switch M1. The first end of the first photodiode PD1 is coupled to the second end of the third switch M3. The first end of the second photodiode PD2 is coupled to the second end of the second switch M2. The second end of the second photodiode PD2 is directly connected to the second end of the first photodiode PD1. The first end of the third photodiode PD3 is directly connected to the first end of the second photodiode PD2. The first end of the fourth switch M4 is coupled to the second end of the third photodiode PD3. The first end of the fifth switch M5 is coupled to the second ends of the first photodiode PD1 and the second photodiode pD2. The fourth switch M4 and the second end of the fifth switch M5 are coupled to a voltage. In this embodiment, the second reference power==voltage GND, common voltage (common v〇itage) or other fixed voltage. 6 201240450 χ ji^^wij4TW 37242twf.doc/n In this embodiment, the level of the reset voltage VRESET is set higher than the ground voltage GND, so the first photodiode pD1 and the second photodiode PD2 are The first end of the second photodiode PD3 is a cathode, and the two ends of the first photodiode PD1, the second photodiode PD2, and the third photodiode PD3 are poles, as shown in FIG. In other embodiments, if the level of the reset voltage VRESET is set lower than the ground voltage gnd, the first h of the first photo-polar body PD1, the second photodiode, and the third photodiode PD3 is The anode, and the second ends of the first photodiode PD1, the second photodiode PD2, and the third photodiode PD3 are cathodes. The first switch M2, the third switch M3, the fourth switch M4 and the fifth switch M5 are respectively controlled by control signals, 〇c and φ(1. FIG. 3 is controlled according to the embodiment of the present invention _ 2 Please refer to FIG. 2 and FIG. 3. In the first-reset period, 'M1, the third switch M3 and the fifth switch Μ5 are turned on (tum 〇η), and the first switch M2 and the fourth switch Μ4 are turned off ( Therefore, the anode of the first photodiode FD1 is grounded, and the cathode of the first photodiode is reset to a level corresponding to the reset voltage VRESET. During the first integration period T2, the fifth The switch M5 is turned on, and the first switch M1, the second switch M2, the third switch M3, and the fourth switch M4 are worn. Therefore, in the first integration period T2, the anode of the first photodiode is grounded. - the cathode voltage level of the photodiode PD1 is depressurized at a rate corresponding to the amount of illumination. The third switch M3 is capable of separating the first photodiode from the first switch (4) at the first-integration That is to say, the charging path can be separated from the stored charge. Thus, the third switch milk can be 201240450 rw 37242twf.doc/n will be -M The switching noise generated during the M1 switching is effective to reduce the overall noise. During the first-read period T3, the third switching milk and the fifth switch M are turned on, and the first switch is switched to the second switch M2 and the first The fourth switch M4 is turned off. Therefore, the row driver 130 can directly or indirectly read the illumination integration result of the first photodiode PD1 through the two switches M3 during the first readout period T3 (ie, the cathode voltage of the first photodiode PD1). During the reading of the first photodiode PD1, the second switch M2 and the fourth switch are continuously turned off without interfering with the signal of the first photodiode PD1. In this embodiment, the pixel The circuit 200 further configures the transistor M6 as a source follower. The control terminal (eg, the gate) of the transistor M6 is coupled to the first ends of the second switch M3 and the third switch M3. The transistor M6 The first end (eg, the drain) is coupled to the third reference voltage. In the embodiment, the third reference voltage may be the power supply voltage VDD or other fixed reference voltage. During the first readout period T3, The transistor M6 can be based on the cathode voltage level of the first photodiode PD1. The second end (e.g., source) of the transistor M6 outputs a sense voltage. The switch M7 is turned on correspondingly during the first readout period T3, so that the sense voltage can be transferred to the row driver 130 via the sense line Ci. M6 can block the first photodiode PD1 from other pixel loads and wire loads in the pixel array 120, so that it can have good noise isolation effect. The transistor M6 can also provide sufficient thrust to 'react faithfully and quickly to the signal. Backend readout circuitry (eg, row driver 130) 8 201240450 37242twf.doc/n Please continue to refer to Figures 2 and 3. During the second reset period 4, the first switch is turned on by the second switch M2 and the fifth switch M5, and the third switch M3 and the fourth switch M4 are worn. Therefore, the anode of the second photodiode ρ 〇 2 is grounded, and the cathode of the second photodiode PD 2 can be reset to a level corresponding to the reset voltage VRESET. During the second integration period τ5, the fifth switch Μ5 is turned on, and the first switch M1, the second switch Μ2, the third switch MS, and the fourth switch Μ4 are turned off. Therefore, during the second integration period τ5, the anode of the second photodiode PD2 is grounded, and the cathode voltage level of the second photodiode pD2 is depressurized at a rate of the amount of illumination. Similar to the third switch M3, the second switch M2 can separate the second photodiode PD2 from the first switch during the second integration period τ5, and the second switch M2 can generate the first switch M1 when switching. The switching noise is effectively suppressed, so the overall noise can be reduced. During the second readout period T6, the second switch milk and the fifth switch milk are turned on, and the first switch m, the third switch M3, and the fourth switch M4 are cut off. The transistor M6 can output a sensing voltage from the source of the transistor 依据 in accordance with the cathode potential of the second photodiode PD2. Therefore, the line driver 130 can pass the illumination integration result of the read line α, the switch milk # = the second photodiode PD2 during the second readout period (6 (i.e., the sense voltage at the first stage). Between π ^ and T6 during the third reset period Τ7, the first switch 第二 the second fourth switch Μ4 is turned on, and the third switch Μ3 and the fifth switch are turned off. In the third integral, the fourth switch _ is the & = switch M1, the first switch M2, the third switch M3, and the fifth gate 5 are 201240450 TW 37242twf.doc/n cutoff. Therefore, during the third integration period T8, the anode of the third photodiode pD3 is grounded to the cathode voltage level of the (four) three-light diode PD3, which is depressurized at a rate at which the deer is exposed to the amount of illumination. The second switch M2 can separate the second photodiode PD3 from the first switch M in the first T8, and the switch M2 can effectively suppress the switching noise generated when the first switch M1 is switched, so The overall noise can be reduced. During the second readout period T9, the second open_M2 and the fourth switch (10) are turned "on" and the first switch (4), the third switch M3, and the fifth switch milk are cut off. The transistor M6 can output a sensing voltage from the source of the transistor M6 in accordance with the cathode voltage level of the third photodiode. Therefore, the row driver 13 can read the illumination integration result of the third photodiode PD3 (ie, the sensing voltage during the third readout period T9) through the readout line 〇 and the switch during the second·|jath period T9. . - The above three photodiodes Pm, pD2, pD3 can be set to receive a primary color, for example, red light, green light, and blue light, respectively. Operating the switches inside the pixel circuit 200 in accordance with the description of Fig. 3 can improve the interference of internal noise. The present invention does not limit the arrangement of the photodiodes pD1, pD2, and PD3. For example, the photodiodes pD1 and pD2 may be arranged side by side on the enamel substrate, or the photodiode pD1 may be arranged along the vertical direction of the substrate. PD2 and PD3 are stacked on the substrate. For example, FIG. 4 is a cross-sectional view showing the layout structure of the diodes PD1, PD2, and PD3 shown in FIG. 2 according to an embodiment of the present invention. In this embodiment, the photodiodes PDi, pD2, and pD3 shown in Fig. 2 are realized by the 201240450 4TW 37242twf.doc/n parasitic diode formed by the three junctions of the photosensors 4' (Triple_Juncti〇n). FIG. 5 is a circuit diagram showing the pixel circuit 200 of FIG. 1 in accordance with another embodiment of the present invention. The embodiment shown in Fig. 5 can be referred to the related description of Fig. 2. Referring to FIG. 5, the pixel circuit 2A includes a photo sensor 4A, a first switch M1, a second switch M2, a third switch M3, a fourth switch M4, and a fifth switch, M5. Referring to FIG. 4 and FIG. 5, the photo sensor 4A includes a first doped, Cong, third doped region DR2, a third #difference region DR3, and a fourth doped region DR4. The first doping region is the same as the third doping [fat is the first conductivity ^ (for example, N-type doping), and the second doped region leg and the fourth doped region leg are of the second conductivity type (for example, p-type doping) The second doped region is fragilely disposed at the first, the doped region DR1 and the fourth doped gDR4L, and the first doped region (4) is adjacent to the second doped region DR2 to form a pN junction (corresponding to the first light) - a polar body I > D1). The germanium-doped region DR1, the second doping & gift, the third doped region DR3 and the fourth doped region are stacked in the substrate along the substrate_straight direction. In the embodiment, the fourth doping region DR4 is implemented as a p-type substrate, as shown in FIG.
第-掺雜區DR3配置於第二摻雜區DR =之广其中第二推雜區DR2與第三捧 Ϊ 第二個™接面(相當於第二光二極體_，且 第二掺雜區DR3^四軸區刪 PN接面(相當於第三光：極體 $第; N型井實現第三掺㈣咖。 ^财疋以 37242twf.doc/n 201240450,4rw 第-開關Mi的第-端接收第—參考電 壓WESET)。第：開關M2與第三開關奶的第一端= ^第:開關M1的第二端。第二開關M2的第二端耗接至 第二#雜區DR3。第三開關M3的第二端輕接至第一捧雜 ^DIU。第四開關M4的第-端輕接至第四掺雜區腦。 第五開關M5的第-端輕接至第二掺雜區dr2。第四 第五開關M5的第二端搞接至第二參考電 地電壓GND)。 =㈣深度打上㈣導電㈣财㈣度而獲得多 所示°藉由不同波長之光源具有不同 /多層ΡΝ接面可以分別接收不同波長之光 摻雜DR1與第二掺雜之間的 接面來感峨色光B，以第二掺雜區DR2i第三掺雜 ^之1的PN接面來感測綠色光G，以第三捧雜區 w; ΐ :摻雜區D R4之間的P N接面來感測紅色光R。 如此就此有效降低面積需求且不需使用遽光片。 上曰1光感測器4〇〇的佈局方式不限於圖4所示。例如， 400 ㈣另—實施例說明圖5所示光感測器 H 4 V°剖面不意圖。圖6所示實施範例可以參照 於圖6路- Ϊ相，說明。不同於圖4所示實施例之處，在 二ρ π I:貫施範例是以Ν型基底實現第一摻雜區DR1， L L井實現第二掺雜區dr2,以N型掺雜區實現第三摻 * 3以P型重掺雜區實現第四摻雜區DR4，如圖6 所示。 12 j4TW 37242twf.doc/n 201240450 圖7是依照本發明的再一實施例說明圖5所示光感測 器400的佈局結構剖面示意圖。圖7所示實施範例可以參 照圖4與圖5的相關說明。不同於圖4所示實施例之處， 在於圖7所示實施範例是將光感測器4〇〇配置於N型基底 71〇中。請參照圖7，& N型基底71〇中形成p型井作為 第四摻雜區DR4。接下來，在第四摻雜區DR4中形成N 里摻雜區作為第二摻雜區DR3。然後在第三摻雜區 中形成P型摻雜區作為第二掺雜區DR2。最後，在第二掺 雜區DR2中形成N型重摻雜區作為第—摻雜區DR卜 =8是依照本發明的更—實施例說明圖$所示光感測 _4Γ佈局結構剖面示意圖。圖8所示實施範例可以參 圖5的相關說明。不同於圖4所示實施例之處， ίΓΓ fΓ實施範例是將光感測器侧配置於P型基底 第旅雜^照圖8’於？型基底810中形成井作為 下來，在第—摻雜區dri中形成p 雜區DR2^後在第二掺雜區dr2 〜品作為第三摻雜區DR3。最後，在第二摻 二型重摻雜區作為第四 路200 “:明實施例說明圖1所示像素電 圖5的相關說明了二=戶^實^例可以參照圖2與 所示實施範例中第斤不實施例之處，在於圖9 的第一導電型為P型摻雜而第第三捧肺廳所屬 區；DR4所屬的第二導 ^ _與第四摻雜 电玉马N型摻雜。另外，圖9 _第 13 201240450 fW 37242twf.doc/n 四開關M4與第五開關M5的第二端所耦接的第二參考電 壓是電源電壓VDD，而第一開關M1的第一端所接收的第 一參考電壓是低於電源電壓VDD的重置電壓VR£set (例 如接近接地電壓GND或等於接地電壓gnd)。 另外，上述圖2、圖5、圖9所示開關M1〜M5的操作 方式不限於圖3的相關說明。本領預知技術人員可以依循 本發明的教示，而按照實際設計需求來調整開關M1〜M5 的操作時序。例如，圖1 〇是依照本發明的另一實施例說明 圖2、圖5、圖9所示控制信號的時序示意圖。 請參照圖2與圖10,於第一重置期^ τ卜第一開 Ml、第二開關]VI3與第五開關M5為導通，而第二開 M2與第四開關M4為戴止。在第一開關M1截止後等— 段時間才把第三開關Μ 3截止。於第_積分期間τ 2 Ρ·Μ5為導通，而第一開關M1、第二開關⑽、第 關M3與第四開關Μ4為戴止。於第1出期間 段，第三開關⑷與第五開關Μ5轉通，而第一開關. 第二開關M2與第四開關Μ4為戴止。此時，行驅動器 可以透過讀出線Ci、關Μ7與電晶體你 極體i>m的光照積分結果。於第-讀出期間T3的中段了 第-開關Μ卜第三開關M3與第五開關奶為導通， 二開關M2與第四開關Μ4為戴止。此日夺，第—光 PD1的光難分結果會被重置為重置麵vreset。 -讀出期間T3的後段，第三開關M3與第五開關奶為導 通’而第-開關Μ卜第二開關M2與第四開關⑽為戴止。 201240450 …4TW 37242twf.d〇c/n 二:=動器】30可以透過讀出、線α、開關m與電晶 f _第—光二極體PD1的重置結果。上述在志 '的前段與後段對第—光二極體PD1進行兩‘ 〇)=二ί為相關性雙取樣(C〇rrelated Double Sa— )。猎由將兩次讀取結果進行相減，可以有效地消除、」 移電壓。因此，所述相關性雙取樣能夠降低固定形式雜ζ (FPN)，所以整聽減降低，尤其非常適合應用 领 域的電路架構。 與剷述第一光二極體PD1的操作相類似，於第二重置 期間T4’第一開關M卜第二開關M2、第四開關^與第 五開關M5為導通，而第三開關M3為截止。於第二積分 期間T5 ’第五開關M5為導通，而第—開關μ卜第二開 關M2、第三開關Μ3與第四開關Μ4為戴止。於第二^ 期間Τ6的前段，第二開關Μ2與第五開關Μ5為導通喝而 第一開關Μ卜第三開關M3與第四開關Μ4為截止。於第 二讀出期間Τ6的中段，第一開關Μ卜第二開關Μ2與第 五開關Μ5為導通，而第三開關M3與第四開關Μ4為戴 止。於第二讀出期間Τ6的後段，第二開關M2與第五開關 Μ5為導通，而第一開關mi、第三開關Μ3與第四開關 Μ4為截止。行驅動器π〇可以在前述第二讀出期間了6的 前段與後段透過讀出線Ci、開關Μ7與電晶體河6對第二 光二極體PD2進行相關性雙取樣(CDS)操作。 於第三重置期間T7，第一開關Ml、第二開關M2與 第四開關M4為導通，而第三開關M3與第五開關M5為 15 201240450^ 37242twf.doc/n 截止。於第二積分期間T8，第四開關M4為導通，而第一 ，_、第二開關M2、第三開關M3與第五開關W為 截止。於第三讀出期間T9的前段，第二開關奶與第四開 關M4為導通，❿第一開關m、第三開關以3與第五開關 M5為截止。於第三讀出期間T9的中段，第—開關⑷、 第二開關M2與第四開關M4為導通，而第三開關m3與 第五開關M5為截止。於第三讀出期間T9的後段，第二開 關M2與第四開關副為導通，而第一開關m、第三開關 M3與第五開關M5為截止。行驅動器13〇可以在前述第三 讀出期間T9的前段與後段透過讀出線α、開關M7與電 晶體M6對第三光二極體PD3進行相關性雙取樣(cd_ 作。 紅亡所述，本發明諸實施例提出新穎之像素電路2〇〇 能使用三接面光感測器400，同時搭配圖3或圖1〇之時序 控制訊號’能讀出三個對於光波㈣應程度不同之光二極 體Pm、PD2與PD3。基本上此三個光二極體pm、pD2 與PD3所接收之光訊號可以設計來接收三原色，也就是分 別接收紅色光、綠色光以及藍色光，如此可無需濾光片即 有彩色影像訊號。爲了能有效利用面積來增加像^密度， 在像素電路200可以使用七顆n型電晶體。若以相關ς雙 取樣(CDS)的時序訊號控制方式，像素電路能夠在固 定形式雜訊(FPN)以及切換雜訊有相當不錯的效果，這些特 性將使得此電路極適合應用於生醫領域。 一 雖然本發明已以實施例揭露如上，然其並非用以限定 本發明，任何所屬技術領域中具有通常知識者，在不脫離 16 201240450 rji^.^TW 37242twf.d〇c/n 本發明之精神和範圍内，當可作些許之更 發明之保護範圍當視後附之申請專利範圍所界定者為^本 【圖式簡單說明】 二;S本發明的實施例說明-種影像感測系_ 等效本發明的實施例說明圖1所示像素電路的 時序依照本發明的實施例說明圖2所示控制信號的 圖4是依照本發明的實施例說明 佈局結構剖面示意圖。 彳丁先一極體的 路的本發明的另一實施例說明圖1所示像素電 圖6是依照本發明的另一實施例說明 盗的佈局結構剖面示意圖。 彳不先感測 料ΪI是依照本發明的再一實施例說明圖5所示光成測 盗的佈局結構剖面示意圖。 九關 %^圖8是依照本發明的更一實施例說明圖5所示# 、Η| $的佈局結構剖面示意圖。 斤不先感測 ⑬的以=本發明的更-實施例說明圖1所示像素電 圖10是依照本發明的另一實施例說明 9所示控制信號的時序示意圖。 圖5圖 17 •tTW 37242twf.doc/n 【主要元件符號說明】 100 :影像感測器 101 :輸出放大器 102 :類比數位轉換器 103 :影像處理器 110 :列驅動器 120 :像素陣列 130 :行驅動器 200 :像素電路 400 :光感測器 710、810 :基底 、<Db、Φο、Φίΐ、OR :控制信號 B :藍色光 Ci :讀出線 DR1〜DR4 :摻雜區 G :綠色光 GND :接地電壓 Ml〜M5、M7 :開關 M6 :電晶體 PD1〜PD3 :光二極體 R :紅色光 Ri :定址線 VDD :電源電壓 VRESET :重置電壓 18The first doping region DR3 is disposed in the second doping region DR=the second doping region DR2 and the third doping region the second TM junction (corresponding to the second photodiode _, and the second doping Area DR3^ four-axis area delete PN junction (equivalent to the third light: polar body $ first; N-type well to achieve the third mixed (four) coffee. ^财疋 to 37242twf.doc/n 201240450, 4rw first-switch Mi's - terminal receives the first reference voltage WESET). The first end of the switch M2 and the third switch milk = ^ the second end of the switch M1. The second end of the second switch M2 is connected to the second # miscellaneous area DR3. The second end of the third switch M3 is lightly connected to the first holding part DIDU. The first end of the fourth switch M4 is lightly connected to the brain of the fourth doping area. The first end of the fifth switch M5 is lightly connected to the first The second doping region dr2. The second terminal of the fourth fifth switch M5 is connected to the second reference ground voltage GND). = (4) The depth is marked with (4) conductive (four) wealth (four) degrees and more is obtained. ° The light source with different wavelengths has different / multi-layer splicing faces, which can respectively receive the junction between the light-doped DR1 and the second doping of different wavelengths. Sensing color B, sensing the green light G with the PN junction of the third doping region DR2i, to the third holding region w; ΐ: PN connection between the doping regions D R4 Face to sense red light R. This effectively reduces the area requirement and eliminates the need for a calender. The layout of the upper 曰1 photo sensor 4 不 is not limited to that shown in FIG. 4 . For example, 400 (d) another embodiment illustrates the H 4 V° profile of the photosensor shown in FIG. The embodiment shown in Fig. 6 can be explained with reference to Fig. 6 - Ϊ phase. Different from the embodiment shown in FIG. 4, in the case of two ρ π I: the first doping region DR1 is realized by a Ν-type substrate, and the second doping region dr2 is realized by the LL well, and the N-doping region is realized. The third doping 3 implements the fourth doping region DR4 in a P-type heavily doped region, as shown in FIG. 12 j4TW 37242twf.doc/n 201240450 FIG. 7 is a cross-sectional view showing the layout of the photosensor 400 of FIG. 5 according to still another embodiment of the present invention. The embodiment shown in Fig. 7 can be referred to the related description of Figs. 4 and 5. Different from the embodiment shown in Fig. 4, in the embodiment shown in Fig. 7, the photo sensor 4 is disposed in the N-type substrate 71A. Referring to Fig. 7, a p-type well is formed as a fourth doping region DR4 in the & N-type substrate 71. Next, an N-doped region is formed as the second doping region DR3 in the fourth doping region DR4. A P-type doped region is then formed in the third doped region as the second doped region DR2. Finally, forming an N-type heavily doped region in the second doped region DR2 as the first doped region DRb=8 is a schematic cross-sectional view of the light sensing_4Γ layout structure shown in FIG. . The embodiment shown in Fig. 8 can be referred to the related description of Fig. 5. Different from the embodiment shown in FIG. 4, the implementation example is to arrange the photosensor side on the P-type substrate. A well is formed in the type substrate 810, and a p-doped region DR2 is formed in the first doped region dri and then a third doped region DR3 is used as the third doped region DR3. Finally, in the second doped type II heavily doped region as the fourth path 200": the description of the pixel electrogram 5 shown in FIG. 1 is illustrated in the embodiment, and the second embodiment can be implemented with reference to FIG. 2 and the illustrated embodiment. In the example, the first embodiment of the first embodiment is that the first conductivity type of FIG. 9 is P-type doping and the third holding area of the lung chamber; the second guide _ and the fourth doped electric jama N to which DR4 belongs In addition, the second reference voltage coupled to the second terminal of the fourth switch M4 and the fifth switch M5 is the power supply voltage VDD, and the first switch M1 is the first switch M1. The first reference voltage received at one end is a reset voltage VR£set lower than the power supply voltage VDD (eg, close to the ground voltage GND or equal to the ground voltage gnd). In addition, the switch M1 shown in FIG. 2, FIG. 5, and FIG. The operation mode of the M5 is not limited to the related description of Fig. 3. The skilled person skilled in the art can adjust the operation timing of the switches M1 to M5 according to the actual design requirements in accordance with the teachings of the present invention. For example, Fig. 1 is another according to the present invention. An embodiment illustrates a timing diagram of the control signals shown in FIGS. 2, 5, and 9. 2 and FIG. 10, in the first reset period ^τ, the first open M1, the second switch] VI3 and the fifth switch M5 are turned on, and the second open M2 and the fourth switch M4 are worn. After the switch M1 is turned off, the third switch Μ 3 is turned off during the period of time. During the _integration period τ 2 Ρ·Μ5 is turned on, and the first switch M1, the second switch (10), the third switch M3 and the fourth switch Μ4 In the first output period, the third switch (4) and the fifth switch Μ5 are turned on, and the first switch. The second switch M2 and the fourth switch Μ4 are worn. At this time, the row driver can be read through The light integration result of the line Ci, the relation 7 and the transistor your polar body i>m. In the middle of the first-reading period T3, the third switch M3 and the fifth switch milk are turned on, and the second switch M2 is The fourth switch Μ4 is worn. On this day, the light diffracted result of the first light PD1 is reset to the reset surface vreset. - After the read period T3, the third switch M3 and the fifth switch milk are turned on. And the second switch M2 and the fourth switch (10) are worn. 201240450 ... 4TW 37242twf.d〇c/n 2: = actuator 30 can be read through, line α, The reset result of the m and the electric crystal f _ the first photodiode PD1. The above-mentioned and the latter part of the above-mentioned 'the second photodiode PD1 are two ' 〇)= two ί are correlation double sampling (C〇rrelated Double Sa—). Hunting effectively subtracts and “shifts the voltage” by subtracting the two readings. Therefore, the correlation double sampling can reduce the fixed form noise (FPN), so the overall hearing loss is reduced, and it is especially suitable for the circuit architecture in the application field. Similar to the operation of the first photodiode PD1, during the second reset period T4', the first switch M, the second switch M2, the fourth switch ^ and the fifth switch M5 are turned on, and the third switch M3 is cutoff. During the second integration period T5', the fifth switch M5 is turned on, and the first switch, the second switch M2, the third switch Μ3, and the fourth switch Μ4 are worn. In the first stage of the second period Τ6, the second switch Μ2 and the fifth switch Μ5 are turned on and the first switch 第三the third switch M3 and the fourth switch Μ4 are turned off. In the middle of the second readout period Τ6, the first switch 第二 the second switch Μ2 and the fifth switch Μ5 are turned on, and the third switch M3 and the fourth switch Μ4 are turned on. In the latter stage of the second readout period Τ6, the second switch M2 and the fifth switch Μ5 are turned on, and the first switch mi, the third switch Μ3, and the fourth switch Μ4 are turned off. The row driver π 〇 can perform a correlated double sampling (CDS) operation on the second photodiode PD2 through the readout line Ci, the switch Μ7 and the transistor river 6 in the front and rear stages of the second readout period 6. During the third reset period T7, the first switch M1, the second switch M2, and the fourth switch M4 are turned on, and the third switch M3 and the fifth switch M5 are turned off by 15 201240450^37242twf.doc/n. During the second integration period T8, the fourth switch M4 is turned on, and the first, _, second switch M2, third switch M3, and fifth switch W are turned off. In the preceding stage of the third readout period T9, the second switch milk and the fourth switch M4 are turned on, and the first switch m, the third switch 3 and the fifth switch M5 are turned off. In the middle of the third readout period T9, the first switch (4), the second switch M2, and the fourth switch M4 are turned on, and the third switch m3 and the fifth switch M5 are turned off. In the latter stage of the third readout period T9, the second switch M2 and the fourth switch pair are turned on, and the first switch m, the third switch M3, and the fifth switch M5 are turned off. The row driver 13A can perform correlated double sampling (cd_) on the third photodiode PD3 through the readout line α, the switch M7, and the transistor M6 in the front and rear stages of the third readout period T9. The embodiments of the present invention provide that the novel pixel circuit 2 can use the three-junction photo sensor 400, and the timing control signal of FIG. 3 or FIG. 1 can read three different degrees of light waves (four). The photodiodes Pm, PD2 and PD3. Basically, the optical signals received by the three photodiodes pm, pD2 and PD3 can be designed to receive the three primary colors, that is, receive red light, green light and blue light respectively, so that no filtering is required. The light film has a color image signal. In order to effectively use the area to increase the image density, seven n-type transistors can be used in the pixel circuit 200. If the correlated ς double sampling (CDS) timing signal control mode is used, the pixel circuit can It has quite good effects in fixed form noise (FPN) and switching noise. These characteristics will make this circuit very suitable for application in the field of biomedicine. Although the present invention has been disclosed above by way of example, it is not In order to limit the scope of the invention, any one of ordinary skill in the art, without departing from the spirit and scope of the invention, may provide some protection scope of the invention. The definition of the patent application scope is as follows: [Simplified description of the drawing] 2; S embodiment of the invention illustrates an image sensing system _ equivalent to the embodiment of the invention illustrates the pixel circuit shown in FIG. FIG. 4 is a cross-sectional view showing a layout structure according to an embodiment of the present invention. FIG. 1 is another embodiment of the present invention. The illustrated pixel electrogram 6 is a cross-sectional view showing a layout structure of a pirate according to another embodiment of the present invention. The first sensing material ΪI is a layout of the optical thief shown in FIG. 5 according to still another embodiment of the present invention. Schematic diagram of the structure. Fig. 8 is a schematic cross-sectional view showing the layout structure of #, Η | $ shown in Fig. 5 according to a further embodiment of the present invention. An example illustrates the pixel shown in Figure 1. Figure 10 is a timing diagram showing the control signal shown in Figure 9 in accordance with another embodiment of the present invention. Figure 5 Figure 17 • tTW 37242twf.doc/n [Description of Main Component Symbols] 100: Image Sensor 101: Output Amplifier 102: Analog to digital converter 103: image processor 110: column driver 120: pixel array 130: row driver 200: pixel circuit 400: photo sensor 710, 810: substrate, <Db, Φο, Φίΐ, OR: control signal B Blue light Ci: readout lines DR1 to DR4: doped region G: green light GND: ground voltage M1 to M5, M7: switch M6: transistors PD1 to PD3: photodiode R: red light Ri: address line VDD : Power supply voltage VRESET : Reset voltage 18