TW201239846A - Gate driving circuit - Google Patents

Abstract

Disclosed herein is a gate driving circuit including a first clock generator to output n (n being a natural number equal to or greater than 2) output control clock pulses having different phases; a second clock generator to create m*n (m being a natural number) output clock pulses having different phases and partially overlapped with one another in high periods thereof, to arrange the m*n output clock pulses in sequence of phase, to bind the m*n output clock pulses arranged in sequence of phase in units of n to generate m groups, each of which has n output clock pulses, and to output the m*n output clock pulses so that a rising edge of an output clock pulse having a k-th sequence of phase included in each group is located in a high period of an output control clock pulse having a k-th sequence of phase among the n output control clock pulses; and a shift register to receive the n output control clock pulses from the first clock generator and the m*n output clock pulses from the second clock generator and to sequentially output a plurality of scan pulses.

Description

201239846 VI. Description of the invention: [Technical field to which the invention pertains] "This is a power-generating circuit, and particularly relates to a gate drive circuit that stops the charge from the set node to stabilize the output from the stage. The shift register outputs a plurality of scan pulse waves to sequentially drive a gate line of a display device such as a liquid crystal display device. To this end, the shift register includes a plurality of switching devices. The oxide semiconductor transistor can be used. As such a switching device, Fig. 1 is a graph showing the relationship between the gate voltage and the gate current of a conventional oxide semiconductor transistor based on temperature. For the use of the _-type oxide semiconductor in the shift register H In the case of a transistor, its critical electric quantity (4) has a positive value < 'However, as the temperature increases, the critical electric current of the oxide semiconductor transistor is the first (4). In the shift temporary storage (10), the input type is closed. == Body = The body may not be normally closed at high temperatures, thereby producing a cap, when the wheel is semi-conductive L2 == at the time: 'When the critical voltage state of the oxide semiconductor transistor is Ip : three??;== /0# It can be seen that although the threshold voltage vth of the oxide semiconductor transistor is -3, the reduced voltage % of the derivative semiconductor transistor is not _, _ _ _ ^; plus this =: set point SUMMARY OF THE INVENTION Accordingly, the present invention is directed to providing a _chain network +; 5: ^ _ ^ ^ ^ 右 淋 ϋ ϋ ϋ _ _ _ _ _ _ _ _ _ _ _ 基本上 基本上 基本上 基本上 基本上 基本上 基本上 基本上 基本上 基本上 基本上 基本上 基本上 基本上 基本上 基本上 基本上_ s or multiple problems caused. 201239846 The gate is a kind of gate drive circuit 'where the pull-up pulse wave that is responsible for the rotation has a non-waveform, thus preventing the dump node from being electrically _= top-mounted button supply == :::rs_ Please use _== X to obtain these goals and their pour point records. For details, as described here in detail, the gate drive circuit includes: a first clock generator to output η ( η = or a natural number greater than 2) an output with a different plurality of phases controls the clock pulse to create m*n (m is a natural number) rrw skin with an output of a plurality of phases The output clock pulses are partially partial to each other during their plurality of high periods, = facilitating the arrangement of the m*n inputs in a phase sequence a pulse wave, such that η is combined with the m*n output clock pulses arranged in a phase sequence to generate m groups of each of the claw groups having n such output clocks a pulse wave, and outputting the centroid output pulse wave so that a rising edge of the - (four) pulse wave having the "kth phase sequence" included in each group is located at the n output controls An output having a kth phase sequence in the clock pulse controls the -high period of the pulse wave; and - shifting the register to receive from the first - clock generation (4) the η output controls a clock pulse and the output pulse pulses from the second clock generator, and sequentially output a plurality of scan pulses. The n outputs control the clock pulse and the mJ|Cn Each of the output clock pulses includes a plurality of periodically generated pulses, and an output included in the group having -kth phase sequence and belonging to a Jth (J is equal to or less than (4) natural number) group. The rising edge of a pulse of the clock pulse is located in the high cycle with the -kth her order-pulse-pulse. The mth η output clock pulse further includes a dummy pulse, and the dummy pulse has the same output timing as one of the phase pulses before the phase of the pulse of the first round. The voltage of each of the n-cycle control pulse pulses at a low period is lower than or equal to the voltage of each of the m*n output pulse waves at a low period. Each of the 11 rounds of the pulse waves of the Xuan et al. m does not overlap with at least one of the n output control clock pulses 5 201239846. Version m!! Move (four) - wheel output terminal output - scan pulse wave, the n output controls 睹m*偭^ from n output control clock line transmission, the heart output pulse wave system is ^ According to the sending - the p (p is a natural number) stage includes: a first switch installed i, = when the device is turned on - will - (p_q) (q is less than the natural number of ρ) stage - output ^ send - from The start pulse wave - the start transfer line is interconnected with the - set node; the second switch device is turned on or off according to any of the n output control clock pulses, and the + 3 set - switch When the device is turned on, the set node is interconnected with the first-line of the transfer-first discharge voltage; and the pull-up switch device is based on the voltage applied to the set node: or off 'and when the pull-up When the switching device is turned on, interconnecting any one of the output clock lines with the output terminal of the third segment, the high period of the output clock pulse is not the same as that provided to the second switching device The output controls the pulse-wave-high period overlap, and the η outputs, the control, and each of the pulse waves are at the low period thereof. The voltage is lower than the scale of the _discharge electric=the _high period of the output pulse wave supplied to the (p_q)th stage and is supplied to the ρth stage, the pulsation of the pulse wave is high The jobs partially overlap, and the rising edge of the output pulse provided to the pull-up switching device is mixed in one of the high periods of the output control clock pulse supplied to the first device. Where q is 1 or 2. The P phase advancement step includes: - a third switching device that is turned on or off according to an output clock pulse from any one of the output clock lines, and when the third switching device is turned on, a charging voltage line transmitting a charging voltage is interconnected with a reset node; a fourth switching device that is turned on or off according to a voltage applied to the setting node, and when the fourth switching device is turned on, the weight is The node is interconnected with a second discharge voltage line that transmits a second discharge voltage; and a pull-down switching device that turns on or off according to a voltage applied to the reset node, and when the pull-down switch device is turned on, The turn-out terminal of the P phase is interconnected with a second discharge voltage line that transmits a third discharge voltage, and both the pull-up switch device and the third switch device are provided with the same output clock pulse. The P phase further includes at least one selected from the following: a fifth switching device that turns on or off according to a scan pulse from a (p+r) (r is a natural number) phase. Off = when 'the set node and the first discharge voltage line ί ί ; ; ί : : Γ ^ ^ from the number of if ' and an eighth switch device 'based on the self - ((4) (S = =:==OFF, and when the eighth switching device is turned on, each of the m*n input (four) pulse waves is higher or equal to the voltage at one of its high periods, and the n output controls are Each of the clock pulses of the clock pulse is included in the voltage of the high-cycle period, and the third-on-position is turned on or off according to the voltage from the output pulse ϊ ϊ ϊ ϊ , , When the fourth switch is mounted to open the common node and the second discharge voltage line of the second discharge voltage, the five-switch device is turned on or off according to the voltage applied to the common point, and When the fifth switching device is turned on, the charging voltage line is interconnected with a reset node; Turning on or off to the voltage of the set node, and 'interconnecting the reset node with the second discharge voltage line when the sixth=device is turned on; and pulling the delta device 'at a time to apply it to the reset The node is lightly turned on or off, and when the pull-down switch device is turned on, 'the output terminal of the third stage and the first first stage of transmitting a third discharge further comprise: a third switching device, according to Turning on or off from a scan pulse of a (p_r) phase and interconnecting the set node with a charge voltage line of 2 to a charge voltage when the third switch device is turned on; a fourth switch device Is turned on or off according to a voltage applied to the setting node, and when the fourth switching device is turned on, interconnecting the reset node with a second discharging voltage line transmitting a second discharging voltage; Pulling a switching device that is turned on or off according to a voltage applied to the reset node, and when the pull-down switching device is turned on, the output terminal of the Pth stage and a third discharging voltage are transmitted a discharge voltage line interconnection; and a capacitor connected between the output clock line 201239846 connected to the pull-up switching device and the reset node. The third stage further includes: a third switching device, Turning on or off from a scan pulse of a (p_s) phase, and interconnecting the set node with a charging voltage line transmitting a charging voltage when the third switching device is turned on; a fourth switching device, It is turned on or off according to an output clock pulse from any one of the output clock lines, and when the fourth switching device is turned on, a charging voltage line transmitting a charging voltage is interconnected with a reset node a fifth switching device that is turned on or off according to a voltage applied to the set node, and when the fifth switching device is turned on, the reset node and a second discharge voltage line that transmits a second discharge voltage Interconnecting; and a pull-down switching device that turns on or off according to a voltage applied to the reset node, and outputs the p-stage when the pull-down switch is turned on End and communicate - the third discharge voltage - voltage line interconnecting the third discharge, the difficulty facing the open fourth pull-up switching means are provided with the same pulse wave output. The P-stage further includes: - a third switching device that is turned on or off according to the voltage applied to the terminal of the ρ phase, and when the third switching device is turned on, a reset node Interconnecting with the second discharge voltage line of the second discharge voltage; the fourth switching device 'turns on or off according to any one of the output pulse pulses from the (four) pulse line and prepares the first When the device _P4 is turned on, the charging voltage of the __ charging voltage will be transmitted.

And when - the second release

When the voltage applied to the reset node is turned on, the output terminal of the P phase is

201239846 One stage advancement step includes: a third switching device, which is connected to the charging electric field and the reset node according to the charging voltage of the self-charging voltage line; the fourth opening ^, from the output clock When any one of the lines - the output pulse pulse is turned on or off and the second off device is turned on, the reset node is connected with the second - the first line of the second discharge voltage. a device that is turned on according to a voltage applied to the set node and, when the fifth job is placed, the reset node and the second discharge electrical connection and a pull-down switch device according to the application to the The power of the reset node is turned on: When the three devices are turned on, 'the output terminal of the p-th phase and the plurality of high periods for transmitting the n-th output control clock pulses are not mutually exclusive. At least two of the first discharge voltage to the third discharge voltage are the same. - a number of stages of the package 'sequentially output a plurality of axis waves = Γ ίί ΐ 2 end output a scan pulse wave 'these η output control clock pulse output ^ ^ system ϊ pulse line transmission, the m * n The output_pulse waves are all transmitted by the m*n^ output clock line, and the -P (p is a natural number) stage includes: The solid time output will control = turn on or off any of the pulse waves and When an output terminal of the first open pq) (q is less than the natural number of P) stage or the 'starting pulse wave-starting transmission line is connected to the setting node; the pull-up is applied to the setting The voltage of the node is turned on. The device root:;r is set to::r is closed, and when the pulse wave of 4 or 3 is turned on or off, the voltage of the node is disconnected from the node. _ Interconnect, and - pull down the ugly, the root lion is added to the reset of the lock-off center -w Γ electric voltage 'second discharge voltage line interconnection, the pull-up (four) ^ set are provided The same output clock pulse, the n output rugged two discharge electric /, ° Xuan (pq) 匕攸 the output of the pulse wave of a high week 201239846 period and provided to the P stage The high-maintenance of the output pulse wave partially overlaps, with the rising edge of the output pulse of the device being located in a high period of the output control clock pulse of the device providing the first device. Ί The shift register comprises a plurality of stages, and a scan pulse is outputted by one of the output terminals in sequence, and the n output control is controlled by the peak output, and the output pulse is detected. Both are transmitted by an output clock line, and a P (P is a natural number) stage includes a ··- the first switch assembly armor is turned on according to the η outputs to control any of the clock pulses, = seek The initial transmission line of the initial pulse wave and the - setting node interconnection are started according to the dragon or the phase, and # the pull-up device is arbitrarily connected to the pulse line and the phase ρ The output terminal is interconnected; a first, and any one-to-one (four) pulse wave from the output line is turned on and the second device is turned on. The reset is reset according to the Xiaguan == set to be applied to the set node. Node and transmission - the second discharge voltage -S is turned on * and the pull-down operation is 'when the switching device is turned on according to the voltage applied to the reset node', the output terminal of the p-stage is switched Three discharge voltage lines are interconnected, and the pull-up switch device and the first sakisaki The output controls a high period overlap of the pulse wave, 嗲箄=1= the comet 'provides to the stage (Μ) stage of the output clock pulse stack p phase _ the output clock pulse A high period is partially concentrated to the _ rising edge of the input (four) pulse wave of the first pull-off device located in the high period of the pulse wave of the output control provided to the first switching device. Age * H output A known pulse wave, the output control clock pulse output control pulse ^ ^ ^ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The device, the root (10) and other n rounds of the control pulse pulse of any one of the opening pulse 201239846 when the device is turned on, the - (pq) (q is less than ? natural number) stage of the output terminal transmission An initial transmission line of the pulse wave is interconnected with a set node; a pull-up switching device is turned on or off according to a voltage applied to the set node, and when the pull-up is mounted, the output pulse line is arbitrary - interconnecting with the output terminal of the p-stage; the three-switch device 'which is based on the charging voltage of the self-charging electric K In order to interconnect the one with a reset node; a fourth switching device that is turned on or off according to a voltage applied to the set point, and when the fourth switch is turned on, a second discharge voltage line interconnection of the two discharge voltages; and - the pull-down switching device eight is turned on or off according to a voltage applied to the "set node, and when the pull-down is turned on," the output terminal of the p-stage is A third discharge switching device transmitting a third discharge voltage and the third switching device are both provided with the same output (four) pulse wave - the high chat is not supplied to the first switch device The voltage of each pulse of the pulse wave is controlled to be lower than or equal to the second discharge voltage and the third discharge voltage, (4) two t (P_q) The stage_transmission (four) pulse wave is partially overlapped with the -high period supplied to the P phase = 3 out of the pulse wave, and is provided to the upper pull pulse wave edge provided to the first - When the output of the switching device is controlled - the shift register 11 includes a plurality of stages to sequentially output a plurality of scan pulse waves, each touch=segment f3-output terminal output-scanning pulse wave, and the n-th output control clock pulse wave=n when the switch device is turned on, One (nw Honda must be ^, when the ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Start: off, and when the line is arbitrarily one output pulse pulse and the pressure line is connected with a common node, a charging voltage is transmitted. A charging current 201239846 The second discharging voltage - the second discharging voltage line are mutually a fifth switching device that is turned on or off according to a voltage applied to the common node, and interconnects the charging voltage line with the reset node when the fifth switching device is turned on; - a sixth switching device Opening or closing according to a voltage applied to the set node, and interconnecting the reset node with the second discharge voltage line when the sixth switching device is turned on; and - a pull-down switching device that is applied according to The voltage of the reset node is turned on or off 'and When the pull-down switch device is turned on, the output terminal of the p-stage is interconnected with the third-discharge voltage line of the third discharge voltage, and the output-clock pulse-high period is not provided to the first- The output of the switching device controls a high period overlap of the pulse wave of the n-th output control clock pulse each of which is lower than the first discharge voltage and the second discharge The voltage pull-up switch device and the third switch device are both provided with the same output clock pulse wave, and the output clock pulse wave supplied to the (p_q)th stage is provided to the first P The phase-out pulse of the stage is partially overlapped, and a rising edge of the output clock pulse supplied to the pull-up switching device is located at the output control provided to the first switching device The wave is in a high cycle. The foregoing summary, as well as the following detailed description of the invention, [Embodiment] & Referring now to the present invention, a preferred embodiment is made with reference to the formula. Wherever possible, the same reference numerals will be used to refer to the Fig. 3 is a block diagram showing a gate driving circuit in accordance with an embodiment of the present invention. The third gate does not include a gate drive circuit including a first clock generation _cGi, a second clock generator CG2, and a shift register sr. The first-clock generator CG1 outputs n (n is a natural number equal to or greater than 2) output control pulse waves i_CLK having different phases, and the n-wall control pulse wave system is output by n Control clock transmission. The second clock generator CG2 outputs _ output clock pulses having different phases. Specifically, the second clock generator CG2 generates an output clock with different phases (m is a natural number), and partially overlaps each other at a high level thereof, and arranges the m*n in a phase sequence. The clock pulse wave is output and combined with the m*n output clock pulses arranged in phase sequence 12 201239846 in units of n to generate m groups. In this case, each group has n second clock generators CG2 outputting 6 output clock pulses to make the pulse pulse of the kth phase sequence having -, . The rising edge is located in the Ϊ transmission: 输出: The output of the pulse-pulse wave with the kth phase sequence controls the ί period η of the clock pulse. The m*n output clock pulses are transmitted by _ one input (four) pulse line. 2 equal η output control clock pulses and each of the m*n output clocks are included = number = complementarily generated pulses. A rising edge of the pulse of the output pulse wave included in the group having the kth phase sequence taking the natural number belonging to the right or right is located in the high period of the pulse having the kth phase sequence. The first round (four) pulse wave advance step includes no _, and the virtual thief has the same output timing as the initial pulse of the phase before the phase of the first output clock pulse. The η outputs control the voltage of each of the pulse waves in each of its low cycle voltages below or equal to the voltage of each of the pulse waves at the low cycle of the m*n outputs. Each of the m*n input (four) pulse waves does not overlap at least one of the n output control clock pulses. The shift register receives the n output control clock two waves from the first clock generator CG1 and the m*n output clock pulses from the second clock generation II CG2, In order to sequentially output h (h rides on or greater than 2 natural numbers) scan pulses. The output control clock pulse output from the first clock generator CG1 and the output clock pulse wave output from the second clock generator CG2 have the following forms. Fig. 4 is a timing chart showing the output control clock pulse wave and the output clock pulse wave in the first embodiment according to the present invention. As shown in FIG. 4, the output control clock pulse includes four outputs with different phases to control the clock pulse to i_CLK4' and the (4) secret wave includes four output clock pulses CLK1 having different phases. To CLK4. That is, Fig. 4 shows the waveforms of the control clock pulse and the output clock pulse when n = 4, m = 1, and > As shown in Fig. 4, the high periods of the first to fourth output clock pulses CLK1 to CLK4 overlap each other by 1/3 second. Each of the first to fourth output clock pulses CLK1 to CLK4 includes a plurality of periodically generated pulses. Each of the first to fourth output control clock pulses i-CLK1 to i-CLK4 includes a plurality of periodically or non-periodically generated pulses. I-CLKl to i-CLK4 cut off the pulse of the 玍. The high periods of the first to fourth output control clock pulses may overlap each other or may not overlap each other. In Fig. 4, the first to fourth output control clock pulses i_CLK1, the first to fourth output control clock pulses i-CLK1 control the clock transmission. The high periods to i-CLK4 do not overlap each other. Up to i-CLK4, by the first to fourth outputs, the first to fourth outputs control the clock of the pulse wave to the rainbow to be lower than the scale to the first to the thin wheel (four) The pulse pulse clki to clk4^ is transmitted by the first to fourth output clock lines at the first to fourth output pulses of the low cycle _ electric 1 . As shown in Fig. 4, the rising edge of the first output clock pulse CLK1 is located in the high period of the first output control clock pulse i_CLK1. The rising edge of the second output clock pulse Cm is located in the high period of the second output control clock pulse i_CLK2. The rising edge of the pulse wave CLK3 at the third output is located in a high period in which the third output control clock pulse is inevitable. The fourth output clock pulse CLK4 rising edge is located in the high period of the fourth output control clock pulse i-CLK4. The high period of the first round-off pulse wave CLK1 overlaps with the first to third output control clock pulses i-CLK1 to i-CLK3' and the high period of the first output clock pulse CLK1 is not It overlaps with the fourth output control clock pulse i-CLK4. a high period of the second output clock pulse CLK2 overlaps with the first to fourth output control clock pulses i_CLK2 to i-CLK4, and a high period of the first output clock pulse CLK2 is not related to the The first output control clock pulse i_CLK1 overlaps. The high period of the third output clock pulse CLK3 overlaps with the third, fourth, and first output control clock pulses i-CLK3, i-CLK4, and i-CLK1, and the third output pulse The high period of the wave CLK3 does not overlap with the second output control clock pulse j_CLK2. a high period of the fourth output clock pulse CLK4 overlaps with the fourth, first, and second output control clock pulses 1-CLK4, CLK1, and i-CLK2' and the fourth output clock pulse The two periods of CLK4 do not overlap with the third output control clock pulse i-CLK3. When the first output control clock pulse i-CLK1 having the high period including the rising edge of the first output clock pulse wave CLK1 is defined as a positive iso clock pulse, The fourth output control clock pulse i-CLK4 of the first period of the first output clock pulse CLK1 may be defined as a negative isotropic clock pulse opposite to the positive isotropic pulse wave. Therefore, in the fourth figure, in the fourth figure, the 'output (four) clock pulse i_CLK1 and the fourth output (four) clock pulse 1-CLK4 are the positive and negative isotropic pulse waves of the first output clock pulse CLK1, respectively. . The output control clock pulse i_CLK2 and the first output control clock pulse are respectively the positive and negative (4) pulse waves of the pulse wave CLK2. The third output (four) clock pulse PCLK3 and the second output control clock pulse are positive and negative isotropic pulse waves of the third output clock pulse wave CLK3, respectively. The fourth output control clock pulse and the third control clock pulse K: LK3 are the positive sum of the fourth output clock pulse (10) and the pulse wave respectively, and the corresponding positive and negative isotropic pulses The waves may overlap each other or may not overlap each other. For example, the first output of the positive and negative isotropic pulse waves of the first-output clock pulse CLK1 is controlled by the pulse wave i-CLK1 and the fourth The output control clock pulse waves may overlap each other. The first one of the pulses included in the fourth output clock pulse wave CLK4 is a virtual pulse. The pulse is synchronized with the start pulse wave. Fig. 5 is a timing chart of the output control clock pulse wave and the output wave in the second embodiment according to the present invention. The first to sixth output clocks are shown in Fig. 5. The high periods of the pulse waves CLK1 to (: 〇 <: 6 overlap each other by 1/3 second. Each of the first to sixth output clock pulses CLK1 to 包括 includes a plurality of periodically generated pulses. Each of the first to third output control clock pulses i-CLK1 to i_CLK3 includes a plurality of periodic or aperiodic periods Similarly, the high periods of the first to third output control clock pulses i-CLK1 to i-CLK3 may overlap each other or may not overlap each other. In FIG. 5, the first to The third output control clock pulse 丨_〇1^1 to 彳_〇: ^3 cycles do not overlap each other. ° ° The first to third outputs control the clock pulse i-CLK1 to i-CLK3 Each of its low-cycle voltages (low voltage) is lower than the low-voltage (low voltage) of each of the pulse waves CLK1 to CLK6 at the first to sixth outputs as shown in FIG. The output control clock pulse includes three output control clock pulses having different phases, and the output clock pulse includes six output clock pulses having different phases, ie, FIG. 5 shows n=3, m=2 ' and j=2, the output controls the clock pulse 15 201239846 and the waveform of the output clock pulse. The output clock pulse and the output control the pulse wave It may have the input (four) pulse wave of FIG. 5' and the output control timing, and the pulse wave at the first to third output The first group of two ==. The pulse wave constitutes the second group. The sixth output clock has a sixth output clock to control the high period of the pulse wave. For example, the first phase sequence is included therein. The fourth round of pulse pulse (10) =

There is::: The first output of the bit sequence is controlled by the pulse (8), the rising edge of J is located between the second output of the first-output control clock pulse, and the control clock of the fine wave (4) secret wave CLK4 The high period of the second pulse of pulse wave i~CLK1 is ten. The edge is located in the first output in a manner of squatting, the first and the fifth (fourth) secret wave clki and the second output control time pulse wave (10), and the rising edge of the first = The third output coffee " ^ Κ 3 at the output control pulse wave and the third output shop clock pulse K3 knife for the first and fourth output clock pulse clki and clk4 positive and eighth: exo The second output control clock pulse (10) and the first output control clock pulse i-CLK: 2 fifth output clock pulse (10) * CLK5 positive and negative isotropic pulse wave. j The second output controls the clock pulse illusion and the first output control clock pulse heart illusion respectively. The second and sixth output clock pulses CLK3 and CLK6 positive and negative isotropic clock pulses. ^ At the same time' In Fig. 5, one of the pulses including the pulse wave like 6 at the sixth output is a dummy pulse. This virtual pulse is synchronized with the starting pulse. Fig. 6 is a view showing the structure of the 丨_shift register SR in detail. As shown in Fig. 6, the shift register SR includes h stages sti to STh. Each of the segments 20121,946, ST1 to STh outputs a frame pulse SP1 to SPh by its output terminal οτ. Each of the stages ST1 to STh uses a scan pulse to drive a gate connected thereto. Further, each of the stages ST1 STh thus controls the operation of the downstream stage. Similarly, each of the stages ST1 to STh can thereby control the operation of the upper stage and the operation of the downstream stage based on the structure of the shift register, and the hth stage STh provides the downstream of the virtual STh of the scan pulse. The ground is provided. Several virtual phases can be provided based on the structure of the shift register. The stages ST1 to STh are sequentially pulsed from the first stage ST1 to the hth stage STh. That is, 'the first stage ST1 outputs the first scan pulse sp and then the second stage ST the second scan pulse SP2, the third stage ST3 wire outputs the third scan pulse sp3, and the third stage STh finally outputs the hth scan pulse sPh. The gate lines of the liquid crystal panel (not shown) are sequentially supplied from the stage ST1 to the still scanned pulse wave, and the gate lines are sequentially scanned except for the dummy stage. Similarly, the scan pulse from each output is only provided to the upstream stage. Alternatively, the scanning wave output from each stage can be supplied to the upper and downstream sections. Alternatively, lions can be provided only to the downstream stage from each stage. The shift register SR can be disposed in the liquid crystal panel. That is, the liquid crystal panel has a display area for displaying an image and a display area __non-display area, and the register is located in the non-display area. The phase m to shift of the shift register SR configured in this manner is supplied with the output control clock pulse and the output clock pulse as described above. In the sixth item, the first to the fourth clock pulses i-CLK1 to i-CLK4 and the fourth map 铉+ 铉 铉 吐 sp, Μ 4 'not the first to the fine output clock pulse CLK1 to CLK4 is provided to the stage. In Fig. 6, the third stage is supplied with the scanning pulse wave from the (6)th phase and the scanning pulse wave in the (Ρ+2) phase. Alternatively, the 'pth phase' may be provided with scanning pulses from the (ρ_2)th order pulse wave and from the (ρ+3)th stage. Similarly, in Figure 6, the ρ phase is interconnected with the upstream phase and the downstream phase. The phase may be interconnected only with the upstream phase. The construction of each stage will be described in more detail below. 17 201239846 y to 17 are diagrams showing the construction of the stages according to the first to eleventh embodiments of the present invention f ° = a pattern of 'b (10) and a rib representing the corresponding positive and negative isotropic pulse waves.

Li shows the positive isotropic pulse wave of CLKC, indicating the negative isotropic time of (10)

Pulse wave. J. It is assumed below that the first to fourth output control clock pulses shown in Fig. 4 are illusory to 1 lean If4 and the first to fourth rounds are provided to the seventh pulse wave CLK1 to CLK4. Figure to the description of the stage of Figure 17. The construction of the stage according to the tenth embodiment will be described below with reference to Fig. 7. As shown in Fig. 7, the 'pth> J segment includes: a first switch device. The second switching device is positive and the pull-up switching device Pu. According to the positive (4) pulse wave, the _th device Τη included in the pth stage, and the output terminal 〇τ of the (p-1)th stage is interconnected with the set node Q when turned on. If the Ρ phase is the first phase in which the initial pulse is supplied, the first switching device Td is connected to the initial transmission line instead of the output terminal 〇τ of the (p-1)th stage. The starting pulse wave is supplied to the initial feed line. The second switching device included in the ρ phase is turned on or off according to the negative isochronous pulse wave, and the set node Q is connected to the transfer first discharge voltage VSS1 when turned on. The power is applied to the pull-up switching device Pu' included in the pth phase according to the voltage applied to the set node Q and interconnects the output clock line with the output terminal 〇τ of the p-th phase when turned on. The output clock pulse CLKe is supplied to the input (four) pulse line connected to the upper simple & For example, CLKc is the first-output clock pulse cua, hCLKa and the heart can be respectively the first output control clock pulse i-CLK1 and the fourth output control clock pulse. The high period of the output control clock pulse supplied to the first switching means Tr1 may overlap with the high period of the output control clock pulse supplied to the second switching means Tr2. Alternatively, the high period of the output control clock pulse supplied to the first switching means Tr1 may not be heavier than the high period of the output control clock pulse supplied to the intermediate Tr2. The high period of the output clock pulse provided by the device to the (p-q)th stage may partially overlap with the high period of the output clock pulse i-CLKa supplied to the Pth stage. The construction of the stage according to the second embodiment will be described below with reference to Fig. 8. 3 18 201239846 As shown in Fig. 8, the P phase includes: first to fourth switching devices Tr1 to Tr4, an upper switching device Pu, and a pull-down switching device pd. And turning on or off the first switching device Tri included in the pth stage according to the positive isotropic pulse wave, and interconnecting the output terminal 〇τ of the (ρ_υ phase with the setting node Q when turned on. If the ρ step is In order to be provided with the first stage of the initial wave, the first switching means Tr1 is interconnected with the starting transmission line without the output terminal 〇τ of the (p-Ι) phase. The starting pulse is supplied Starting transmission line, according to the negative isotropic pulse wave, turning on or off the second switching device 2 included in the ρ phase, and interconnecting the setting node Q and transmitting the first discharging voltage vss pressing line when turned on 』木双€冤 according to the output of the pulse line when the pulse is turned on or off is included in the _ 纽 _ _ _ _ _ press line and = = voltage applied to the set node Q on or off The fourth switching device r4 in the pth stage, and the standby switch interconnects the reset node QB and the second discharge voltage discharge voltage line. The younger one is turned on or off according to the voltage applied to the set node Q. Level = Pu ' and output the clock line and the output terminal of the p-th phase when turned on〇 The interconnect 3 OJCe is supplied to the output clock line connected to the pull-up. The J CLKc is the first-output clock pulse CLK, i CLKa and i cLKb can control the clock pulse i-CLK1 and the first The four output control clock pulse is similar. ", the first output is turned on or off according to the electric (four) applied to the reset node QB, and is included in the p-th shut-off device Pd' and the output terminal of the p-stage is sent when turned on. Putting the third discharge voltage line of VSS3 with each other - the discharge of the electric dust, the pull-up switch device, and the third switch device are all raised = electricity = Γ. Each of the clock pulses is low at each The periodic core discharge voltage VSS1 is equal to or different from the second discharge voltage VSS2. When the voltage VSS1 is different from the second discharge voltage VSS2, the first discharge f is still at the second discharge voltage VSS2. VSS1 is lower than or or, - The third discharge voltages VSS1 to VSS3 may be the same. As another option, 201239846 two of the first to second discharge voltages VSS1 to VSS3 may be the same. The rising edge of the pulse wave supplied to the output of the pull-up switching device pu may be The output is supplied to the first switching device Td to control the high cycle of the pulse wave The construction of the stage according to the third embodiment will be described below with reference to Fig. 9. The 'stage' includes the first to eighth switching device switching devices Pu and the pull-down switching device pd as shown in Fig. 9. The isotropic clock pulse or the duty is included in the p-th phase of the -th device plus, and: when turned on, the output terminal of the (p]) phase is connected to the set node 。. If the pth step ^ In order to be provided with the first phase of the initial pulse wave, the first switching device Tr1 is interconnected with the initial transmission line without the output terminal 〇Τβ of the (p-1)th stage being supplied to the start a transmission line. according to the negative isotropic «pulse wave turns on or off the second switching device anode included in the pth phase, and when set to open, sets the node Q and the first thunderbolt voltage for transmitting the first discharge voltage VSS1 Line interconnection. Coin wind €1: According to the output of the self-output pulse line (four) pulse or the third switching device Tr3' included in the ρth phase and when the turn-on, the charging voltage line that transmits the charging voltage is interconnected with the reset section . Instead of the output clock pulse wave, the charging voltage or another output clock pulse wave (other than CLKc) may be supplied to the third switching device Tr3. /, the fourth switch r4' included in the pth phase is turned on or off according to the voltage applied to the set node q and the reset node QB is interconnected with the transfer second discharge voltage discharge voltage line when turned on. The gradation pulse from the (p+2)th stage turns on or off the fifth opening Tr5' included in the Pth stage and the set node Q and the first release=device TV5 can be provided when turned on There are scan pulses from the (p+3)th stage instead of the +5th stage scan pulse. p; according to the input terminal 〇τ of the P phase, the electric switching device is included in the sixth switching device of the p-th phase. And when turned on, the reset node QB is interconnected with the second discharging voltage line. . The age is based on the (P+2) stage, the pulse wave is turned on or the color is included in the seventh stage of the Pth stage = device Tr7' and when turned on, the output terminal 〇τ of the pth stage and the third discharge voltage line Mutual White = The seventh switching device Tr7 can be supplied with a scanning pulse wave from the (Ρ+3)th stage without the scanning pulse wave from the (P+2)th stage. 201239846 Turns on or off the switching device Tr8' included in the pth stage according to the scanning pulse from the S(ρ-1) stage and interconnects the charging voltage line with the setting node q when turned on. If the stage is the first stage in which the initial pulse wave is supplied, the eighth switching means Tr8 is supplied with the start pulse line from the start transmission line instead of the (p-1)th stage. The pull-up switching device Pu' included in the p-th stage is turned on or off according to the voltage applied to the set node Q and the output clock line is interconnected with the output end $ 〇τ of the p-th stage when turned on. The output pulse wave CLKe is supplied to the input (four) pulse connected to the pull-up & If CLKc is the first-output clock pulse CLK1, and the rainbow can be the first output control clock pulse i-CLK1 and the fourth output control clock pulse i_CLK4, respectively. Turning on or off the pull-down switching device Pd′ included in the p-th stage according to the voltage applied to the reset node QB and, when turned on, the output terminal 〇τ of the p-th phase and the third discharging voltage line transmitting the third discharging voltage VSS3 even. The first to third discharge voltages VSS1 to VSS3 and the charging voltage VDD are direct current voltages. The first to second discharge voltages VSS1 to VSS3 are set lower than the charging voltage VDD. For example, the charging voltage VDD can have a positive value, and the discharging electric house can have a negative value. The first to third discharge voltages VSS1 to VSS3 may have the same voltage value. Alternatively, at least two of the first to second discharge voltages VSS1 to VSS3 may have different values. In a case where at least two of the first to second discharge voltages VSS1 to VSS3 have different values, the first discharge voltage VSS1 may be The highest or lowest, the second discharge voltage VSS2 may be the highest or lowest, or the third discharge voltage VSS3 may be the highest or lowest. Alternatively, the first discharge voltage VSS1 may be set to the highest, the third discharge voltage VSS3 may be set to the lowest, and the second discharge voltage VSS2 may be set to be between the first discharge voltage vssi and the third discharge voltage Vss3. Similarly, the second discharge voltage VSS2 can be set to the highest level. The third discharge voltage VSS3 can be set to the lowest, and the first discharge voltage VSS1 can be set to be between the second discharge voltage VSS2 and the third discharge voltage VSS3. Similarly, the third discharge voltage VSS3 can be set to the highest, the first discharge voltage VSS1 can be set to the lowest ' and the second discharge voltage Vss2 can be set between the third discharge voltage VSS3 and the first discharge voltage VSS1. Likewise, the first discharge voltage VSS1 and the third discharge voltage VSS3 may be set to be the same ' and the second discharge voltage VSS2 may be set equal to or lower than the third discharge voltage VSS3. The rising edge of the output pulse wave supplied to the pull-up switching device Pu may be located in the high period of the output control clock pulse supplied to the 21st 201239846 switching device Tr1. At the same time, in the third embodiment, the first discharge voltage VSS1 can be replaced with the output clock pulse. In this case, the pulse pulse of the output of the first discharge voltage VSS1 is replaced with the output pulse wave supplied to the pull-up switching device Pu. In the third embodiment, each of the output control clock pulses i-CLK1 to i-CLK4 is set to be equal to or lower than the output clock pulse wave CLK1 at its still period voltage (high voltage). Each of CLK4 is at its high cycle voltage (high voltage similarly, the first and second discharge voltages VSS1 and VSS2 may be equal to or lower than the voltage of each of the output control clock pulses at its low cycle. At the same time, at least one of the fifth to eighth switching devices Tr5 to Tr8 can be removed from the structure of the third embodiment. The construction of the stage according to the fourth embodiment will be described below with reference to FIG. As shown in Fig. 10, the ρ phase includes: first to sixth switching devices Td to Tr6, a pull-up switching device Pu, and a pull-down switching device Pd. The pulse is turned on or off according to the positive isotropic pulse wave. a first switching device Tr1 of the stage, and interconnecting the output terminal OT of the (P-1)th stage with the setting node Q when turned on. If the Pth stage is the first stage in which the initial pulse wave is supplied, the first switch The device Tr1 is interconnected with the starting transmission line instead of the (ρ-I)th order Output terminal 〇τ. The initial pulse wave is supplied to the initial transmission line. The second switching device Tr2 included in the ρth phase is turned on or off according to the negative isotropic clock pulse, and is turned on when turned on The set node Q is interconnected with the first discharge voltage line that transmits the first discharge voltage VSS1. The third pulse device Tr3' included in the pth phase is turned on or off according to the output pulse pulse from the output pulse line and is turned on when turned on. The charging voltage line transmitting the charging voltage vdD is interconnected with the common point CN. The fourth switching device Tr4' included in the pth phase is turned on or off according to the voltage applied to the setting node Q and the common node CN and the transmitting portion are turned on when turned on The second discharge voltage line of the two discharge voltage VSS2 is interconnected. The fifth switching device Tr5' included in the pth phase is turned on or off according to the voltage applied to the common node CN and the charging voltage line and the reset node QB are mutually turned on when turned on. The voltage of the node q is turned on or off to the sixth switch 22 201239846 device Tr6 included in the pth stage, and when turned on, the reset node QB is interconnected with the second discharge voltage line. The voltage of the set node Q turns on or off the pull-up switching device Pu' included in the p-th phase and interconnects the output clock line with the output terminal OT of the p-th phase when turned on. The output pulse S CLKe is supplied to With the field open (9) mixed (four) pulse. If CLKc is the first-output clock pulse CLK1, and the same as the rainbow can be the first output control clock pulse 1-CLK1 and the fourth output control clock The pulse wave i_CLK4 turns on or off the pull-down switching device Pd included in the pth stage according to the voltage applied to the reset node QB, and when the turn-on, turns the output terminal 〇τ of the pp segment and the third discharge voltage VSS3 Three discharge voltage lines are interconnected. The fourth embodiment-to-third discharge voltage may have the same characteristics as the third embodiment. The input (4) secret wave edge that provides the top-up PU can be recorded in the high period of the output control clock pulse supplied to the first switching device Tr1. The construction of the stage according to the fifth embodiment will be described below with reference to Fig. 11. As shown in Fig. 11, the first pji includes: first to sixth switching devices Td to plus, pull-up switching device Pu, and pull-down switching device Pd. The stage of the fifth embodiment is the same as the fourth embodiment except that the second discharge VSS2 is the same as the third discharge voltage VSS3. That is, as shown in the nth figure, the second discharge voltages VSS1 and VSS2 are applied. The first and second discharge voltages VSS1 and VSS2 may have the same characteristics as those of the second embodiment. Alternatively, the first and second discharge voltages VSS1 and VSS2 may have the same characteristics as those of the third embodiment. The construction of the stage according to the sixth embodiment will be described below with reference to Fig. 12. As shown in Fig. 12, the p-stage includes: first to fourth switching devices Td to the switching device Pu, the pull-down switching device Pd, and the capacitor c. The 开关-switch device included in the p-th phase is turned on according to the positive isotropic pulse wave, and the output terminal 〇1 of the (p-Ι) phase is interconnected with the set node Q when turned on. For example, the P phase is the first stage in which the initial pulse wave is supplied, and the first switch is connected to the output terminal OT of the start transmission line instead of the (p-1) p segment. The initial pulse wave is supplied to the initial transmission according to the negative isotropic clock pulse to turn on or off the second switching device included in the pth segment 23 23 201239846 and when turned on, the setting "point Q secret transmission" - discharging the first discharge voltage line of vssi. The scan pulse according to the (p 1 ) 13⁄4 & is turned on or depends on the third switching device Tr3 included in the pth stage, and the set node q is turned on when turned on Interconnecting with a charging voltage line that transmits a charging voltage. According to (4) nU $ point Q, the fourth switch TY4' included in the 帛p phase is turned on or off and the node qb is reset and the second discharging voltage is transmitted when turned on. The second discharge voltage line is disconnected. - the pull-up switching device Pu included in the p-th stage is turned on or off according to the voltage applied to the set node q, and the output terminal of the clock line and the 帛p stage is output when turned on 〇τ interconnection. The output clock pulse CLKe is supplied to the input (four) pulse line connected to the upper pull-off device %. If CLKC is the first output pulse wave CLK1, i-CLKa and i-CLKb can be respectively An output control clock pulse i-CLK1 and a fourth output control pulse Wave i_CLK4. Turns on or off the pull-down switching device Pd included in the pth stage according to the voltage applied to the reset node QB, and turns on the output terminal 〇th of the pth stage and the third discharge of the third discharge voltage VSS3 when turned on The voltage line is interconnected. The capacitor C is connected between the output clock line connected to the pull-up switching device Pu and the reset node QB. The first to third discharge voltages VSS1 to VSS3 of the sixth embodiment may have At the same time, in the sixth embodiment, the first discharge electric power SVss1 can be replaced with the output clock pulse wave. In this case, the output clock of the first discharge voltage VSS1 is replaced. The pulse wave is the same as the output clock pulse supplied to the pull-up switching device Pu. In the sixth embodiment, the output control clock pulse is set to be equal to or lower than the voltage β of each of its high periods. The voltage of each of the output pulse waves is at its high period. Similarly, the third discharge voltage VSS may be scaled or lower than the voltage of each of the output control clock pulses at its low period. Up to the pull switch device Pu The rising edge of the output clock pulse may be located in a high period of the output control clock pulse supplied to the first switching device Tr1. The construction of the phase according to the seventh embodiment will be described below with reference to Fig. 13. 24 201239846 13 shows that the 'pth stage includes: first to fifth switching devices Tri to ^^, pull-up switching device Pu, and pull-down switching device pd. According to the positive isotropic pulse wave on or off is included in the P phase a first switching device Tr1, and interconnecting the output terminal 〇τ of the (pd)th stage with the set node Q when turned on. If the Pth stage is the first stage of providing the initial pulse wave, the first switching device The Trl is interconnected with the starting transmission line instead of the output terminal 〇τ of the (p-ι) stage. The starting pulse wave is provided to the initial transmission line. The second switching device Tr2 included in the pth phase is turned on or off according to the negative isotropic clock pulse, and the set node Q is interconnected with the first discharge voltage line transmitting the _discharge voltage VSS1 when turned on. The set switch node q and the transfer charging voltage line are mutually multiplexed according to the scan pulse from the (p-Ι) stage to turn on or off the third switch device Τι3' included in the pth stage. ; brother € according to the application of 5$ 晋自Π里·t AA «35» RE- ΒΒ J-, na ue i* Λ·丨_

The charging circuit is connected to the reset node according to the input (4) pulse of the self-input itj clock line and is included in the p-th switching device Tr4' and when turned on. Device Tr5 discharges voltage line interconnections.

According to the voltage applied to the setting node Q, the voltage is turned on or off in the p-th device PU' and when the 瞎肱铋山姓(10) is turned on, the same characteristic is described. The rising edge of the output pulse wave supplied to the pull-up switching device Pu may be located in the high period of the output control clock pulse supplied to the first switching device Tr1. The construction of the stage according to the eighth embodiment will be described below with reference to Fig. 14. As shown in Fig. 14, the p-th stage includes first to fifth switching devices Tr] to Tr5, a pull-up switching device Pu, and a pull-down switching device Pd. The first switching device Td included in the pth stage is turned on or off according to the positive isotropic clock pulse, and the output terminal 第 of the (P-1)th stage is interconnected with the setting node q when turned on. If the P phase is the first phase in which the initial pulse wave is supplied, the first switching device Tr1 is interconnected with the initial transmission line instead of the output terminal OT of the (p-Ι) phase. The starting pulse wave is provided to the initial transmission line. The second switching device Tr2 included in the pth stage is turned on or off according to the negative isotropic clock pulse, and the set node q is interconnected with the first discharging voltage line transmitting the first discharging voltage VSS1 when turned on. Turning on or off the third switching device Tr3 included in the pth stage according to the voltage applied to the output terminal OT of the pth stage, and turning the reset node qB and the second discharging voltage transmitting the second discharging voltage VSS2 when turned on Line interconnection. The charging signal line Tr4' included in the pth stage is turned on or off according to the output pulse wave from the output clock line, and the charging voltage line transmitting the charging electric M is interconnected with the reset node QB when turned on. The fifth switching device Tr5' included in the pth stage is turned on or off according to the voltage applied to the setting node Q and the reset node qb is interconnected with the second discharging voltage line when turned on. • The pull-up switching device Pu included in the p-th stage is turned on or off according to the electric (four) applied to the set node Q, and the output clock line is interconnected with the output terminal 〇τ of the p-th stage when turned on. The output clock pulse CLKc is supplied to the output clock line connected to the pull-up switch i & If CLKc is the first 'iB clock CLK1, the mKa and the milky county can output the clock pulse i-CLK1 and the fourth output control clock pulse ^^4. The pull-down switching device Pd' included in the p-th stage is turned on or off according to the voltage applied to the reset node qB and the output terminal of the p-stage is connected to the second de-embedded voltage line when turned on. The lower subtraction earning Pd may be interconnected with the third discharge voltage line instead of the second discharge voltage line. In this case, the 'first to third discharge voltages qing to vss3' may have the same characteristics as those of the third embodiment 26 201239846. The fourth_device Tr4 is supplied with the same output clock pulse as the pull-up duty Pu. The first and second discharges « VSS1 and VSS2 may have the same characteristics as those of the second embodiment. Alternatively, the first and second discharge voltages VSS1 and VSS2 may have the same characteristics as those of the third embodiment. The rising edge of the output pulse wave supplied to the pull-up switching device Pu may be located in the high period of the output control clock pulse supplied to the first switching device Tr1. The construction of the stage according to the ninth embodiment will be described below with reference to Fig. 15. As shown in Fig. 15, the p-th stage includes first to fourth switching devices Td to Tr4, a pull-up switching device Pu, and a pull-down switching device Pd. The first switching device Td included in the pth stage is turned on or off according to the positive isotropic clock pulse, and the output terminal 〇τ of the (p-1)th stage is interconnected with the setting node Q when turned on. If the P phase is the first phase in which the initial pulse wave is supplied, the first switching device Td is interconnected with the initial transmission line instead of the output terminal 0 of the (p-Ι) phase. The starting pulse wave is provided to the initial transmission line. Opening or closing the second switching device Tr2 included in the pth phase according to the negative isotropic clock pulse, and interconnecting the setting node Q with the first discharging voltage line transmitting the first discharging voltage when turned on . The third switching device Tr3 included in the pth stage is turned on according to the charging voltage VDD of the self-charging voltage line, and the charging voltage line is connected to the reset node. The fourth switching means Tr4 included in the pth stage is turned on or off according to the output pulse wave from the output clock line, and the reset node QB is interconnected with the second discharge electric dust line when turned on. Here, the second discharge voltage line transmits the second discharge voltage vss2. According to the setting applied to the setting section, the voltage of the point Q turns on or off the pull-up switch Pu' included in the p-th stage and the pulse wave CLKe is supplied when the output clock line and the output terminal 〇τ of the p-stage are turned off when turned on. To the thin wire connected to ± open the hidden pu. For example, ^^LKc is the first-output clock pulse CLK1, and the melon can be the first-input: the clock pulse i-CLK1 and the fourth output control clock pulse i_CLK4. The third discharge voltage line of the VSS3 is interconnected according to the application device Pd applied to the reset node qB and when turned on. The voltage turns on or off the output terminal OT of the P-phase included in the p-th phase and transmits the third discharge voltage. 27 201239846 The fourth switching device TM and the pull-up switching device PU are provided with the same output clock pulse wave. The first to third discharge voltages VSS1 to VSS3 may have the same characteristics as the phase 1 of the third embodiment. The rising edge of the pulse wave supplied to the output of the pull-up switching device Pu may be located at the output supplied to the first switching device Tr1 Controls the high period of the pulse wave. The construction of the stage according to the tenth embodiment will be described below with reference to Fig. 16. As shown in Fig. 16, the p-th stage includes first to sixth switching devices Tn to Tr6, a pull-up switching device Pu, and a pull-down switching device Pd. The first switching device included in the pth stage is turned on or off according to the positive isotropic clock pulse, and the output terminal 第 of the (p-1)th stage is interconnected with the setting node q when turned on. If the P phase is the first phase in which the initial pulse wave is supplied, the first switching device Tr1 is interconnected with the initial transmission line instead of the output terminal OT of the (p-Ι) phase. The starting pulse wave is provided to the initial transmission line. The second switching device Tr2 included in the pth stage is turned on or off according to the negative isotropic clock pulse, and the set node Q is interconnected with the first discharge voltage line transmitting the first discharging voltage .VSS1 when turned on. According to the output pulse pulse from the output pulse line, the pulse wave is turned on or off, the first switching device Tr3 included in the pth stage, and when turned on, the charging voltage line of the charging voltage vdd is transmitted and shared ^

Point CN interconnection. /eight P turns on or off the fourth switching device Tr4 included in the pth stage according to the voltage applied to the setting node Q, and interconnects the common node CN and the second discharging voltage line transmitting the second discharging voltage vs. . The fifth switching device Tr5 included in the pth stage is turned on or off according to the voltage applied to the common node CN, and the charging voltage line and the reset node qb are connected when turned on. The sixth switching device Tr6 included in the pth stage is turned on or off according to the voltage applied to the setting node Q, and the reset node qB and the second discharging voltage line are connected when turned on. The pull-up switching device Pu included in the pth phase is turned on or off according to the voltage applied to the set node Q, and the output clock line is interconnected with the output terminal of the pth phase when turned on. The output clock pulse CLKc is supplied to the output clock line connected to the pull-up switching device. For example, CLKc is the first output clock pulse CLK1, fCLKa and "cLKb can be the first output control clock pulse 1-CLK1 and the fourth output control clock pulse i_CLK4 respectively. 28 201239846 according to the reset node The voltage of QB turns on or off the pull-down switching device Pd included in the p-th stage, and interconnects the output terminal 〇τ of the p-th stage with the second discharging voltage line when turned on. The first and second discharging voltages VSS1 and VSS2 may It has the same characteristics as the second embodiment. Alternatively, the first and second discharge voltages VSS1 and VSS2 may have the same characteristics as those of the third embodiment. The rising edge of the pulse wave provided to the output of the pull-up switching device Pu may be located. The output supplied to the first switching device Tr1 controls the high period of the pulse wave. The construction of the stage according to the first embodiment will be described with reference to Fig. 17. As shown in Fig. 17, the p stage includes : first to fifth switching devices Td to Tr5, pull-up switching device Pu, and pull-down switching device Pd. Turning on or off the first switching device included in the pth stage according to the positive isotropic pulse wave, and when turned on The output terminal 〇τ of the (p_l)th stage is interconnected with the set node q. If the second stage is the first stage in which the initial pulse is supplied, the first switching device Tr1 is interconnected with the starting transmission line instead of the first (ρ 1) an output terminal of the phase. The initial pulse wave is supplied to the initial transmission line. The second switching device Tr2 included in the ρ phase is turned on or off according to the negative isotropic clock pulse, and is turned on. The set node Q is interconnected with a pin line transmitting the first discharge voltage VSS1. The third switching device ΊΥ3' included in the pth stage is turned on according to the charging voltage VDD of the self-charging voltage line and the charging voltage line is connected The node QB is reset. The fourth switching device Tr4 included in the pth phase is turned on or off according to the output pulse pulse from the output clock line, and when turned on, the node QB is reset and the second discharging voltage vss is discharged. The voltage line is interconnected. The fifth switching device Tr5 including the sand ρ phase is applied according to the setting _q(4), and the reset node QB is interconnected with the second discharging voltage discharging voltage line when turned on. Device Q The Lai Kai or the amount is included in the P-stage pull-up switching device Pu, and the output pulse line and the output terminal 〇τ of the p-th stage are supplied to the pull-up device when the device is turned on. The input (four) pulse fruit (10) is the first-output clock pulse (10), and the (10) and the second (10) can control the clock pulse i-CLK1 and the fourth output control pulse wave respectively. 2012. The output terminal 〇τ of the pth phase is interconnected with the second discharge voltage line when the pull-down of the p-th phase is turned on. The first to third discharge voltages VSS1 to VSS3 may have the same as the third embodiment. The input (four) pulse wave rising edge provided to the pull-up device Pu may be mixed in the high cycle of the output control clock pulse supplied to the first switching device Tr1. In the following, the operation of the pulse wave αΚ1 to ^ in the fourth to fourth output according to Fig. 4 and the pulse to the fourth to fourth wheel control is also given to the operation of the ninth stage. description of. Assuming that the stage of Fig. 9 is the fifth stage, it can be seen that i<:LKa is the first-output control clock pulse i-CLKl, hCLKb is the fourth round-out control clock pulse, and CLKc is the first. The pulse wave, SP(pl) is the scan pulse from the fourth position, and sp(p+i) is the scan pulse from the sixth stage. Similarly, it is assumed that the first to third discharge voltages VSS1 to vss3 are the same. First, when the first output control pulse 30CLjq is maintained at a high power, the first and eighth P devices Tr1 and TY8 are turned on. Therefore, the scanning pulse from the fourth stage is supplied to the setting section by the first switching device Τι*1 which is turned on, and the charging voltage is supplied to the setting node Q by the eighth switching means which is turned on. Therefore, the set node Q is charged, and the pull-up switching device Pu and the fourth switch device Tr connected to the charged setting node Q via the gate electrode are turned on. Similarly, the second discharge power, VSS2 is supplied to the reset node qb by the turned-on fourth switching device Tr4. Therefore, the reset node QB is discharged, and therefore, the pull-down switching device Pd that is lightly connected to the discharged reset node via the gate electrode is turned off. ' Subsequently, when the first output clock pulse CLK1 is maintained at a high voltage, the first output clock pulse wave CLK1 is opened by the pull-up switch device & as the scan pulse wave output 1 sweep finger pulse by The output terminal οτ is supplied to the fifth gate line, the fourth stage (the fifth and seventh switching devices Tr5 and Tr7), and the sixth stage (the first and eighth switching devices Tr1 and Tr8) e in other words, the scanning with high voltage The pulse wave is supplied to the output terminal OT. Therefore, the sixth switching device Tr6 connected to the output terminal via the gate electrode is turned on, and the second discharging voltage v s S2 is supplied to the reset node qb by the turned-on sixth switching device Tr6. 201239846 At the same time, the third switching device Tr3 is turned on by the first output clock pulse CLKi, and the charging voltage VDD is supplied to the reset node qb by the turned-on third switching device Tr3. The reset node QB is maintained in a discharge state independent of the charging voltage VDD because the reset node QB is supplied with the second discharge voltage vsS2 by the fourth and sixth switching devices Tr4 and Tr6. Subsequently, the scanning pulse wave from the sixth stage is supplied to the gate electrode of the fifth switching device Tr5 and the gate electrode of the seventh switching device Tr7, whereby the fifth switching device τΓ5 and the seventh switching device Tr7 are turned on. Therefore, the first discharge voltage vssi is supplied to the set node Q by the turned-on fifth switching means Tr5 to discharge the set node Q. Therefore, the set node Q is discharged, and is turned off by the pull-up switching device Py and the fourth switching device I# connected to the set node Q by the gate electrode. At the same time, the third discharge voltage VSS is supplied to the output terminal OT by the turned-on seventh switching device Tr7. Therefore, the output terminal is discharged, and the sixth switching device Tr6 connected to the discharged output terminal OT via the gate electrode is turned off. At the same time, since the fourth and sixth switching devices Tr4 and Tr6 are turned off, the reset node QB is charged with the charging voltage vdd supplied from the turned-on third switching device Tr3. That is, the scanning pulse from the sixth stage is generated by the third output clock pulse CLK2. The third switching device is still turned on to charge the reset node QB with a period corresponding to 1/3 period, wherein the second output clock pulse clk2 and the first output clock pulse CLK1 overlap each other. Gj, the pull-down switching device Pd connected to the charged reset node QB via the gate electrode is turned on. Therefore, the third discharge voltage Na is supplied to the output terminal 〇τ by the open pull-down switching device Pd. Thereafter, when the fourth output control pulse ί < χ κ4 is maintained at a high voltage, the second switching device ΊΥ 2 = il' and the first discharging voltage VSS1 is supplied to the setting node Q by the turned-on second switching device. Therefore, the set node Q is discharged. According to the present invention, the low voltage of the output control clock pulse is set to be lower than the low voltage of the output control clock pulse (corresponding to the low voltage of the scanning pulse), and is set lower than the first to third discharge voltages VSS1. To VSS3. Therefore, it is possible to add and minimize the current by the first and second switching means > Na-segment time, and the pulse wave of the control is kept at a low battery. $ ^ ' will be given below the operation of the first to fourth output clock pulse CLK1 segment according to Fig. 4 to the fourth output control clock pulse gamma to the first step of the graph. The stage of the 10th figure is the fifth stage. It can be seen that when LCLKa is the first output control 31 201239846 pulse wave l-CLKl ' i-CLKb is the fourth output control clock pulse rainbow, CLKc is the first The pulse wave, and SP(pl) is the scan pulse from the fourth stage. Similarly, 'the first to third discharge voltages VSS1 to VSS3 are assumed to be the same. First, when the pulse-pulse i<:LK1 is maintained at a high voltage in the first-output control, the first switching device Tr1 is turned on. Therefore, the scanning pulse from the fourth stage is supplied to the setting node Q by the first switching means m that is turned on. Therefore, the setting node q is charged, and the pull-up switching device PU, the fourth switching device Tr4, and the sixth switching device ΊΥ6 connected to the charged setting node Q via the gate electrode are turned on. Similarly, the second discharge voltage VSS2 is supplied to the common node CN by the turned-on fourth switching device Tr4. Therefore, the common node CN is discharged, and therefore, the fifth switching device connected to the common node CN via the gate electrode is turned off. On the other hand, the second discharge voltage VSS2 is supplied to the reset node qB by the turned-on sixth switching device Tr6. Therefore, the reset node QB is discharged, and therefore, the pull-down switching device Pd connected to the discharged reset node qB via the gate electrode is turned off. Subsequently, when the first output clock pulse wave CLK1 is maintained at a high voltage, the first output clock pulse wave CLK1 is output as a scan pulse wave by the open pull-up switching device Pu. The scan pulse is supplied to the fifth gate line and the sixth stage (its first switching means Tr1) by the output terminal OT. At the same time, the third switching device Tr3 is turned on by the first output clock pulse CLK1, and the charging voltage VDD is supplied to the common node CN by the turned-on third switching device τ3. The common node CN is maintained in a discharge state independent of the charging voltage VDD because the common node sCN is supplied with the second discharge voltage vsS2 by the fourth switching device Tr4. Subsequently, when the fourth output control time pulse wave i-CLK4 is maintained at a high voltage, the second switching device Tr2 is turned "on" and the first discharge voltage VSS1 is supplied to the set defect by the turned-on second switching device Tr2 Q. Therefore, the set node q is discharged, and the pull-up switching device Pu, the fourth switching device Tr4, and the sixth switching device Tr6 connected to the set node Q via the gate electrode are turned off. At the same time, since the fourth switching device Tr4 is turned off, the common node CN is charged with the charging voltage VDD supplied from the turned-on third switching device Tr3. That is, the scan pulse from the sixth stage is generated by the second output clock pulse CLK2. The third switching device Tr3 is turned on to charge the common node CN - a period corresponding to the /3 cycle, wherein the second output clock pulse CLK2 and the first output pulse wave CLK1 overlap each other. Therefore, the fifth 32 201239846 switching device Tr5 connected to the common node CN via the gate electrode is turned on. Therefore, the charging voltage vdd is supplied to the reset node qB by the turned-on fifth switching device Tr5. Therefore, the reset section SQB is charged, and the pull-up switching device pu connected to the charged reset node QB via the gate electrode is turned on. The third discharge voltage VSS3 is supplied to the fifth gate line and the sixth stage by the open pull-up switching device Pu (the first switching device Tr1 thereof), according to the present invention, the low voltage of the output control clock pulse is set to be low The output control clock pulse wave (corresponding to a low voltage of the scan pulse wave), and is set lower than the first to third discharge voltages VSS1 to VSS3. Therefore, the first and second switching devices Tr1 and Tr2 can be used. Minimizing the current leakage for a period of time, wherein the output control clock pulse is kept at a low voltage. Figure 18 is a diagram showing the first to fourth output clock pulses CLK1 to ^^^^ and first to fourth of FIG. The output controls an analog waveform diagram of the pulse wave i_CLK1 to i_CLK4, wherein the first figure (8) shows the first to fourth output clock pulses CLK1 to CLK4, and the 18th (9) shows the first to fourth output control pulses. Waves i-CLK1 to i-CLK4. Fig. 19 is an analog waveform diagram showing the positive isotropic clock pulse and the negative isotropic clock pulse with respect to the first output clock pulse CLK1 of Fig. 18. $ 20 The figure shows the voltage at the setting _q and the reset node QB and according to Fig. 8 The operation of the segment is mixed with miscellaneous money. (4) The secret wave of the secret wave. From the figure, it can be seen that the 'first-switch device Tr1 is turned on to charge the set node 一段时间 for a period of time. - the round-off control pulse wave isolating and the scanning pulse wave (4) is maintained at a high voltage. At this time, the fourth output control clock pulse is kept at a low voltage, and thus the 'first-switching device Tr2 is turned off. Thereafter, If the voltage of the pulse wave CLK1 turns at the first output, the scan pulse is generated for the high county. Thereafter, when the pulse wave appears to have two voltages when the fourth output is controlled, the set node Q is discharged. In the voltage circuit, when the node is set to be held at a low voltage, the pulse wave CLK1 leads to a leakage current. Therefore, it is preferable to set the dragon at the node Q by the clock system of the combination. According to the present invention, when _q is set, the discharge voltage is maintained at a low voltage, and the pulse wave CLK1 is maintained at a south voltage. Fig. 21 is a diagram showing the voltage at the set node Q and the reset node (9) and according to the u 33 201239846 The scanning pulse generated by the operation of the image An analog waveform diagram of the voltage of the output pulse wave. Fig. 2 is an analog waveform diagram showing the output control clock pulse and the output clock pulse of the stage supplied to Fig. 13 and Fig. 14. In Fig. 22, the first to fourth output clock pulses clki to CLK4 have a voltage of 25 V (high voltage) in their high period and a voltage of 5 V (low voltage) in their low period. Similarly, the first Each of the pulse signals up to the fourth output control clock pulse to KLK4 has a voltage of 2 〇v (high voltage) in its high period and a voltage of -15 volts (low voltage) in its low period. Fig. 23 shows the setting node An analog waveform diagram of the voltage at the q and the reset node qB and the voltages of the sweep and wave (four) pulse waves generated according to the operation of the phase of the second graph. Fig. 24 is a diagram showing the waveforms of the voltage at the set node q and the reset node qB and the voltage-distributed wave and the (four) pulse wave according to the stage (4) of the u-th diagram. Specifically, FIG. 24(a) shows that the voltages at the node q and the reset node QB are set under the conditions that the first and third discharge voltages VSS1 and VSS3 are _5v and the second=electrical voltage VSS2 A -7V and Scanning the pulse wave and outputting the voltage of the pulse wave; 24th _(incidentally setting the node q under the condition that the first and third discharge voltages VSS|々 and VSS3 are -5V, and the second discharge voltage VSS2 is ·2ν And resetting the voltage at the known point QB and the voltage of the scanning pulse wave and the output clock pulse wave. Fig. 25 is a view showing the operation of setting the voltage at the node q and the reset node QB and the operation of the step & An analog waveform diagram of the generated scanning pulse wave and the voltage of the output clock pulse wave. Fig. 26 is a view showing the scanning pulse wave generated by setting the voltage at the node q and the reset node qB and the operation according to the stage of Fig. 17 An analog waveform diagram of the voltage of the output pulse wave is shown in Fig. 27. Fig. 27 is a view showing a modified structure of Fig. 8. As shown in Fig. 27, the stage of Fig. 8 does not include the second switching device Tr2. 27, the P stage may include: the first switching device Tr1, the third switching device □, the first The switching device Tr4, the pull-up switching device pu, and the pull-down switching device ρ (in this case, the gate line connecting the node Q from its upstream phase (ie, the previous stage) is discharged by a low voltage. The first switching device Tr1, the third switching device Tr3, the fourth switching device Tr4, the pull-up switching device PU, and the pull-down switching device Pd, and the first switching device Tr1 and the third switching device Tr3 shown in FIG. The fourth switching device Tr4, the pull-up switching device Pu, and the pull-down switching device Pd are identical. In this case, the output to the (pq) stage is controlled to control the pulse wave "CLKa's 34 201239846 j period bribe s the part of the delivery system that is supplied to the HP stage is overlapped. At the same time, the gate electrode of the third switching device Tr3 of the charge 27 of the pulse wave CLKC is replaced by the first supply. The rising edge of the output pulse wave of the pull-off switching device Pu may be located in the high period of the pulse wave for providing the output control of a switching device Tr1. Fig. 28 is a view showing the modified structure of Fig. 27. Third open The closing device Tr3 may have the connection structure shown in Fig. 28. That is, as shown in Fig. 28, the third switching device is positively turned on or off according to the output pulse line from the output pulse line and is connected when the opening The (four) pulse line and the reset node qb are output. The output pulse wave CLKc is supplied to the output clock line connected to the third switching device. If CLKc is the first output, the pulse wave can be separated from the pulse. For the first control clock pulse i-CLK1 and the fourth output control clock pulse "Jiang Yi. In the case of T's supply to the (p_q) stage of the output control, the pulse wave can be at the same period The pulse wave also partially overlaps with the high cycle of the pulse control provided to the p-th stage. The rise of the input (four) secret wave providing the up-down PU can be recorded in the high period of the output control clock pulse supplied to the first switching device Tr1. Fig. 29 is a schematic view showing another modified structure of Fig. 27. The third switching device Tr3 shown in Fig. 27 may have a connection structure shown by the 29th thief. That is, as shown in Fig. 29, the 'third switching device Tr3 is turned on according to the charging voltage VDD of the self-charging voltage line' and connects the output clock line to the reset node QB. The output clock pulse clKc is supplied to the output clock line connected to the third switching device Tr3. If the CLKc$ first output clock pulses CLIU'i-CLKa and i-CLKb can be the first output control clock pulse rainbow and the fourth output control clock pulse i-CLK4, respectively. At the same time, the pulse pulse CLKc in place of the output voltage VDD can be applied to the gate electrode of the third switching device Tr3 of Fig. 29. The rising edge of the output pulse wave supplied to the pull-up switching device Pu may be located in the high period of the output control clock pulse supplied to the first switching device Tr1. Fig. 30 is a schematic view showing another modified structure of the first drawing. 5 35 201239846 As shown in Fig. 30, the stage of the ι〇 diagram does not include the second switching device Tr2. That is, the 'pth stage' as shown in Fig. 30 may include the first switching means Td, the third to sixth switching means Tr3 to Tr6, the pull-up switching means Pu, and the pull-down switching means Pd. In this case, the gate line connecting the node Q from its upstream stage (i.e., the previous stage) is discharged by a low voltage. At the same time, the drain electrode of the third switching device Tr3 of Fig. 30 can be connected to the charging voltage line which replaces the pulse at the output. In this case, the high period of the output control clock pulse LCLKa supplied to the (p_q)th stage may partially overlap with the high period of the output control clock pulse i_CLKa supplied to the pth stage. At the same time, the charging voltage VDD of the output clock pulse CLKc can be applied to the gate electrode of the third switching device τ3 of Fig. 30. It is known that the rising edge of the output pulse wave of the output to the pull-up switching device pu can be located in the high period of the output control clock pulse supplied to the first switching device Tr1. At the same time, in all embodiments, two identical discharge voltages can be provided by separate discharge voltage lines or by separate discharge voltage lines. As can be seen from the above description, the gate driving circuit according to the present invention is configured such that the output control clock pulse low voltage is lower than the output control clock pulse low voltage (corresponding to the low voltage of the scanning pulse wave) ), and the first to third discharge voltages ^, therefore, the first and second switching devices can minimize the drain leakage time - where the output control clock pulse is kept at a low voltage, thereby stabilizing the self-shift The output of the bit buffer. It will be appreciated that various modifications and changes can be made to the present invention without departing from the spirit and scope of the invention. Therefore, it is to be understood that the invention is intended to cover the modifications and variations of the invention This application claims the Korean Patent Application No. 10-2011-0015738 filed on February 22, 20, and on July 5, 2011, the rights of the smugglers, s. As a reference to arsenic, please refer to the following figure, which provides a further understanding of the present invention and a part of the social book - part _ her__ job-zhan ^ her == 36 201239846 explanation. In the figure: Figure 1 is a graph showing the temperature-based relationship between the gate voltage and the gate current of a conventional oxide semiconductor transistor; Figure 2 is the voltage of the light and scan pulse at the setting _ Schematic diagram of the change of the threshold voltage of the base semiconductor transistor; FIG. 3 is a block diagram of the display circuit according to the present gamma-based wiper gate; FIG. 4 is a diagram showing the output control pulse according to the first embodiment of the present invention; The timing diagram of the wave and the output clock pulse wave, FIG. 5 is a timing chart of the output control clock pulse wave and the output clock pulse wave according to the second embodiment of the present invention; FIG. 6 is a detailed display! A schematic diagram of the structure of the shift register of the drawing; FIGS. 7 to 17 are schematic views showing the construction of the stages according to the first to eleventh embodiments of the present invention; and FIG. 18 is a view showing the first of FIG. Schematic diagram of the analog waveforms of the pulse wave and the first to fourth output control clock pulses to the fourth output; FIG. 19 is a view showing the positive isotropic pulse wave and the negative isotropic pulse wave relative to the 18th The first waveform of the graph shows the analog waveform of the pulse wave; the 20th figure shows the voltage at the set node and the reset node and the scan pulse and the output clock pulse generated according to the operation of the phase of Fig. 8. 21 is an analog waveform diagram showing the voltage at the set node and the reset node and the voltage of the scan pulse wave and the output clock pulse generated according to the operation of the phase of FIG. 11; Figure 22 is an analog waveform diagram showing the output control clock pulse and output clock pulse provided to the stages of Figs. 13 and 14; Figure 23 is a graph showing the voltage at the set node and the reset node and Scanning pulse generated by the operation of the stage of Figure 1 And an analog waveform diagram of the voltage of the output pulse wave; FIG. 24 is a diagram showing the voltage at the set node and the reset node and the voltage of the scan pulse and the output clock pulse generated according to the operation of the stage of FIG. Figure 25 is an analog waveform diagram showing the voltage at the set node and the reset node and the voltage of the scan pulse and the output clock pulse generated according to the operation of the phase of the πth diagram; An analog waveform diagram of the voltages of the scanning pulse wave and the output clock pulse generated by setting the voltage at the node and the reset node and the operation of the step 37 201239846 according to the diagram of the first diagram; Fig. 27 is a diagram showing Fig. 8 Schematic diagram of a modified structure; Fig. 28 is a schematic view showing a modified structure of Fig. 27; Fig. 29 is a schematic view showing another modified structure of Fig. 27; and Fig. 30 is another modified structure showing Fig. 10 Schematic diagram. [Main component symbol description] C capacitor CG1 first clock generator CG2 second clock generator CN common node CLK output clock pulse i-CLK output control clock pulse OT output terminal Pd pull-down switch device Pu pull-up Switching device Q setting node QB reset node SR shift register ST1 to STh first stage to hth stage SP1 to SPh first scanning pulse wave ~ hth scanning pulse wave Tr1 to Tr8 first switching device - eighth switch Device VDD Charging Voltage VSS Discharge Voltage 38

Claims (1)

201239846 VII. Patent application scope: 1. A gate drive circuit, including: - the first-clock generator's output control when the output n (n is a natural number equal to or greater than 2) has a different number of phases Pulse wave; ^ - second clock generator to create m*n (m is a natural number) with different complex phases of the output wave and the output _ pulse wave in each of its multiple high-peripheral shots The eight parts overlap each other to facilitate arranging the scales m*n (four) pulse waves in a phase sequence, thereby combining the m*n output clock pulses arranged in a phase sequence by η^ elements to generate a group of melons. Each group of the out-of-group has n such output clock pulses, and outputs (four) output pulse waves so as to have -k phase sequences included in each group - output The rising edge of the pulse wave is located in a high cycle of the k-th bit-output control clock pulse wave in the n-transmission pulse pulse wave; and - shifting the temporary storage H to receive from The n-th output of the first-clock generator controls the clock pulse wave and the scale m*n output noise pulse generated from the second impurity H And a few scans. 2. The gate driving circuit according to claim 1, wherein the η output control clock pulses and the m*n output clock pulses each have a plurality of cycles a pulse generated sexually, and a rising edge of a pulse of an output clock pulse included in a group having a -kth phase sequence and belonging to a first (j is a natural number equal to or less than (7)) In a high period of a pulse with a kth phase = column. 3. The gate driving circuit according to claim 2, wherein the 5th m*nth output clock pulse further comprises a dummy pulse, and the virtual pulse has a first output clock The phase of the pulse wave is one of the previous phases, and the starting pulse wave has the same output timing. A gate driving circuit according to claim 2, wherein each of the n output control clock pulses is lower than or equal to the claws at a low period of each of the pulse pulses. Lost 39 201239846 Each of the clock pulses is at a low cycle voltage. 5. The closed-circuit drive according to item 4 of the scope of the patent application: each of the clock pulses is not controlled by the scale pulse. 6. The closed-pole drive according to the scope of claim 5 The circuit, the shift register includes a plurality of stages, in order of the field, each of the - by the squad - the secret = pulse wave, the stage of an output terminal or the transmission of a starting pulse == == 启 or ϊϊ ΐ ΐ η: out of the control clock _ any - an electric - the first ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ ^ Any one of the pulse lines and the p-stage clock stacking period is not related to the output provided to the second switching device. The output is controlled by the control station, and the battery age in the secret is lower than or equal to :ii=:S^; One is supplied to the 201239846. 7. The gate driving circuit according to claim 6 of the patent application, which is 1 or 2. 8. The gate driving circuit of claim 6, wherein the p-stage further comprises: a second switching device that outputs an output pulse wave according to any one of the output clock lines Turning on or off, and when the third switching device is turned on, a charging voltage line that transmits a charging ink is interconnected with a reset node, and a fourth switching device is configured to be applied to the setting node. Turning the voltage on or off, and when the fourth on-position is turned on, interconnecting the reset node with a second discharge voltage line transmitting the second discharge dust, and - pulling down Switching on or off according to a voltage applied to the reset node, and interconnecting the output terminal of the p-stage with a third discharge voltage line transmitting a third discharge voltage when the pull-down switch device is turned on, Both the pull-up switching device and the third switching device are provided with the same output clock pulse. 9. According to the "patent surface 8th torn, one step includes at least one selected from the following devices: 中中-哀PI white domain you and the door = device' according to a self (一+Γ) (Γ a scan pulse of the phase of the natural number ί= ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί ί Interconnecting the reset node with the second discharge electrical discharge voltage line; and the output terminal of the _ρ phase and the third thin ΐ=installation 'based on a first (ps) (s is a natural number) a phase-scanning pulse and when the eighth switching device is turned on, the charging age is set to 10. The closed-circuit driving circuit according to claim 2, wherein the m*n 201239846 outputs Each of the pulse waves at a high cycle voltage is controlled by the voltage of the parent of the pulse wave at a high cycle thereof, or equal to the η output-steps including the sixth term a gate drive circuit of 4, wherein the ρ phase-in-third switch device is based on the pulse from the output Waves are turned on or off, and when the third switching device is turned on, the clock-charge voltage line is interconnected with a common node; and a fourth switching device that transmits a charging voltage is provided. According to the setting to the setting, and when the fourth switching device is turned on, the common node is turned on or off, and the second discharge voltage line is interconnected; the first discharge voltage is first and when the fifth switching device is turned on or Shutdown, inflammation and /, brother - discharge voltage line interconnection; - pull-down switch device 'which is supplied to the reset node, the pull-up and the third switch device are provided with phase_output clock Pulse wave - Step 1 package 2 includes the interpole drive circuit according to item 6 of the patent application scope, and the third stage is opened and closed, and: Ϊ3ΞL is based on the scan pulse wave from the first (ρ_Γ) stage Turning on or off the charging voltage __, __ transmitting - _ pressure one; 'it is turned on or off according to the voltage applied to the setting node, and w and transmitting a tenth opening, according to Applied to the heavy recording pressure to turn off or off, the parallel-down switch device When turned on, interconnecting the output terminal of the p-stage with a third discharge voltage line transmitting a third discharge 42 201239846; and a capacitor connected to the output clock of the pull-up switch device The connection between the line and the reset node. The gate drive circuit according to claim 6, wherein the p-stage further comprises: a second switching device according to the self- (p_s) stage __Scan pulse wave to turn on or off 'and when the first job is turned on' interconnects the set point with a charging voltage line of the transfer-charging voltage; - the fourth switching device, according to the input (four) The (4)-wave of the pulse line is turned on or off, and when the device is turned on, the charging voltage line is interconnected with a reset node; j and ; = ::= 2 are turned on according to the voltage applied to the set node or Turning off, and when the fifth switch device of Tianyuan is turned on, interconnecting the reset node with the second-discharge voltage line of the second-discharge; and the electro-drug (four)-draw-down switch device's according to the electric power applied to the When the pull-down switch device is turned on , the first 启1 is turned on or off and the electric voltage-third discharge voltage ^ Ρ ^ the output terminal and the transmission of a third release of the fourth open _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ - Step 1 The package 4 includes the wheel drive circuit of the item -6, wherein the third stage of the third-to-third switching device is applied according to the first opening or closing, and when the third switching device is opened a voltage of the terminal and a second discharge voltage line of the power-on voltage are interconnected; resetting the defect and transmitting a second discharge-fourth switching device that is turned on or off according to the wave from the turn, and when Any one of the fourth switching device gates is connected to the reset node; the 'starting time' will transmit - the charging voltage - a fifth switching device, according to which is applied to the And when the fifth switching device is turned on, the voltage of the heavy gp point is turned on or off, and the point is interconnected with the second discharging electrical line; and the device is applied to the 43 201239846 and the pull-down device according to Resetting the voltage of the node to be turned on or off, and preparing the pull-down device to open a series, interconnecting a third discharge voltage line of the third discharge voltage, the fourth switching device and the pull-up Switching devices are provided with the same output Pulse wave. 15_ According to the Mizuho circuit described in the sixth paragraph of the patent application, the finding of the p-stage further includes: the first-switching device 'opens according to a charging electric grinder of the self-charging voltage line to connect the charging voltage line And a reset node; - the fourth switching device is turned on or off according to any one of the output clock pulses, and when the four-off device is turned on, the reset node is Transmitting a second discharge voltage line interconnecting a second discharge voltage; and pulling down the switching device to turn on or off according to a voltage applied to the reset node, and when the pull-down switch device is turned on, the p-stage The output terminal is interconnected with a third discharge voltage line that transmits a third discharge voltage, and the fourth switching device and the pull-up switch device are both provided with the same output clock pulse. 16. The gate driving circuit according to claim 6, wherein the step comprises: - a third switching device that is turned on according to a charging voltage from the charging voltage line to connect the charging voltage line with a Resetting the node; - the fourth switching device 'turns on or off according to any one of the output pulse pulses from the output clock line, and when the fourth switching device is turned on, the reset node is Transmitting a second discharge voltage line interconnecting a second discharge voltage; - a fifth switching device that is turned on or off according to a voltage applied to the set throttling, and connecting the reset when the fifth switching device is turned on a node and the second discharge voltage line; and a pull-down switching device that is turned on or off according to a voltage applied to the reset node, and when the pull-down switch device is turned on, the output terminal of the P-stage is transmitted and transmitted A third discharge voltage line of a third discharge voltage is interconnected, and both the fourth switch device and the second switch device are provided with the same output clock pulse. 44 201239846 17. According to the gate drive circuit described in claim 6, the plurality of high periods of the control pulse wave do not overlap each other, wherein the η outputs are pressed to the base 8 The crane circuit, and at least two of the ~ third discharge pairs are smoke. ', the first discharge electric power 19. According to the application of the scope of the second paragraph of the inter-polar drive circuit wave transmission, the bit device includes a plurality of stages 'to sequentially output the complex emperor 5 Hai mother a stage by An output terminal output-scanning pulse wave, pulse 1 η output control clock pulse is controlled by n outputs, the m*n output clock pulses are all transmitted by _ a (four) pulse transmission · A P (P is a natural number) phase consists of: '' or 'off', and when the first-on-off device is turned on, a first (p_q two-stage phase-output terminal or transmit-start pulse start) The transmission line ^ is less than connected, , : : : : ! ί ί ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ ̄ a pulse wave is turned on or off, and when the second switching device is turned on, the transmission-electric voltage line is interconnected with a reset node; - the fourth switching device is turned on or off according to a voltage applied to the set node And when the fourth device is turned on, the reset node is transmitted Transmitting a second discharge voltage line interconnection of the second discharge cake; and a-pull-down device, turning on or _ according to a voltage applied to the reset_, and when the pull-down switch device is turned on, the p The output terminal of the phase is interconnected with a third discharge voltage line that transmits a third discharge voltage, and the pull-up switching device and the third switching device are both provided with the same output clock pulse wave, and the n output Controlling each of the clock pulses at a low period of time is lower than or equal to 45 201239846 equal to, the second discharge and the third discharge voltage, the stage to the first P being provided to the pull-up switch device The first opening of the transmission pulse is provided to the occupational driving circuit described in the second item of the patent application, wherein the = position yn includes a general stage, and the scale is input H ^ a = paragraph Lai By its output terminal output - scan pulse wave = η solid wheel out control pulse pulse wave is transmitted by "output control clock line, work: = = by "clock line transmission, start or close:: when loaded ; the first - its == = stage, the terminal or the first wave of a wave - on Pulling on the device _ device's wire to the same and when the pull-up switch device is turned on, 'turns off any special electric dust of the output clock line, and the output terminal is interconnected; ~ / / In the third stage, the second opening difficulty is recorded from the input (four) scale, and the fourth "device" is applied to the spine secret and when the fourth switch device is turned on, the reset node is transmitted and transmitted. f two discharge voltage line interconnection; and a first-pull-down earning of the electric voltage, the rotation is applied to the reset section = the pull-down setting is turned on, the input of the second job is two = off 2 electric voltage a third discharge voltage line interconnect, the second release of the pull-up switch device and the third switch device are provided with the same output pulse of the pulse pulse is not provided to the first An i i1 wave, a high period overlap of the clock pulse, the output control 46 201239846 〇 11 rounds of the control pulse pulse each of the voltages in a low period is lower than the cloth equal to the first a second discharge voltage and the third discharge voltage, _, s provide a high value of the pulse wave of the output to the (pq)th stage The period overlaps with a high period of the output clock pulse provided to the 兮坌P section, and 6 P provides the output pulse pulse to the upper (four) off device - the rising edge is located at the providing - This output of the switching device controls a high period of the pulse wave. " 21. According to the gate drive circuit of claim 2, wherein the bit temporary storage H comprises a plurality of ·, _ sequentially output a plurality of scanning pulse waves, 5 hai each stage by one The output terminal outputs a scanning pulse wave, and the η output control clock pulses are transmitted by n output control clock lines, and the 111 η output clock pulses of the mode are output by m*n The pulse transmission, a P (P is a natural number) phase includes: a start-off device that opens according to any one of the n output control pulse waves; an output terminal of the UI or a transmission start An initial transmission line of the pulse wave and a set node; and the switching device 'opens or closes according to the setting node, and installs any one of the output clock lines and the p-stage a third switching device that is turned on according to any one of the output clock lines of the self-charging voltage line and the -reset node interconnecting to enable the =four switching device to be applied to the setting node Voltage:; ί: when the switch is turned on, reset the node and transmit - a discharge voltage line interconnection of the second discharge voltage; and an electrical calendar applied to the reset node to turn on or off 'mutually: the first ρ _ the round terminal and the transmission t The three-switch devices are all provided with the same output clock pulse, and the period is not provided with the clear-open __ '47 201239846 in the 嶋-low-level simplification or equal::: period and provided to the first. The rising edge of the pulse wave of the turn-off pulse of the first -== pull-up device is located in a high period of the pulse wave of the output control supplied to the first switching device. 22. The gate driving circuit according to claim 2, wherein the multi-bit temporary storage H comprises a plurality of stages for sequentially outputting a plurality of scanning pulse waves, the mother phase being outputted by the output terminal thereof Output-scanning pulse wave, = one output control clock pulse wave is transmitted by n output control pulse waves, the transmission pulse wave is transmitted by _ one (four) pulse line, one p (P) The stage of the natural number includes: · Secret, Tao ^: When turned on, a (pq) (q is less than p self; white-and-output terminal or a start transmission of a starting pulse wave a day-off device that turns "on" or "off" according to a voltage applied to the set node, and: =^ when starting - any of the output clock lines and the first stage - the third switching device Turning on or off according to any one of the output (four) pulses - and outputting a charging voltage line and interconnecting a charging voltage line with a common node when the third switching device is turned on ; and when 』' it is turned on or off according to the voltage applied to the set node, and ^ When the four-switch device is turned on, the common node is interconnected with a second discharge voltage line; the electric energy $-fifth switching device is turned on according to the voltage applied to the common node, and when the fifth switch When the device is turned on, the charging voltage line is interconnected with a reset node; inside, according to the voltage applied to the set node, the device is turned on and the device is turned on, and when the switch device is turned on, the reset node is a second discharge voltage line interconnection; with 48 201239846 and a pull-down switching device 'which is based on the voltage applied to the reset node and when the pull-down switch device is turned on, the ===: electric voltage of the p-stage The three discharge voltage lines are interconnected, and the second second high-up period is not provided with the first-opening_output_output clock two (four) each--in the low-talking electricity «below the first pull-up switch And the device and the third open device are both financed phase_transmission (four) pulse wave, a high period of the output clock pulse supplied to the (pq) phase and the output clock provided to the first phase a high period of the pulse wave partially overlaps and is supplied to the pull up The rising edge of the pulse wave of the turn-off pulse of the device is located in a high period of the output control clock pulse supplied to the first switching device. 49 4»