201237616 六、發明說明： 【發明所屬之技術領域】 [⑽1]本發明涉及一種訊號測試系統及方法，尤其關於一種串 列週邊設備介面匯流排測試系統及方法。 【先前技術】 [0002] 串列週邊設備介面（Serial Peripheral Interface ’ SPI)匯流排是一種串列同步通訊匯流排。利用該匯流 排’ SPI主設備可以與一個或多個spi從設備以串列方式 進行資料傳輸。 [0003] 為了保證資料傳輸的正確性，需要對SPI匯流排進行測試 。目前’對SPI匯流排的測試需要依靠::作業員的手工操作 ’測試時需要逐一測量SPI匯流排的卷银參數，判斷各個 參數是否符合相關規範。手工操作的測試方法不僅速度 慢、效率低，而且容易出錯，已不能滿足快速高品質生 產的競爭需求。 【發明内容】 [0004] 鑒於以上内容，有必要提供一種串列週邊設備介面（201237616 VI. Description of the Invention: [Technical Field of the Invention] [(10) 1] The present invention relates to a signal testing system and method, and more particularly to a serial peripheral device interface busbar testing system and method. [Prior Art] [0002] A Serial Peripheral Interface (SPI) bus is a serial synchronous communication bus. With this bus ’s SPI master, data can be transferred in tandem with one or more spi slaves. [0003] In order to ensure the correctness of data transmission, the SPI busbar needs to be tested. At present, the test of the SPI busbar relies on: the manual operation of the operator. The test needs to measure the silver parameters of the SPI busbar one by one to determine whether each parameter meets the relevant specifications. Manually-tested test methods are not only slow, inefficient, and error-prone, and are no longer able to meet the competitive needs of fast, high-quality production. SUMMARY OF THE INVENTION [0004] In view of the above, it is necessary to provide a serial peripheral device interface (
Serial Peripheral Interface，SPI)匯流排測試系 統及方法’能夠快速準確地測試串列週邊設備介面匯流 排。 [0005] 100107983 一種SPI匯流排測試系統，所述SPI匯流排包括資料訊號 、時脈訊號及選擇訊號，該系統包括：獲取模組，用於 獲取SPI匯流排的資料訊號、時脈訊號及選擇訊號的波形 :載取模組’用於根據選擇訊號的波形從資料訊號與時 脈訊號的波形中載取資料訊號與時脈訊號的有效波形； 表單編號A0101 第4頁/共20頁 1002013557-0 201237616 ❹ [0006] Ο [0007] 疊加模組，用於以時脈訊號的各個上升沿為基準，向前 及向後各推移指定時間，從資料訊號與時脈訊號的有效 波形中截取各段資料訊號與時脈訊號的有效波形，將截 取的各段資料訊號與時脈訊號的有效波形各自疊加，得 到資料訊號與時脈訊號的眼圖；繪製模組，用於根據SPI 匯流排的技術規範和時脈訊號的眼圖，在資料訊號的眼 圖中繪製資料訊號的規範眼圖；判斷模組’用於判斷疊 加得到的資料訊號的眼圖與繪製的資料訊號的規範眼圖 是否相交，以確定SPI匯流排的資料傳輸是否正常；及輸 出模組，用於輸出所述SPI匯流排的測試結果。 一種SPI匯流棑測試方法，所述SPI匯流排包括資料訊號 、時脈訊號及選擇訊號，該方法包括步驟：獲取SPI匯流 排的資料訊號、時脈訊號及選擇訊號的波形，根據選擇 訊號的波形從資料訊號與時脈訊號的波形中截取資料矾 號與時脈訊號的有效波形；以時脈訊號的各個上升沿為 基準，向前及向後各推移指定時間，從資料訊號與時脈 訊號的有效波形中截取各段資料訊號與時脈訊號的有效 波形，將截取的各段資料訊號與時脈訊號的有效波形各 自疊加，得到資料訊號與時脈訊號的眼圖；根據SPI匯流 排的技術減和時脈訊號的_，在魏訊號的眼圖中 繪製資料訊號的規祕圖；判斷疊加得到的資料訊號的 眼圖與繪製的資料訊號的規範眼圖是否相交，以確定SPI 匯流排的資料傳輸疋否正常；及輸出所述SPI匯流排的測 試結果。 本發明串列週邊設備介面匯流排測試系統及方法，可以 100107983 表單煸號A0101 第5頁/共20頁 1002013557-0 201237616 快速準破地對串列週邊設備介面匯流排實施測試。 【實施方式】 [0008] 參閱圖1所示’係本發明串列週邊設備介面（SeHal Peripheral Interface，SPI )匯流排測試系統較佳實 施例的應用環境示意圖。所述SPI匯流排測試系統1 〇運行 於資料處理設備11 (例如電腦）中。該資料處理設備u 與示波器12及顯示設備1 3通訊連接。示波器1 2透過測試 探頭探測SPI從設備14 (例如EEPROM)的SPI匯流排15 。所述SPI從設備14透過該SPI匯流排15與SPI主設備（ 圖上未畫出）進行資料傳輸。SPI匯流排測試系統10測試 SPI匯流排15 ’以確定SPI從設備14的資料傳輪是否正常 。所述SPI匯流排15包括資料訊號16、時脈訊號17及選 擇訊號18。所述顯示設備13用於顯示SPI匯流排15的測 試結果。 [0009] 參閱圖2所示，係圖1中SPI匯流排測試系統1〇的功能模組 圖。所述SPI匯流排測試系統10包括獲取模組2〇〇、截取 模組210、疊加模組220、繪製模轉230、判斷模組240及 輸出模組250。 [0010] 所述獲取模組200用於獲取SPI匯流排15的資料訊號16、 時脈訊號17及選擇訊號18的波形。在本實施例中，獲取 模組200發送波形捕獲命令給示波器12。根據該波形捕獲 命令’示波器12捕獲SPI匯流排15的資料訊號16、時脈 訊號17及選擇訊號18的波形，並將捕獲的資料訊號16、 時脈訊號17及選擇訊號18的波形返回資料處理設備11。 如圖4所示’ 40為SPI匯流排15的資料訊號16的波形，41 100107983 表單編號A0101 第6頁/共20頁 1002013557-0 201237616 為時脈訊號17的波形，42為選擇訊號18的波形。 [〇〇11] 所述戴取模組210用於根據選擇訊號18的波形從資料訊號 16與時脈訊號17的波形中戴取資料訊號16與時脈訊號17 的有效波形。需要說明的是，僅當選擇訊號18有效時， 資料訊號16傳送有效資料。選擇訊號18保持有效所對應 的資料訊號16與時脈訊號17的波形即為資料訊號16與時 脈訊號17的有效波形》在本實施例中，所述選擇訊號18 低電平有效，載取模組210從選擇訊號18的波形中確定選 Ο 擇訊號18為低電平的起始時間及終止時間，以該起始時 間與該終止時間作為資料訊號丨6與_脈訊號丨7的有效波 形的起始時間與終止時間，從獲取的資料訊號16與時脈 訊號17的波形中截取資料訊號16與時脈訊號17的有效波 形。如圖4所示，截取模組21〇截取的資料訊號16與時脈 訊號17的有效波形的起始時間是τ〇，終止時間是n。 [〇〇12]所述疊加模組220用於以時脈訊號17的各個上升沿為基準 向别及向後各推移指定時間，從資料訊號16與時脈訊 〇 號17的有效波形中截取各段資料訊號16與時脈訊號17的 有效波形，並將截取的各段資料訊號16與時脈訊號的 有效波形各自疊加，得到資料訊號丨6與時脈訊號丨7的眼 圖。在本實施例中，疊加模組22〇以時脈訊號17的各個上 升沿為基準，向前及向後各推移二分之一時脈訊號週期 來截取各段資料訊號16與時脈訊號17的有效波形。如圖4 所示，43為截取的一段資料訊號16與時脈訊號17的有效 波形。需要說明的是，為了克服抖動的影響，可以以時 脈訊號17的各個上升沿為基準，向前及向後各推移略大 100107983 表單編號A0101 第7頁/共20頁 1002013557-0 201237616 於一分之一（例如八分之五）時脈訊號週期來截取各段 資料訊號16與時脈訊號17的有效波形。如圖5所示，5〇為 疊加得到的資料訊號16的眼圖，51為疊加得到的時脈訊 號17的眼圖。 [0013] [0014] 所述繪製模組230用於根據SPI匯流排15的技術規範和時 脈Λ波1 7的眼圖，在貧料訊號1 6的眼圖中、纟會製資料吼楚 16的規範眼圖。在本實施例中，依據的spi匯流排15的技 術規範包括資料訊號16的建立時間規範值、保持時間規 範值'、高電壓規範值、低電壓規範值、上升時間規範值 及下降時間規範值。如圖5所示，52係繪製的資料訊號j 6 的規範眼圖，該規範眼圖以時脈訊號17的眼'圖的上升沿 為基準，由SPI匯流排15的資料訊號16的建立時間規範值 53、保持時間規範值54、高電壓規範值55、低電壓規範 值56、上升時間規範值57及下降時間規範值58而確定。 所述判斷模組2 4 0用於判斷疊加得到的資料訊號1 6的眼圖 與繪製的 > 料说说1 6的規範..跟爾是否相交，以確定ς p I匯 流排15的資料傳輸是否正常。若疊加得到的資料訊號16 的眼圖與繪製的資料訊號16的規範眼圖不相交，則SPI匯 流排15的資料傳輸正常。否則，若疊加得到的資料訊號 1 6的眼圖與續·製的資料訊號16的規範眼圖相交，則Sp j匯 流排15的資料傳輸異常。 所述輸出模組2 50用於輸出所述sp ί匯流排丨5的測試結果 。在本實施例中，輸出模組250將SPI匯流排15的測試結 果顯示在與資料處理設備u相連的顯示設備13上。 100107983 表單編號A0101 第8頁/共20頁 1002013557-0 [0015] 201237616 [0016] [0017] Ο [0018] Ο 參閱圖3所示’係本發明SPI匯流排測試方法較佳實施例 的流程圖。 步驟S301 ’獲取模組2〇〇獲取spi匯流排15的資料訊鱿16 、時脈訊號17及選擇訊號18的波形。在本實施例中，獲 取模組200發送波形捕獲命令給示波器12。根據該波形捕 獲命令’示波器12捕獲SPI匯流排15的資料訊號16、時 脈訊號17及選擇訊號18的波形，並將捕獲的資料訊號16 、時脈訊號17及選擇訊號18的波形返回資料處理設備^ 。如圖4所示，4〇為SPI匯流排15的資料訊號16的波形， 41為時脈訊號Π的波形，42為選擇訊緣18的波形。 步驟S302，戴取模組21〇根據選擇訊鐃18的波形從資科 訊號16與時脈訊號17的波形中截取資料訊號16與時脈訊 號1*7的有效波形。需要說明的是，僅當選擇訊號18有致 時，資料訊號16傳送有效資料。選擇訊號18保持有欵所 對應的資料訊號16與時脈訊號17的波形即為資料訊鱿16 與時脈訊號17的有效波形。在本實施例中，所述選擇吨 號18低電平有效，截取模組21〇從選擇訊號丨8的波形中確 定選擇訊號18為低電平的起始時間及終止時間，以該起 始時間與該終止時間作為資料訊號丨6與時脈訊號丨7的有 效波形的起始時間與終止時間，從獲取的資料訊號16與 時脈訊號17的波形令截取資料訊號丨6與時脈訊號17的有 效波形。如圖4所示，截取模組21〇截取的資料訊號16與 時脈訊號17的有效波形的起始時間是Τ0，終止時間是T1 [0019] 100107983 步驟S303，疊加模組220以時脈訊號17的各個上升沿為 表單編號A0101 第9頁/共20頁 1002013557-0 201237616 基準’向前及向後各推移指定時間，從資料訊號16與時 脈訊號17的有效波形中載取各段資料訊號16與時脈訊號 17的有效波形，並將截取的各段資料訊號丨6與時脈訊號 17的有效波形各自疊加，得到資料訊號16與時脈訊號17 的眼圖。在本實施例中，疊加模組2 2 〇以時脈訊號17的各 個上升沿為基準，向前及向後各推移二分之一時脈訊號 週期來截取各段資料訊號16與時脈訊號丨7的有致波形。 如圖4所不，43為截取的一段資料訊號16與時脈訊號I?的 有效波形。需料明的是，為了克服抖動的影響，;以' 以時脈訊號17的各個土升礙為基準，向前及向後各推移 略大於—分之例如八分之五）時脈訊號週期來截取 各段資料訊號16與時脈訊號Π的有效波形。如圖5所示， 50為疊加得到的資料訊號16的眼圖，51為疊加得到的時 脈訊號17的眼圖。 [0020] 步驟s3G4 ’緣製模組23,據SPI匯流排15的技術規範和 時脈訊號17的眼圖’在資料訊號16的眼圖中緣製資料訊 號16的規範眼圖。在本實施婦中’依據的則匯流排⑽ 技術規範包括資料訊號16的建立時間規範值、保持時間 規範值、高電壓規範值、低電壓規範值、上升時間規範 52為繪製的資料訊號 值及下降時間規範值。如圖5所示， 16的規範眼圖，該規範眼圖以時脈訊號17的眼圖的上升 沿為基準，由SPI匯流排15的資料訊號16的建立時間規範 值53、保持時間規範值54、高電壓規範值55、低電壓規 範值56、上升❹ 1規隸57及下降，規範⑽而確定 100107983 表單編號A0101 第10頁/共20頁 1002 201237616 [0021] 步驟S305，判斷模組240判斷疊加得到的資料訊號16的 眼圖與繪製的資料訊號16的規範眼圖是否相交，以確定 SPI匯流排15的資料傳輸是否正常。若疊加得到的資料訊 號16的眼圖與繪製的資料訊號16的規範眼圖不相交，則 SPI匯流排15的資料傳輸正常。否則，若疊加得到的資料 訊號16的眼圖與繪製的資料訊號16的規範眼圖相交，則 SPI匯流排15的資料傳輸異常。 [0022] 步驟S306，輸出模組250輸出所述SPI匯流排15的測試結 果。在本實施例中，輸出模組250將SPI匯流排15的測試 Ο 結果顯示在與資料處理設備11相連的顯示設備13上。 [0023] 綜上所述，本發明符合發明專利要件，爰依法提出專利 申請。惟，以上所述者僅為本發明之較佳實施例，本發 明之範圍並不以上述實施例為限，舉凡熟悉本案技藝之 人士援依本發明之精神所作之等效修飾或變化，皆應涵 蓋於以下申請專利範圍内。 【圖式簡單說明】 〇 [0024] 圖1係本發明串列週邊設備介面（Ser ial Per ipheral I nter f ace，SPI )匯流排測試系統較佳實施例的應用環 境示意圖 [0025] 圖2係圖1中SPI匯流排測試系統的功能模組圖。 [0026] 圖3係本發明SPI匯流排測試方法較佳實施例的流程圖。 [0027] 圖4係SPI匯流排的資料訊號、時脈訊號及選擇訊號的波 形圖。 [0028] 圖5係疊加得到的資料訊號與時脈訊號的眼圖，以及繪製 100107983 表單編號 A0101 第 11 頁/共 20 頁 1002013557-0 201237616 的資料訊號的規範眼圖。 【主要元件符號說明】 [0029] SPI匯流排測試系統：10 [0030] 資料處理設備：11 [0031] 示波器：1 2 [0032] 顯示設備： 13 [0033] SPI從設備 :14 [0034] SPI匯流排 ：15 [0035] 資料訊號： 16 [0036] 時脈訊號： 17 [0037] 選擇訊號： 18 [0038] 獲取模組： 200 [0039] 截取模組： 210 [0040] 疊加模組： 220 [0041] 繪製模組： 230 [0042] 判斷模組： 240 [0043] 輸出模組： 250 100107983 表單編號A0101 第12頁/共20頁 1002013557-0The Serial Peripheral Interface (SPI) bus test system and method' is capable of quickly and accurately testing the serial peripheral interface bus. [0005] 100107983 A SPI bus test system, the SPI bus includes a data signal, a clock signal, and a selection signal. The system includes: an acquisition module, configured to acquire a data signal, a clock signal, and a selection of the SPI bus The waveform of the signal: the loading module 'is used to capture the effective waveform of the data signal and the clock signal from the waveform of the data signal and the clock signal according to the waveform of the selection signal; Form No. A0101 Page 4 / Total 20 pages 1002013557- 0 201237616 ❹ [0006] Ο [0007] The overlay module is used to reference the rising edges of the clock signal, forward and backward for each specified time, and intercept the segments from the effective waveforms of the data signal and the clock signal. The effective waveform of the data signal and the clock signal superimposes the intercepted data signals and the effective waveforms of the clock signals to obtain the eye signals of the data signals and the clock signals; and the drawing module for the technology according to the SPI bus The eye diagram of the specification and the clock signal, the specification eye diagram of the data signal is drawn in the eye diagram of the data signal; the judgment module 'is used to judge the eye diagram of the superimposed data signal Whether the specification eye diagram of the drawn data signal intersects to determine whether the data transmission of the SPI bus is normal; and the output module is configured to output the test result of the SPI bus. A method for testing a SPI bus, the SPI bus includes a data signal, a clock signal, and a selection signal. The method includes the steps of: acquiring a data signal, a clock signal, and a waveform of the selection signal of the SPI bus, according to the waveform of the selection signal. Intercepting the effective waveforms of the data nickname and clock signal from the waveforms of the data signal and the clock signal; using the rising edges of the clock signal as the reference, shifting forward and backward for a specified time, from the data signal to the clock signal In the effective waveform, the effective waveforms of each segment of the data signal and the clock signal are intercepted, and the intercepted data signals of each segment and the effective waveform of the clock signal are superimposed to obtain an eye diagram of the data signal and the clock signal; according to the technology of the SPI bus Subtracting the clock signal _, drawing a rule map of the data signal in the eye diagram of the Wei signal; judging whether the eye pattern of the superimposed data signal intersects with the standard eye diagram of the drawn data signal to determine the SPI busbar Whether the data transmission is normal; and outputting the test result of the SPI bus. The system and method for testing the interface bus of the serial peripheral device of the present invention can be tested in the form of a serial peripheral device busbar with a rapid quasi-breaking ground 100107983 form number A0101 page 5 / total 20 pages 1002013557-0 201237616. [Embodiment] [0008] Referring to Figure 1 is a schematic diagram of an application environment of a preferred embodiment of a SeHal Peripheral Interface (SPI) busbar test system of the present invention. The SPI bus test system 1 is operated in a data processing device 11 (e.g., a computer). The data processing device u is communicatively coupled to the oscilloscope 12 and the display device 13. The oscilloscope 1 2 probes the SPI bus 15 of the SPI slave device 14 (eg, EEPROM) through the test probe. The SPI slave device 14 transmits data to the SPI master device (not shown) through the SPI bus bar 15. The SPI busbar test system 10 tests the SPI busbar 15' to determine if the data path of the SPI slave device 14 is normal. The SPI bus 15 includes a data signal 16, a clock signal 17, and a selection signal 18. The display device 13 is used to display the test result of the SPI bus. [0009] Referring to FIG. 2, it is a functional module diagram of the SPI busbar test system in FIG. The SPI bus test system 10 includes an acquisition module 2, an intercept module 210, a superposition module 220, a rendering module 230, a determination module 240, and an output module 250. The acquisition module 200 is configured to acquire waveforms of the data signal 16, the clock signal 17, and the selection signal 18 of the SPI bus 15 . In the present embodiment, the acquisition module 200 sends a waveform capture command to the oscilloscope 12. According to the waveform capture command, the oscilloscope 12 captures the waveforms of the data signal 16, the clock signal 17 and the selection signal 18 of the SPI bus 15, and returns the waveforms of the captured data signal 16, the clock signal 17 and the selection signal 18 to the data processing. Device 11. As shown in Fig. 4, '40 is the waveform of the data signal 16 of the SPI busbar 15, 41 100107983, the form number A0101, the sixth page, the total 20 pages, 1002013557-0 201237616, the waveform of the clock signal 17, and the waveform of the selection signal 18 . [11] The wearing module 210 is configured to capture the effective waveforms of the data signal 16 and the clock signal 17 from the waveforms of the data signal 16 and the clock signal 17 according to the waveform of the selection signal 18. It should be noted that the data signal 16 transmits valid data only when the selection signal 18 is valid. In the present embodiment, the selection signal 18 is active low, and the waveform of the data signal 16 and the clock signal 17 corresponding to the selection signal 18 remains valid. The module 210 determines, from the waveform of the selection signal 18, the start time and the end time of the selection signal 18 being low, and the start time and the end time are valid as the data signal 丨6 and the _ pulse signal 丨7. The start time and the end time of the waveform are used to intercept the effective waveforms of the data signal 16 and the clock signal 17 from the acquired waveforms of the data signal 16 and the clock signal 17. As shown in FIG. 4, the start time of the effective waveforms of the data signal 16 and the clock signal 17 intercepted by the intercepting module 21 is τ 〇, and the end time is n. [〇〇12] The superimposing module 220 is configured to take a time corresponding to each of the rising edges of the clock signal 17 and to shift back from the effective waveforms of the data signal 16 and the clock signal 17 The effective waveforms of the segment data signal 16 and the clock signal 17 are superimposed on each of the intercepted data signals 16 and the effective waveforms of the clock signals to obtain eye patterns of the data signal 丨6 and the clock signal 丨7. In this embodiment, the superimposing module 22 uses the rising edges of the clock signal 17 as a reference, and shifts the data signal 16 and the clock signal 17 of each segment forward and backward by one-half clock signal period. Effective waveform. As shown in FIG. 4, 43 is an effective waveform of the intercepted data signal 16 and the clock signal 17. It should be noted that, in order to overcome the influence of the jitter, the rising edge of the clock signal 17 can be used as a reference, and the forward and backward directions are slightly larger. 100107983 Form No. A0101 Page 7 / Total 20 pages 1002013557-0 201237616 One (for example, five-eighths) clock signal period intercepts the valid waveforms of each segment of data signal 16 and clock signal 17. As shown in Fig. 5, 5〇 is an eye diagram of the superimposed data signal 16, and 51 is an eye diagram of the superimposed clock signal 17. [0014] The drawing module 230 is configured to perform the data according to the technical specifications of the SPI bus 15 and the eye diagram of the clock pulse 17 in the eye diagram of the poor signal 16. The standard eye diagram of 16. In this embodiment, the technical specification of the spi bus 15 includes the establishment time specification value of the data signal 16, the retention time specification value, the high voltage specification value, the low voltage specification value, the rise time specification value, and the fall time specification value. . As shown in FIG. 5, the specification eye diagram of the data signal j 6 drawn by the 52 series is based on the rising edge of the eye diagram of the clock signal 17, and the setup time of the data signal 16 by the SPI bus 15 is as shown. The specification value 53, the hold time specification value 54, the high voltage specification value 55, the low voltage specification value 56, the rise time specification value 57, and the fall time specification value 58 are determined. The judging module 2400 is configured to determine the eye pattern of the superimposed data signal 16 and the drawing of the material. The specification of the 16: whether or not the intersection intersects to determine the data of the ς p I bus 15 Whether the transmission is normal. If the eye pattern of the superimposed data signal 16 does not intersect with the normalized eye pattern of the drawn data signal 16, the data transmission of the SPI bus 15 is normal. Otherwise, if the eye pattern of the superimposed data signal 16 intersects with the speculative eye pattern of the continuous data signal 16, the data transmission of the Sp j bus 15 is abnormal. The output module 205 is configured to output a test result of the sp 汇 bus bar 丨5. In the present embodiment, the output module 250 displays the test result of the SPI bus 15 on the display device 13 connected to the data processing device u. 100107983 Form No. A0101 Page 8 / Total 20 Pages 1002013557-0 [0015] [0016] [0018] 参阅 Refer to FIG. 3 is a flow chart of a preferred embodiment of the SPI busbar test method of the present invention. . Step S301, the acquisition module 2 obtains the waveforms of the data channel 16, the clock signal 17, and the selection signal 18 of the spi bus 15 . In the present embodiment, the acquisition module 200 sends a waveform capture command to the oscilloscope 12. According to the waveform capture command, the oscilloscope 12 captures the waveforms of the data signal 16, the clock signal 17 and the selection signal 18 of the SPI bus 15, and returns the waveforms of the captured data signal 16, the clock signal 17, and the selection signal 18 to the data processing. Device ^. As shown in FIG. 4, 4 is the waveform of the data signal 16 of the SPI bus 15, 41 is the waveform of the clock signal ,, and 42 is the waveform of the selected edge 18. In step S302, the wearing module 21 intercepts the effective waveforms of the data signal 16 and the clock signal 1*7 from the waveforms of the credit signal 16 and the clock signal 17 according to the waveform of the selection signal 18. It should be noted that the data signal 16 transmits valid data only when the selection signal 18 is available. The waveform of the data signal 16 and the clock signal 17 corresponding to the selection signal 18 is the effective waveform of the data signal 16 and the clock signal 17. In this embodiment, the selection of the tonnage 18 is active low, and the intercepting module 21 determines the start time and the end time of the selection signal 18 from the waveform of the selection signal 丨8 to the start. The time and the end time are used as the start time and the end time of the effective waveform of the data signal 丨6 and the clock signal 丨7, and the data signal 丨6 and the clock signal are intercepted from the acquired waveforms of the data signal 16 and the clock signal 17 17 effective waveform. As shown in FIG. 4, the start time of the effective waveforms of the data signal 16 and the clock signal 17 intercepted by the intercepting module 21 is Τ0, the end time is T1 [0019] 100107983, step S303, and the superimposing module 220 uses the clock signal. The rising edge of 17 is the form number A0101. Page 9/20 pages 1002013557-0 201237616 The benchmark 'specified time for each forward and backward shift, and the data signals of each segment are taken from the effective waveforms of the data signal 16 and the clock signal 17 The effective waveform of 16 and the clock signal 17 is superimposed on each of the intercepted data signals 丨6 and the effective waveform of the clock signal 17 to obtain an eye pattern of the data signal 16 and the clock signal 17. In this embodiment, the superimposing module 2 2 uses the rising edges of the clock signal 17 as a reference, and shifts each segment of the data signal 16 and the clock signal by one-half clock signal period forward and backward. 7 has a waveform. As shown in Fig. 4, 43 is an effective waveform of a piece of data signal 16 and clock signal I? It should be noted that, in order to overcome the influence of the jitter, the clock signal period is based on the fluctuation of each soil of the signal signal 17 and the forward and backward movements are slightly larger than - for example, five-eighths of the time. Intercept the effective waveform of each segment of data signal 16 and clock signal Π. As shown in Fig. 5, 50 is an eye diagram of the superimposed data signal 16, and 51 is an eye diagram of the superimposed clock signal 17. [0020] Step s3G4 ‘edge module 23, according to the technical specification of SPI bus 15 and the eye diagram of clock signal 17, the standard eye pattern of data signal 16 is formed in the eye diagram of data signal 16. In this implementation, the technical specification of the busbar (10) includes the establishment time specification value, the retention time specification value, the high voltage specification value, the low voltage specification value, and the rise time specification 52 of the data signal 16 as the data signal value and the drop. Time specification value. As shown in FIG. 5, the specification eye diagram of 16 is based on the rising edge of the eye diagram of the clock signal 17, and the setup time specification value 53 and the retention time specification value of the data signal 16 of the SPI bus 15 are used. 54. High voltage specification value 55, low voltage specification value 56, rising ❹ 1 specification 57 and falling, specification (10) and determination 100107983 Form number A0101 Page 10 / Total 20 pages 1002 201237616 [0021] Step S305, determining module 240 It is judged whether the eye pattern of the superimposed data signal 16 and the normalized eye pattern of the drawn data signal 16 intersect to determine whether the data transmission of the SPI bus 15 is normal. If the eye pattern of the superimposed data signal 16 does not intersect with the normalized eye pattern of the drawn data signal 16, the data transmission of the SPI bus 15 is normal. Otherwise, if the eye pattern of the superimposed data signal 16 intersects with the normalized eye diagram of the drawn data signal 16, the data transmission of the SPI bus 15 is abnormal. [0022] Step S306, the output module 250 outputs the test result of the SPI bus bar 15. In the present embodiment, the output module 250 displays the test Ο result of the SPI bus 15 on the display device 13 connected to the data processing device 11. [0023] In summary, the present invention complies with the requirements of the invention patent, and submits a patent application according to law. The above is only the preferred embodiment of the present invention, and the scope of the present invention is not limited to the above-described embodiments, and equivalent modifications or variations made by those skilled in the art in light of the spirit of the present invention are It should be covered by the following patent application. BRIEF DESCRIPTION OF THE DRAWINGS [0024] FIG. 1 is a schematic diagram of an application environment of a preferred embodiment of a Serial Peripheral Interface (SPI) busbar test system of the present invention [0025] FIG. Figure 1 shows the functional block diagram of the SPI busbar test system. 3 is a flow chart of a preferred embodiment of the SPI busbar testing method of the present invention. [0027] FIG. 4 is a waveform diagram of a data signal, a clock signal, and a selection signal of the SPI bus. [0028] FIG. 5 is an eye diagram of the data signal and the clock signal superimposed, and a standard eye diagram of the data signal of 100107983 Form No. A0101, Page 11 of 20 1002013557-0 201237616. [Main component symbol description] [0029] SPI busbar test system: 10 [0030] Data processing device: 11 [0031] Oscilloscope: 1 2 [0032] Display device: 13 [0033] SPI slave device: 14 [0034] SPI Busbar: 15 [0035] Information signal: 16 [0036] Clock signal: 17 [0037] Select signal: 18 [0038] Get module: 200 [0039] Intercept module: 210 [0040] Overlay module: 220 [0041] Drawing module: 230 [0042] Judging module: 240 [0043] Output module: 250 100107983 Form number A0101 Page 12 / Total 20 pages 1002013557-0