TW201236108A - Reduced number of masks for IC device with stacked contact levels - Google Patents

Abstract

A three-dimensional stacked IC device has a stack of contact levels at an interconnect region. According to some examples of the present invention, it only requires Y masks to provide access to a landing area at 2<SP>Y</SP> contact levels. According to some examples 2<SP>x-1</SP> contact levels are etched for each mask sequence number x.

Description

201236108

i vv /v/urvA VI. Description of the Invention: Field of the Invention The present invention relates generally to a high-density integrated circuit device, and more particularly to an interconnect structure for a multilayer three-dimensional stacked device. [Prior Art] [0002] In the manufacture of a high-density memory device, the amount of data per unit area on an integrated circuit can be a key factor. Therefore, when the critical dimensions of the memory φ device reach the limits of lithography, techniques for stacking multi-layer memory cells have been proposed in order to achieve higher storage density and lower cost per bit. [0003] For example, in Lai et al., "A Multi-Layer Stackable Thin-Film Transistor (TFT) NAND-Type Flash Memory," IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006, and Jung "Three Dimensionally Stacked NAND Flash Memory Technology Using Stacking Single $ Crystal Si Layers on ILD and TANOS Structure for Beyond 30nm Node", IEEE Int'l Electron Devices Meeting, 11-13 Dec. 2006, Thin Film Transistor The technology is applied to charge trapping memory. [0004] Meanwhile, in "The 512-Mb PROM With a Three-Dimensional Array of Diode/Anti-fuse Memory Cells" by Johnson et al., IEEE J. of Solid-State Circuits, vol. 38, no. 11, Nov. In the 2003 document, cross-point array technology has been applied to anti-fuse memory. Also refer to the title of Cleeves as 201236108

TW7070PA "Three-Dimensional Memory", US Patent No. 7,081,377. [0005] Literature of Kim et al., "Novel 3-D Structure for Ultra-High Density Flash Memory with VRAT and PIPE**, 2008 Symposium on VLSI Technology Digest of Technical Papers; 17-19 June 2008; pages 122-123 Another structure for providing a vertical NAND cell in a charge trapping memory technology is described. [0006] In a three-dimensional stacked memory device, an electrical conductor penetrates a higher layer of a memory cell for use in memory The lower layers of the body unit are coupled to the decoding circuit and its similar circuitry. The cost of completing the interconnection increases with the number of lithographic steps required. Tanaka et al., "Bit Cost Scalable Technology with Punch and Plug Process for Ultra High

Density Flash Memory", 2007 Symposium on VLSI

A method of reducing the number of lithographic steps is described in the literature of Technology Digest of Technical Papers; 12-14 June 2007, pages: 14-15. [0007] However, one of the disadvantages of the conventional three-dimensional stacked memory device is that a separate mask is typically used for each contact layer. Thus, for example, if there are 20 contact layers, typically 20 distinct masks are required, each of which requires the creation of a mask for the contact layer and an etching step for the contact layer. SUMMARY OF THE INVENTION [0008] According to some examples of the invention, only γ masks are required, with 201236108 1 vv a v / urn providing access to the landing area of the Y-th contact layer located at 2. According to some examples, for each mask sequence number X, 2 (X _1 ) contact layers can be etched.

A first example of a method for use in a three-dimensional stacked 1C device having interconnected regions of a contact layer to create interconnected contact regions that are aligned with landing regions of the contact layer and exposed to landing regions of the contact layer. A combination of N etch masks is used to create a contact layer of up to and including 2 N-th interconnect contact regions with a stack of contact layers. Each mask includes a masked area φ domain and an etched area. N is an integer at least equal to two. X is the sequence number used for the mask so that one of the masks has X equal to 1 and the other mask has X equal to 2, and then until X is equal to N. At least a portion of any upper layer that is disposed over the interconnect region above the stack of contact layers is removed. The mask is used to etch the interconnect region N times in the selected order. This results in a contact opening extending from the surface layer to each of the contact layers, and in each of the N-th contact layers of 2, the contact opening is aligned with the landing area and provides access to the landing area. For each mask of sequence number X during the etching step, φ etches 2 (X-1) power contacts. At this time, an electrical conductor passing through the contact opening can be formed to contact the landing region located at the contact layer. Some examples include the steps of: coating a fill material over the contact opening to define a via patterned surface; opening a via through the fill material, exposing the landing area in each contact layer; A conductive material is deposited in the pores. In some examples, the access step is performed by N being at least equal to four. In some examples, the removal step is performed using an additional mask of the exposed interconnect region, while in other examples, the removal step is performed by using a carpet etch step for the interconnect region. In some examples, the sidewall material acts as N 201236108

One of the TW7070PA #刻遮罩. [0010] Another example of a method for three-dimensionally stacking 1C devices is to provide a power connection to electrically connect to a landing region of a stack of contact layers located in the interconnect region. The 1C device is of a type including an interconnect region comprising an upper layer and a stack of at least first, second, third and fourth contact layers below the upper layer. At least first and second openings are formed in the upper layer, each of the openings exposing a surface area of the first contact layer, and the first and second openings are partially bordered by the upper side walls. Depositing sidewall material on the sidewalls of each of the first and second openings, and at the first portion of each portion of the surface portion, and retaining the second portion of the surface portion such that there is no second portion Side wall material. Extending the first and second openings through the second portion of the surface portion to expose the surface of the second contact layer for each of the first and second openings. At least some of the sidewall material is removed from each opening to expose at least some of the first portion of the surface portion of each opening to form an interconnect contact region in the second opening. The interconnect contact regions of the second opening are aligned with the landing regions of the first and second contact layers. Further extending from the first portion exposed by the (1) surface portion, the first opening penetrates the first and second contact layers, exposes the surface of the third contact layer, and further extends from the surface exposed by the (2) second contact layer The extended first opening penetrates the second and third contact layers to expose the surface of the fourth contact layer. This will form an interconnect contact area with the landing areas of the third and fourth contact layers at the first opening. An electrical conductor electrically connected to the landing regions of the first, second, third, and fourth contact layers is formed. In some examples, the electrical conductor forming step includes: applying a filling material over the opening to define a through-hole patterned surface; opening a through-hole through the filling material, exposing the landing in each contact layer 201236108 1 vy i \j /\jrt\ area; and depositing conductive material in the via. [0011] An example of a mask combination for three-dimensionally stacking 1C devices to create interconnected contact regions that are aligned with landing regions of the interconnected regions of the interconnected regions, with upper cover contacts Stacking of layers. Each of the N etch mask combinations includes a masking region and an etched region for arranging up to 2 (N-1) power contacts for the 3D stack 1C in the interconnect region The layer creates an interconnected contact area that can be aligned with the landing area. N is an integer at least equal to 3, and X is φ for the sequence number of the mask such that one of the masks has X equal to 1, and the other mask has X equal to 2, and then until X is equal to N. In some examples, the sidewall material acts as one of the N surname masks. In some examples, the etch mask includes a dummy masking region on at least one of the masks of the etch mask. In some examples, the #etch mask includes a virtual masking region at a corresponding location on at least some of the masks of the etch mask. In some examples, the surname mask includes at least one virtual masking region at a corresponding location on each mask of the money mask. In some examples, N is greater than or equal to 4. [0012] Another example of a mask combination is for three-dimensionally stacking 1C devices to create interconnected contact regions that are aligned with landing regions of the interconnected regions of the stack of contact layers. Each of the N mask combinations includes a masking area and an etched area for generating energy and landing for a three-dimensional stacked 1C device in the interconnected area up to and including 2 N-th contact layers Area-aligned interconnect contact area. N is an integer at least equal to 2, and X is the sequence number used for the mask such that one of the masks has X equal to 1, and the other mask has X equal to 2, and then until X is equal to N. 201236108 '

TW7070PA

Other embodiments and advantages of the present invention can be seen by reviewing the following drawings, detailed description and claims. Embodiments [0044] FIG. 1 is a cross-sectional view of a device including a three-dimensional structure having an interconnect structure 19〇. The interconnect structure has a small footprint (f〇〇tprint), and the small occupied region, the electrical conductor 18〇 extends to different contact layers 160-1 to 160-4 in the device. In the example shown, four contact layers are shown to 160-4. In general, the small interconnect structure described herein can be implemented in a structure having layers 0 through N and N at least 2. [0045] The electrical conductors 180 are disposed within the interconnect structure 19A to contact the landing regions on the different contact layers 160-1 through 160-4. As described in detail below, the conductors 18 for each particular layer extend through openings in the layer lying above, with landing areas 16Ma, 1611b, 161_2a, 161_2b, 161-3a, 161-3b , 161-4 contact. Conductor 180 is used in this example for engaging contact contact layers i6〇_i to i6〇_4 to interconnect lines 185 that are lying in the wire layers above contact layers 16〇1 to 160-4. . [0046] The landing area is a portion of the contact layers 160-1 to 160-4 for contact with the conductor ι8. The size of the landing zone is large enough to provide space for the electrical conductor 180 to be sufficient to couple the electrically conductive landing zone in the landing zone of the different contact layers to 160-4 to the interconnecting line 185' lying above. The problem is that the conductors 180 for the landing area in the different layers and the openings lying above one of the layers are not aligned. [0047] The size of the drop zone is therefore dependent on several factors, including the size and number of conductors used by 201236108 1 W f\J/\jrj\, and will vary from embodiment to embodiment. In addition, the number of electrical conductors 180 can vary from the number of landing zones. [0048] In the illustrated example, the contact layers 160-1 to 160_4 are composed of respective planar conductive layers of materials, such as doped polysilicon, wherein the separation contact layer (9) "to 16" 4 The insulating material layer 曰曰165. Alternatively, the contact layer purchased to 16〇_4 does not need to be a planar stacked two material layer, but instead replaces a material layer which can be different along the vertical dimension. [0049] and the different contact layer 16 (The conductors 180' of the M to 16 〇_4 contacts are arranged in a direction extending along the cross section shown in Fig. 1A. ^ The conductors (10) in contact with the dissimilar contact layers 16G-1 to 16G-4 The direction in which the arrangement is defined is referred to herein as the "longitudinal" direction. The "lateral" direction is perpendicular to the longitudinal direction 'and is the direction of the paper feed surface and the paper exit surface along the cross section shown in Figure 1A. Both the longitudinal and lateral directions They are all considered to be "lateral dimensions", meaning that the contact layer 16〇1 to 16〇4 is flat = the direction in the dimension region. The "length" of the structure or feature is the length of the vertical direction = And the "width" of the structure or feature is in the lateral direction [0050] the contact layer woq is complex The lowest contact layer of the contact layer 16〇_ι to 1. The contact layer WO·! is located above the insulating layer 164. [〇〇51] Contact | 16G_1 includes a contact with the conductor (10) and a second landing area 161-la, i61_lb. 160-1 is 161-la, 161-lb of the interconnect structure 19〇. [0052] In FIG. 1, the opposite end portions of the contact layer include two landing areas 201236108

In another embodiment of the TW7070PA, the landing areas 161-1a, 161-1b are omitted - [0053] FIG. 2A illustrates the landing area 161-la, 161-1b in the occupied area of the interconnect structure 190. A plan view of the contact layer 160-1. The occupied area of the interconnect structure 190 can be close to the width of the via size for the electrical conductor and has a length that can be much longer than this width. As shown in Fig. 2A, the landing area 161-la has a width 200 in the lateral direction and a length 201 in the longitudinal direction. The landing area 161-1b has a width 202 in the lateral direction and a length 203 in the longitudinal direction. In the embodiment of Fig. 2A, the landing areas 161-1a, 161-1b each have a rectangular cross section. In an embodiment, the landing zones 161-1a, 161-1b can each have a circular, elliptical, square, rectangular or somewhat irregular profile. [0054] Since the contact layer 160-1 is the lowest contact layer, the conductor 180 does not need to penetrate the contact layer 160-1 to the layer disposed below. Thus, in this example, contact layer 160-1 does not have an opening within interconnect structure 190. Referring back to FIG. 1, the contact layer 160-2 lies above the contact layer 160_1. Contact layer 160-2 includes an opening 250 that lies above landing area 161-1a on contact layer 160-1. The opening 250 has a distal longitudinal side wall 251a and a proximal longitudinal side wall 251b defining a length 252 of the opening 250. The length 252 of the opening 250 is at least the same as the length 201 of the landing region 161-la disposed below to allow the conductor 180 for the landing region 161-1a to penetrate the contact layer 160-2. [0056] The contact layer 160-2 also includes an opening 255 that lies above the landing area 161-1b. The opening 255 has a distal end and a proximal longitudinal side wall 256a, 256b defining a length 257 of the opening 255. Opening 255 length 257 to 201236108

1 W7U7UPA is less than the length 203 of the landing area 161-1b disposed below, so that the conductor 180 for the landing area 16Mb can penetrate the contact layer 160-2. [0057] Contact layer 160-2 also includes first and second landing regions 161-2a, 161-2b adjacent to openings 250, 255, respectively. The first and second landing regions 161-2a, 161-2b are portions of the contact layer 160-2 for contact with the conductor 180. 2B is a plan view showing a portion of the interconnect layer 190 including the first and second landing regions 161-2a, 161-2b and the contact layers 160-2 φ of the openings 250, 255. As shown in FIG. 2B, the opening 250 has longitudinal sidewalls 251a, 251b defining a length 252 and lateral sidewalls 253a, 253b defining a width 254 of the opening 250. The width 254 is at least the same as the width 200 of the lowering region 161-la disposed below to allow the electrical conductor 180 to penetrate the opening 250. [0060] The opening 255 has longitudinal sidewalls 256a, 256b defining a length 257 and having lateral sidewalls 258a, 258b defining a width 259. The width φ 259 is at least the same as the width 202 of the landing area 16b provided below to allow the conductor 180 to penetrate the opening 255. [0061] In the plan view of Fig. 2B, the openings 250, 255 each have a rectangular cross section. In an embodiment, the openings 250, 255 are shaped according to the shape of the mask used to form the openings, and each may have a circular, elliptical, square, rectangular or somewhat irregular profile. As shown in FIG. 2B, the landing area 161-2a is adjacent to the opening 250' and has a width 204 in the lateral direction and a length 205 in the longitudinal direction. The landing area 丨61-2b is adjacent to the opening 255 and has a lateral direction of 201236108

The TW7070PA has a width of 206 and a length 207 in the longitudinal direction. Referring back to FIG. 1, the contact layer 160-3 is placed over the contact layer 160_2. The contact layer 160-3 includes an opening 260 that lies above the landing region 161-la on the contact layer 160-1 and lies above the landing region 161_2a of the contact layer 160-2. The opening 260 has a distal end and a proximal longitudinal side wall 261a, 261b defining a length 262 of the opening 260. The length 262 of the opening 260 is at least the same as the sum of the lengths 201 and 205 of the landing regions 161-la and 161-2a disposed below to allow the electrical conductors 180 for the landing regions 161-1a and 161-2a to be in contact with each other. Layer 160-3. [0064] As shown in FIG. 1, the distal longitudinal side wall 261a of the opening 260 is vertically aligned with the distal longitudinal side wall 251a of the opening 250 disposed below. In the manufacturing embodiments described in detail below, an opening in a single etch mask and an additional mask formed in the opening in the single etch mask can be used, as well as a process for etching the additional mask. To form an opening without the need for a critical alignment step. This results in an opening having distal longitudinal sidewalls (261a, 251a, ...) along the perimeter of the vertically aligned single etched mask. [0065] The contact layer 160-3 also includes an opening 265 that lies above the landing region 161-1b of the contact layer 160-1 and lies above the landing region 161-2b of the contact layer 160-2. The opening 265 has an outer side 267 defining an opening 265 and an inner longitudinal side wall 266a, 266b. The outer longitudinal side wall 266a of the opening 265 is vertically aligned with the outer longitudinal side wall 256a of the opening 255 provided below. [0066] The length 267 of the opening 265 is at least the same as the sum of the lengths 203 and 207 of the landing areas 161-1b and 161-2b disposed below, and is used for the landing area 161-lb and 161 by 12 201236108 iw/υ/υΡΑ. The electrical conductor 180 of -2b can penetrate the contact layer 160-3. [0067] Contact layer 160-3 also includes first and second landing regions 161-3a, 161-3b adjacent to openings 260, 265, respectively. The first and second landing regions 161-3a, 161-3b are portions of the contact layer 160-3 for contact with the conductor 180. [0068] FIG. 2C is a plan view showing a portion of the contact layer 160-3 φ including the first and second landing regions 161-3a, 161-3b and the openings 260, 265 in the interconnect structure. [0069] As shown in FIG. 2C, the opening 260 has longitudinal side walls 261a, 261b defining the outer and inner sides of the length 262, and lateral side walls 263a, 263b defining the widths 264a, 264b of the opening 260. The width 264a is at least the same as the width 2 (10) of the landing region disposed below. The width 264b is at least the same as the width 204 of the landing region 16b 2a disposed below to allow the electrical conductor 180 to penetrate the opening 260. [0070] In the illustrated embodiment, the widths 264a and 264b are substantially the same φ. Alternatively, to accommodate landing areas having different widths, the widths 264a and 264b can be different. [0071] The opening 265 has longitudinal sidewalls 266a, 266b defining a length 267 and has lateral sidewalls 268a, 268b defining a width 269a, 269b. The width 269a is at least the same as the width 202 of the landing region 161-1b disposed below, and the width 269b is at least the same as the width 206 of the landing region 161-2b disposed below to allow the electrical conductor 180 to penetrate the opening 265. [0072] As shown in FIG. 2C, the landing area 161-3a is adjacent to the opening 260 and has a width 214 in the lateral direction and a length in the longitudinal direction. 3 13 201236108

TW7070PA 215. The landing zone 161-3b is adjacent to the opening 265' and has a width 216 in the lateral direction and a length 217 in the longitudinal direction. Referring back to FIG. 1, the contact layer 160-4 lies above the contact layer 160-3. The contact layer 160-4 is disposed above the landing area 161-1a of the contact layer 160-1, lying above the landing area 161-2a on the contact layer 160-2, and lying on the contact layer 160-3. An opening 270 above the landing zone 161-3a. The opening 270 has longitudinal side walls 271a, 271b defining a length 272 of the opening 270. The length 272 of the opening 270 is at least the same as the sum of the lengths 201, 205 and 215 of the landing areas 161-1a, 161-2a and 161-3a disposed below, for use in the landing areas 161-3a, 161-2a and 161. The electrical conductor 180 of -3a can penetrate the contact layer 160-4. As shown in Fig. 1, the longitudinal side wall 271a of the opening 270 is vertically aligned with the longitudinal side wall 261a of the opening 260 provided below. [0074] The contact layer 160-4 also includes a landing area 161-2b lying above the contact layer 160-1, lying above the landing area 161-2b on the contact layer 160-2, and lying on the contact layer. An opening 275 above the landing zone 161-3b on 160-3. The opening 275 has longitudinal side walls 276a, 276b defining a length 277 of the opening 275. The longitudinal side wall 276a of the opening 275 is vertically aligned with the longitudinal side wall 266a of the opening 265 disposed below. [0075] The length 277 of the opening 275 is at least the same as the sum of the lengths 203, 207, and 217 of the landing areas 161-1b, 161-2b, and 161_3b disposed below, so as to be used for the landing areas 161-1b, 161-2b, and The conductor 180 of 161-3b can penetrate the contact layer 160-4. [0076] Contact layer 160-4 is also included in landing region 161-4 between openings 270,275. The landing area 161-4 is for contacting the electrical conductor 180 201236108

Part of the contact layer 160-4 of 1 W ν υ / UFA. In Fig. 1, the contact layer 160-4 has a landing area 161-4. Alternatively, contact layer 160_4 can contain more landing areas than one. 2D is a plan view showing a portion of the interconnect structure 190 including the landing region 161-4 and the contact layer 16〇_4 of the openings 270, 275. [0078] As shown in FIG. 2D, the opening 270 has longitudinal sidewalls 271a, 271b defining a length 272 and has lateral sidewalls 273a, 273b defining a width 274a, 274b, 274c of the opening 270. The widths 274a, 274b, φ 274c are at least the same as the widths 200, 204 and 214 of the landing areas 161-1a, 161-2a and 161-3a disposed below so that the conductor 180 can penetrate the opening 270. [0079] The opening 275 has longitudinal side walls 276a, 276b defining a length 277 and having lateral sidewalls 278a, 278b defining a width 279a, 279b, 279c. The widths 279a, 279b, 279c are at least the same as the widths 202, 206 and 216 of the landing regions 161-lb, 161-2b and 161-3b disposed below so that the electrical conductor 180 can penetrate the opening 275. Φ [0〇8〇] As shown in Fig. 2D, the landing area 161-4 is located between the openings 270, 275 and has a width 224 in the lateral direction and a length 225 in the longitudinal direction. Referring back to FIG. 1, the distal longitudinal side walls 271a, 261a, and 251a of the openings 270, 260, and 250 are vertically aligned such that the differences in lengths of the openings 270, 260, and 250 are caused by the side walls 271b. The horizontal offset of 261b and 251b. As used herein, an element or feature "vertically aligned" substantially flushes an imaginary plane perpendicular to both the lateral and longitudinal directions. As used herein, the term "substantially flushing" is intended to cover 201236108

TW7070PA is a manufacturing tolerance in the formation of an opening that is formed using a single etched opening in the mask and using multiple etch processes that can cause variations in the planarity of the sidewall. As shown in FIG. 1, the distal longitudinal sidewalls 276a, 266a, and 256a of the openings 275, 265, and 255 are vertically aligned. [0083] Similarly, the lateral sidewalls of the openings in the layer are also vertically aligned. Referring to Figures 2A through 2D, the lateral side walls 273a, 263a and 253a of the openings 270, 260 and 250 are vertically aligned. Further, the lateral side walls 273b, 263b, and 253b are vertically aligned. For openings 275, 265, and 255, longitudinal sidewalls 276a, 266a, and 256a are vertically aligned, and lateral sidewalls 278b, 268b, and 258b are vertically aligned. [0084] In the illustrated embodiment, the openings have substantially the same width in the lateral direction from different contact layers to 160-4. Alternatively, in order to accommodate landing areas having different widths, the width of the opening may vary along the longitudinal direction, e.g., in a step-like manner. [0085] This technique for implementing interconnect structure 190 as described herein can reduce the area or footprint required for contact with complex contact layers 160-1 through 160-4 as compared to prior memory techniques. Area. Therefore, more space can be realized in the different contact layers 160-1 to 160-4 to implement the memory circuit. Compared to the previous memory technology, it is possible to increase the storage density and reduce the cost per bit in the upper layer. [0086] In the cross-sectional view of Fig. 1, the opening ' in the interconnect structure 19' causes the contact layers to have a step-like pattern on both sides of the landing region 161-4 on the contact layer 160-4. That is, the two openings in each layer are axisymmetric with respect to the longitudinal direction and the lateral direction, and the two landings of each layer 201236108 w/υ/υι^Α are also axisymmetric. Knowing the manufacture of the cover in the formation of the opening: symmetry is intended to be a difference, in which the opening is formed using the opening of the mask, and the use of multiple variations that can cause variations in the dimensions of the side walls. Engraved. In another embodiment, each layer comprises a single opening and a single landing zone, the layers having a step-like pattern on only one side. [〇〇88] In the case of the Fan, the appearance of a contact layer 16 (M to ΓΓνΛΙlike, the small interconnect structure described here can be implemented in layers, at least 2. In general, The layer (1) lies on the layer (i and the ancient towel (1) is equal to 1 to N, and the layer (1) is adjacent to the opening (1) of the landing area (1) on the layer (1). The opening (1) extends over the landing area on the layer (1) Above 'and when (1) is greater than i, the opening in the layer 〇. Opening (1) end = upper opening 〇 - the distal longitudinal side of the 对齐 is aligned far: = side wall 'and has a proximal end defining the length of the opening (1) Longitudinal side wall. Right side of the living, the length of the opening (1) is at least the same as the falling area (the degree of the upper opening (Η). When (1) is greater than !, the opening = j has the opening with the layer (i - ( ( Dimensions of the lateral side of the dip 〇-υ: the width of the same (丨) at least with the landing area _9] other types of memory cells and other types of memory cells that can be used for additional use, including;丨Electricity electricity capture and oceanic gate memory unit. For example, the other layer of f is implemented as insulation material The planar partition bad note frightened ^ J and using the related art thin film transistor or the layer formed on the access counter 17201236108 * ^

TW7070PA and access line. Further, the interconnect structure described herein can be implemented in other types of three-dimensional stacked circuit devices, wherein it is useful to have electrical conductors that extend into different layers of the device within a small footprint. 3A is a cross-sectional view of a portion of a three-dimensional stacked integrated circuit device (8). The three-dimensional stacked integrated circuit device 100 includes an array region 110 and a surrounding region 12A having an interconnection structure 19〇 derived therefrom. [091] In FIG. 3A, the memory array region 11() is implemented as a one-time programmable multi-layer memory cell as described in U.S. Patent Application Serial No. 12/579,192, the disclosure of which is incorporated herein by reference. The invention is owned by the assignee of the present application and incorporated herein by reference. The three-dimensional interconnect structure described herein can be implemented in the integrated circuit structure described and represented herein. [0092] The memory array area 11A includes a memory access layer, and the memory access layer 112 includes horizontal field effect transistor access devices 131a, 131b, and the horizontal field effect transistor access devices 131a, 131b are half The conductor substrate 130 has source regions 132a and 132b and drain regions 13 such as 134b. The substrate 130 can comprise a bulk layer of tantalum or an insulating layer or other conventional structure for supporting an integrated circuit. The trench isolation structures 135a, 135b are separated from the regions in the substrate 130. The word lines 14A, 14B function as gates of the access devices 131a, 131b. Contact plugs 142a, 142b extend through interlayer dielectric 144 to couple drain regions 134a, i34b to bit lines 150a, 150b. Contact pads 152a, 152b are coupled to contacts 146a, 146b disposed below and to the source regions 132a, 132b of the access transistor. Contact pads 152a, 152b and bit lines 150a, 150b are located within interlayer dielectric 154. 201236108 i w/υ/ϋΗΑ [0094] In the illustrated example, the contact layers are composed of respective planar conductive layers of material, such as doped polycrystalline. Alternatively, the contact layers need not be a layer of material that is planarly stacked, but rather a layer of material that can vary in vertical and dimensionality. [0095] The insulating layers 165-1 to 165-3 separate the contact layers 16〇1 to 160-4 one by one. The insulating layer 166 is disposed above the contact layers 160-1 to 160-4 and the insulating layers 165-1 to 165-3. [0096] The plurality of electrode columns 171a, 171b are arranged on top of the memory cell access φ layer 112 and extend through the contact layers. In this figure, the first electrode post 171a includes a central conductive core 170a, which is made, for example, of tungsten or other suitable electrode material, and is surrounded by a polycrystalline stone 172a. The anti-fuse material layer 174a' or other layer of programmable memory material is formed between the polysilicon sheath body 172a and the plurality of contact layers boys to 160-4. In this example, the contact layers 160-1 to 160-4 include a relatively late 搀:hetero n-type polycrystalline cleavage, however, the polycrystalline shi shi 172a includes a relatively two-degree disturbed p-type polycrystalline . Preferably, the thickness of the &apos;polycrystalline body 172a is greater than the depth of the consumable area formed by the P-n junction. The depth portion of the depletion region is determined by the associated doping concentration of the n-type and p-type polycrystals used to form the depletion region. The contact layers 160-1 to 160-4 and the sheath 172a can also be implemented using amorphous germanium. Similarly, other semiconducting materials can be used. [0097] The first electrode post 171a is coupled to the contact pad 152a. A second electrode post 171b' including a conductive core 170b, a polysilicon sheath body 172b, and an anti-fuse material layer 174b is selectively coupled to the contact pad 52b. [0098] plural contact layer ι6 (Μ to 16〇_4 and electrode column nia, i71b 19 201236108

The interface area between TW7070PA, including the memory component, which includes the programmable components connected in series with the rectifier, will be explained in detail below. [0099] In the native state, the anti-fuse material layer 174a of the electrode post 171a has a high electrical resistance, and the anti-solvent material layer 174a can be a bismuth fossil, a oxynitride or other dream oxide. Other materials such as nitrite can be used. After being programmed by applying appropriate voltages to the word line 140, the bit line 150, and the plurality of contact layers bod to 160_4, the anti-fuse material layer 174 collapses and is within the anti-fuse material of the adjacent corresponding layer. The active area presents a low resistance state. [0100] As shown in FIG. 3A, the plurality of conductive layers of the contact layers 160-1 to 160-4 extend into the peripheral region 120 where they are supported for connection to the plurality of contact layers 160-1 to 160-4. Circuit and conductor 18〇. A wide variation of the device is implemented in the surrounding area 12A to support the decoding logic or other circuitry on the integrated circuit 1〇〇. [0101] Electrical conductors 180 are disposed within interconnect structure 190 to contact landing regions on different contact layers 160-1 through 16〇_4. As discussed in more detail below, the electrical conductors 180 for each particular contact layer MOq through 16A_4 extend through the opening of the layer lying above to the conductor layer comprising conductive interconnects 185. Conductive interconnects 185 are provided as interconnections between the contact layers 160-1 through 160-4 and the decoding circuitry in the surrounding area 12A. The electric conductor 18's which are in contact with the dissimilar contact layers 160-1 to 160-4 as shown by broken lines in Fig. 3A are arranged to extend in the longitudinal direction into the cross section shown in Fig. 3A. [0101] FIG. 3B is a cross-sectional view of the third embodiment of FIG. 3 taken along the 3b to 3B lines and penetrates the interconnection region 19〇, and shows the class 20 201236108 iw/υ/υι^Α 1 is a view of the interconnect structure 190 shown. As can be seen in Figure 3B, the electrical conductors 180 for each particular layer extend through the openings in the upper layer to contact the landing zone. [0102] In the illustrated example, four contact layers 160-1 through 160-4 are shown. More generally, the small interconnect structure described herein can be implemented in layers 〇 to N, where N is at least two. [0103] Other types of memory cells and configurations can be used in other embodiments. For example, in another layer of the device, a planar memory array separated by φ insulating material can be implemented, and access devices and access lines are formed using thin film transistors or related techniques within the layers. Moreover, the interconnect structures described herein can be implemented in other types of three-dimensional stacked integrated circuit devices in which conductors having different layers extending into the device in a small footprint are useful. [0104] In FIGS. 3A and 3B, a single interconnect structure 190 is illustrated. For example, the plurality of interconnect structures are surrounded by the memory array region 110, and a plurality of interconnect structures can be arranged at different locations in the device to provide more power distribution. φ Figure 4 is a top plan view of an embodiment of an apparatus 100 comprising two serials of interconnect structures, as embodied in regions 190-1 and 190-2 in the surrounding area 120 on each side of the array. Plural string. Figure 5 is a top view of the layout of the embodiment, the embodiment comprising four series of interconnect structures in the surrounding area 120 on all four sides of the array, such as comprising strings 190-1, 190-2, 190-3, 190-4. For a sample array size comprising 1000 rows of cells and 1000 rows and having 10 layers, there is a feature size F defining a word line width and a bit line width, and a landing area on the layer The size is about F, at this time it can be seen that by a 21 201236108 '

The width of the area where the TW7070PA interconnect structure is lighted is about twice the number of layers or about 20F' while the distance between each word line is about 2F or more, and the width of the array is about 2000F. Therefore, after this example, about one interconnect structure can be formed in a string such as a series 19〇_3 along the width of the array, and a similar number can be formed in the string along the width of the array. 19〇_3 is in the list b. [0105] In still other embodiments, having an interconnect structure in addition to or in place of the surrounding area 120, has one or more interconnect structures capable of being implemented in the memory array region u〇 Inside. Moreover, the interconnect structure can extend in a diagonal direction or in any other direction without necessarily being parallel to the perimeter of the memory array region 110. [0106] FIG. 6 is a block diagram showing a portion of a memory device including the interconnect structure described therein. The first electrode post 171a is coupled to the access transistor 131a selected using the bit line 150a and the word line 14A. The plural § memory elements 544-1 to 544-4 are connected to the electrode column 171a. Each memory element is included in the series of programmable elements M8 and rectification 549. Even if the anti-glare material layer is located at the p_n junction, the string is arranged to represent the structure shown in Figures 3A and 3B. The programmable element 548 is represented by a symbol commonly used to indicate anti-fuse. However, it will be appreciated that other types of stabilizing resistive materials and structures can be used. [0107] In addition, the rectifier 549 implemented by the conductive plane in the electrode column and the P-n junction between the polyliths can also be replaced by other rectifiers. For example, a rectifier based on a solid electrolyte such as a strayite or other suitable material can be used to provide a rectifier. For other representative solid electrolyte materials, please refer to U.S. Patent No. 7,382,647. 22 201236108

TW7070PA

[0108] The memory elements 544_丨 to 544_4 are summarized to the corresponding contact layers 16G_1 to 16 (Μβ this contact layer is purchased via the derivative=6〇 and line 185 to the planar decoder (10). This plane decoding benefit 546 response The address, such as the voltage layer of ground 547, causes the rectifier in the memory element to be applied with a voltage of the positive = and selected layer or floated so that the rectifier in the memory is biased or [0109] FIG. 7 is a diagram showing an integrated circuit device 3 including an interconnect memory array having a description. The column decoder 361 is integrated into the memory column. The complex digital line line arrangement (4) 3 The row of the memory array is arranged to read and program from the memory unit of the array. The plane decoding is written (10) via the conductor 180 and the interconnect line The 185 faces are joined to the plurality of contact layers 160-1 to 16〇_4 in the memory array. The address is supplied to the row decoder 363, the column decoder 361, and the plane decoder 546 on the bus milk. ς The sense amplifier and data input structure in block 366 is transmitted through The material bus 367 is coupled to the row decoder 363. From the input/output port on the integrated circuit 3, through the data input line 371, the data is supplied to the data input structure in block 366. In the illustrated embodiment The integrated circuit 300 includes other circuits 374 'such as general purpose processors or special purpose application circuits' or a combination of modules providing system single chip functions. The sense amplifiers in block 366 are transmitted through the data output lines 372. The data is supplied to the input/output port on the integrated circuit 300, or to other data elements inside or outside the integrated circuit 300. 23 201236108

TW7070PA

[0110] The controller in this example is implemented using a biasing arrangement state machine 369 that controls the application of the supply voltage via a voltage supply or a bias generated or provided by the supply in block 368. 'For example, read voltage and stylized voltage. The controller can be implemented using special purpose logic circuitry as is known in the art. In other embodiments, the controller includes a general purpose processor 'this processor can be implemented on the same integrated circuit'. The integrated circuit executes a computer program to control the operation of the device. In other embodiments, a combination of a special purpose logic circuit and a general purpose processor can be used in the implementation of this controller. [0111] FIGS. 8A through 8C through 15 illustrate steps in an embodiment of a manufacturing process for fabricating an interconnect structure described herein and having a very small footprint. 8A and 8C are cross-sectional views showing a first step of the manufacturing process, and FIG. 8B is a top view showing a first step of the manufacturing process. For the purposes of this application, the first step involves forming a plurality of contact layers (10) to 160-4 lying above the provided memory cell access layer 112. In the illustrated embodiment, the structure depicted in Figures 8-8 to 290 is formed using the process described in U.S. Patent Application Serial No. 12/430,290, the entire disclosure of which is incorporated herein by reference. And combined with this. [0113] In other embodiments, the contact layers can be formed by standard processing as in the prior art, and can include, for example, transistors and diodes, word lines, bit lines and source lines, and conductive plugs. And a device for doping the doped regions in the substrate, depending on the device, the interconnect structure described herein is implemented. [0114] As described above, other types for the memory array region retention and configuration can also be used in other embodiments. 24 201236108

1 w/u/urA

[0115] Next, the first mask 800 having the opening 810 is formed on the structures shown in FIGS. 8A to 8C, and is the structure shown in the top view and the cross-sectional view of the 9A and 9B, respectively. The first mask 8 can be formed by depositing a layer for the first mask and forming the opening 810' by patterning the layer using lithography. The first mask can, for example, comprise a hard mask material such as tantalum nitride, niobium oxide or niobium oxynitride. [0116] The opening 81 of the first mask 800 surrounds the periphery of the combination of the landing areas on the contact layers "o" to 160-4. Accordingly, the width 192 of the opening 810 is at least the same as the width of the landing region on the contact layers 160-1 to 160-4 so that the subsequently formed electrical conductor 180 can penetrate the opening in the contact layer. The length 194 of the opening 810 is at least the same as the sum of the lengths of the landing regions on the contact layers 160-1 to 160-4 so that the subsequently formed electrical conductor 180 can penetrate the opening in the contact layer. [〇117] Then, the second etch mask 9〇〇 included in the opening 81〇 is formed on the structures shown in the 9A and 9β, and becomes the top view and the cross-sectional view of the first 〇A and 10B, respectively. The structure shown. As indicated by φ, the first etch mask 9 has a length 910 that is less than the length 194' of the opening 810 and the second etch mask 900 has a width that is at least the same as the width 192 of the opening 810. [0118] In the illustrated embodiment, the second etch mask 9A includes a material that is selectively etchable relative to the material of the first mask 800 such that the second mask 900 is within the opening 81〇 The length can be selectively reduced in the subsequent processing steps described below. In other words, the etch rate of the material of the second mask 900 for reducing the length of the second mask 9 is greater than the etch rate of the material of the first mask 800. For example, this embodiment 25 201236108

In the IW7070FA, the first mask 800 includes a hard mask material, and the second mask can include a photoresist material. [0119] Next, the first and second masks 8 and 900 are used as an etch mask, and the etching process is performed on the structures shown in FIGS. 10A and 10B to become the top view of FIGS. 11A and 11B and The cross-sectional views are shown separately. The etching process can be performed using, for example, a timing mode etch using a single etch chemistry. Alternatively, an etching process can be performed using a different etching chemistry to individually etch the insulating layer 166, the contact layer 16A_4, the insulating material 165-3, and the contact layer 16A_3. [0120] This etch will form an opening 1〇〇〇 through the contact layer ι6〇_4, a portion of the exposed contact layer 160-3. The opening 1 lie is placed above the landing area i6l_la on the contact layer 160-1. The opening 1〇〇〇 has a length 1〇〇2 which is at least the same as the length of the falling region 161-la, and has a width 1〇〇4 which is at least the same as the width of the falling region 161-la. [0121] This remaining portion also forms an opening 1010 penetrating the contact layer ι6〇_4, which is part of the exposed contact layer 160_3. The opening 1〇1〇 is placed over the landing area 161_lb on the contact layer 160-1. The opening 1〇1〇 has a length 1012 which is at least the same as the length of the landing area 161-1b, and has a width 丨〇〇4 which is at least the same as the width of the landing area 161-1b. [0122] Next, the length 910 of the mask 9 〇 0 is reduced to form a reduced length mask 11 长 having a length 1110, which is the structure shown in the top view and the cross-sectional view of the 12A and 12B drawings, respectively. In the illustrated embodiment, the mask 900 comprises a photoresist material and the mask 9 can be trimmed, for example, using reactive ion etching with a chemical based on ci2 or HBr. [0123] Next 'the first mask 8 〇〇 and the reduced length mask 26 201236108

1 W/U/WA 1100 is used as an etch mask, and etching treatment is performed on the structures shown in Figs. 12A and 12B to become the structures shown in the top view and the cross-sectional view of Figs. 13A and 13B, respectively. [0124] The etching process extends through the openings 1000, 1010 through the contact layer 160-3, and the portions of the exposed contact layer 160-2 disposed below. [0125] This etch also forms openings 1200, 1210 that penetrate portions of contact layer 160-4, and due to the reduction in the length of mask 1100, openings 1200, 1210 are no longer covered by mask 1100, thereby exposing contact layer 160. The φ part of -3. The opening 1200 is formed adjacent to the opening 1000 and lies above the landing area 161-2a on the contact layer 160-2. The opening 1200 has a length 1202 that is at least the same as the length of the landing area 161-2a and has a width 1204 that is at least the same as the width of the landing area 161-2a. [0126] The opening 1210 is formed adjacent to the opening 1010 and lies above the landing area 161-2b on the contact layer 160-2. The opening 1210 has a length 1212 that is at least the same as the length of the landing area 161-2b and has a width 1204 that is at least the same as the width of the landing area 161-2b. φ [0127] Next, the length 1110 of the mask 1100 is reduced to form a reduced length mask 1300 having a length of 1305. The first mask 800 and the mask 1300 are used as an etch mask to perform an etching process, and the structure is shown in the upper view and the cross-sectional view of Figs. 14A and 14B. [0128] The etching process extends through the openings 1000, 1010 through the contact layer 160-2, and exposes the landing regions 161-1a, 161-1b on the contact layer 160-1. The etching process also extends through the openings 1200, 1210 through the contact layer 160-3 to expose the landing regions 161-2a, 161-2b on the contact layer 160-2. [0129] This etch also forms openings 27 201236108 iw/υ/υκ ports 1310, 1320 that penetrate portions of the contact layer 160-4, and no longer cover portions of the layer 160-4 due to the reduction in the length of the mask 1300. Thereby, the landing areas 161-3a, 161-3b on the contact layer 160-3 are exposed. [0130] The opening 1310 is formed adjacent to the opening 1200. The opening 1310 has a length at least the same as the length of the landing area 161-3a and has a width 1314 which is at least the same as the width of the landing area 161-3a. [0131] The opening 1320 is formed adjacent to the opening 1210. The opening 1320 has a length 1322' that is at least the same as the length of the landing region 161-3b and has a width 1324° that is at least the same as the width of the landing region 161-3b. [0132] Next, the insulating filler material 1400 is deposited at the 14A and 14B The structure is shown, and a planarization process such as chemical mechanical polishing (CMP) is performed to remove the masks 800, 1300' to become the structure shown in the cross-sectional view of Fig. 15. [0133] Next, a lithographic pattern is formed to define via holes for the conductor 18 〇 and connected to the landing region. Reactive ion etching can be applied to form deep and high aspect ratio vias through the insulating fill material 14A to provide vias for the conductors 180. After the via holes are opened, the via holes are filled with tungsten or other conductive 10 material to form the electrical conductors 18〇. Metallization is applied at this point to form interconnects 185 to provide interconnection between the conductors 8 and the planar decoding circuitry on the device. Finally, the back end 〇f Hne (beol) process is applied to complete the integrated circuit, and becomes the structure shown in the third and third FIGS. [0134] In different contact layers, the contact layer is patterned by using an opening 810 of a single etch mask 800 t, and is formed for passing through the conductor to be disposed below by using a side mask treatment. The opening of the landing area on the contact layer 28 201236108 iw /υ/υ^Α without having to use the key alignment steps. Thus, openings having vertically aligned sidewalls are formed in different contact layers in a semi-aligned manner. [0135] In the example shown above, the opening 810 in the mask 800 has a rectangular cross-section in a plan view. Thus, the openings in the different contact layers have substantially the same width in the lateral direction. Alternatively, depending on the shape of the landing zone of the different contact layers, the opening in the mask 800 can have a circular, elliptical, square, rectangular or somewhat irregular profile. φ [0136] For example, to accommodate landing regions having different widths, the width of the opening in the mask 800 can vary in the longitudinal direction. Fig. 16 is a plan view showing the opening 1510 in the mask 800. The mask 800 has different widths in the longitudinal direction in a stepwise manner, and the width of the opening in the contact layer is thereby different. The invention will now be described primarily with reference to Figures 17 to 47. [0138] The following description will generally refer to embodiments and methods of specific structures. It is to be understood that the invention is not intended to be limited to the details of the embodiments of the invention, and the invention may be practiced with other features, elements, methods and embodiments. The preferred embodiments are described to illustrate the invention, and are not intended to limit the scope of the invention as defined by the scope of the claims. The usual skill in the art will recognize the various equivalent variations described below. Similar elements in different embodiments are collectively referred to by like element symbols. [0139] Figure 17 is a simplified flow diagram of a method for generating interconnect contact regions 14 in accordance with the present invention. The interconnect contact area generation method of Figure 17 includes the obtaining of a combination of obtaining a mask in step 12. Further steps in method 10 shown in Figure 17 will be followed by 18 to 29 201236108

TW7070PA 27 is discussed below. Figures 18 through 27 illustrate a first example of a method for practicing the present invention. [0140] Referring to f 27 g, a combination of N masks is used to create a contact layer of a plurality of interconnecting contact regions 14 in the contact layer, the like, the like, and the stack (four). It is an interconnected area 17 located in the three-dimensional stack 1C device. The interconnect region 17 will typically be a surrounding interconnect region as shown in Figures 4 and 5, but can also be located in other regions. In the two percent examples of Figures 18 through 44, for ease of illustration, four contact layers are shown on substrate 19, and a two-dimensional stacked Ic device will typically have more contact layers. As will be discussed below, 'each mask includes a masked area and an etched area, N is an integer at least equal to 2, and χ is the serial number used for the mask so that one of the masks is equal to 1 'the other mask X is equal to 2, and then until X is equal to Ν. When X is equal to 1, the remaining step for the associated mask engraves a contact layer 18' when χ is equal to 2, the etching step for the associated mask will engrave the two contact layers, and so on. [0141] Next, referring to FIG. 17, a partial removal step 20 is performed, with reference to FIG. 9, to remove a portion 22 of the upper layer 24 above the stack 16 of the contact layer 18. In this example, the upper layer 24 includes first and second shihed oxide layers 26, 28, and a charge trapping layer 27 typically formed of nitriding between the shixi oxide layers. In this example, referring to Fig. 18, this removal is accomplished using an additional mask 30 having an open region 32 to permit etching of a portion 22 of the overlayer 24 shown in FIG. In this example, each of the contact layers 18 comprises a conductive layer 34, typically a patterned polysilicon layer, to form an electrical conductor, such as a word line, and an insulating layer 36, typically comprising a tantalum oxide or tantalum nitride compound. . In order to simplify the manner in which the conductive layer 34 of the i36 / u/um portion of the 201236108 is referred to, it will generally be referred to as the polysilicon layer 34. However, the upper conductive layer 34 can be made of other suitable materials, such as metal, metal cerium, and more than one layer of polycrystalline, metal dreaming, and metal combinations. The etching through the dielectric layer 28 of the upper layer 24 is typically controlled by a selective etching process using a material. For example, when the dielectric layer 28 is tantalum oxide and the upper conductive layer 34 is polysilicon, reactive ion etching is used to etch the penetrating dielectric layer 28, and the etching is effectively stopped by reaching the upper conductive layer 34. . In other cases, a similar technique φ can be used to control the etch depth. Other techniques for controlling the etch depth can also be used. Since the additional mask 30 can simply open the space for etching the stack 16 of contact layers 18, the additional mask 30 can be considered as part of a combination of N masks. In the example discussed herein with respect to Figures 28 through 34, carpeting etching is used to remove any additional upper layer 24 from the interconnect contact areas without the need for additional masking. [0142] FIG. 20 illustrates the formation of a first mask 38.1 on the stack 16 of contact layers 18 of FIG. In this example, the first mask 38.1 φ includes the photoresist mask elements 40.1, 40.2, 40.3, wherein the mask element 40.2 covers the central portion 42.1 of the first polysilicon layer 34.1, and the mask element 40.3 covers the first The edge portion 42.2 of the wafer layer 34.1. Figure 21 illustrates the result of the etching step in which portions of the contact layer 18.1 that are not covered by the photoresist mask element 40 are etched down to the contact layer 18.2. That is, in this first etching step, a contact layer 18 is etched. [0143] FIG. 22 illustrates the formation of a second photoresist mask 38.2 on the stack 16 of contact layers 18 of FIG. As suggested by the virtual guideline in Figure 22, the mask 38.2 covers the polysilicon layer 34.1 and 34.2. 31 201236108

TW7070PA exposed part, this part is used for interconnection contact areas 14.1 and 14.2. Figure 23 illustrates the results of a second etching step of etching the two contact layers. In particular, the exposed surface portion 44 of the polysilicon layer 34.2 is etched down two layers, exposing portions 46 of the polysilicon layer 34.4. In addition, the exposed surface portion 42.3 of the polysilicon layer 34.1 is also etched down to the two contact layers, exposing portions 47 of the polysilicon layer 34.3. Figure 24 illustrates the removal of the second mask 38.2 and the retention of portions of the polysilicon 34.1, 34.2, 34.3, and 34.4 to act as interconnecting contact regions 14.1, 14.2, 14.3, and 14.4. The thin row portion 48 of the contact layer 18.1, sometimes referred to as a dummy stack or a local high vacation stack, can be deliberately formed or as a result of manufacturing tolerances. [0144] In the examples of FIGS. 18-24, two masks 38.1, 38.2 are used to provide access to the landing zone, which is located at four of the four distinct contact layers 18-1 through 18-4. Connect the contact areas 14.1 to 14.4. In accordance with the present invention, the interconnect regions 17 are etched N times using N masks to create interconnect contact regions 14 for each of the 2 N-th contact layers 18. As discussed below with reference to Figure 27, in each of the N-th contact layers of 2, the mutual contact area 14 can be aligned with the landing area 56 and provide access to the landing area 56. Each etching step, including for each mask of the sequence number X, etches a (x-1) power contact layer of 2. Refer to the Interconnected Area Silver Engraving Step 49 in Figure 17. [0145] FIG. 25 illustrates the result of an optional step of laying the etch stop layer 50 over the exposed surface of the etched stack 16 of the contact layer 18, such as when the interlayer insulating layer is tantalum oxide, for example, the etch stop layer 50 It is a tantalum nitride layer. Thereafter, as shown in FIG. 26, the interlayer dielectric 52 is deposited on the structure of FIG. 25 by etching the 32 201236108 iw/υ/υ^ region filling step of FIG. The material 52 and the conductor 54 of the etch stop layer 50 are formed to form a conductive landing area with respect to the interconnect contact region 14

Electrical contact. The material can be made into an electrical conductor 54 which forms a through hole penetrating the dielectric filling (4) to provide an opening to the landing area on the second layer, where CVD or pVD treatment is used. In the through hole, the wire is in contact with the wire, and the τ is used to sink the through hole, and the vertical conductor 54 is formed. This is illustrated in Fig. 27 and is the conductor forming step 60 of Fig. 17. [0146] A second example will be discussed with reference to Figures 28 through 34, where the _ number' refers to an element similar to that in the first example of Figures 17-27. The stack 16 of contact layers 18 of the interconnect region 17 of Figure 28 has the same basic structure as the 18th® towel. In this case, the dielectric layer 23 and the charge trapping layer of the upper layer 24 are removed by carpeting and engraving to eliminate the need for an additional mask 3G. The first glaze is on the dielectric layer 28 between the mask elements 4〇1 and 4〇2 and between the elements 40.2 and 40.3, and the mask 381 has an open area 4ι and 4−1]° followed by The first step shown in FIG. 31, thereby forming a penetrating dielectric layer in the mask W 4 (the openings 41.1 and 41.2 ' between the U and 40.2 and between the mask members 4〇2 and 4〇3) 28 and the opening of the polycrystalline material 34 ι 62, 63. Although the surname step can continue down to the polycrystalline layer = 2.2' but not needed here, the reason for this will be discussed in the μ and It is time to demonstrate that the second mask 38.2 is now formed on the etched stack 16 of the contact layer 18. The second mask 38.2 comprises masks MG.4 and 40.5, and the eight-mask element 40.5 covers the opening 63' Keep opening ^, magic room 33 201236108

A portion 64 of the dielectric layer 28 of the TW7070PA is not covered. [0147] FIG. 33 illustrates the result of the second etching step in which the two contact layers are etched. Specifically, the opening 62 is etched down to the oxide layer 36.3 while a portion 64 of the dielectric layer 28 etches the two contact layers down to the oxide layer 36.2. Thereafter, the second mask 38.2 is removed and the interlayer dielectric 52 is deposited over the etched structure as shown in FIG. Subsequently, electrical conductors 54.1 to 54.4 penetrating the interlayer dielectric 52 and the oxide layers 28, 36.1, 36.2, 36.3 covering the polysilicon layers 34.1 to 34.4 are formed to generate a landing region 56.1 to the interconnection regions 14.1 to 14.4 to 56.4 contact. [0148] As in the examples of FIGS. 18 to 24, two masks 38.1, 38.2 are used in the figures 28 to 34 to provide to the four interconnect contact regions 14.1 located in the four distinct contact layers 18.1 to 18.4. Access to the landing zone 56.1 to 56.4 of 14.4. In accordance with the present invention, interconnect regions 17 are etched N times using N masks to create interconnect contact regions 14 for each contact layer 18. At each of the Nth contact layers of 2, the interconnect contact regions 14 are aligned with the landing regions 56 and provide access to the landing region 56. Again, this etching step includes etching (X _ 1) power contact layers of 2 for each mask of the sequence number X. [0149] Figures 35 through 44 illustrate a third example of a method of re-implementing the invention with similar element symbols referring to similar elements. A first mask 38.1 is formed over the upper layer 24 and over the stack 16 of contact layers 18 of the interconnect regions 17. As shown in Fig. 35, between the mask elements 40.1 and 40.2 and between the mask elements 40.2 and 40.3, the photoresist mask elements 40.1, 40.2 and 40.3 form open areas 66.1 and 66.2. The portion of the upper layer 24 disposed below the open areas 66.1 and 66.2 201236108 1 w /υ/υΐΆ is slid down to the polycrystalline dream layer 34.1 of the first contact layer i8, and the first and the first layers are generated in the upper layer 24. Two openings 68.1, 68.2. The openings 68.1 and 68.2 expose the surface portions 70.1, 70.2 of the first polysilicon layer 34.1.

[0150] Figure 38 illustrates the results of depositing sidewall materials 72.1 and 72.2 on the side walls of the first and second openings 68.1, 68.2. This can be done in a different manner by, for example, depositing a layer of insulating material such as tantalum nitride over a wafer by CVD or sputtering, followed by anisotropic etching until except adjacent to vertical Material outside the area of the sidewall is removed from the horizontal surface of the wafer to preserve sidewall spacing. The sidewall materials 721 and 72.2 cover the first portions 74.1, 74.2 of each of the surface portions 70.1, 70.2 while leaving the second portions 76.1, 76.2 of each of the surface portions 7〇1, 7〇 2 uncovered. (d) At this time, for example, by anisotropic reaction ions (4), the structure of Fig. 38 is engraved, the ship does not attack the sidewall material, reduces the size of the sidewall material W, 72.2, and extends the first and second meetings. Port 68. Bu 6:2 penetrates the contact layer and exposes the polycrystalline layer 34.2. Refer to Figure 39. Then, 'remove the side wall material 72', 79 〇a sergeant 72, 2', refer to Fig. 40, and fill the surface portion 7 of the exposed surface portion 7 (the first portions 741, 74 2 of U, 70.2 are shown in Fig. 40). · Figure 1 depicts the first opening of the heart (4) at the moment of the second mask under the second portion of the ^2, which penetrates the two contact layers 18 and exposes the second portion 76^. The portion of layer 34.3 is covered by the structure of the layer 42 by the interlayer dielectric 52 as shown in Fig. 43. Fig. 44 shows 35 201236108

TW7070PA results in the formation of electrical conductors 54.1 through 54.4 in contact with landing regions 56.1 through 56.4 at interconnect contact regions 14.1 to 14.4. [0153] When the relatively upper upper layer 24 is used over the stack π of the contact layer 18, the method shown in the figures 35 to 44 is particularly suitable. The layer 50 used in conjunction with the examples of Figures 18 through 27 can be used with the second and third examples. [0154] FIG. 45 illustrates an example of stacking for 16 contact layers 18. In accordance with the present invention, the interconnect contact regions 14 for the 16 contact layers 18 can be completed using only four masks 38. In this example, the first mask 38.1 has eight photoresist mask elements 40 labeled 1, 3, 5, etc., followed by open etch regions 41 labeled 2, 4, ό, etc. In this example, each edge of each etch mask element 4 and open etched region 41 has a unit of longitudinal dimension. A single layer is etched using the first mask 381. The first mask 38.2 has four photoresist mask elements labeled 1/2, 5/6, ..., etc., followed by open etched regions labeled 3/4, 7/8, ..., etc., each region Both have 2 units of vertical scale. The second layer is etched using the second mask 382. The third mask 38.3 has an array of 22 photoresist mask elements, followed by open etched regions labeled 5-8, 13, 16 each having a longitudinal dimension of 4 units. Four layers were engraved using a third mask of 38.3. The fourth mask 38 4 has two photoresist mask elements labeled i_4, 9_12, followed by open etched regions labeled 5_8, 丨6, each of which has a longitudinal dimension of 4 units. Use the second mask 38.3 to engrave four layers. The fourth mask has one of the photoresist mask elements labeled 1-8, followed by an open etched area labeled 9-16, each of which has a longitudinal dimension of 8 units. Use the fourth mask 384 36 201236108

1 W/U/UFA name is engraved with eight layers. [0155] As discussed above, when the first mask % is used, χ is equal to i, and the last name is a single layer 18 (2X-1=2〇==1); when the second mask 38.2 is used, two etchings are performed. Layer 18 (2χ-1=2ΐ=2); when using the third mask 38 3, the remaining 4 layers 18 (wide 1 = 22 = 4); when using the fourth mask 38.4, the money is engraved 8 Layer 18 (2 = 23 = 8). In this method, any contact layer 18 between the worker and the 16 can be completed using some combination of the surname i layer, the remaining 2 layers, the last 4 layers, and the 8 layers. In another way of thinking, four masks represent the number of digits of the four binary digits, which is the corresponding decimal digit (10).

0000, 0001, ...,] ηι. And also, the second 丄 L 10 1 is exemplified by δ, in order to access the contact layer

The interconnection contact area 14 of At requires engraving to penetrate 12 contact layers 'where, by using the third mask 38.3 (_ penetrates 4 contact layers) and the fourth, ', 38.4 ((4) penetrates 8 Contact layer) open 4ι = engraved. The result of the use of the mask 38. (1) 8.4 of Fig. 45 is the stack 16 of contact layers 18 shown in Fig. A different mask, resulting in a more expensive pass: t side, will require 16 1 defensive double 炅 plus mussels and the increased chance of failure due to tolerance build-up. The example of Figs. 45 and 46 results in a continuous open staircase region for connecting the touch region 14 with the landing region %ha:j. Figure 47, wherein four masks 38 are arranged to create 16 contact layers for the second time: a complete height boundary H between the interconnecting contact regions 14, adjacent to the contact regions 14, 16 having a full height edge ^ 4 stop. Whether or not a dummy stack 82 is created, this embodiment has a dummy stack 82 between each of the interconnected contact regions 14 by providing a virtual masking region 8 in the parent mask 38. =, 37 201236108

TW7070PA In some embodiments, one or more dummy stacks 82 can be eliminated. Likewise, the longitudinal dimensions of the dummy stacks 82 need not be the same for each other. [0157] It is not necessary to use the mask 38 in the order of the number of contact layers 蚀刻8 etched by each mask. That is, the mask 38.2 can be used before the mask 381. However, for a larger processing window, it is preferable to use a mask in the order of the number of contact layers to be etched, that is, first etching a single contact layer using a mask, and then etching the two contact layers using a mask. And so on. [0158] In the example of FIG. 47, a virtual masking region 86 is provided corresponding to the location of each etch mask 38 such that the resulting dummy stack 82 is a full-fill stack. For one or more but not all of the masks, for example, a partial high vacation stack of thin row portions 48 of Fig. 24 can be made by providing virtual masking regions 86 for corresponding locations. [0159] Although the present invention discusses the case where n is equal to 2, please refer to the figures of FIGS. 17 to 44, and for the case where n is equal to 4, please refer to the figures 45 to 47, and the number of masks can be other numbers of 3 Or can be more than 4 N. Although it is possible to use a combination of masks to create a N-th contact layer of the interconnect contact region 2, a combination of n masks can be used to generate up to N of the interconnect contact region by φ. The second contact layer. For example, as N is equal to 4, four masks can be used to create 16 contact layers that are smaller than the interconnect contact regions, such as I], 14 or 15 contact layers of the interconnect contact regions. The present invention has been disclosed by reference to the preferred embodiments and examples thereof. Modifications and combinations will occur at any time for those skilled in the art, and modifications and combinations will be in the spirit of the present invention and the following applications 38 201236108

Within the scope of the I W /O /WA patent scope. BRIEF DESCRIPTION OF THE DRAWINGS Figures 1 through 16 and related descriptions are taken from U.S. Patent Application Serial No. 12/579,192, filed on Jan. 14, 2009, the content of which is entitled &quot;3D Integrated Circuit Layer Interconnect having The same assignee as this application is incorporated herein by reference. 1 is a cross-sectional view of a device including a three-dimensional structure having an interconnect structure 190 having a small footprint, where the conductor 180 extends to different contact layers 160-1 in the device. To 160-4. Fig. 2A is a plan view showing the contact layer 160-1 showing the landing area. Fig. 2B is a plan view showing the contact layer 160-2 adjacent to the opening of the landing area. Fig. 2C is a plan view showing the contact layer 160-3 adjacent to the opening of the landing area. φ Fig. 2D is a plan view showing the contact layer 160-4 adjacent to the opening of the landing area. Figs. 3A and 3B each show an orthogonal view of a portion of a three-dimensional stacked integrated circuit device including a 3D interconnect structure having a small occupied area. Figure 4 is a top plan view showing the layout of an embodiment of the apparatus including interconnect structures in the periphery of the memory array. Figure 5 is a top plan view of an embodiment of an apparatus including interconnect structures in the periphery of four sides of the memory array. 39 201236108

The TW7070PA is a block diagram showing an architectural view of a portion of a memory device that includes the interconnect structure described herein. Figure 7 is a simplified block diagram of an integrated circuit including a three dimensional memory array having the interconnect structure described herein. Figures 8 through 8C through 15 illustrate steps in the manufacturing process for fabricating the interconnect structure described herein. Figure 16 is a plan view of the opening in the mask having different widths in the longitudinal direction in a step-like manner to accommodate different widths of the landing areas on the layer. DESCRIPTION OF THE INVENTION The present invention mainly refers to Figures 17 to 47. Figure 17 is a simplified flow diagram of a method for creating interconnected contact regions in accordance with the present invention. 18 through 27 illustrate a first example of a method for generating interconnect contact regions for a plurality of contact layers in an interconnect region of a three-dimensional stacked IC device. Figure 18 is a simplified cross-sectional view showing a stack of contact layers having additional masks formed over the upper layer. Figure 19 illustrates the penetration of the upper layer through the open etch in the additional mask of Figure 18. Mask Figure 20 illustrates the first layer of the stack of contact layers laid in Figure 19. Figure 21 shows the result of using a first mask to etch a single contact layer. The mask is shown in Fig. 22 as a stack of contact layers placed on the first nail map. Fig. 23 shows the result of etching through the two contact layers of Fig. 22. Figure 24 is a green diagram showing the structure of the second mask removed from Fig. 23, thus outside 201236108

1 W7070PA Exposure contact area of four distinct contact layers. Fig. 25 is a view showing a structure in which an etch stop layer is formed over the exposed surface of the structure of Fig. 24 in Fig. 24. Figure 26 is a diagram showing the structure covered by an interlayer dielectric in Figure 25. Fig. 27 is a view showing the structure of Fig. 26 after the formation of the conductor penetrating the interlayer dielectric and the etch stop layer to make contact with the landing region of the interconnection contact region of each of the four contact layers. Figures 28 through 34 illustrate a second example of a method for creating interconnected contact regions for a plurality of contact layers of an interconnect region φ domain of a three-dimensional stacked 1C device. 35 through 44 illustrate a third example of a method for creating interconnect contact regions for a plurality of contact layers of an interconnect region of a three-dimensional stacked 1C device. Figures 45 and 46 illustrate a processing example for the stacking of 16 contact layers, while Figure 46 depicts the residual results. Figure 47 illustrates the etching results when the mask has a dummy contact area to create a false stack between the interconnect contact areas. Φ [Main component symbol description] 10: Interconnection contact region generation method 12, 20, 49, 60: Step 14, 14.1, 14.2, 14.3, 14.4: Interconnection contact region 16: Stack 17: Interconnection region 18, 18.1 18.2, 18.3, 18.4: Contact layer 19: Substrate 22, 46, 47, 64, 78, 80: Part 41 201236108

TW7070PA 23, 28: dielectric layer 24: upper layer 26, 28: tantalum oxide layer 27: charge trapping layer 30: additional mask 32. open regions 34, 34.1, 34.2, 34.3, 34.4: upper conductive layer; polysilicon Layer 36: lower insulating layer 36.1, 36.2, 36.3: oxide layer 38, 38.1, 38.2, 38.3, 38.4: mask 40, 40.1, 40.2, 40.3, 40.4, 40.5: photoresist mask elements 41, 41.1, 41.2: Open area; opening 42.1: central portion 42.2: edge portion 42.3, 44, 70.1, 70.2: surface portion 48: thin row portion 50: etch stop layer; SiN layer 52: interlayer dielectric 54, 54.1 to 54.4: electrical conductor 56, 54.1 to 54.4: landing area 62, 63, 68.1, 68.2: opening 66.1, 66.2: open area 72.1, 72.2: side wall material 74.1, 74.2: first part 76.1, 76.2: second part 42 201236108

i W /O/UFA 82: dummy stack 84: full height boundary stack 86. virtual mask area 100: three-dimensional stacked integrated circuit device; integrated circuit 110: array area 112: memory access layer 120: surrounding area 131a, 131b: horizontal field effect transistor access device φ130: semiconductor substrate 132a, 132b: source region 134a, 134b: drain region 135a, 135b: trench isolation structure 140, 140a, 140b: word line 131a, 131b: access device; access transistor 142a, 142b: contact plug 144: interlayer dielectric 10 146a, 146b: contact 150, 150a, 150b: bit line 152a, 152b: contact pad 154: interlayer dielectric 160 - 1 to 160-4: contact layers 161-1a, 161-1b, 161-2a, 161_2b, 161-3a, 161-3b, 161-4: landing area 164: insulating layers 165-1 to 165-3, 166 : Insulation layer 43 201236108 iw / υ / υ ι ^ Α 171a, 171b: electrode column 170a, 170b: conductive core 172a, 172b: polysilicon sheath body 174, 174a, 174b: anti-fuse material layer 180: conductor 185: interconnection Line 190: interconnect structure 190-1, 190-2, 190-3, 190-4: tandem 192, 200 '202 '204 ' 206 ' 214, 216 ' 224 ' 254 ' 259 ' 264a, 264b, 269a, 269b, 274a, 274b, 274c '279a, 279b, 279c, 1004, 1204, 1314, 1324: width 194 '201 ' 203 ' 205, 207 ' 215 ' 217 , 225 ' 252 , 257 , 262 , 267, 272, 277, 910, 1002, 1012, 1110, 1202, 1212, 1305, 1312, 1322: lengths 250, 255, 260, 265, 270, 275, 810, 1000, 1010, 1200, 1210, 1310, 1320, 1510: openings 251a, 251b, 256a, 256b, 261a, 261b, 266a, 266b, φ 271a, 271b, 276a, 276b: longitudinal side walls 253a, 253b, 258a, 258b, 263a, 263b, 268a, 268b, 273a 273b, 278a, 278b: lateral side wall 300: integrated circuit 360: memory array 361: column decoder 363: row decoder 365: bus bar 44 201236108 1 W/ϋ/ϋΡΑ 366, 368: block 367: data Bus 369: Bias Arrangement State Machine 371: Data Input Line 372: Data Output Line 374: Other Circuits 544-1 to 544-4: Memory Element 546: Planar Decoder φ 547: Ground 548: Programmable Element 549 · Rectifier 800: first mask 900: second mask 1100, 1300: reduced length mask 1400: insulation fill Material

45

Claims (1)

201236108 1 W7U70FA VII. Patent Application Range: 1. A method for a three-dimensional stacked 1C device having a stack of a plurality of contact layers in an interconnected region to be aligned with a plurality of landing regions of the contact layers The contact layers expose a plurality of interconnect contact regions of the landing regions, the method comprising: using a combination of N etch masks to produce up to and including 2 N powers for the stack having the contact layers Each of the interconnecting contact region layers, each of the masks includes a plurality of masking regions and a plurality of etched regions, N is an integer at least equal to 2, and X is a sequence number for the masks to mask one of the masks X is equal to 1, another mask X is equal to 2, and then until X is equal to N; removing at least a portion of any of the upper layers lying above the stack having the contact layers is removed from the interconnect region; The selected sequence etches the interconnect region N times using the masks to generate a plurality of contact openings extending from a surface layer to each of the contact layers, each of the 2 N-th contact layers Contact openings and Having the landing areas aligned and providing access to the landing areas; and the etching step includes etching (2 - 1) power contact layers of 2 for each of the sequence numbers X; thereby forming a pass The plurality of electrical conductors contacting the openings to contact the landing regions of the contact layers. 2. The method of claim 1, further comprising: applying a filling material over the contact openings to define a through-hole patterned surface; opening a plurality of through holes penetrating the filling material, Exposing the landing areas in each of the 46 201236108 1 W/O/WA contact layers; and depositing a conductive material in the vias. 3. The method of claim 1, wherein the step is performed by the masks, and at least J of the masks comprise a virtual masking area. 4. The method of claim 2, wherein the steps are performed by the masks, and the plurality of locations on the at least some of the masks comprise a plurality of virtual masking regions. The method of claim 1, wherein the method is implemented by using a mask, and each of the masks includes at least one virtual masking area on each of the plurality of locations. The method of claim 1, wherein the method of applying the V is performed by at least equal to four. Wherein, the method of the shifting, as described in the scope of the patent application, is carried out in the order of the serial number. Guangniu I. The method described in claim 1 of the patent application, wherein the step is to implement the additional light of the domain. In addition to the steps, the movement is due to the meteorites, the hits 丄 ^ /, T. The method of claim 1, wherein: the opening is formed by the plurality of sidewalls partially forming an exposed first contact in the upper layer. Laminating a boundary; and including a 5H interconnect region etching step 47 201236108 TW7070PA, depositing sidewall material on the sidewalls of the opening and at a first portion of the top surface portion, and retaining the top surface portion a second portion such that there is no sidewall material on the second portion; extending the opening to penetrate the second portion of the top surface portion to provide access to the top surface of the contact layer disposed below; and shifting Except at least some of the sidewall material, thereby exposing at least some of the first portion of the top surface portion, such that the first contact layer and the contact layers disposed underneath are formed in alignment with the landing regions and provided The interconnecting contact regions to the accesses of the landing regions; Φ whereby the sidewall material acts as one of the N etch masks. 11. The method of claim 10, wherein the step of removing the sidewall material exposes the landing areas. 12. The method of claim 10, wherein the sidewall material removal step is performed by removing substantially all of the sidewall material. 13. The method of claim 10, wherein the opening forming step is performed by using the upper layer as the top layer and the selected contact layer as the first contact layer. 14. The method of claim 1, wherein: the removing step comprises forming a first opening and a second opening in the upper layer and exposing a top surface portion of the first contact layer to the opening The openings are partially bordered by a plurality of sidewalls; and the interconnecting region etching step includes: on each of the sidewalls of the opening and on each of the top surface portions 48 201236108 iw/υ/υι^上上=积- sidewall material, and retaining a second portion of each of the top surface portions such that no sidewall material is present on the second portion; extending each opening in the first opening and the second opening The second portion of the top surface portion is exposed to the top surface of each of the second contact layers of the opening; at least some of the sidewall material is removed from each opening to expose the top surface to each of the openings At least some of the first portions form the interconnecting contact regions in the second opening, and the interconnecting contact regions in the second opening are associated with the first contact layer and the second contact layer Some landing areas are aligned, Providing access to the landing areas located in the first layer and the second contact layer; and penetrating from the exposed first portion of the top surface portion (1) The first contact layer and the second contact layer expose the top surface of the contact layer, and (7) the exposed top surface of the second contact layer further extends the first opening σ to penetrate the The second contact layer and the third contact layer exposing the top surface of the fourth contact layer to be aligned with the lower opening regions of the third and fourth contact layers And providing the interconnecting contact regions to the access areas of the landing areas; whereby the sidewall material acts as one of the one of the etched masks. 15. A method for providing a plurality of electrical connections to electrically connect to a plurality of landing regions 2 of a stack of one of a plurality of contact layers located in an interconnect region and for use in a type of three-dimensional stacked IC device, the type comprising An interconnect region including an upper layer and a stack of a second contact layer, a second contact layer, a third contact layer, and a fourth contact layer below the upper layer, the method comprising Forming at least one first opening and a second opening in the upper layer, each opening: exposing a surface portion of each of the first contact layers, the first opening and the second opening being partially localized by a plurality of upper sidewalls Providing a boundary material; and depositing the sidewall material on the sidewalls of each of the first opening and the opening of the second opening and the first portion of each of the surface portions a second portion of the surface portion such that there is no sidewall material on the second portion; = extending the first opening π and the second opening penetrating the second portions of the surface portions for the first opening and The first mouth Exposing a surface of one of the second contact layers; the mother opening at least some of the sidewall material is removed from the opening, the first portion of the surface portion of the surface portion is exposed, and the two openings form the interconnect contact regions And wherein the first contact region is aligned with the first contact region and the interconnect region of the germanium: and the plurality of exposed portions of the contact layer Step-to-step extension: contact 2 = layer and the second contact layer, the surface of the exposed dew further extends the first __ brother to the contact layer, and the other one opens the second technical stroke «Dou a second contact layer exposing the fourth contact contact layer and the opening to form the interconnection contact regions on the two sides of the third contact layer to be aligned with the first landing region; And a plurality of electrical conductors connected to the recording contact layer, the second layer of the second layer of the second layer of the fourth layer of the fourth layer of the fourth layer of the fourth layer of the fourth layer of the semiconductor layer. The electrical conductor forming step includes: Applying a filling material over the openings to define a through-hole pattern that penetrates the plurality of through holes of the filling material, exposed to the landing areas in each of the contact layers; and/or according to the through holes A conductive material is deposited inside. The method of claim 15, wherein the solid layer: opening forming step, exposing the first contact: and performing the step extending step, exposing to the two contact layers and the fourth contact These landing areas of the layer. '&quot; 18. A kind of mask combination for a plurality of interconnected contact areas of a field, the interconnected area]: a second upper area = a plurality of contact layers - a plurality of stacked two; : θ overlaying the stack of the contact layers, the fresh combination comprising: a combination of a plurality of masks, each mask comprising a plurality of mask regions (the (four) regions for the production of the three The interconnecting regions of the two interconnected regions that are up to and including the blanks 1) are in contact with the landing regions, and the integers of N and 3 are used as the sequence numbers for the masks. The mask of one of eight is equal to 1, and the other mask is equal to 2, and then X is equal to Ν. The mask assembly of claim 18, wherein the 51 201236108 TW7070PA sidewall material acts as one of the N etch masks. 20. The mask assembly of claim 18, wherein the etch masks comprise a dummy masking region on at least one of the etch masks. 21. The mask assembly of claim 18, wherein the etch masks comprise a plurality of virtual masking regions at corresponding plurality of locations on at least some of the masks of the etch masks. 22. The mask assembly of claim 18, wherein the residual mask comprises at least one virtual masking region at a respective plurality of locations on each of the plurality of masks. 23. The mask combination of claim 18, wherein the plurality of longitudinal extents of the etched regions are substantially equal for the selected etch mask. 24. The mask combination of claim 18, wherein: the masking regions and the etched regions have a plurality of longitudinal dimensions; and for the selected masks, the masking regions and the etched regions It is said that these longitudinal dimensions are roughly equal to each other. 25. The mask combination of claim 18, wherein: the masking regions and the etched regions have a plurality of longitudinal dimensions; and for all of the masks, the masking regions and the etching The longitudinal dimensions of the region are substantially equal to each other. 26. The mask combination of claim 18, wherein the N series is greater than or equal to four. 52 201236108 1 WYU/UPA 27. A mask combination for a three-dimensional stacked IC device to create a plurality of interconnect regions that are aligned with a plurality of contact layers in an interconnect region a stack of a plurality of landing areas, the mask combination comprising: a combination of N masks, each mask comprising a plurality of masking regions and a plurality of etched regions, the etched regions being used for the three-dimensional stacked 1C device Up to and including 2 N-th contact layers of the interconnect region, the interconnect contact regions capable of being aligned with the landing regions, N being an integer equal to at least φ, and X being used for the masks The serial number of the mask so that one of the masks has X equal to 1, and the other mask has X equal to 2, and then until X is equal to N. 53