201236080 ，， 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種半導體元件及其製法，尤指—種 具有電晶體的半導體元件及其製法。 【先前技術】 近年來，半導體電子元件已經被廣泛地應用在液晶顯 示器的像素（pixel)驅動、開關元件、或靜態隨機存取:己 憶體（static random access memory，簡稱 SRA3VI)的主 負載等電子產品中。 動 在液晶顯示器的應用方面，為了符合液晶顯示器在製 程上的低溫限制與大尺寸面積的需求，其積體電路驅動元 件已經開始以頂閘極之複晶矽薄膜電晶體為其主要元件。 然而，為了進一步提升半導體本身的操作特性，習知 技術有以下幾種作法❶ 13 首先’如第6,229，177B1號美國專利與第6,38〇〇4ibi 號美國專利所示，此兩專利皆是利用離子佈值的方式來對 水平結構的通道進行斜向（角度由〇度至6〇度）摻雜且 不同種類的半導體（N型或P型）是使用不同的原子進行 摻雜，但是摻雜的強度通常隨著通道深度而減弱，又摻雜 兀後必須經過900 C至1〇5〇。(；的快速熱退火以增強摻雜的 效果，所以此類製程係要求在相當高的溫度下進行，且所 需的成本也較高。 再者，如西元2005年的應用物理學期刊（AppHed Physics Letters)第 87 卷的「C〇ntr〇1〇fthresh〇ldv〇ltagein 4 111886 201236080 pentacene thin-film transistors using carrier doping at the charge-transfer interface with organic acceptors」所示，其 係在半導體的通道上直接蓋一層受體層（acceptor layer)， 並藉由調控載子摻雜濃度，而改變元件特性（例如臨界電 壓等），但是如果結構為雙層材料時，則可能會遇到互溶 的問題，且如果調控的載子濃度沒有控制好，則容易會遇 到背面通道漏電的問題。 又，如西元2004年的應用物理學期刊（Applied Physics ❶ Letters )第 84 卷的「Enhancement-mode thin-film field-effect transistor using phosphorus-doped ( Zn,Mg ) O channel」所 示，其係在例如氧化辞（ZnO )的半導體中摻雜鎂（Mg) 以調控半導體的能隙大小，或者，在例如氧化鋅（ZnO) 的半導體中摻雜磷（P)以降低元件的電子濃度，但是此 種方式難以調整到適當的比例，且不容易控制元件的漏電 流。 馨此外，如西元2007年的應用物理學期刊（Applied Physics Letters)第 90 卷的「Improvements in the device characteristics of amorphous indium gallium zinc oxide thin-film transistors by Ar plasma treatment」所示，其係利 用鼠氣電浆來處理元件的源極與沒極，以降低元件的注入 能障，並降低元件的電阻率，但是因為只有對元件電極的 介面做處理，所以元件特性的提升有限。 因此於上述習知技術所存在之問題，如何有效且 方便地改善電子元件的元件特性，特別是提高電晶體的載 5 111886 201236080 子移動率，以增進電子元件的效能，實已成為目前亟欲解 決之課題。 【發明内容】 鑒於上述習知技術之缺失，本發明揭露一種具有電晶 體的半導體元件之製法，係包括：提供一承載板；於該承 載板上形成金屬氧化物半導體層；於該金屬氧化物半導體 層上形成介電層，使該金屬氧化物半導體層夾置於該承載 板與介電層之間；於該介電層上形成圖案化遮罩層，該圖 案化遮罩層係構成微奈米級線寬的圖案，以外露部分該介 修 電層；移除未被該圖案化遮罩層所覆蓋之介電層，以形成 介電層開孔，俾使該金屬氧化物半導體層外露於該介電層 開孔；對外露之該金屬氧化物半導體層進行表面處理，以 使該金屬氧化物半導體層之外露表面的載子濃度增加；以 及於外露之該金屬氧化物半導體層上形成源極金屬層與汲 極金屬層。 本發明揭露另一種具有電晶體的半導體元件之製 φ 法，係包括：提供一承載板；於該承載板上形成金屬氧化 物半導體層，該承載板是單一材質層、或是包括導電層與 其一側上的絕緣層，且該金屬氧化物半導體層係設於該絕 緣層上；對部分該金屬氧化物半導體層之頂表面進行表面 處理，以令部分該金屬氧化物半導體層之頂表面的載子濃 度增加，俾使該金屬氧化物半導體層之表層構成具有微奈 米級線寬的圖案的高載子濃度子層；以及於該金屬氧化物 半導體層上形成源極金屬層與汲極金屬層。 s 6 111886 201236080 前述之具有電晶體的半導體元件之製法中，復可包括 於該金屬氧化物半導體層上形成介電層，並於該介電層上 形成閘極金屬層，該閘極金屬層係可間隔設置於該源極金 屬層與;及極金屬層之間，且該源極金屬層與沒極金屬層復 各自延伸通過該金屬氧化物半導體層的侧壁，並延伸至該 承載板上。 依上述之具有電晶體的半導體元件之製法，該承載板 之材質可為玻璃、塑膠或石夕等，且微奈米級線寬的圖案係 遮罩層開孔，該遮罩層開孔可為圓形孔、矩形孔、三角形 孔、圓環形孔、十字形孔或不規則孔。 依上述之製法，該金屬氧化物半導體層之材質可為氧 化鋅（zmc oxlde，Zn0 )、氧化銦辞（滅咖★⑻心， ιζο)、或氧化銦鎵鋅（indiumgaUiumzinc〇xide，igz〇) 等’且該介電層之材質可為聚（4_乙基苯酚） (poly-(4-vinylphenol) ’簡稱PVP )、聚甲基丙烯酸甲酉旨 φ (Polymethylmethacrylate，簡稱 PMMA)、或聚乙烯醇 (Polyvinyl Alcohol，簡稱 PVA)，但不限於此。 又依上述之製法，表面處理該金屬氧化物半導體層之 方式可為包含光退火處理等各種可以提升半導體摻雜濃度 之製程方法，例如氬氣電漿、氧氣電漿、氫氣電漿、紫外 光(UV)、或雷射退火等。 依上述之具有電晶體的半導體元件之製法，該圖案化 遮罩層係可間隔設置於該源極金屬層與汲極金屬層之間， 且該源極金屬層與汲極金屬層復可各自延伸通過該金屬氧 111886 7 201236080 化物半導體層的側壁，並延伸至該承載板上。 於本發明之製法中，該承載板可包括導電層與其一侧 上的絕緣層，且該金屬氧化物半導體層係設於該絕緣層上。 依上述之製法，該導電層可為經摻雜的半導體層，該 承載板復可包括設於該導電層另一側上的基底層，俾使該 導電層設於該絕緣層與該基底層之間。 又依上述之具有電晶體的半導體元件之製法，該圖案 化遮罩層之材質可為金屬或絕緣材料。 本發明復揭露一種具有電晶體的半導體元件，係包 鲁 括：承載板；金屬氧化物半導體層，係設於該承載板上； 介電層，係設於該金屬氧化物半導體層上，該介電層係構 成微奈米級線寬的圖案，俾外露部分該金屬氧化物半導體 層，該金屬氧化物半導體層之外露表面的載子濃度大於該 金屬氧化物半導體層内部的載子濃度；圖案化遮罩層，係 設於該介電層之頂面上；以及源極金屬層與汲極金屬層， 係設於外露之該金屬氧化物半導體層上。 Φ 本發明揭露另一種具有電晶體的半導體元件，係包 括：承載板；金屬氧化物半導體層，係設於該承載板上， 該金屬氧化物半導體層之表層具有微奈米級線寬的圖案的 高載子濃度子層，該承載板是單一材質層、或是包括導電 層與其一側上的絕緣層，且該金屬氧化物半導體層係設於 該絕緣層上；以及源極金屬層與汲極金屬層，係分設於該 金屬氧化物半導體層兩端之表面上。 前述之具有電晶體的半導體元件中，復可包括介電層 8 111886 201236080 與閘極金屬層，該介電層係設於該金屬氧化物半導體層 上，該閘極金屬層係設於該介電層上，該閘極金屬層係可 間隔設置於該源極金屬層與汲極金屬層之間，且該源極金 屬層與汲極金屬層復各自延伸通過該金屬氧化物半導體層 的側壁，並延伸至該承載板上。 依上述之半導體元件，該承載板之材質可為玻璃、塑 膠或矽等，且微奈米級線寬的圖案係介電層開孔，該介電 層開孔可包含圓形孔、矩形孔、三角形孔、圓環形孔、十 ❶ 字形孔或不規則孔。又依上述之半導體元件，該金屬氧化 物半導體層之材質可為氧化鋅（zinc oxide，ZnO )、氧化 銦辞（indium zinc oxide，IZO)、或氧化銦鎵鋅（indium gallium zinc oxide，IGZO)等，且該介電層之材質可為聚 (4-乙基苯酴）（poly-(4-vinylphenol)，簡稱 PVP)、聚甲 基丙稀酸甲醋（Polymethylmethacrylate，簡稱 PMMA)、或 聚乙婦醇(Polyvinyl Alcohol，簡稱PVA)，但不限於此。 馨 依上述之具有電晶體的半導體元件，該圖案化遮罩層 係可間隔設置於該源極金屬層與汲極金屬層之間，且該源 極金屬層與汲極金屬層復可各自延伸通過該金屬氧化物半 導體層的側壁，並延伸至該承載板上。 於本發明之半導體元件中，該承載板可包括導電層與 其一側上的絕緣層，且該金屬氧化物半導體層係設於該絕 緣層上。 依上述之半導體元件，該導電層可為經摻雜的半導體 層，該承載板復可包括設於該導電層另一側上的基底層， 111886 9 201236080 俾使該導電層設於該絕緣層與該基底層之間。 又依上述之具有電晶體的半導體元件，該圖案化遮罩 層之材質可為金屬或絕緣材料。 由上可知，本發明係於頂閘極或底間極電晶體的通道 處形成微奈来等級的圖形摻雜，使得通道區域中的導電率 上升，造成有效載子遷移率明顯的提高，以增進對於周遭 電路的電流驅動力；此外，本發明之具有電晶體的半導體 元件的源極㈣極可直接形成在高載子遷移率的通道上， 這樣不僅能夠減少製程步驟，也能降低成本，更能夠降低φ 接觸電阻’形成歐姆麵，進*提高整體元件效能。 【實施方式】 以下藉由特定的具體實施例說明本發明之實施方 式，熟悉此技藝之人士可由本說明書所揭示之内容輕易地 暸解本發明之其他優點及功效。 須知’本說明書所附圖式所繪示之結構、比例、大小 等’均僅用以配合說明書所揭示之内容，以供熟悉此技藝 之人士之瞭解與閱讀，並未完全按照實際比例來繪製，且 · 並非用以限定本發明可實施之限定條件，故不具技術上之 實質意義’任何結構之修飾、比例關係之改變或大小之調 整’在不影響本發明所能產生之功效及所能達成之目的 下’均應仍落在本發明所揭示之技術内容得能涵蓋之範圍 内。同時，本說明書中所引用之如「上」、「頂」、「底」 及「一」等之用語，亦僅為便於敘述之明暸，而非用以限 定本發明可實施之範圍，其相對關係之改變或調整，在無 10 111886 201236080 實質變更技術内容下，當亦视為本發明可實施之範疇。 第一實施例 請參閱第1A至1G圖，係本發明之具有電晶體的半導 體元件之製法之第一實施例的剖視圖，其中，第1B’與1C， 圖係第1B與1C圖之另一實施態樣，第iG，圖係第ig圖 之俯視圖。 如第1A圖所示，提供一承載板1〇,該承載板1〇之材 質可為玻璃、塑膠或矽等，並於該承載板1〇上形成金屬氧 化物半導體層11，該金屬氧化物半導體層11之材質可為 氧化鋅（zinc oxide，ZnO )、氧化銦鋅（indiUm zinc oxide， IZO )、或氧化銦錄鋅（indium gallium zinc oxide，IGZO )， 該金屬氧化物半導體層11之材質較佳為非晶氧化銦鎵鋅 (amorphous In-Ga-Zn-Ο，簡稱 a-IGZO)等，且於該金屬 氧化物半導體層11上形成介電層12,該介電層12之材質 可為聚乙基笨酚）（poly-(4-vinylphenol)，簡稱 PVP )、 &曱基丙浠酸甲醋（Polymethylmethacrylate，簡稱 MMA)或 t 乙埽醇(p〇iyvinyi Aic〇h〇i，簡稱 pva)，但 不限於此。 如第1B至1〇圖所示，於該介電層12上形成金屬材 質的遮罩層13 ’迷於該遮罩層13上形成阻層14，接著以 德1奈米壓印模具ls壓印該阻層14以構成圖案化阻層14，， 且移除未被該圖案化阻層14’覆蓋的該遮罩層13以構成圖 案化遮罩層13’，最後，移除該圖案化阻層14,。 或者’如第IB，、1C’與id圖所示，於該介電層12 11 ^1886 201236080 上塗佈複數微奈米球16，並於該介電層12與微奈米球16 上形成金屬材質的遮罩層13，接著移除該微奈米球16及 其上的遮罩層13以構成圖案化遮罩層13’。 如第1D圖所示，此時該介電層12上形成有圖案化遮 罩層13’，該圖案化遮罩層13’係構成微奈米級（一般是10 奈米至999微米的範圍）線寬的圖案，且該圖案化遮罩層 13’具有遮罩層開孔130，以外露部分該介電層12 ;於本實 施例中，該圖案化遮罩層13’之圖形係以複數個圓形孔作 為例示，且舉例來說，該遮罩層開孔130之孔徑可為5奈 籲 米至50微米，當然，該遮罩層開孔130亦可為矩形孔、三 角形孔、圓環形孔、十字形孔、不規則形狀孔、或其他形 狀之孔洞，而不以圓形孔為限。 如第1E圖所示，移除未被該圖案化遮罩層13’所覆蓋 之介電層12，以形成介電層開孔120，俾使該金屬氧化物 半導體層11外露於該介電層開孔120，其中，移除該介電 層12之方式可為氧氣電漿、氬氣電漿、或濕式蝕刻，且該 φ 介電層開孔120可為圓形孔、矩形孔、三角形孔、圓環形 孔、十字形孔、不規則形狀孔、或其他形狀之孔洞。 如第1F圖所示，對外露之該金屬氧化物半導體層11 進行表面處理，以令該金屬氧化物半導體層11之外露表面 的載子濃度增加，俾使該金屬氧化物半導體層11之表層構 成高載子濃度子層111，其中，表面處理該金屬氧化物半 導體層11之方式可為包含光退火處理等各種可以提升半 導體摻雜濃度之製程方法，例如氬氣電漿、氧氣電漿、氫201236080, 6, invention description: TECHNICAL FIELD The present invention relates to a semiconductor device and a method of fabricating the same, and more particularly to a semiconductor device having a transistor and a method of fabricating the same. [Prior Art] In recent years, semiconductor electronic components have been widely used in pixel driving, switching elements, or static random access of a liquid crystal display: a main load of a static random access memory (SRA3VI). In electronic products. In the application of liquid crystal displays, in order to meet the low temperature limit and large size of the liquid crystal display in the process, the integrated circuit driving element has begun to use the top gate polysilicon film transistor as its main component. However, in order to further enhance the operational characteristics of the semiconductor itself, the prior art has the following several methods: 13 First, as shown in U.S. Patent No. 6,229,177 B1 and U.S. Patent No. 6,38,4, to U.S. Ion cloth values are used to dope the horizontal structure channels diagonally (angles from 6 to 6 degrees) and different types of semiconductors (N-type or P-type) are doped with different atoms, but doped The strength of the impurity usually decreases with the depth of the channel, and it must pass 900 C to 1 〇 5 兀 after doping. Rapid thermal annealing to enhance the doping effect, so such processes are required to be carried out at relatively high temperatures and at a higher cost. Furthermore, such as the 2005 Applied Physics Journal (AppHed) Physics Letters), Volume 87, "C〇ntr〇1〇fthresh〇ldv〇ltagein 4 111886 201236080 pentacene thin-film transistors using carrier doping at the charge-transfer interface with organic acceptors", which is shown on the channel of the semiconductor Directly cover an acceptor layer and change component characteristics (such as threshold voltage, etc.) by adjusting the carrier doping concentration, but if the structure is a two-layer material, it may encounter mutual solubility problems. And if the concentration of the regulated carrier is not well controlled, it is easy to encounter the problem of leakage of the back channel. Also, for example, "Enhancement-mode thin-film", Volume 84, Applied Physics ❶ Letters, 2004 Field-effect transistor using phosphorus-doped (Zn,Mg) O channel", which is doped in a semiconductor such as oxidized (ZnO) Magnesium (Mg) regulates the energy gap of a semiconductor, or is doped with phosphorus (P) in a semiconductor such as zinc oxide (ZnO) to reduce the electron concentration of the element, but this method is difficult to adjust to an appropriate ratio, and It is easy to control the leakage current of the component. In addition, as in the "Improvements in the device characteristics of amorphous indium gallium zinc oxide thin-film transistors by Ar plasma treatment", Volume 90 of the Applied Physics Letters, 2007 It is shown that it uses the rat gas plasma to process the source and the immersion of the component to reduce the injection energy barrier of the component and reduce the resistivity of the component, but since only the interface of the component electrode is processed, the component characteristics are improved. Therefore, in the above-mentioned problems of the prior art, how to effectively and conveniently improve the component characteristics of the electronic component, in particular, to improve the sub-movement rate of the transistor to improve the performance of the electronic component has become the present I want to solve the problem. SUMMARY OF THE INVENTION In view of the above-mentioned deficiencies of the prior art, the present invention discloses a method for fabricating a semiconductor device having a transistor, comprising: providing a carrier plate; forming a metal oxide semiconductor layer on the carrier plate; Forming a dielectric layer on the semiconductor layer, sandwiching the metal oxide semiconductor layer between the carrier and the dielectric layer; forming a patterned mask layer on the dielectric layer, the patterned mask layer forming a micro layer a pattern of a nano-scale line width, the exposed portion of the dielectric layer; removing a dielectric layer not covered by the patterned mask layer to form a dielectric layer opening, and etching the metal oxide semiconductor layer Exposed to the opening of the dielectric layer; surface-treating the exposed metal oxide semiconductor layer to increase the concentration of the carrier on the exposed surface of the metal oxide semiconductor layer; and on the exposed metal oxide semiconductor layer A source metal layer and a drain metal layer are formed. The invention discloses another method for fabricating a semiconductor device having a transistor, comprising: providing a carrier plate; forming a metal oxide semiconductor layer on the carrier plate, the carrier plate being a single material layer or comprising a conductive layer and An insulating layer on one side, and the metal oxide semiconductor layer is disposed on the insulating layer; and a portion of the top surface of the metal oxide semiconductor layer is surface-treated to partially cover a top surface of the metal oxide semiconductor layer The concentration of the carrier is increased, and the surface layer of the metal oxide semiconductor layer constitutes a high carrier concentration sublayer having a pattern of a micron-meter line width; and a source metal layer and a drain are formed on the metal oxide semiconductor layer Metal layer. s 6 111886 201236080 In the foregoing method for fabricating a semiconductor device having a transistor, the method further includes forming a dielectric layer on the metal oxide semiconductor layer, and forming a gate metal layer on the dielectric layer, the gate metal layer The source metal layer and the electrodeless metal layer respectively extend through the sidewall of the metal oxide semiconductor layer and extend to the carrier plate. on. According to the above method for manufacturing a semiconductor device having a transistor, the material of the carrier plate may be glass, plastic or Shixia, and the pattern of the micro-nano-scale line width is an opening of the mask layer, and the opening of the mask layer may be It is a circular hole, a rectangular hole, a triangular hole, a circular hole, a cross hole or an irregular hole. According to the above method, the material of the metal oxide semiconductor layer may be zinc oxide (zmc oxlde, Zn0 ), indium oxide (inactivated coffee ★ (8) heart, ιζο), or indium gallium zinc oxide (indiumgaUiumzinc〇xide, igz〇) And the material of the dielectric layer may be poly(4-ethylphenol) (poly-(4-vinylphenol) 'PVP for short), polymethylmethacrylate (PMMA), or polyethylene Polyvinyl Alcohol (PVA), but is not limited thereto. According to the above method, the surface treatment of the metal oxide semiconductor layer may be a method including a photo annealing treatment, which can improve the doping concentration of the semiconductor, such as argon plasma, oxygen plasma, hydrogen plasma, ultraviolet light. (UV), or laser annealing. According to the above method for fabricating a semiconductor device having a transistor, the patterned mask layer may be disposed between the source metal layer and the drain metal layer, and the source metal layer and the drain metal layer may be respectively provided. Extending through the sidewall of the metal oxide 111886 7 201236080 compound semiconductor layer and extending onto the carrier plate. In the method of the present invention, the carrier sheet may include a conductive layer and an insulating layer on one side thereof, and the metal oxide semiconductor layer is disposed on the insulating layer. According to the above method, the conductive layer may be a doped semiconductor layer, and the carrier plate may include a base layer disposed on the other side of the conductive layer, and the conductive layer is disposed on the insulating layer and the base layer between. Further, according to the above method for fabricating a semiconductor device having a transistor, the material of the patterned mask layer may be a metal or an insulating material. The present invention recloses a semiconductor device having a transistor, comprising: a carrier plate; a metal oxide semiconductor layer disposed on the carrier plate; and a dielectric layer disposed on the metal oxide semiconductor layer, The dielectric layer forms a pattern of a micron-level line width, and a portion of the metal oxide semiconductor layer is exposed, and a carrier concentration of the exposed surface of the metal oxide semiconductor layer is greater than a carrier concentration inside the metal oxide semiconductor layer; A patterned mask layer is disposed on a top surface of the dielectric layer; and a source metal layer and a drain metal layer are disposed on the exposed metal oxide semiconductor layer. Φ The present invention discloses another semiconductor device having a transistor, comprising: a carrier plate; a metal oxide semiconductor layer disposed on the carrier plate, the surface layer of the metal oxide semiconductor layer having a micron-line width pattern a high carrier concentration sublayer, the carrier plate is a single material layer, or includes a conductive layer and an insulating layer on one side thereof, and the metal oxide semiconductor layer is disposed on the insulating layer; and the source metal layer and The drain metal layer is provided on the surfaces of both ends of the metal oxide semiconductor layer. In the foregoing semiconductor device having a transistor, the dielectric layer 8 111886 201236080 and a gate metal layer are disposed on the metal oxide semiconductor layer, and the gate metal layer is disposed on the gate The gate metal layer may be disposed between the source metal layer and the drain metal layer, and the source metal layer and the gate metal layer respectively extend through the sidewall of the metal oxide semiconductor layer. And extend to the carrier board. According to the above semiconductor component, the material of the carrier plate may be glass, plastic or germanium, and the micro-nano-line width pattern is a dielectric layer opening, and the dielectric layer opening may include a circular hole and a rectangular hole. , triangular holes, circular holes, ten-shaped holes or irregular holes. Further, according to the above semiconductor device, the material of the metal oxide semiconductor layer may be zinc oxide (ZnO), indium zinc oxide (IZO), or indium gallium zinc oxide (IGZO). Etc., and the material of the dielectric layer may be poly-(4-vinylphenol) (PVP), polymethylmethacrylate (PMMA), or poly Polyvinyl Alcohol (PVA), but not limited to this. According to the above semiconductor device having a transistor, the patterned mask layer may be disposed between the source metal layer and the drain metal layer, and the source metal layer and the drain metal layer may each extend Passing through the sidewall of the metal oxide semiconductor layer and extending to the carrier plate. In the semiconductor device of the present invention, the carrier may include a conductive layer and an insulating layer on one side thereof, and the metal oxide semiconductor layer is provided on the insulating layer. According to the above semiconductor device, the conductive layer may be a doped semiconductor layer, and the carrier plate may include a base layer disposed on the other side of the conductive layer, 111886 9 201236080 俾 the conductive layer is disposed on the insulating layer Between the base layer and the base layer. Further, in the above semiconductor device having a transistor, the material of the patterned mask layer may be a metal or an insulating material. It can be seen from the above that the present invention forms a micron-grade pattern doping at the channel of the top gate or the bottom pole transistor, so that the conductivity in the channel region rises, resulting in a significant increase in effective carrier mobility. The current driving force for the surrounding circuit is improved; in addition, the source (four) electrode of the semiconductor device with a transistor of the present invention can be directly formed on the channel of high carrier mobility, thereby not only reducing the process steps but also reducing the cost. It is also possible to reduce the φ contact resistance to form an ohmic surface, and to improve the overall component performance. [Embodiment] The embodiments of the present invention are described below by way of specific embodiments, and those skilled in the art can readily understand the other advantages and functions of the present invention from the disclosure. It should be noted that the structures, proportions, sizes, etc. shown in the drawings of the present specification are only used to cope with the contents disclosed in the specification for the understanding and reading of those skilled in the art, and are not drawn in full proportion. And / are not intended to limit the conditions for the implementation of the present invention, and therefore do not have technical significance. 'Modification of any structure, change of proportional relationship or adjustment of size' does not affect the effects and functions of the present invention. The objectives of the present invention should still fall within the scope of the technical contents disclosed in the present invention. In the meantime, the terms "upper", "top", "bottom" and "one" are used in this specification for the purpose of description and are not intended to limit the scope of the invention. Changes or adjustments to the relationship are considered to be within the scope of the invention, without departing from the spirit of the invention. 1A to 1G, which is a cross-sectional view showing a first embodiment of a method for fabricating a semiconductor device having a transistor according to the present invention, wherein 1B' and 1C, FIG. 1B and FIG. The implementation aspect, the i-th, is a top view of the ig diagram. As shown in FIG. 1A, a carrier board 1 is provided. The material of the carrier board 1 can be glass, plastic or tantalum, and a metal oxide semiconductor layer 11 is formed on the carrier board 1 . The material of the semiconductor layer 11 may be zinc oxide (ZnO), indium oxide zinc (IZO), or indium gallium zinc oxide (IGZO), and the material of the metal oxide semiconductor layer 11 Preferably, an amorphous in-Ga-Zn-germanium (a-IGZO) or the like is formed, and a dielectric layer 12 is formed on the metal oxide semiconductor layer 11. The material of the dielectric layer 12 can be Poly-(4-vinylphenol) (PVP), & Polymethylmethacrylate (MMA) or t-acetol (p〇iyvinyi Aic〇h〇i, Referred to as pva), but not limited to this. As shown in FIG. 1B to FIG. 1 , a mask layer 13 of a metal material is formed on the dielectric layer 12 to form a resist layer 14 on the mask layer 13 , followed by a stamping die ls pressure of 1 nm. The resist layer 14 is printed to form the patterned resist layer 14, and the mask layer 13 not covered by the patterned resist layer 14' is removed to form the patterned mask layer 13'. Finally, the patterning is removed. Resistive layer 14, Alternatively, as shown in the IB, 1C' and id diagrams, a plurality of micro-nanospheres 16 are coated on the dielectric layer 12 11 ^ 1886 201236080 and formed on the dielectric layer 12 and the micro-nanosphere 16 The mask layer 13 of metal material is then removed from the micro-nanosphere 16 and the mask layer 13 thereon to form a patterned mask layer 13'. As shown in FIG. 1D, a patterned mask layer 13' is formed on the dielectric layer 12, and the patterned mask layer 13' constitutes a micron-level (generally ranging from 10 nm to 999 μm). a pattern of line widths, and the patterned mask layer 13' has a mask layer opening 130, and the dielectric layer 12 is exposed; in the embodiment, the pattern of the patterned mask layer 13' is A plurality of circular holes are exemplified. For example, the aperture of the mask layer opening 130 may be from 5 nanometers to 50 micrometers. Of course, the mask layer opening 130 may also be a rectangular hole or a triangular hole. Circular, perforated, irregularly shaped, or other shaped holes, not limited to circular holes. As shown in FIG. 1E, the dielectric layer 12 not covered by the patterned mask layer 13' is removed to form a dielectric layer opening 120, and the metal oxide semiconductor layer 11 is exposed to the dielectric. The layer opening 120, wherein the dielectric layer 12 is removed by oxygen plasma, argon plasma, or wet etching, and the φ dielectric layer opening 120 can be a circular hole or a rectangular hole. A triangular hole, a circular hole, a cross hole, an irregular shape hole, or a hole of other shape. As shown in FIG. 1F, the exposed metal oxide semiconductor layer 11 is surface-treated to increase the concentration of the carrier on the exposed surface of the metal oxide semiconductor layer 11 to cause the surface of the metal oxide semiconductor layer 11 to be layered. The high-concentration concentration sub-layer 111 is formed. The surface treatment of the metal oxide semiconductor layer 11 may be a method including a photo-annealing treatment, such as argon plasma, oxygen plasma, or the like. hydrogen
S 12 111886 201236080 氣電漿、紫外光(uv)、或雷射退火。 如第1G與1G，圖所示，於外露之該金屬氧化物半導體 層11上形成源極金屬層17與汲極金屬層18，該圖案化遮 罩層13’係間隔設置於該源極金屬層17與汲極金屬層18 之間，該源極金屬層17與汲極金屬層18復可延伸通過該 金屬氧化物半導體層11的側壁，並延伸至該承載板1〇上， 至此即完成本發明之頂閘極（top gate)型式的具有電晶體 的半導體元件，即該圖案化遮罩層13,係作為閘極使用。 本發明復揭露一種具有電晶體的半導體元件，係包 括：承載板10;金屬氧化物半導體層n，係設於該承載板 10上；介電層12，係設於該金屬氧化物半導體層u上， 該介電層12係構成微奈米級線寬的圖案，俾外露部分該金 屬氧化物半導體層11，該金屬氧化物半導體層u之外露 表面的載子濃度大於該金屬氧化物半導體層u内部的載 子濃度；圖案化遮罩層13’，係設於該介電層12之頂面上； # 以及源極金屬層17與汲極金屬層18，係設於外露之該金 屬氧化物半導體層11上。 依上述之結構，該承載板10之材質可為玻璃、塑膠 或矽等’且該微奈米級線寬的圖案係介電層開孔12〇，該 介電層開孔120可為圓形孔、矩形孔、三角形孔、圓環形 孔、十字形孔、不規則形狀孔、或其他形狀之孔洞。 於本發明之具有電晶體的半導體元件中，該金屬氧化 物半導體層11之材質可為氧化鋅（zinc oxide，ZnO)、 氧化銦鋅（indium zinc oxide ’ IZO )、或氧化銦鎵鋅（indium 111886 13 201236080 gallium zinc oxide > IGZO )，該金屬氧化物半導體層11 之材質較佳為非晶氧化姻錄辞（amorphous In-Ga-Zn-O， 簡稱a-IGZO)等’該介電層12之材質可為聚（4-乙基苯 酚）（p〇ly-(4-vinylphenol)，簡稱 PVP)、聚曱基丙稀酸 甲酯（Polymethylmethacrylate，簡稱 PMMA)、或聚乙烯醇 (Polyvinyl Alcohol ’簡稱PVA)，但不限於此。該圖案化遮 罩層13 ’之材質可為金屬材料、絕緣層材料，但不限於此。 又依前述之半導體元件，該圖案化遮罩層13,係間隔 設置於該源極金屬層17與汲極金屬層18之間，且該源極 · 金屬層17與汲極金屬層18復可各自延伸通過該金屬氧化 物半導體層11的側壁，並延伸至該承載板1 〇上。 請參閱第2圖，分別係習知與本發明之具有電晶體的 半導體元件的汲極電流（ID)對閘極電壓（VG)的關係圖， 其中，A是代表習知之具有電晶體的半導體元件，B是代 表本發明之具有電晶體的半導體元件，習知之遮罩層未形 成有複數個圓形孔，而本發明之圖案化遮罩層13’具有複 φ 數個圓形孔，兩者其餘之參數均相同，該承載板10之材質 係玻璃，該金屬氧化物半導體層11之材質係50奈米厚的 非晶氧化銦鎵辞（amorphous In-Ga-Zn-Ο，簡稱 a-IGZO)， 該介電層12之材質係420奈米厚的聚（4-乙基苯酚） (poly-(4-vinylphenol)，簡稱 PVP)，該源極金屬層 17 與 汲極金屬層18之材質係鋁，該圖案化遮罩層13,之材質係 100奈米厚的銘。 承上述，從該實驗中另計算出元件特性比較表如下：S 12 111886 201236080 Gas plasma, ultraviolet (uv), or laser annealing. As shown in FIGS. 1G and 1G, a source metal layer 17 and a gate metal layer 18 are formed on the exposed metal oxide semiconductor layer 11, and the patterned mask layer 13' is spaced apart from the source metal. Between the layer 17 and the gate metal layer 18, the source metal layer 17 and the gate metal layer 18 extend through the sidewall of the metal oxide semiconductor layer 11 and extend onto the carrier plate 1 to complete The top gate type of semiconductor device having a transistor, i.e., the patterned mask layer 13, of the present invention is used as a gate. The present invention discloses a semiconductor device having a transistor, comprising: a carrier 10; a metal oxide semiconductor layer n is disposed on the carrier 10; and a dielectric layer 12 is disposed on the metal oxide semiconductor layer The dielectric layer 12 is formed into a pattern of a micron-level line width, and the metal oxide semiconductor layer 11 is exposed, and the carrier concentration of the exposed surface of the metal oxide semiconductor layer u is larger than the metal oxide semiconductor layer. u internal carrier concentration; patterned mask layer 13' is disposed on the top surface of the dielectric layer 12; # and the source metal layer 17 and the drain metal layer 18 are disposed on the exposed metal oxide On the semiconductor layer 11. According to the above structure, the material of the carrier board 10 may be glass, plastic or germanium, and the micro-nano-line width pattern is a dielectric layer opening 12, and the dielectric layer opening 120 may be circular. Holes, rectangular holes, triangular holes, circular holes, cross-shaped holes, irregularly shaped holes, or other shaped holes. In the semiconductor device having a transistor of the present invention, the material of the metal oxide semiconductor layer 11 may be zinc oxide (ZnO), indium zinc oxide (IZO), or indium gallium zinc oxide (indium). 111886 13 201236080 gallium zinc oxide > IGZO ), the material of the metal oxide semiconductor layer 11 is preferably amorphous in-Ga-Zn-O (abbreviated as a-IGZO), etc. The material of 12 may be poly(4-ethylphenol) (p〇ly-(4-vinylphenol), abbreviated as PVP), polymethylmethacrylate (PMMA), or polyvinyl alcohol (Polyvinyl Alcohol). 'PVA for short, but not limited to this. The material of the patterned mask layer 13' may be a metal material or an insulating layer material, but is not limited thereto. In addition, according to the foregoing semiconductor device, the patterned mask layer 13 is disposed between the source metal layer 17 and the gate metal layer 18, and the source metal layer 17 and the gate metal layer 18 are reconfigurable. Each extends through the sidewall of the metal oxide semiconductor layer 11 and extends onto the carrier plate 1 . Please refer to FIG. 2, which is a diagram showing the relationship between the gate current (ID) and the gate voltage (VG) of a semiconductor device having a transistor of the present invention, wherein A is a conventional semiconductor having a transistor. The element B is a semiconductor element having a transistor of the present invention. The conventional mask layer is not formed with a plurality of circular holes, and the patterned mask layer 13' of the present invention has a plurality of circular holes of φ, two The remaining parameters are the same, the material of the carrier plate 10 is glass, and the material of the metal oxide semiconductor layer 11 is 50 nm thick amorphous indium oxide gallium (amorphous In-Ga-Zn-Ο, a-refer to a- IGZO), the dielectric layer 12 is made of 420 nm thick poly(4-ethylphenol) (PVP), and the source metal layer 17 and the drain metal layer 18 The material is aluminum, and the patterned mask layer 13 is made of 100 nm thick. Based on the above, a comparison table of component characteristics calculated from the experiment is as follows:
S 14 111886 201236080 習知元件A 本發明元件B 最大載子遷移率 2 β .max(cm /Vs) 4.6 79.18 開關比（〇n/Off ratio) 3.8xl05 2.7xl06 由上可知，本發明之具有電晶體的半導體元件可大幅 提升載子遷移率約π倍，且開關比也能維持在1〇6個數量 級。 ®第二實施例 請參閱第3A至3F圖，係本發明之具有電晶體的半導 體元件之製法之第二實施例的剖視圖，其中，第3B’與3C’ 圖係第3B與3C圖之另一實施態樣。 本實施例與前一實施例之主要差異在於前一實施例 是先形成介電層12、再形成高載子濃度子層111，而本實 施例是先形成高載子濃度子層111、再形成介電層12，詳 ·> 如下所述，且相同的構件將不再重複說明。 如第3A圖所示，提供一承載板10，並於該承載板10 上形成金屬氧化物半導體層11。 如第3B至3D圖所示，於該金屬氧化物半導體層11 上形成阻層14，接著以微奈米壓印模具15壓印該阻層14 以構成圖案化阻層14’，且對外露之該金屬氧化物半導體 層11進行表面處理，以令該金屬氧化物半導體層11之外 露表面的載子濃度增加，俾使該金屬氧化物半導體層11 之表層構成具有微奈米級線寬的圖案的高載子濃度子層 15 111886 201236080 111，最後，移除該圖案化阻層14’。 或者，如第3B’、3C’與3D圖所示，於該金屬氧化物 半導體層11上塗佈複數微奈米球16，並對外露之該金屬 氧化物半導體層11進行表面處理，以令該金屬氧化物半導 體層11之外露表面的載子濃度增加，俾使該金屬氧化物半 導體層11之表層構成具有微奈米級線寬的圖案的高載子 濃度子層111，最後，移除該等微奈米球16。 如第3E圖所示，於該金屬氧化物半導體層11上形成 介電層12，於該介電層12上形成閘極金屬層19。 如第3F圖所示，於外露之該金屬氧化物半導體層11 上形成源極金屬層Π與汲極金屬層18，該閘極金屬層19 係間隔設置於該源極金屬層17與汲極金屬層18之間，該 源極金屬層17與汲極金屬層18復可延伸通過該金屬氧化 物半導體層11的側壁，並延伸至該承載板10上，至此即 完成本發明之頂閘極（top gate )型式的具有電晶體的半導 體元件。 本發明復揭露另一種具有電晶體的半導體元件，係包 括：承載板10，該承載板10是單一材質層；金屬氧化物 半導體層11，係設於該承載板10上，該金屬氧化物半導 體層11之表層具有微奈米級線寬的圖案的高載子濃度子 層111 ;以及源極金屬層17與汲極金屬層18，係分設於該 金屬氧化物半導體層Π兩端之表面上。 於本發明之具有電晶體的半導體元件中，復包括介電 層12與閘極金屬層19,該介電層12係設於該金屬氧化物S 14 111886 201236080 Conventional element A Element B of the invention Maximum carrier mobility 2 β .max (cm /Vs) 4.6 79.18 Switching ratio (〇n/Off ratio) 3.8xl05 2.7xl06 From the above, the present invention has electricity The semiconductor component of the crystal can greatly increase the carrier mobility by about π times, and the switching ratio can be maintained at the order of 1 〇 6 orders of magnitude. ® Second Embodiment Please refer to FIGS. 3A to 3F, which are cross-sectional views showing a second embodiment of the method for fabricating a semiconductor device having a transistor of the present invention, wherein the 3B' and 3C' diagrams are the other of the 3B and 3C patterns. An implementation. The main difference between this embodiment and the previous embodiment is that in the previous embodiment, the dielectric layer 12 is formed first, and the high carrier concentration sub-layer 111 is formed. In this embodiment, the high carrier concentration sub-layer 111 is formed first, and then The dielectric layer 12 is formed, as described below, and the same components will not be repeatedly described. As shown in FIG. 3A, a carrier 10 is provided, and a metal oxide semiconductor layer 11 is formed on the carrier 10. As shown in FIGS. 3B to 3D, a resist layer 14 is formed on the metal oxide semiconductor layer 11, and then the resist layer 14 is imprinted by the micro-nano imprinting mold 15 to form a patterned resist layer 14', and exposed. The metal oxide semiconductor layer 11 is surface-treated to increase the concentration of the carrier on the exposed surface of the metal oxide semiconductor layer 11, so that the surface layer of the metal oxide semiconductor layer 11 has a line width of micron. The patterned high carrier concentration sublayer 15 111886 201236080 111, and finally, the patterned resist layer 14' is removed. Alternatively, as shown in FIGS. 3B', 3C' and 3D, a plurality of micro-nanospheres 16 are coated on the metal oxide semiconductor layer 11, and the exposed metal oxide semiconductor layer 11 is surface-treated. The concentration of the carrier on the exposed surface of the metal oxide semiconductor layer 11 is increased, so that the surface layer of the metal oxide semiconductor layer 11 constitutes the high carrier concentration sub-layer 111 having a pattern of a micron-meter line width, and finally, removed. These micro-nano balls 16. As shown in Fig. 3E, a dielectric layer 12 is formed on the metal oxide semiconductor layer 11, and a gate metal layer 19 is formed on the dielectric layer 12. As shown in FIG. 3F, a source metal layer Π and a drain metal layer 18 are formed on the exposed metal oxide semiconductor layer 11, and the gate metal layer 19 is spaced apart from the source metal layer 17 and the drain Between the metal layers 18, the source metal layer 17 and the gate metal layer 18 extend through the sidewall of the metal oxide semiconductor layer 11 and extend onto the carrier 10, thereby completing the top gate of the present invention. A (top gate) type semiconductor device having a transistor. The present invention further discloses a semiconductor device having a transistor, comprising: a carrier board 10, the carrier board 10 is a single material layer; a metal oxide semiconductor layer 11 is disposed on the carrier board 10, the metal oxide semiconductor The surface layer of the layer 11 has a high carrier concentration sub-layer 111 of a micron-scale line width pattern; and the source metal layer 17 and the gate metal layer 18 are disposed on the surface of the metal oxide semiconductor layer on. In the semiconductor device with a transistor of the present invention, a dielectric layer 12 and a gate metal layer 19 are provided, and the dielectric layer 12 is provided on the metal oxide.
S 16 111886 201236080 半導體層11上，該閘極金屬層19係設於該介電層12上。 依上述之具有電晶體的半導體元件，該閘極金屬層19 係間隔設置於該源極金屬層17與汲極金屬層18之間，且 該源極金屬層17與浪極金屬層18復各自延伸通過該金屬 氧化物半導體層丨1的側壁，並延伸至該承載板10上。 第三實施例 請參閱第4 A與4B圖，係本發明之具有電晶體的半導 體元件之第三實施例的剖視圖，其中，第4B圖係第4A圖 ❶之另-實施態樣。 如第4A圖所示，係對應至第1G圖’本實施例與第一 實施例大致相同，其主要差異在於第一實施例是屬於頂閘 極型式’而本實施例屬於底閘極（bottom gate)型式。 詳而言之，本實施例之承載板係包括導電層101 與其一侧上的絕緣層102’且該金屬氧化物半導體層11係 設於該絕緣層102上，該導電層1〇1係可為經摻雜的半導 • 體層’該導電層101之材質較佳為高度摻雜的P型半導體 且最佳為高度摻雜的P型矽（P+-Si)，該絕緣層102之材 質較佳為氮化矽（SiNx)，由於本實施例係以該導電層1〇1 作為閘極使用，因此該遮罩層13 (或圖案化遮罩層13’） 之材質較佳為不導電之氧化矽（si0x)。 如第4B圖所示，該承載板1〇復包括設於該導電層ι〇1 另側上的基底層1〇3 ’俾使該導電層1〇丨設於該絕緣層 102與該基底層丨〇3之間，此時，該絕緣層1〇2之材質可 為氮化矽（SiNx)、氧化矽（Si〇x)、聚甲基丙烯酸曱酯 17 111886 201236080 (Polymethylmethacrylate，簡稱 PMMA)、或聚乙烯醇 (Polyvinyl Alcohol，簡稱PVA)，但不限於此。該基底層 103之材質可為玻璃、塑膠、或矽，該導電層101之材質 可為金屬（例如紹或金）或一般透明電極（例如ITO或 FTO)。 至於本實施例之製法基本上與第一實施例相同，故不 在此贅述。 第四實施例 請參閱第5A與5B圖，係本發明之具有電晶體的半導 籲 體元件之第四實施例的剖視圖，其中，第5B圖係第5A圖 之另一實施態樣。 如第5A圖所示，係對應至第3F圖，本實施例與第二 實施例大致相同，其主要差異在於第二實施例是屬於頂閘 極型式，而本實施例屬於底閘極型式。 詳而言之，本實施例之承載板10係包括導電層101 與其一側上的絕緣層102,且該金屬氧化物半導體層11係 $ 設於該絕緣層102上，該導電層101係可為經摻雜的半導 體層，該導電層101之材質較佳為高度摻雜的P型半導體 且最佳為高度摻雜的P型矽（P+-Si)，該絕緣層102之材 質較佳為氮化矽（SiNx)，由於本實施例係以該導電層101 作為閘極使用，因此不需設置該介電層12與閘極金屬層 19，甚至該圖案化阻層14’或微奈米球16亦可保留在半導 體元件上（未圖示此情況）。 如第5B圖所示，該承載板10復包括設於該導電層101S 16 111886 201236080 On the semiconductor layer 11, the gate metal layer 19 is provided on the dielectric layer 12. According to the above semiconductor device having a transistor, the gate metal layer 19 is disposed between the source metal layer 17 and the gate metal layer 18, and the source metal layer 17 and the wave metal layer 18 are respectively disposed. It extends through the sidewall of the metal oxide semiconductor layer ,1 and extends onto the carrier plate 10. THIRD EMBODIMENT Please refer to Figs. 4A and 4B, which are cross-sectional views showing a third embodiment of a semiconductor device having a transistor of the present invention, wherein Fig. 4B is a further embodiment of Fig. 4A. As shown in FIG. 4A, the present embodiment corresponds to the first embodiment. The present embodiment is substantially the same as the first embodiment. The main difference is that the first embodiment belongs to the top gate type and the present embodiment belongs to the bottom gate (bottom). Gate) type. In detail, the carrier board of the embodiment includes a conductive layer 101 and an insulating layer 102 ′ on one side thereof, and the metal oxide semiconductor layer 11 is disposed on the insulating layer 102 , and the conductive layer 1 〇 1 can be The material of the conductive layer 101 is preferably a highly doped P-type semiconductor and is preferably a highly doped P-type germanium (P+-Si), and the material of the insulating layer 102 is better than that of the doped semiconductor layer. Preferably, the nitride layer (SiNx) is used because the conductive layer 1〇1 is used as the gate. Therefore, the material of the mask layer 13 (or the patterned mask layer 13') is preferably non-conductive. Cerium oxide (si0x). As shown in FIG. 4B, the carrier layer 1 includes a base layer 1 〇 3 ′ disposed on the other side of the conductive layer 〇 1 , such that the conductive layer 1 is disposed on the insulating layer 102 and the base layer Between the three, at this time, the material of the insulating layer 1〇2 may be tantalum nitride (SiNx), yttrium oxide (Si〇x), polymethyl methacrylate 17 111886 201236080 (Polymethylmethacrylate, referred to as PMMA), Or Polyvinyl Alcohol (PVA), but is not limited thereto. The material of the base layer 103 may be glass, plastic, or tantalum. The conductive layer 101 may be made of metal (for example, gold or gold) or a general transparent electrode (such as ITO or FTO). The method of the present embodiment is basically the same as that of the first embodiment, and therefore will not be described herein. Fourth Embodiment Referring to Figures 5A and 5B, there is shown a cross-sectional view of a fourth embodiment of a semiconductor semiconductor device having a transistor, wherein Figure 5B is another embodiment of Figure 5A. As shown in Fig. 5A, which corresponds to the 3F, the present embodiment is substantially the same as the second embodiment, and the main difference is that the second embodiment belongs to the top gate type, and the present embodiment belongs to the bottom gate type. In detail, the carrier 10 of the present embodiment includes a conductive layer 101 and an insulating layer 102 on one side thereof, and the metal oxide semiconductor layer 11 is disposed on the insulating layer 102, and the conductive layer 101 is For the doped semiconductor layer, the conductive layer 101 is preferably a highly doped P-type semiconductor and is preferably a highly doped P-type germanium (P+-Si). The insulating layer 102 is preferably made of a material. Cerium nitride (SiNx), since this embodiment uses the conductive layer 101 as a gate, it is not necessary to provide the dielectric layer 12 and the gate metal layer 19, even the patterned resist layer 14' or micronene. The ball 16 can also remain on the semiconductor component (this is not shown). As shown in FIG. 5B, the carrier board 10 is further disposed on the conductive layer 101.
S 18 111886 201236080 另一側上的基底層103，俾使該導電層ίο!設於該絕緣層 102與該基底層103之間，此時，該絕緣層1〇2之材質可 為氮化石夕（SiNx)、氧化石夕（si〇x)、聚曱基丙稀酸曱酉旨 (Polymethylmethacrylate，簡稱 PMMA)、或聚乙烯醇 (Polyvinyl Alcoho卜·簡稱pVA)，但不限於此。該基底層 103之材質可為玻璃、塑膠、或矽，該導電層ιοί之材質 可為金屬（例如鋁或金）或一般透明電極（例如ITO或 FTO)。 至於本實施例之製法基本上與第二實施例相同，故不 在此贅述。 綜上所述’本發明係於電晶體的通道（channel)處（包 含通道正面或背面）形成微米或奈米等級的圖形摻雜 (micro-patterned doping or nan〇_patterned d〇ping，簡稱 MPDorNPD)，使得通道區域中的導電率上升，造成有效 載子遷移率有明顯的提高，以增進對㈣遭電路的電流驅 動力；又本發明可應用在頂閘極型式或底閘極型式的電晶 體上，且祕該圖案化料層的方式可使用微奈米壓印技 術或微奈米球塗佈技術；此外，本發明之具有電晶體的半 導體元件_極與祕可直接形成在高駐遷移率的通道 上，這樣不僅能夠減少製程步驟，也能降低成本，更能夠 降低接觸電阻，形成_接觸，進喊高整體元件效能。 上述實施㈣用間示性說明本發明之原理及兑功 效，而非用於限制本發明。任何熟習此項技藝之人士均可 在不違f本發明之精神及料下，對上述實_進行修 111886 19 201236080 改。因此本發明之權利保護範圍，應如後述之申請專利範 圍所列。 【圖式簡單說明】 第1A至1G圖係本發明之具有電晶體的半導體元件之 製法之第一實施例的剖視圖，其中’第1B ’與1 c，圖係第 1B與1C圖之另一實施態樣，第1G，圖係第ig圖之俯視 園， 第2圖分別係習知與本發明之具有電晶體的半導體元 件的汲極電流對閘極電壓的關係圖； 第3A至3F圖係本發明之具有電晶體的半導體元件之 製法之第二實施例的剖視圖，其中，第3B，與3C，圖係第 3B與3C圖之另一實施態樣； 第4A與4B圖係本發明之具有電晶體的半導體元件之 第三實施例的剖視圖，其中，第4B圖係第4A，圖之另一實 施態樣；以及 第5A與5B圖係本發明之具有電晶體的半導體元件之 第四實施例的剖視圖，其中，第5B圖係第5A 施態樣。 【主要元件符號說明】 10 承載板 101 導電層 102 絕緣層 103 基底層 11 金屬氧化物半導體層 s 20 ,11886 201236080 111 高載子濃度子層 12 介電層 120 介電層開孔 13 遮罩層 13’ 圖案化遮罩層 130 遮罩層開孔 14 阻層 14’ 圖案化阻層 • 15微奈米壓印模具 16 微奈米球 17 源極金屬層 18 汲極金屬層 19 閘極金屬層 A 習知之具有電晶體的半導體元件 B 本發明之具有電晶體的半導體元件 21 111886S 18 111886 201236080 The base layer 103 on the other side is disposed between the insulating layer 102 and the base layer 103. At this time, the material of the insulating layer 1〇2 may be nitrided (SiNx), oxidized stone (si〇x), polymethylmethacrylate (PMMA), or polyvinyl alcohol (Polyvinyl Alcohob, pVA for short), but is not limited thereto. The material of the base layer 103 may be glass, plastic, or tantalum. The material of the conductive layer may be metal (such as aluminum or gold) or a general transparent electrode (such as ITO or FTO). The method of the present embodiment is basically the same as that of the second embodiment, and therefore will not be described herein. In summary, the present invention is based on a channel of a transistor (including a front side or a back side of a channel) to form a micro-patterned doping or nan〇_patterned d〇ping (MPDorNPD). ), the conductivity in the channel region is increased, resulting in a significant increase in effective carrier mobility to enhance the current driving force on the (four) circuit; and the invention can be applied to the top gate type or the bottom gate type of electricity The micro-nano embossing technique or the micro-nanosphere coating technique can be used on the crystal, and the micro-nano embossing technique or the micro-nanosphere coating technique can be used; in addition, the semiconductor element having the transistor of the present invention can be directly formed at a high station. On the channel of mobility, this not only reduces the number of process steps, but also reduces the cost. It can also reduce the contact resistance, form a _contact, and increase the overall component performance. The above-described embodiments (4) are illustrative of the principles and advantages of the present invention, and are not intended to limit the present invention. Anyone who is familiar with the art can make improvements to the above-mentioned real-life under the spirit and scope of the present invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1G are cross-sectional views showing a first embodiment of a method of fabricating a semiconductor device having a transistor of the present invention, wherein '1B' and 1 c, the other of FIGS. 1B and 1C Embodiments, FIG. 1G, the plan view of the ig diagram, and FIG. 2 are diagrams showing the relationship between the gate current and the gate voltage of the semiconductor device having the transistor of the present invention; FIGS. 3A to 3F A cross-sectional view of a second embodiment of a method of fabricating a semiconductor device having a transistor of the present invention, wherein FIGS. 3B and 3C are diagrams showing another embodiment of FIGS. 3B and 3C; FIGS. 4A and 4B are diagrams of the present invention. A cross-sectional view of a third embodiment of a semiconductor device having a transistor, wherein FIG. 4B is a fourth embodiment of FIG. 4A, and FIG. 5A and FIG. 5B are diagrams showing a semiconductor device having a transistor of the present invention. A cross-sectional view of a fourth embodiment, wherein Fig. 5B is a fifth embodiment. [Main component symbol description] 10 carrier plate 101 conductive layer 102 insulating layer 103 base layer 11 metal oxide semiconductor layer s 20 , 11886 201236080 111 high carrier concentration sub-layer 12 dielectric layer 120 dielectric layer opening 13 mask layer 13' patterned mask layer 130 mask layer opening 14 resist layer 14' patterned resist layer • 15 micronm imprint mold 16 micro nanosphere 17 source metal layer 18 drain metal layer 19 gate metal layer A conventional semiconductor element B having a transistor. The semiconductor element 21 having a transistor of the present invention