201225668 六、發明說明： 【發明所屬之技術領域】 本發明係一種三維影像轉換系統，特別是一種可應用於 DLP、PDP或LCD等顯示器，將複數種三維影像格式轉換為 棋盤式，或圖場循序，或行交錯等影像輸出。 【先前技術】 目前，隨著電影科技曰益發展，各種三維影像格式由各家 廠商自行訂定’目前高解析多媒體介面協會(High七efinitiQn Multimedia Interface ; HDMI)制定之主要三維影像格式有三： 其一，三維影像圖框封包(ftame—packing)技術用之於藍光 三維，此技術係將左右眼之影像以重疊方式顯示傳輪； 其二’三維影像併排(side-by-side)格式用之於廣播三維， 此技術係將左右眼影像以併排方式顯示傳輸； 其二’二維影像由上至下(top-and-bottom)格式用之於廣播 三維’此技術係將左右眼影像以由上至下方式顯示傳輪。 所謂二維影像棋盤格式(Checkboard) ’係將左右眼之影像 以採用棋盤式交錯於每一個像素(Pixel)方式顯示，用之於較早 DLP三維顯示器，該DLp三維顯示器只支援三維影像棋盤袼 式，為了讓DLP三維顯示器能夠支援HDMI制定之三維格式，B1· 3 201225668 必須藉由轉換系統方能達成。 至於圖場循序（Field/Frame Sequential)或行交錯(Ljj^ Interlaced)等排列訊號格式，則將左右眼之影像以採用循序式 交錯於每一個圖場或行方式顯示，用之液晶三維顯示器或電锻 三維顯示器，為了讓液晶三維顯示器或電漿三維顯示器能夠支 援HDMI制定之三維格式，必須藉由轉換系統方能達成。 【發明内容】 本發明提供一種三維格式影像轉換系統，包含下列步驟： 由HDMI傳輸輸入三維影像訊號至可編程邏輯閘陣列元件 (FPGA)轉換處理，再經由舰^傳輸輸出至DLp三維顯示 器’則FPGA分為三大部分： 其一，影像輸入單元，此單元係將一輸入三維影像之左右 • 目艮影像由影像分離器①麵X)分離，並傳輸至影像控制單元； 其二’影_鮮元，較㈣換公趣三_像格式使 用第二代雙倍速率同步動態隨機存取記憶體①贿 =介’將4影像格式轉換為三維影像棋盤格式、或圖場循 或仃父錯等排顺式並且輸出至影像輸出單元； 維少傻舰 〜祕判早元所轉換之肩 瞧序、紐购排·式，經 像=併器（MUX)编槪，細_ 4 201225668 【實施方式] 關於本發明之特徵與實作，賊合圖示作最佳實施例詳細 說明如下： 一種二維影像轉換系統，包含下列步驟： 如第1圖所示，由11〇]^(八01)傳輸輸入三維影像訊號 (A02)經可蝙程邏輯閘陣列元件(a〇3)轉換處理，再經由 HDMI(A04)傳輪輪出至DLp三維顯示器(A〇5)。 如第2圖所示，可編程邏輯閘陣列元件ppGA)包括有： 影像輸入單元(B01)，此單元將三維影像以HDMI輸入 (_) ’以影像分離器_〇)將左右眼影像分離為奇數像素影 像及偶數像素影像分別暫存於輸人奇數像素資料緩衝區⑽1 ^ 以及輸入偶數像素資料緩衝區(B012)内，並傳輸至影像控制單 元(B02); 影像控制單元(B02)’使用轉換公式將三維影像格式存放於 第二代雙倍速率同步動態隨機存取記憶體，並且 使用相對轉換公式，將其相對之三維影像格式轉換為三維影像 棋盤格式、或圖場循序、或行交錯等排列格式，並且輸出至影 像輸出單元(B04); 影像輸出單元(B04) ’將由影像控制單元(B〇2)所轉換輸出 201225668 3數像細_數㈣影像暫存犧奇數像素 資料緩 °° 从細贿料f瓶舰(Β〇42)ι^，經由影像 讀器_3)合併為料三_雜赌式、賴場循序^ 盯交錯等侧格式之影像，再纟廳轉輸輸師〇5)。 有一、中上述―維影轉齡統之影像控鮮元其轉換方式201225668 VI. Description of the Invention: [Technical Field] The present invention relates to a three-dimensional image conversion system, in particular to a display such as a DLP, a PDP or an LCD, which converts a plurality of three-dimensional image formats into a checkerboard type, or a field Image output such as sequential or line interleaving. [Prior Art] At present, with the development of film technology, various 3D image formats have been set by various manufacturers. The current three-dimensional image format (High-Analytical Multimedia Interface (HDMI)) has three main image formats: First, the 3D image frame packing (ftame-packing) technology is used for Blu-ray 3D. This technology displays the images of the left and right eye images in an overlapping manner; the second '3D image is used side by side (side-by-side) format. In broadcast three-dimensional, this technology displays the left and right eye images in a side-by-side manner; the second 'two-dimensional image is used in the top-and-bottom format for broadcast three-dimensional' The top-down mode shows the transfer wheel. The so-called 2D image board format (Checkboard) is used to display the left and right eye images in a checkerboard pattern for each pixel (Pixel). It is used in earlier DLP 3D displays. The DLp 3D display only supports 3D image board. In order to enable the DLP 3D display to support the 3D format developed by HDMI, B1·3 201225668 must be achieved by converting the system. As for the alignment of the signal format such as Field/Frame Sequential or Ljj^ Interlaced, the left and right eye images are displayed in a sequential manner in each field or line mode, and the liquid crystal three-dimensional display or The electric forging three-dimensional display, in order to allow the liquid crystal three-dimensional display or the plasma three-dimensional display to support the three-dimensional format developed by HDMI, must be achieved by a conversion system. SUMMARY OF THE INVENTION The present invention provides a three-dimensional format image conversion system, comprising the following steps: transmitting and inputting a three-dimensional video signal by HDMI to a programmable logic gate array component (FPGA) conversion processing, and then transmitting the output to a DLp three-dimensional display via a ship^ The FPGA is divided into three parts: First, the image input unit, which separates the left and right images of an input 3D image from the image separator 1 and transmits it to the image control unit; Fresh yuan, compared to (four) for public interest three _ image format using the second generation double rate synchronous dynamic random access memory 1 bribe = media 'convert 4 image format to 3D image board format, or map field or father error Isochronous and output to the image output unit; Wei Shaosuo Ship ~ Secret Judgment of the conversion of the shoulders of the early Yuan, the new purchase row, the image = the compiler (MUX), fine _ 4 201225668 Means for the features and implementation of the present invention, the preferred embodiment of the thief is illustrated as follows: A two-dimensional image conversion system comprising the following steps: As shown in Fig. 1, by 11〇]^(八01 )transmission The three-dimensional image signal (A02) by the programmable logic gate array may bat element (a〇3) conversion process, and then the three-dimensional display to DLp (A〇5) through (A04) transfer wheel wheel HDMI. As shown in Fig. 2, the programmable logic gate array element ppGA) includes: an image input unit (B01), which separates the left and right eye images into three-dimensional images by using HDMI input (_) 'with image separator_〇) The odd pixel image and the even pixel image are temporarily stored in the input odd pixel data buffer (10) 1 ^ and the input even pixel data buffer (B012), and transmitted to the image control unit (B02); the image control unit (B02) 'use The conversion formula stores the 3D image format in the second generation double rate synchronous dynamic random access memory, and uses the relative conversion formula to convert the relative 3D image format into a 3D image checkerboard format, or a field sequential or row interleaving. Arrange the format and output to the image output unit (B04); Image output unit (B04) 'The output will be converted by the image control unit (B〇2) 201225668 3 number image fine _ number (four) image temporary storage sacred pixel data slow ° From the bribes of the brigade (Β〇42) ι^, through the image reader _3) merged into the material of the three _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Teacher 5)There is a conversion method of the above-mentioned image-control fresh-keeping element
其冑一維影像圖框封包格式轉換至三維影像棋盤格 式如第3圖左眼影像及第4圖右眼影像，運用FPGA轉換合 併為第5圖之棋盤格式三維影像； 其二，將三維影像併排格式轉換至三維影像棋盤格式，如 第6圖左眼影像(401)及右眼影像(4〇2)，運帛FPGA轉換合併 為第7圖之棋盤格式三維影像； 其三’將三維影像由上至下格式轉換至三維影像棋盤格 式’如第8圖左眼影像(601)及右眼影像(6〇2)，FpGA轉換合併 為第9圖之棋盤格式三維影像。 其中，上述三維影像轉換系統中於DDRII之三維影像資料 配置如第1〇圖所示。 其中，上述三維影像轉換系統影像處理單元將三維影像格 式轉換為棋盤影像格式’或圖場循序’或行交錯等排列格式之 演譯法如第11圖所示；又，棋盤影像格式，或圖場循序，或 201225668 行交錯等排列格式為轉換後影像格式取代之，並且於第12七 圖揭露圖場Μ時，奇數行與偶數行在DDRn讀寫狀態。即： DRIIR。卩魏舰置將區分為*大暫存記憶體區塊，如 第1〇圖所不’其内容分別為圖框1、圖框2、圖框3及圖框4, 其中單—難倾，鱗行雜之奇錄紅及觀之偶數像 ’、構成貝jFPGA將依照如第u圖影像控制演算法方式運 • #，並進行存取職1之動作，進而達到轉換影像之效果。 第U圖之衫像控制演算法由四個工作時序所組成，第一時 序Ln為處理左眼奇數行以及偶數行影像。 如第12圖所示，處理左眼奇數行影像之動作有四：其一， 將待轉換核影叙每行奇數像素由 資料緩衝區讀出並寫入 y圖框丄Π可數像素的暫存記憶體區塊(DDRII);其二，將 _ 鄕換左㈣像之每行贿像素由資料緩雛讀丨並寫入位 框^框1内偶數像素的暫存記憶體區塊(DDRII);其三，將圖 王之奇數像素資料由暫存記憶體區塊(DDRII)讀ώ並寫入至 齡奇數像素貝料緩衝區；其四，將圖框4之偶數像素資料由 m 1 4並寫人錄出減像素資料緩衝 景眼偶數行影像之動作亦有四：其…將待轉換左眼 行奇數像素由資料緩衝區讀出並寫入位於圖框1内 201225668 奇數像素的暫存記憶體區塊(DDRII);其二，將待轉換左眼影 像之每行偶數像素由資料緩衝區讀出並寫入位於圖框〗内偶 數像素的暫存記憶體區塊(DDRII);其三，將圖框4之奇數像 素資料由暫存記憶體區塊(DDRII)讀出並寫入至輸出奇數像素 資料緩衝區；其四，將圖框3之偶數像素資料由暫存記憶體區 塊(DDRII)讀出並寫入至輸出偶數像素資料緩衝區。即完成第 一時序Ln之動作。 第二時序Rn為處理右眼奇數行以及偶數行影像。如第13 圖所示，處理右眼奇數行影像之動作有四：其一，將待轉換右 眼影像之每行奇數像素由資料緩衝區讀出並寫入位於圖棍2 内奇數像素的暫存記憶體區塊(DDRII);其二，將待轉換右眼 影像之每行偶數像素由資料緩衝區讀出並寫入位於圖框2内 偶數像素的暫存記憶體區塊(DDRII);其三，將圖框3之奇數 像素資料由暫存記憶體區塊(DDRII)讀出並寫入至輸出奇數像 素資料緩衝區；其四，將圖框4之偶數像素資料由暫存記憶體 區塊(DDRII)讀出並寫入至輸出偶數像素資料緩衝區。 處理右眼偶數行影像之動作亦有四：其一，將待轉換右眼 影像之每行奇數像素由資料緩衝區讀出並寫入位於圖框2内 奇數像素的暫存記憶體區塊(DDRII);其二，將待轉換右眼影 像之母行偶數像素由資料緩衝區讀出並寫入位於圖框2内偶 數像素的暫存記憶體區塊(DDRII);其三，將圖框4之奇數像 201225668 素資料由暫存記憶體區塊(DDRII)讀出並寫入至輸出奇數像素 資料緩衝區；其四，將圖框3之偶數像素資料由暫存記憶體區 塊(DDRII)讀出並寫入至輸出偶數像素資料緩衝區。即完成第 一時序Rn之動作。 第三時序Ln+Ι為處理左眼奇數行以及偶數行影像。如第 14圖所示，處理左眼奇數行影像之動作有四：其一，將待轉 換左眼影像之每行奇數像素由資料緩衝區讀出並寫入位於圖 框3内奇數像素的暫存記憶體區塊(〇〇见1);其二，將待轉換 左眼影像之每行偶數像素由資料緩衝區讀出並寫入位於圖框3 内偶數像素的暫存記憶體區塊(DDRII);其三，將圖框1之奇 數像素資料由暫存記憶體區塊(DDRII)讀出並寫入至輸出奇數 像素資料緩衝區；其四，將圖框2之偶數像素資料由暫存記憶 體區塊(DDRII)讀出並寫入至輸出偶數像素資料緩衝區。 處理左眼偶數行影像之動作亦有四：其一，將待轉換左眼 影像之每行奇數像素由資料緩衝區讀出並寫入位於圖框3内 奇數像素的暫存記憶體區塊(DDRII);其二，將待轉換左眼影 像之每行偶數像素由資料緩衝區讀出並寫入位於圖框3内偶 數像素的暫存記憶體區塊(DDRn);其三，將圖框2之奇數像 素資料由暫存記憶體區塊(DDRII)讀出並寫入至輸出奇數像素 資料缓衝區；其四，將圖框丨之偶敫像素資料由暫存記憶體區 塊(DDRII)讀出並寫入至輸出偶數像素資料緩衝區。即完成第 201225668 二時序Ln+l之動作。 第時序Rn+l為處理右眼奇數行以及偶數行影像。如第 15圖所示’處理右眼奇數行影像之動作有四：其-，將待轉 、艮景/像之每行奇數像素由資料緩衝區讀出並寫入位於圖 框4内奇數像素的暫存記憶體區塊①咖）；其二，將待轉換 右眼影像之每行偶雜素㈣機衝_纽寫人位於圖框4 内偶數像素的暫存記憶體區塊(DDRn);其三，將圖框i之奇 數像素倾由暫存記㈣區塊(DDRII)讀ώ並寫人至輸出奇數 像素資料緩衝區；其四，關框2之偶數像素f料由暫存記憶 體區塊⑽M)讀$並冑人至輸ώ偶數像素資料緩衝區。 處理右眼偶數行影像之動作亦有四：其一，將待轉換右眼 影像之每行奇數像素由資料緩衝區讀出並寫入位於圖框4内 奇數像素的暫存記憶體區塊(DDRII);其二，將待轉換右眼影 像之每行偶數像素由資料緩衝區讀出並寫入位於圖框4内偶 數像素的暫存記憶體區塊(DDRII);其三，將圖框2之奇數像 素資料由暫存記憶體區塊(DDRII)讀出並寫入至輸出奇數像素 資料緩衝區；其四’將圖框1之偶數像素資料由暫存記憶體區 塊(DDRII)讀出並寫入至輸出偶數像素資料緩衝區。即完成第 四時序Rn+1之動作。 FPGA經由重復上述時序動作達成影像轉換成棋盤影像格 式之目的。 201225668 同理，FPGA經由重復第16-19圖的時序動作，町遠成影 像轉換成圖場循序格式之目的。 或，FPGA經由重復第20-23圖的時序動作，邛達成影像 轉換成行交錯格式之目的。 上述三維影像轉換系統之輸入及輸出單元，以使用HPMI l，4a傳輸協定作為三維影像之傳輸介面。 【圖式簡單說明】 第1圖係本發明三維影像轉換系統之方塊圖； 第2圖係本發明可編程式邏輯閘陣列元件之方塊圖； 第3圖係三維影像圖框封包(ftam^packing)格式的左眼影像； 第4圖係三維影像圖框封包格式的右眼影像； 第5圖係本發明將圖框封包格式轉換至棋盤格式之實施例； 第6圖係三維影像併排(side-by-side)格式的左眼影像及右眼影 像； 第7圖係本發明將併排格式轉換至棋盤格式之實施例； 第8圖係三維影像由上至下格式的左眼影像及 右眼影像·， 201225668 第9圖係本發日歸由上至-p格式雜至棋雜式之實施例； 第10圓係本發明於DDRII之三維影像f料配置圖； 第π圖係本發明三維影像轉換祕影像控制之演算示意圖； 第叫5 _轉換成棋盤影像格式之圖場w 的記憶體讀寫狀態圖； 仃興 第⑹9隱轉換成圖場循序格式之圖場^ 行 的記憶體讀寫狀態圖； 行… 第⑽圖係轉換成行交錯格式之圖場M奇數行與偶數行的 記憶體讀寫狀態圖。 、 【主要元件符號說明】 A01輸入 ❿ A02三維影像訊號 A03可編程邏輯閘陣列元件 A04輸出 A05三維顯示器 B01影像輸入單元 BOO HDMI 輸入 12 201225668 B010影像分離器 B011輸入奇數像素資料緩衝區 B012輸入偶數像素資料緩衝區 B02影像控制單元 B03第二代雙倍速率同步動態隨機存取記憶體(DDRII) B04影像輸出單元 B041輸出奇數像素資料緩衝區 B042輸出偶數像素資料緩衝區 B043影像合併器 B05HDMI 輸出 13The one-dimensional image frame packet format is converted to a three-dimensional image board format such as the left eye image of FIG. 3 and the right eye image of FIG. 4, and is converted into a three-dimensional image of the checkerboard format of FIG. 5 by using FPGA conversion; The side-by-side format is converted to a three-dimensional image board format, such as the left-eye image (401) and the right-eye image (4〇2) in Figure 6, which is converted into a three-dimensional image in the checkerboard format of Figure 7; From top to bottom format conversion to 3D image board format 'like left eye image (601) and right eye image (6〇2) in Fig. 8, FpGA conversion is merged into 3D image in checkerboard format in Fig. 9. The three-dimensional image data configuration of the DDRII in the above three-dimensional image conversion system is as shown in FIG. Wherein, the image processing unit of the three-dimensional image conversion system converts the three-dimensional image format into a format of a checkerboard image format 'or a field sequence' or a line interlace, as shown in FIG. 11; and, a checkerboard image format, or a figure The field sequential, or 201225668 line interleaving format is replaced by the converted image format, and when the picture field is revealed in the 12th figure, the odd line and the even line are in the DDRn read and write state. Namely: DRIIR.卩Wei Shipyard will be divided into *large temporary memory blocks, as shown in Figure 1. The contents are frame 1, frame 2, frame 3 and frame 4, where single-difficult, The singularity of the singularity of the singularity of the singularity of the singularity of the singularity of the singularity of the singularity of the singularity of the singularity of the singularity of the imagery. The shirt image control algorithm of the U-picture is composed of four working sequences, and the first time sequence Ln is for processing the odd-numbered lines of the left eye and the even-numbered lines of images. As shown in Fig. 12, there are four actions for processing the odd-numbered line images of the left eye: First, the odd-numbered pixels of each line of the to-be-converted kernel are read out from the data buffer and written into the y frame. Memory block (DDRII); second, change _ 鄕 to the left (four) image of each line of bribe pixels read from the data and write to the temporary memory block (DDRII) of the even pixel in the frame Third, the odd pixel data of the king is read from the temporary memory block (DDRII) and written to the odd-odd pixel buffer; fourth, the even pixel data of the frame 4 is m 1 4 And the action of recording the pixel data buffering even-numbered line image is also four: it... the odd-numbered pixels of the left-eye line to be converted are read from the data buffer and written into the temporary storage of the 201225668 odd pixel in the frame 1. Memory block (DDRII); second, the even-numbered pixels of each line of the left-eye image to be converted are read from the data buffer and written into the temporary memory block (DDRII) of the even-numbered pixels in the frame; Third, the odd pixel data of frame 4 is read out from the temporary memory block (DDRII) and written to the output odd pixel Buffer; Fourth, the frame 3 of the even-numbered pixel data read from the temporary memory region block (DDRII) and an even-numbered pixel data is written to the output buffer. That is, the action of the first sequence Ln is completed. The second timing Rn is to process odd-numbered lines and even-line images of the right eye. As shown in Fig. 13, there are four actions for processing the odd-numbered lines of the right eye: first, the odd-numbered pixels of each line of the right-eye image to be converted are read from the data buffer and written into the odd-numbered pixels in the stick 2 Memory block (DDRII); second, each row of even pixels of the right eye image to be converted is read from the data buffer and written into the temporary memory block (DDRII) located in the even pixel of the frame 2; Third, the odd pixel data of frame 3 is read out from the temporary memory block (DDRII) and written to the output odd pixel data buffer; fourth, the even pixel data of frame 4 is from the temporary memory. The block (DDRII) is read and written to the output even pixel data buffer. There are also four actions for processing the even-numbered lines of the right eye. First, the odd-numbered pixels of each line of the right-eye image to be converted are read from the data buffer and written into the temporary memory block located in the odd-numbered pixels in the frame 2 ( DDRII); Second, the even-numbered pixels of the parent line of the right-eye image to be converted are read from the data buffer and written into the temporary memory block (DDRII) of the even-numbered pixels in frame 2; third, the frame is The odd number of 4 is like 201225668. The data is read from the temporary memory block (DDRII) and written to the output odd pixel data buffer. Fourthly, the even pixel data of frame 3 is from the temporary memory block (DDRII). Read and write to the output even pixel data buffer. That is, the action of the first timing Rn is completed. The third sequence Ln+Ι is for processing the odd-numbered lines of the left eye and the even-numbered lines of images. As shown in Fig. 14, there are four actions for processing the odd-numbered lines of the left eye: first, the odd-numbered pixels of each line of the left-eye image to be converted are read from the data buffer and written into the odd-numbered pixels in the frame 3 The memory block (see 1); the second, the even pixel of each line of the left eye image to be converted is read from the data buffer and written into the temporary memory block located in the even pixel in the frame 3 ( DDRII); Third, the odd pixel data of frame 1 is read out from the temporary memory block (DDRII) and written to the output odd pixel data buffer; fourth, the even pixel data of frame 2 is temporarily The memory block (DDRII) is read and written to the output even pixel data buffer. There are also four actions for processing the image of the even-numbered lines in the left eye. First, the odd-numbered pixels of each line of the left-eye image to be converted are read from the data buffer and written into the temporary memory block located in the odd-numbered pixels in the frame 3 ( DDRII); second, the even-numbered pixels of each line of the left-eye image to be converted are read from the data buffer and written into the temporary memory block (DDRn) of the even-numbered pixels in the frame 3; third, the frame is The odd pixel data of 2 is read by the temporary memory block (DDRII) and written to the output odd pixel data buffer; fourthly, the even pixel data of the frame is saved by the temporary memory block (DDRII). Read and write to the output even pixel data buffer. That is, the action of the second sequence Ln+l of 201225668 is completed. The timing Rn+1 is for processing odd-numbered lines and even-line images of the right eye. As shown in Fig. 15, there are four actions for processing the odd-line image of the right eye: -, the odd pixels of each row of the image to be rotated, the scene/image are read out from the data buffer and written into the odd pixel in the frame 4. The temporary storage memory block 1); secondly, each row of the right eye image to be converted (4) is rushed to the temporary memory block (DDRn) of the even pixel in the frame 4 Third, the odd pixel of frame i is read by the temporary memory (four) block (DDRII) and written to the output odd pixel data buffer; fourth, the even pixel of the closed box 2 is read by the temporary memory. The body block (10) M) reads $ and swears to the even pixel data buffer. There are also four actions for processing the even-numbered lines of the right eye. First, the odd-numbered pixels of each line of the right-eye image to be converted are read from the data buffer and written into the temporary memory block located in the odd-numbered pixels in the frame 4 ( DDRII); Second, the even pixels of each line of the right eye image to be converted are read from the data buffer and written into the temporary memory block (DDRII) of the even pixels in the frame 4; third, the frame is 2 odd pixel data is read from the temporary memory block (DDRII) and written to the output odd pixel data buffer; the fourth 'reads the even pixel data of frame 1 from the temporary memory block (DDRII) Output and write to the output even pixel data buffer. That is, the action of the fourth timing Rn+1 is completed. The FPGA achieves the purpose of converting the image into a checkerboard format by repeating the above-described sequential actions. 201225668 In the same way, FPGA repeats the sequence action of Figure 16-19, and the image is converted into a sequence format. Or, the FPGA performs the purpose of converting the image into a line interleaving format by repeating the timing actions of FIG. 20-23. The input and output units of the above-mentioned three-dimensional image conversion system use the HPMI l, 4a transmission protocol as a transmission interface of the three-dimensional image. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a three-dimensional image conversion system of the present invention; FIG. 2 is a block diagram of a programmable logic gate array component of the present invention; and FIG. 3 is a three-dimensional image frame package (ftam^packing) The left eye image of the format; the fourth image is the right eye image of the 3D image frame packing format; the fifth figure is the embodiment of the present invention for converting the frame packing format to the checkerboard format; the sixth figure is the 3D image side by side (side -by-side) format left-eye image and right-eye image; Figure 7 is an embodiment of the present invention for converting a side-by-side format to a checkerboard format; Figure 8 is a three-dimensional image of a left-eye image and a right eye in a top-down format Image·, 201225668 Fig. 9 is an embodiment of the present day returning to the -p format miscellaneous to the chess pattern; the tenth circle is the three-dimensional image f material configuration diagram of the present invention in DDRII; The calculus diagram of the image conversion secret image control; the memory read/write state diagram of the map field y converted into the board image format; the ( 第 (6) 9 implicit conversion into the field of the scene format of the map field Write state diagram; line... (10) diagram conversion A memory read/write state diagram of odd-numbered rows and even-numbered rows of a field in an interlaced format. [Main component symbol description] A01 input ❿ A02 3D image signal A03 programmable logic gate array component A04 output A05 3D display B01 image input unit BOO HDMI input 12 201225668 B010 image separator B011 input odd pixel data buffer B012 input even pixel Data buffer B02 image control unit B03 second generation double rate synchronous dynamic random access memory (DDRII) B04 image output unit B041 output odd pixel data buffer B042 output even pixel data buffer B043 image combiner B05HDMI output 13