TW201225262A - Nonvolatile stacked NAND memory - Google Patents

Abstract

A NAND string of memory cells has stacks of split word lines (gates), with resulting increased bit density. Variants add a top assist gate to the NAND string, a bottom assist gate to the NAND string, or both a top assist gate and a bottom assist gate to the NAND string.

Description

I 201225262 11 0 '6. Description of the Invention: [Technical Field] The present invention relates to a non-volatile NAND memory having a plurality of consecutively disposed in a vertical direction outside a plane of a substrate And adjacent memory cells that are not disposed only along or parallel to one of the substrate faces. [Prior Art] • by Jinyoung Kim et al.

A paper published in the technical paper of the W Super Large Integral Circuit (VL SI) Technical Abstract, entitled "Ultra-High Density Flash for Vertical-Recess-Array-Transistor (VRAT) A novel 3D structure of memory (pp. 122-123) having a plurality of stacked memory cell systems arranged to have continuous channels in an internal region covered by a plurality of stacked gates and charge storage material. This method separates a plurality of adjacent columns of gates with horizontal channel spacing. • This method requires the creation of a number of undercuts that must fill the gate electrode. The technical papers of the 2009 Super Large Integral Circuit (VLSI) Technical Digest by Jinoung Kim et al. Published a paper entitled "VSAT, Vertical-Stacked-Array for Ultra High Density and Cost-Effective NAND Flash Memory Devices and Solid State Drives (SSD) -Transistor)" (pp. 186 to 187), the plurality of stacked memory cell systems are arranged to have continuous channels in an outer region covered by a plurality of stacked 201225262 poles and a charge storage material. In this manner, the plurality of horizontally-oriented channels are spaced apart from each other by a plurality of adjacent gate stacks, and the pitch of the vertical channels is run up at one of the sides of each of the stacked members and is in each of the stacked members. Run down on the other side. In order to help reduce the off current, each stack is a different wide gate, and each gate simultaneously controls two channels of vertical length, that is, on both sides of each gate. The channel in the vertical direction on the side. SUMMARY OF THE INVENTION One aspect of the present invention is a memory device including a NAND string of a memory cell, wherein the memory cells are electrically connected in series to a first end of a semiconductor body and Between a second end. The NAND string includes a plurality of word line stacks and a semiconductor channel material covering the stacks. The word lines in one of the stacks are electrically isolated from one another, such as by a dielectric, such as an oxide, for isolation. These stacks extend outside the semiconductor body. The semiconductor channel material covers such stacks. The semiconductor channel material is, for example, polysilicon. The NAND string has an electrical series between the first end and the second end via the semiconductor channel material. In some embodiments, when all of the portions of the semiconductor channel material controlled by a particular gate are turned on along the gate of the NAND string, and assuming that the selected transistors on the bottom of the NAND string are simultaneously turned on, This electrical series is electrically conductive. In some embodiments, when one or more of the gates along the NAND string have a voltage that is turned off by one of the portions of the semiconductor channel material controlled by a gate, or is assumed to be in the NAND string When a selective transistor on the bottom end is turned off, the electrical series is turned off. The semiconductor channel material covering the stack of word lines is disposed to extend over a plurality of ridges outside the semiconductor body. A ridge (a ridge of the semiconductor channel material) covers a plurality of adjacent stacks of the stack of word lines. For example, one of the first ridges of the semiconductor channel material covers an adjacent first and a A stack of second word lines. • Some embodiments include a non-conductive material electrically isolating a plurality of stacks covered by one of the ridges of the semiconductor channel material. Such a non-conductive material is, for example, Monooxide. In other examples, the oxide is part of an oxide-charge trapping nitride-oxide structure, and the structure and oxide-charge trapping covering a plurality of stacks The compound-oxide structure shares the same material because the two structures are obtained by a common process step. Some embodiments include a bottom auxiliary gate material covered by a stack of word lines and semiconductor channel material (bottom) The bottom auxiliary gate material helps control the portion of the semiconductor channel material that is closest to the bottom auxiliary gate material. In some embodiments, the bottom auxiliary gate material helps control the horizontal portion of the semiconductor channel material. In some embodiments, the control circuit is biased to use the bottom auxiliary gate material. For example, the control circuit applies a first bias to the bottom. The auxiliary gate material assists in electrical series connection through the semiconductor channel material. The device is turned off and a second bias is applied to the bottom auxiliary gate material to facilitate conduction through the electrical series of semiconductor channel material. In another example 201225262, the control circuit applies a negative bias to the bottom assist Gate material to resist leakage during programming. Some embodiments include overlaying a plurality of word line stacks And a top assist gate material of the semiconductor channel material helps control a portion of the semiconductor channel material that is closest to the top auxiliary gate material. In some embodiments, the top auxiliary gate material helps control the semiconductor channel material. The vertical direction portion. In some embodiments, the control circuit is thinned to use the top auxiliary gate material. For example, the control circuit applies a positive bias to the top auxiliary gate material to assist in erasing the NAND string. In another example, the control circuit applies a first bias to the top auxiliary gate material to assist in programming one of the memory cells in the NAND string, and applies a second bias to the top auxiliary gate material to resist the NAND string. Programming, the first bias voltage is less than the second bias voltage. The 1L example includes a charge storage material covering a plurality of stacked pieces. The semiconductor channel material covers the charge buffer material, such as a charge trapping material. The charge in the portion of the charge storage material that is closest to the corresponding gate determines whether a particular NAND memory cell turns the channel in the semiconductor pass, the corresponding portion of the material on or off. Coating: These embodiments include charge storage materials located between adjacent stacks of ridges of semiconductor channel material. These charge memories = two are off: adjacent to the semiconductor channel material, so in the case of some embodiments, the electrode pin can have a small influence. However, in the case where the charge storage material is formed along the charge storage material, the valence structure is formed by a plurality of word line stacks such as an oxide-charge trapping nitride-P, and thus is omitted. A 1 201225262 * ' f ν·ί i / 1 ip * track process steps. Another aspect of the invention is a method of manufacturing an N-touch D method, in particular, forming one of a plurality of memory cells, a method of NAND string, a mr-type string material, a body body cutting, and a first material. The method steps include: the first piece extends beyond the semiconductor body; the character stacks are reduced by the electrical spacer _ word line material to form an intermediate portion of the second stack, and the first-stack and the a stacking member having a right-handedness from the stacking member than the first stacking member, wherein in the second stacking member

φ φ . The sub-line material layer is a plurality of word lines of a plurality of memory cells in the NAND string. The second stack is covered by the vehicle: semiconductor channel material, the NAND string passing through the conductor channel material, between the first electrical φ and μ% of the NAND string - the embodiment includes: prior to forming the first stack, A cover auxiliary gate material is formed. Some embodiments of the bottom f of the bull conductor body having the bottom auxiliary interpole material further include the steps of: material extraction: a control circuit to apply a first bias to a bottom auxiliary gate off-bias to assist the passage of the semiconductor channel material The electric (four) coupling is applied with a second bias to the bottom auxiliary gate material to assist in the conduction of the electrical series of materials, which is biased. Some embodiments having a bottom auxiliary gate material include the steps of: 201225262 providing a control circuit to apply a negative bias to the bottom auxiliary open material to resist leakage during programming. An embodiment includes: forming a top auxiliary gate material overlying the semiconductor channel material after covering the second stack with a semiconductor channel material. Some embodiments having a top auxiliary gate material further include the steps of: providing a control circuit to apply a first bias voltage to the top auxiliary gate (four) 'α (d) in the NAND string - memory cell programming and applying - Two biases are applied to the top auxiliary gate material to resist programming of the nand string, the first bias voltage being less than the second bias voltage.

Some embodiments further include the step of: applying a control circuit to apply a positive bias to the top auxiliary to assist in erasing the NAND string. An embodiment includes: covering the second stack with a semiconductor channel material overlying structure. An embodiment includes: before the first stack, a charge reservoir is formed in the plurality of turns to remove the intermediate portion, and the plurality of portions are removed by removing the intermediate portion (the non-conductive material in (4)) And further comprising the step of removing the second charge of the second stack by covering the second stack with a semiconductor channel material to cover the charge storage layer of the first oxide layer and the second oxide layer of the oxide layer. = 201225262 I VV I : 71 VJ\ ' l Other embodiments are also disclosed herein. [Embodiment] FIG. 1 is a diagram showing an equivalent circuit of a stacked NAND string according to an embodiment, and the setting of the equivalent circuit diagram is close to The actual physical structure of the stacked NAND string is set in the embodiment. The equivalent circuit of this embodiment shows that a NAND string is usually set as three ridges, and each ridge includes six gates. The area φ is divided into two stacks, each stack having three gates. The left ridge has stacked word lines WL1, WL2, WL3 on one side and stacked characters on the other side of the left ridge Lines WL4, WL5, WL6. The intermediate ridge has stacked word lines WL7, WL8, WL9 on one side and stacked word lines WL10, WL11, WL12 on the other side. The right ridge has stacked word lines WL13 on one side, WL14, WL15 and stacked word lines WL16, WL17, WL18 on the other side. 9 Because each ridge can effectively include a plurality of gates that have been isolated in the horizontal direction, the bit density can be multiplied. (different in the example shown). Other embodiments have different numbers of ridges and/or different numbers of word lines in each word line stack. In this setup, the gate Attached to the opposite interior of the ridge, and the channel is on the opposite outer side of the ridge. The NAND string on the endpoint is selected by a transistor, a GSL (ground selection) transistor, and an SSL (source selection) The transistor is terminated. This SSL and GSL process is completed in a same patterning process as a plurality of 201225262 word lines. However, the gate length of SSL/GSL is determined by the layout. Has the picture shown in Figure 1 A plurality of adjacent NAND strings having the same plurality of word lines through adjacent NAND strings and different NAND strings resolved by different bit lines connected to different NAND strings by SSL selection transistors. The figure shows an example of a series of process steps for fabricating a stacked NAND string having a top auxiliary gate and a bottom auxiliary gate. Figure 2 illustrates a p-type substrate 10. Performing ion implantation to form a bottom auxiliary gate The electrode 12 is activated by, for example, activation by annealing to reduce parasitic resistance. Figure 3 illustrates the formation of the bottom auxiliary gate dielectric 14. Figure 4 illustrates the polysilicon 16 and a plurality of alternating layers of buried oxide 18. The polysilicon layer is finally formed as a stacked word line of the NAND string, and the polysilicon character lines in the same stack are electrically isolated from each other by the buried oxide. Figure 5 illustrates the formation of a hard mask 20, such as tantalum nitride. Figure 6 illustrates the patterning of the hard mask 20 with the retention portion of the hard mask 20 etching portions of the polysilicon 16 and buried oxide 18 that are not obscured by the hard mask. A plurality of word line stacks electrically isolated from each other by the oxide material are formed. Figure 7 illustrates the patterned photoresist 22 to separate a plurality of word line material stacks. Figure 8 illustrates the erosion of the portion of the hard mask 20 that is not protected by the photoresist 22. 201225262 1 w〇j i^nf\ ' * Figure 9 illustrates the removal of the photoresist 22 protecting the hard mask 20 portion. Figure 10 illustrates the etching of the unmasked portion of the polycrystalline stone eve 16 and the buried oxide 18, which is etched up to the gate dielectric layer. The plurality of word line material stacks previously formed which are electrically isolated from each other by the oxide material are effectively doubled in number. Figure 11 illustrates the removal of the hard mask 20. The word line stack formed by the misalignment of the mask affects the thickness of the word line. However, due to the self-alignment ΟΝΟ and the channel deposition process, it is not a problem for the memory cell characteristics. Figure 12 illustrates the formation of material 22, which is simultaneously: (1) an oxide layer entering the gap, the gap formed by the etching step of Figure 10 is such that the adjacent word line stacks are electrically isolated, and (2) The charge storage material 'is, for example, a charge trapping nitride, covering all of the word line rows. For example, an oxide-charge trapping nitride-oxide. Steps (1) and (2) are alternatively performed in other different steps. Figure 13 illustrates the formation of semiconductor channel material 24, such as polycrystalline. Figure 14 illustrates the formation of a top auxiliary gate dielectric layer 26. Figure 15 illustrates the formation of the top auxiliary gate 28. The stacked NAND string of Figure 15 is also referred to as an anti-symmetric vertical stackable NAND memory with auxiliary dual-gate memory (Asymmetrical

Vertical Stackable NAND memory, AVS NAND memory). Since the plurality of word lines of the two stacks under each ridge of the semiconductor channel material effectively doubles the bit density, the stacked NAND strings as shown in Fig. 15 can increase the bit density. 201225262 The top auxiliary gate improves the electrical properties of stacked NAND strings. The bottom auxiliary gate reduces the parasitic channel resistance of the stacked NAND strings. In some embodiments, the top auxiliary gate is connected from the top of the gate and the bottom auxiliary gate is connected from the bottom substrate. The different operating examples for biasing the top auxiliary gate and the bottom auxiliary gate are shown below: Read: The auxiliary gate bias can be the same as the pass gate voltage, for example, 7V to 11V. Programming/Erase: The floating polysilicon channel is important; the negative bias applied to the bottom φ auxiliary gate helps turn the channel off. Programming: For the selected memory cell, apply a negative bias to the top auxiliary gate to increase the electric field and increase the programming speed. A positive bias is applied to the other top auxiliary gates to reduce the electric field, so the programmed distribution is suppressed. For the bottom auxiliary gate, set a negative bias to reduce leakage during programming. Wipe: Block erase is used, and a positive bias is applied to increase the erase field and improve the erase speed. Figure 16 illustrates another example of a stacked NAND string having a top auxiliary gate but no bottom auxiliary gate. The stacked NAND string of Figure 16 is also referred to as an anti-symmetric vertical stackable NAND memory with auxiliary top gate memory. Since the plurality of word lines of the two stacks under each ridge of the semiconductor channel material effectively doubles the bit density, the stacked NAND strings as shown in Fig. 16 can increase the bit density. The top auxiliary gate improves the electrical properties of the stacked NAND strings. Figure 17 shows a bottom auxiliary gate but does not have a top auxiliary 12 201225262

1 w * 7 "/;\ I Another example of a stacked NAND string of helper gates. The stacked NAND string of Figure 17 is also referred to as an anti-symmetric vertical stackable NAND memory with auxiliary bottom gate memory. Since the plurality of word lines of the two stacks under each bump of the semiconductor channel material effectively doubles the bit density, the stacked NAND string as shown in FIG. 17 can increase the bit density. The bottom auxiliary gate reduces the parasitic channel resistance of the stacked NAND string. Figure 18 shows another example of a stacked NAND string without a top auxiliary gate and a bottom auxiliary gate. The stacked NAND string of Figure 18 is also Known as anti-symmetric vertical stackable NAND memory. Since the multiple word lines of the two stacks under each bump of the semiconductor channel material effectively double the bit density, as shown in Figure 18. The stacked NAND string can increase the bit density. Figure 19 shows a simplified block diagram of an integrated circuit with a stacked NAND string. • Figure 19 shows an integrated circuit 1950, which includes an integrated circuit 1950. Improved 3D non-volatile memory Array 1900. A word line decoder and driver 1901 is coupled to a plurality of word lines 1902 disposed along columns in memory array 1900 and is electrically coupled by word line 1902. One bit line decoder And a plurality of drivers 1903 are coupled to a plurality of bit lines 1904 disposed along rows in the memory array 1900 and electrically communicated by bit lines 1904, the rows in the memory array 1900 being used to read The data and the data are written into a plurality of memory cells in the memory array 1900. The address is provided via the bus 1905 to the word line decoding 13 201225262

TW6319PA and driver 丽 and bit line decoder and driver crying. A plurality of sense amplifiers and complex numbers in the intestine are lightly coupled to the bit line solution via the busbar (4) and drive = Cong = input from the brain of the integrated circuit Μ ^ 古治魏士 - 枓 lose Human structure. The data is supplied from the sense amplifier in block 1906 and via the data output line 1915 to a plurality of (four) input streams on the integrated circuit 1950, which are provided to the integrated circuit 1950 (4) or other external data destinations. - The bias setting state is located at circuit 19G9 + ' to control the plurality of bias settings to supply voltage contacts. The biasing means provides a bias to provide a 3D array of any top auxiliary gate and/or bottom auxiliary gate, j. The following illustrations are simulated: (1) Paper presented by Jin (Jiyoung Kim) et al. at the 2009 Technical Presentation of the Very Large Integrated Circuit (VLSI) Technical Digest, titled "For Excess Density and Cost Benefits NAND flash memory device and solid state device (SSD, Solid State Drive) novel vertical stacked array transistor (VSAT, Vertical-Stacked-Array-Transistor) (pp. 186 to 187); (2) For example, the anti-symmetric vertical stackable (AVS) structure 32 shown in Fig. 18; (3) for example, the AVS_AG (top gate) structure 31 shown in Fig. 16; (4) for example, as shown in Fig. AVS_BG (bottom gate) structure 30; and (5) AVS_DG (double gate) structure as shown in Fig. 15, for example

I 201225262 1 vv uj I * Figure 20 shows the relationship between the gate current and the gate voltage of a different analog stacked NAND string. Figure 21 is a table of memory characteristics of a different analog stacked NAND string. This table lists the threshold voltage Vt (threshold voltage), the sub-threshold slope SS (subthrehsold slope), and the transconductance value Gm (transconductance) ° compared to VSAT, other stacked NAND parametric structures with double bit density have Acceptable memory cell characteristics. Figure 22 is a diagram showing the relationship between the threshold voltage of a different analog stacked NAND string and the horizontal pitch. Figure 23 is a diagram showing the relationship between the threshold voltage of a different analog stacked NAND string and the vertical pitch. The auxiliary gate enhances gate control and controls short-channel capability. Figure 24 shows the threshold voltage of a different analog stacked NAND string. • Change the relationship to electron density. It also shows the theoretical limit 34. It is the same as the VSAT' programming window, but has twice the bit density. Figure 25 is a diagram showing the Vpass interference of a different analog stacked NAND string.

The Vpass interference system is related to interference from adjacent pass gates. Figure 26 is a diagram showing the z-interference of a different analog stacked NAND string 201225262 · —— , (Z-interference). The Z interference system is related to interference from adjacent vertical layers. The interference in the other four stacked NAND structures is similar compared to the general VSAT. Figure 27 is a diagram showing the relationship between the threshold voltage and the number of strings of a different analog stacked NAND string. Figure 28 is a diagram showing the relationship between the transconductance pairs of a different analog stacked NAND string. With the design of the auxiliary gate, the on-state current of the stacked NAND string is acceptable. In summary, although the invention has been disclosed above by way of example, it is not intended to limit the invention. A person skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims.

I 201225262 Information w υj 1 1 [Simple description of the drawing] FIG. 1 is an equivalent circuit diagram of a stacked NAND string of an embodiment. The setting of the equivalent circuit diagram is close to the actual physical structure of the stacked NAND string of the embodiment. Settings. 2-15 illustrate a series of process steps for fabricating a stacked NAND string having a top auxiliary gate and a bottom auxiliary gate. Figure 16 is a diagram showing another example of a stacked NAND string having a top auxiliary gate but no bottom auxiliary gate. • Figure P shows another example diagram of a stacked NAND string with a bottom auxiliary gate but no top auxiliary gate. Figure 18 is a diagram showing another example of a stacked NAND string without a top auxiliary gate and a bottom auxiliary gate. Figure 19 is a simplified block diagram of an integrated circuit with stacked NAND strings. Figure 20 is a graph showing the relationship between the gate current and the gate voltage of a different analog stacked NAND string. • Figure 21 shows the memory cell characteristics of a different analog stacked NAND string. Figure 22 is a diagram showing the relationship between the threshold voltage of a different analog stacked NAND string and the horizontal pitch. Figure 23 is a diagram showing the relationship between the threshold voltage of a different analog stacked NAND string and the vertical pitch. Figure 24 is a graph showing the relationship between the threshold voltage change and the electron density of a different analog stacked NAND string. Figure 25 is a diagram showing the relationship of 201225262 ^ I WUJ _ I* interference of a different analog stacked NAND string. Figure 26 is a diagram showing the Z-interference of a different analog stacked NAND string. Figure 27 is a diagram showing the relationship between the threshold voltage and the number of strings of a different analog stacked NAND string. Figure 28 is a diagram showing the relationship between the transconductance pairs of a different analog stacked NAND string. [Main component symbol description] 10: Substrate 12: Bottom auxiliary gate 14: Gate dielectric 16: Polysilicon 18: Buried oxide 20: Hard mask 22: Photoresist or material 24: Semiconductor channel material 26: Top Auxiliary gate dielectric layer 28: top auxiliary gate 1950: integrated circuit 1900: memory array 1901: word line decoder and driver 1902: word line 1903: bit line decoder and a plurality of drivers 1904: bit Yuan line 201225262 > i vy i 7i /jy

I 1905, 1907: Busbar 1906: Block 1908: Bias Setting Supply Voltage 1909: Circuit 1911 Data Input Line 1915: Data Output Line GSL: Ground Selection Transistor SSL: Source Selective Transistor, WL8, WL16, • WU, WL2, WL3, WL4, WL5, WL6, WL7 WL9, WL10, WL1 WL12, WL13, WL14, WL15, WL17, WL18: word line

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Claims (1)

201225262 ' * ·. VII. Patent application scope: '* 1. A memory device comprising: one of a plurality of memory cells and a gate (NAND) string, the memory cells being electrically connected in series to a semiconductor body Between a first end and a second end, the method includes: a plurality of sub-line stacks, and the plurality of character lines located in one of the stacks are electrically isolated from each other, and the stacks Extending out of the semiconductor body, and a semiconductor channel material covering the word line stack, the NAND string passing through the semiconductor channel material, and an electrical series connection between the second end of the string and the second end, the semiconductor channel and the material A plurality of ridges are disposed outside the semiconductor body, wherein the ridge portion of the secret tissue covers a plurality of adjacent stacks of the word line stacks. The memory device according to claim 1 of the patent scope further includes: This electrical (four), electrically isolated (four) semiconductor material material of the second uplift. The adjacent stacks covered by the ridge in the raft. 3. If you apply for a patent scope! The memory device described in the item A bottom auxiliary gate material is covered by the word line stack channel material. a stack and the semiconductor device. 4. The memory device according to claim 1, further comprising a bottom auxiliary material 'four' word line stack and the semiconductor 20 I 201225262 * ο ι yi * body Covered by the channel material, and the control circuit, applying a first bias voltage to the material 'to assist the passage of the semiconductor channel material: string == closed, = apply - second bias to the bottom auxiliary interpole The material, the voltage series of the electrical series member passing through the county conductor channel material is less than the second bias voltage. The first part of the pass 5H: 5. The memory hit as described in item i of the patent application scope, and the bottom part of the auxiliary secret (4) '(4) covered by the four-body channel material, and the control The circuit is applied with a negative bias M to the bottom auxiliary closed-pole material to resist leakage during programming. The material includes: 6. The memory device according to claim 1 of the patent application, further comprising a conductor pass = help _ (four) ' (four) difficult word stack and the half 7. As described in claim 1 The memory device further includes: a human conductor (4), a cover-up stack of 4 pieces, and a semi-assisted (four) (four) clear auxiliary egg material. The memory device according to the first application of the patent scope, including 0 a top assisted difficulty (four), «these word line stacks and the half 21 201225262 conductor channel material, and a control circuit, applying a -first bias to the top auxiliary gate material to assist in the NAND NAND Programming of one of the memory cells in the string, and applying a first-to-first auxiliary interpole material to resist programming of the nand string, the first bias voltage being less than the second bias voltage. 9. The memory device of claim 4, wherein: ??? a charge storage material covering the stack of word lines, the semiconductor channel material covering the charge storage material. 10. The memory device of claim 2, further comprising: an electric 4 storage material 'located adjacent to the ridges covered by the ridges of the radiant portions of the semiconductor channel material between. 11. A method comprising: forming a plurality of memory cells and a gate (NAND) string, the memory cells being electrically connected to - between the first end and the second end of the semiconductor body, comprising: Forming a plurality of first stacks extending beyond the semiconductor body' the stacks in the first stacks comprise a plurality of layers of word line material electrically isolated from each other; a plurality of intermediate portions of a stack to form a plurality of second stacks, the second stacks having more stacks than the first stacks, wherein the second stacks The plurality of word line material layers are the word lines of the 2 memory cells in the NAND string; and 22 201225262 IW〇〇|yri^ the cattle conductor channel material covers the second stacks, The ND string has an electrical series connection between the end and the second end via the semiconductor channel material. 12. The method of claim 5, further comprising: forming a method for covering the semiconductor body before the substrate. 13. The method of claim U, further comprising: forming the Before the stacking member, forming a material covering the bottom-substrate (four) 1 pole material, and (4) the material circuit of the body is applied - first biased to the bottom auxiliary opening pole 2: the second assisting the electrical material passing through the semiconductor channel material The material is: and a second bias is applied to the bottom auxiliary gate to assist passage of the semiconductor channel material through the first voltage system. The guide of the article 14. The method described in the scope of patent application 更 u, further includes: - bottom = material = front 'forms the material covering the semiconductor body, running the bottom auxiliary gate material 1: a patent range 11 The method of the present invention further includes: forming a second auxiliary stack material to cover the second stacking member to form a top auxiliary gate material. The method of claim 11, further comprising: covering the semiconductor via = material covering the second stack, the top (four) channel material 顶部 one of the top auxiliary gate material, and 23 201225262 • y, Tyir\ % t provides a control circuit that applies a first bias voltage to the top auxiliary gate material 'to (4) the memory cell programming in the NAND string, and applies a second bias to the top auxiliary The interpole material is programmed to resist the _AND string, the first bias voltage being less than the second bias voltage. 17. The method of claim 2, further comprising: forming a top auxiliary gate material overlying the semiconductor channel material after covering the second stack with a semiconductor channel material, and A control circuit is applied to the top auxiliary material to assist in erasing the NAND string. 18. The method of claim 5, further comprising: covering the second stack with a charge storage structure prior to covering the second stack with the semiconductor channel material. 19. The method of claim 153, further comprising: forming a non-conductive material in a plurality of gaps formed by removing the intermediate portions. 20. The method of claim 5, further comprising: Forming a non-conductive material in the plurality of gaps formed by removing the intermediate portions, including: covering the second stack members with a + conductor channel material, first covering the second electrical stack And a second stacking member, the charge storage structure comprises a deuterated layer, a -f-loaded storage layer covering the first oxide layer, and a second oxide layer covering the first oxide layer. twenty four