TW201223056A - Over voltage protecting circuit - Google Patents

Abstract

An over voltage protecting circuit coupling between a pad and an analogy signal processing circuit is provided. The over voltage protecting circuit include a voltage detecting unit, a P type transistor and a N type transistor. A gate and a bulk of the P type transistor respectively receives a gate driving voltage and a control voltage come from the voltage detecting unit. Sources and drains of the P type transistor and N type transistor are coupled the pad and the analogy signal processing circuit. A gate of the N type transistor receives a operation voltage. When an inputting voltage come from the pad is lower than the operation voltage, the gate driving voltage is enabled, the control voltage is equal to the operation voltage. When the inputting voltage is higher than the operation voltage, the gate driving voltage is disabled, the control voltage is equal to the inputting voltage.

Description

201223056

-0085-TW 36197twf.doc/I VI. Description of the Invention: [Technical Field] The present invention relates to a protection circuit, and more particularly to an overvoltage protection circuit disposed in a wafer. [Prior Art] With the prevalence of the system design concept, the function of the touch circuit is also strong and complicated. In order to integrate many functions on the same chip, the number of output pins of the chip is also increasing. "Because the packaging cost of the high circuit is very high, the integrated circuit package is also improved." Therefore, it is necessary to re-integrate the cost of the integrated circuit into the design cost. In order to overcome the problem of insufficient pins, in addition to increasing the number of pins, it can also be received through the same pin in the mode. Different types of == can receive digital signals and staff ratios in different modes through the same-pin. (4) - Generally speaking, the voltage of the digital high-level will be close to $2 and the voltage of the analog signal will be between G is between 3 and 3 volts. Therefore, the withstand voltage of the digital processing circuit is usually designed to be 5V, _bit signal, the _ of the circuit is usually designed to be 3·3ν, and the voltage of the digital processing circuit is usually 5V. The operating voltage of the analog-like processing circuit is usually ',,, 3.3V. More specifically, the upper limit of the voltage that the high-level voltage component of the digital signal can withstand. Analogy However, when the digital signal processing circuit and the analog bit signal deal with When the road with the same pin, pin electrical dust may be receiving close to 5V (ie, high level

201223056 HM-2OlO-0085-TW 36197twf.doc/I voltage) digital signal. At this time, when the analog bit signal processing circuit receives the digit # of the near 5V, the bit signal processing circuit is damaged because the received voltage exceeds the financial pressure. Therefore, in the pin and the analog bit signal ^ circuit configuration - the circuit, the bribe analog bit L said that the processing circuit is not destroyed by the digital signal of the high level voltage. SUMMARY OF THE INVENTION The present invention provides an overvoltage protection circuit that is disposed between a processing circuit of a chip to prevent an input voltage from being transmitted to an analog processing circuit when the input voltage received by the pin is a large operating voltage. This protection is analogous to signal processing circuits. The invention provides an overvoltage protection circuit and a __ rational circuit _: '== === The voltage protection circuit is lightly connected to the pin and the electrical and the first N-type transistor. Electricity: electricity === into the electricity __ drive electricity = Lishi 'to the Langji drive voltage, (four) ^ ^ into the motor than the work remuneration 'forbidden closed pole power = at the input voltage. The first voltage unit of the first P-type transistor receives the gate driving voltage, and the first-p-type two-cardiac sensing unit receives the control power, the first-P-type source, and the extreme -p type transistor of the second 201223056

HM-2O1U-0085-TW 36197twf.doc/I 类 analog signal processing circuit. The control end of the first N-type transistor receives the operating voltage, and the first source/汲 terminal of the first N-type transistor is coupled to the first source and the terminal of the first p-type transistor, and the first N-type transistor The second source/no end is coupled to the second source/汲 terminal of the first germanium transistor. In an embodiment of the invention, the voltage detecting unit includes a voltage generating unit and a gate driving unit. The voltage generating unit is coupled to the pin to output the control voltage and the switching voltage according to the input voltage. When the input voltage is less than or equal to the operating voltage, the control voltage is equal to the operating voltage, and the switching voltage is less than or equal to the operating voltage minus the threshold voltage. When the input voltage is greater than the operating voltage, the control voltage and the switching voltage are equal to the input voltage ◎ the gate driving unit coupling pin and the voltage generating unit to output the gate driving voltage according to the input voltage, the control voltage and the switching voltage. When the input voltage is less than or equal to the operating voltage, the gate drive voltage is enabled. When the input voltage is greater than the operating voltage, the gate drive voltage is disabled. In an embodiment of the invention, the voltage generating unit includes a first defect, a first radiant point, a step-down unit, a second p-type transistor, a third p-type transistor, and a fourth 电-type transistor. The first node outputs a switching voltage. The first node outputs a control voltage. The buck unit receives the input voltage, and the output of the buck unit is coupled to the first node. The first control terminal of the second 电-type transistor receives the operating voltage, the first source/汲 terminal of the second p-type transistor receives the input voltage, and the second source/汲 terminal of the second Ρ-type transistor is coupled to the first node The second control end of the second die transistor is coupled to the second node. The first control end of the third p-type transistor is coupled to the first node, the first source/汲 terminal of the third p-type transistor receives the working voltage, and the second source of the third p-type transistor has no terminal 201223056 HM- 20I0-0085-TW 36197twf.doc/I ^Connected to f-point' The second control terminal of the second P-type transistor is coupled to the second section. The first control terminal of the fourth P-type transistor receives the operating voltage, The first source/sigma terminal of the four p 2 crystal receives the input voltage, and the fourth::::= is connected to the second node, the first one is in the embodiment of the present invention. Crystal. The second (four) transistor controls her to act as a voltage, and the first source/secret of the second N-type transistor receives the second source/汲 terminal _ node of the input. In an embodiment of the invention, the step-down feature includes a first resistor coupled between the input voltage and the first node. - In an embodiment of the invention, the above-described open-pole driving unit comprises a fourth point, a voltage dividing unit, a buffer material, a fifth p-type transistor, a sixth p-crystal, and a third N-type transistor. The third node turns off the gate drive voltage. The voltage dividing unit reduces the voltage generating unit to receive the butterfly voltage, and according to the control voltage, the buffer unit _ voltage dividing unit is used to divide the wheel standard voltage. The first control terminal of the fifth P-type transistor is connected to the voltage to generate the switching voltage, the third (p) of the fifth p-type transistor is connected to the buffer unit to receive the level voltage, and the second of the fifth p-type transistor is The source voltage generating unit receives the control voltage. The terminal end of the sixth 电 type transistor receives the working power, the first source of the sixth Ρ type transistor/no extreme pin is connected to receive the input voltage, the second and the extreme output of the sixth 电 type transistor The sixth reference voltage to the third node, the second control of the sixth 电 type transistor

201223056 HM-2010-0085-TW 36197twf.doc/I terminal is coupled to the voltage generating unit to receive the control voltage. The control end of the third N-type transistor is coupled to the operating voltage, the first source/汲 terminal of the third N-type transistor is coupled to the buffer unit to receive the level voltage, and the second source/汲 terminal of the third N-type transistor The third node is coupled. In an embodiment of the invention, the voltage dividing unit is composed of a plurality of N-type transistors connected in series. In an embodiment of the invention, the voltage dividing unit comprises a second resistor and a third resistor. The first end of the second resistor is coupled to the voltage generating unit to receive the control voltage, and the second end of the second resistor outputs the divided voltage. The first end of the third resistor is coupled to the second end of the second resistor, and the second end of the third resistor is coupled to a ground voltage. The resistance value of the third resistor is smaller than the resistance value of the second resistor. In an embodiment of the present invention, the buffer unit includes a first inverter and a second anti-arm, and the input end of the first-inverted phase II is connected to the voltage dividing unit to receive the partial pressure and the second inversion (four). The output terminal of the input terminal _ the first inverter and the output terminal of the second inverter output the voltage. D. In the present invention, the buffer unit includes a comparison, and the above divided voltage and comparison voltage are compared to output a level voltage. Based on the above-mentioned 'this type of pressure circuit, which is arranged between the analog signal and the pin, the overvoltage (four) circuit is when the input voltage is greater than the work rule, and the input voltage is greater than the threshold voltage. The analogy of the input voltage is destroyed in the over-the-counter input voltage. The above features and advantages of the present invention can be more clearly understood, and the following is a detailed description of the following. 201223056

HM-2010-0085-TW 36197 twf.doc/I [Embodiment] Fig. 1 is a partial system diagram of the inside of a wafer according to an embodiment of the present invention. Referring to FIG. 1, in the embodiment, the wafer includes at least a pin PD, a digital processing circuit 20, an overvoltage protection circuit 1A, and an analog signal processing circuit 30. The digital signal processing circuit 2 is coupled to the pin pD to receive the input voltage Vin, and the overvoltage protection circuit 1 is connected between the pin pD and the analog signal processing circuit 30 to protect the analog signal processing circuit. The destruction of the voltage. The operating voltage of the digital signal processing circuit is assumed to be 5V, and the operating voltage VDD of the analog signal processing circuit 3〇 is assumed to be 3.3V, and the digital signal processing circuit 2〇 and the analog signal processing circuit 30 are assumed to be not simultaneously turned on. In other words, when the digital signal processing circuit 2 is turned on, the digital signal processing circuit 20 can directly receive the digital signal through the pin PD (ie, the input voltage Vin will switch between approximately 0V and approximately 5V), and when the input voltage Vin is close to At 5V, the overvoltage protection circuit 1〇〇 will be non-conducting to prevent the input voltage Vin from destroying the analog signal processing circuit. When the analog processing circuit 30 is turned on, the overvoltage protection circuit 100 will be turned on to transmit. The analog signal received by the pin PD (ie, the input voltage Vin will be between 0V and 3.3V) to the analog signal processing circuit 3 and the digital signal processing circuit 20, and since the operating voltage of the digital signal processing circuit 2 is 5V' That is, the digital signal processing circuit 2() has a dust resistance greater than 5V. Therefore, the digital signal processing circuit 2 (^ will be destroyed by the influence of the analog signal. Further, the overvoltage protection circuit 1 includes a voltage detecting unit. 201223056

Ruvi-, such as i \>0085-TW 36197twf.doc/I 110, transistor PM1 (i.e., first p-type transistor) and can (i.e., first N-type transistor). The voltage detecting unit 11 is coupled to the pin pD to output the gate driving voltage VGD and the control voltage VCL according to the input voltage vin received by the pin PD. The gate of the transistor PM1 (ie, the first control terminal) is connected to the voltage detecting unit 110 to receive the gate driving voltage VGD, and the bulk (second control) end of the transistor pMi is coupled to the voltage detecting unit 11 To receive the control voltage VCL, the source of the transistor PM1 (ie, the first source/汲 terminal) is coupled to the pin PD, and the drain of the transistor PM1 (ie, the second source/汲 terminal) is coupled to the analog signal processing circuit. The gate (ie, the control terminal) of the transistor NM1 receives the operating voltage VDD of the analog signal processing circuit 30, and the source (first source/汲 terminal) of the transistor NM1 is coupled to the source of the transistor PM1, and the transistor NM1 is turned on. The pole (ie, the second source/汲 terminal) is coupled to the drain of the transistor PM1. When the pin pD is receiving a digital signal, the input voltage Vin will be close to 〇v or close to 5V. When the input voltage Vin is close to 5V (that is, greater than the operating voltage VDD and the voltage difference between the input voltage Vin and the operating voltage VDD is greater than the threshold voltage), the control voltage VCL output by the voltage detecting unit 110 is close to 5V (that is, greater than the operating voltage VDD). And the voltage detecting unit 11() disables the gate driving voltage VGD (for example, a high-level voltage close to 5v), so that the transistor pM1 is not turned on because its gate is close to or the same as the voltage of its body. And since the input voltage Vin is greater than the operating voltage VDD, that is, the voltage of the source of the transistor NM1 is higher than the voltage of its gate, the transistor NM1 is also rendered non-conductive. When the pin PD is receiving the analog signal, the input voltage vin is between ov

201223056 HM-2010-0085-TW 36197twf.doc/I to 3_3V, that is, the input voltage Vin is less than or equal to the operating voltage vdd. When the input voltage Vin is less than or equal to the operating voltage VDD, the control voltage VCL output by the voltage detecting unit 110 is equal to the operating voltage VDD, and the voltage detecting unit 110 enables the gate driving voltage VGD (for example, a low level close to ον). Voltage), at this time, the transistor PM1 and the transistor 1^1; 11 form a complementary transmission switch to transmit the input voltage Vin to the analog signal processing circuit 3〇. 2 is a system diagram of the voltage detecting unit of FIG. 1 according to an embodiment of the invention. Referring to Figures 1 and 2, in the present embodiment, the voltage extraction unit 110 includes a voltage generating unit 21A and a gate driving unit 220. The voltage generating unit 210 is coupled to the pin pd' to output the control voltage VCL and the switching voltage VSW in accordance with the input voltage vin. When the input voltage Vin is less than the operating voltage VDD, the control voltage VCL is equal to the operating voltage VDD, and the switching voltage VSW is equal to the operating voltage VDD minus the threshold voltage (threshold). When the input voltage vin is greater than the operating voltage VDD (i.e., the high level voltage of the digital signal is 5V), the control voltage VCL and the switching voltage VSW will be equal to the input voltage Vin. The gate driving unit 220 is coupled to the pin PD and the voltage generating unit 210 to output the gate driving voltage VGD according to the input voltage Vin, the control voltage VCL, and the switching voltage VSW. When the input voltage Vin is less than or equal to the operating voltage VDD, the gate driving voltage VGD is enabled. When the input voltage Vin is greater than the operating voltage VDD, the gate drive voltage VGD is disabled. 3 is a schematic diagram of the system of the voltage generating unit of FIG. 2 in accordance with an embodiment of the present invention. Referring to FIG. 1 to FIG. 3, in this embodiment, voltage generation

S 11

201223056 mvwuiu-0085-TW 36197twf.doc/I unit 210' includes a node N1 (ie, a first node), N2 (ie, a second node), a buck unit 310, a transistor PM2 (ie, a second p-type transistor), pM3 (ie, the third P-type transistor) and PM4 (ie, the fourth P-type transistor). Node N1 outputs the switching voltage VSW. The node N2 outputs a control voltage VCL. The buck unit 310 engages the pin PD to receive the input voltage vin and is lightly connected to the node N1. The gate of the transistor PM2 receives the operating voltage VDD'. The source of the transistor PM2 receives the input voltage vjn, the drain of the transistor pM2 is coupled to the node N2, and the body of the transistor PM2 is coupled to the node N2. The gate of the transistor PM3 is connected to the node N1 to receive the switching voltage VSW', the source receiving operating voltage vdd of the transistor PM3, the drain of the transistor PM3 is coupled to the node N2, and the body of the transistor PM3 is coupled to the node 1^ . The gate of the transistor PM4 receives the operating voltage VDD, the source of the transistor pM4 receives the input voltage Vin', the pole of the transistor PM4 is connected to the node N2, and the body of the transistor PM4 is coupled to the node N2. According to the circuit operation of Fig. 3, when the input voltage Vin is less than or equal to the operating voltage VDD, the transistors PM2 and PM4 are not turned on because the voltage of the gate is greater than the voltage of the source. Further, the voltage of the node N1 (i.e., the switching voltage VSW) is lower than or equal to the operating voltage VDD by a threshold voltage. The transistor PM3 is turned on because the voltage of its gate is less than the voltage of its source (ie, the operating voltage VDD) and the voltage difference between its gate and its source is greater than or equal to a threshold voltage, so that the voltage of the node N2 (also That is, the control voltage VCL) will be equal to the operating voltage VDD. When the input voltage Vin is greater than the operating voltage VDD (ie, the digital signal high level voltage is 5V), the transistors PM2 and PM4 will be due to the voltage of their gates.

201223056 HM-2010-0085-TW 36197twf.doc/I is less than the voltage of its source and its voltage difference is greater than one voltage and turns on the voltage of node N1 (ie, switching voltage v input voltage Vm. The crystal HPM3 will not conduct due to the voltage of its gate being greater than the voltage of its source. At this time, the voltage of the node N2 (that is, the (four) lightning voltage VCL) is equal to the input voltage Vin. Further, in this embodiment, the step-down unit 31〇 includes the transistor nm2 (ie, the second N-type transistor), the gate of the transistor should be coupled to the operating voltage DD, the transistor of the transistor NM2 and the receiving input of the transistor Vin, the source of the transistor NM2 is coupled. Node N1. The transistor NM2 is turned on under the condition that the voltage difference between the gate and the source must be greater than or equal to the threshold voltage, because the voltage of the source of the transistor NM2 is equal to the operating voltage VDd minus the threshold voltage, that is, the node The voltage of N1 is equal to the operating voltage VDD minus the threshold voltage. Fig. 4 is a schematic diagram of the system of the voltage generating unit according to another embodiment of the present invention. Referring to Figs. 3 to 4, the voltage generating units 21〇, 21, and 21〇 The difference is in the buck unit 410. In this embodiment The buck unit 41A includes a resistor R1 (ie, a first resistor) that is lightly connected between the input voltage Vin and the node N1, wherein the resistance value of the set resistor ri is transmitted such that the voltage of the node N1 is less than or equal to the operating voltage VDD minus FIG.5 is a schematic diagram of a system of a gate driving unit according to an embodiment of the invention. Referring to FIG. 1, FIG. 2 and FIG. 5, in the embodiment, the gate driving unit 220 includes a node N3 ( That is, the third node), the voltage dividing unit 51〇, the buffer unit 520, the transistor PM5 (ie, the fifth P-type transistor), pm6 (ie, the sixth P-type transistor), and the NM3 (ie, the third N-type transistor) The node N3 outputs the gate driving voltage VGD. The voltage dividing unit 510 is coupled to the voltage 13 201223056

-U085-TW 36197twf.doc/I generating unit 210 receives the control voltage VCL and outputs a divided voltage VD according to the control voltage vcl, that is, dividing the control voltage VCL to output a divided voltage VD 'for example, the divided voltage Vd is smaller than the control Half of the voltage vcl. The buffer unit 520 is coupled to the voltage dividing unit 510 to output the level voltage VL according to the divided voltage VD. When the divided voltage VD is greater than or equal to one half of the operating voltage, the 'level voltage VL is a high level voltage (for example, 3jv). When the divided voltage VD is less than half of the operating voltage VDD, the level voltage VL is: a level voltage (for example, 0V). The gate of the transistor PM5 is coupled to the voltage generating unit=〇 to receive the switching voltage vsw, the source of the transistor PM5 is coupled to the buffer 520 to receive the level voltage VL, and the drain of the transistor pM5 is coupled to the node N3. The body of the transistor PM5 is coupled to the voltage generating unit 21 to receive the control voltage VCL. The gate of the transistor PM6 receives the operating voltage vdd, the source of the transistor PM6 is coupled to the pin PD to receive the input voltage Vin, the drain of the transistor pM6 is coupled to the node N3, and the body pole coupling voltage of the transistor pM6 is generated. Unit 210 receives the control voltage VCL. The gate of the transistor NM3 is coupled to the operating voltage VDD' transistor NM3. The source is coupled to the buffer unit 52A to receive the level voltage VL, and the gate of the transistor NM3 is coupled to the node N3. According to the circuit operation of FIG. 3 and FIG. 5, when the input voltage Vin is less than or equal to the working voltage VDD, the switching voltage VSW is less than or equal to the operating voltage VDD, and a threshold voltage is lowered. When the control voltage is ,, (4) VD is less than the operating voltage = the output of the buffer unit 520 The level voltage VL will be a low level voltage (ie ον). Also, the transistor PM6 will have a voltage greater than or equal to its gate 2012-0556

HM-2010-0085-TW 36197twf.doc/I The voltage of the source is not turned on. The transistors PM5 and NM3 form a complementary transfer switch, which transmits the level voltage VL to the node N3 (ie, the gate drive voltage VGD). ).

When the input voltage Vin is greater than the operating voltage VDD (i.e., the digital signal high level voltage is 5V), the switching voltage VSw and the control voltage VCL are equal to the input voltage Vin. Since the control voltage VCL rises, the divided voltage VD rises, and the level voltage VL output from the buffer unit 520 will be the operating voltage VDD. At this time, the transistor PM6 will be turned on because the voltage of its gate is less than the voltage of its source and the voltage difference between its source and its gate is greater than the threshold voltage. Therefore, the voltage of the node N3 (ie, the gate driving voltage VGD) will be Input voltage Vin. Further, in the present embodiment, the voltage dividing unit 51A includes transistors NM4 to NM8. The gates of the transistors NM4 to NM8 are all coupled to the drain thereof, that is, the gate of the transistor NM4 is coupled to the drain of the transistor ^^4, and the gate of the transistor NM5 is coupled to the gate of the transistor NM5. Extreme, the rest is like this. Moreover, the drains of the transistors NM5 to NM8 are coupled to the source of the previous transistor, that is, the drain of the transistor NM5 is coupled to the source of the transistor NM4, and the drain of the transistor NM6 is coupled to the transistor NM5. The source, the rest, and so on. In addition, the drain of the transistor NM4 is coupled to the voltage generating unit 21A to receive the control voltage VCL, the source of the transistor NM6 is divided by the voltage VD, and the source of the transistor NM8 is coupled to the ground voltage. According to the above, the control voltage VCL is greater than the operating voltage vdd (ie 2) and the transistor _~NM8 is to be turned on. The voltage difference between the pole and the source must be greater than or equal to the threshold voltage, so in the real NM4~NM8 (ie For example, five Lei Riji, Mochu. 0 electric Japanese body erects an electric scorpion). And, with the output partial pressure 15

201223056 ηινι-^υιυ-0085-TW 36197twf.doc/I node, three voltage transistors NM4~NM6 are arranged above the voltage dividing node, and two transistors NM7 and NM8 are arranged below the voltage dividing node, so the voltage dividing VD will be It is equal to 2/5 times of the control voltage VCL (ie, less than half of the control voltage VCL). However, the number of transistors of other embodiments of the present invention is not limited thereto, and may be adjusted according to the circuit design, and the partial voltage VD is smaller than half of the control voltage VCL by the effect of serial voltage division through the transistor. . For example, two transistors are placed above the voltage divider node, and one transistor is placed under the voltage divider node. Furthermore, in the present embodiment, the buffer unit 520 includes an inverter NOT1 (ie, a first inverter) and a NOT2 (ie, a second inverter). The input end of the inverter NOT1 is coupled to the voltage dividing unit 510 to receive the divided voltage VD, the input end of the inverter NOT2 is coupled to the output end of the inverter NOT, and the output end of the inverter NOT outputs the level voltage VL. When the divided voltage VD is less than, for example, half of the operating voltage VDD, the inverter N〇T1 outputs a high level voltage, and the inverter NOT2 outputs a low level voltage (i.e., the level voltage VL). When the divided voltage VD is greater than or equal to half of the operating voltage VDD, the inverter N〇T1 will output a low level voltage, and the inverter N〇T2 will output a high level voltage (ie, the level voltage VL). Figure 6 is a schematic diagram of the system of the gate driving unit of Figure 2 in accordance with another embodiment of the present invention. Referring to FIGS. 5 and 6, the gate driving units 22A and 22B are different from the voltage dividing unit (10) and the buffer unit 62G. In the present embodiment, a knife unit 610 includes a resistor (ie, a second resistor) and R3 (ie, a second resistor. The first end of the resistor R2 is connected to the voltage generating unit 21A to receive the control voltage VCL 'the second end of the resistor R2 Output divided voltage VD. Resistance 201223056

HM-2010-0085-TW 36197twf.doc/I The third end of R3 is connected to the second end of resistor R2, and the second end of the resistor is connected to the ground voltage. Wherein the resistance value of the resistor R3 is smaller than the resistance value of the resistor such that the divided voltage VD is less than half of the control voltage VCL. The buffer unit 620 includes a buffer. When the dust separation is less than -^ of the working electric dust vDD, the level voltage VL of the buffer BF is a low level voltage; when the partial pressure VD is greater than or equal to a sheep of the working voltage VDD The level voltage VL output by the buffer bf is a high level voltage (ie, the operating voltage vdd). ® 7 is a system diagram of Figure 2 in accordance with a further embodiment of the present invention. Referring to Figures 5 and 7, the gate drive unit 220,, and 220' differ from the top of the buffer unit. Buffer list = 710 in this embodiment includes a comparator (implemented here with an operational amplifier 〇p). The negative input terminal of the operational amplifier OP receives the comparison voltage VCM, the positive input terminal of the operational amplifier OP receives the divided voltage VD, and the output terminal voltage VL of the output terminal A|| 〇p, wherein the comparison voltage VCM, for example, is equal to Half of the operating voltage VDD. In summary, the overvoltage protection circuit of the embodiment of the present invention is configured between the analog signal processing circuit and the pin, and the overvoltage protection circuit is used when the digital signal processing circuit receives the digital signal through the pin. When the digital signal is at a high level voltage, it does not conduct, so as to avoid the high level of the digital signal to destroy the analog signal processing circuit. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the invention, and any one of ordinary skill in the art can make some modifications and refinements without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.

201223056 HM-7U10-0085-TW 36197twf.doc/I [Simplified Schematic] FIG. 1 is a partial system diagram of the inside of a wafer according to an embodiment of the present invention. 2 is a schematic diagram of a system of a voltage detecting unit according to an embodiment of the invention. Figure 3 is a schematic diagram of the system of the voltage generating unit of Figure 2 in accordance with an embodiment of the present invention. 4 is a schematic diagram of a system of a voltage generating unit according to another embodiment of the present invention. FIG. 5 is a schematic diagram of the system of the gate driving unit of FIG. 2 according to an embodiment of the invention. FIG. FIG. 6 is a schematic diagram of the system of the gate driving unit of FIG. 2 according to another embodiment of the present invention. FIG. 7 is a schematic diagram of the system of the gate driving unit of FIG. 2 according to still another embodiment of the present invention. [Description of Main Component Symbols] 10. Wafer 20: Digital Signal Processing Circuit 30: Analog Signal Processing Circuit 100: Overvoltage Protection Circuit 110: Voltage Detection Unit 210, 210', 210'': Voltage Generation Unit 18 201223056

HM-2010-0085-TW 36197twf.doc/I 220, 220', 220", 220",: gate drive unit BF: buffers N1 to N3: node NCm, NOT2: inverter OP: operational amplifier PD: Pins PM1 to PM6, NM1 to NM8: Transistors R1 to R3: Resistor VCL: Control voltage VCM: Comparison voltage VD: Divided voltage VDD: Operating voltage VGD: Gate drive voltage

Vin : input voltage VL : level voltage VSW : switching voltage

19

Claims (1)

201223056 hm-2U i υ-0085-TW 3 6197twf.doc/I Seventh 谞 谞 利 范 : :: 1. An overvoltage protection circuit for a pin, signal processing circuit and analog signal processing Wei - The chip, the ancient processing power _ is connected to the pin, the overvoltage protection circuit is pure _ ^ and the analog § § processing circuit, the overvoltage protection circuit includes: - voltage side unit, _ the pin, to An input voltage received by the pin outputs a gate driving voltage and a control voltage, and the input voltage is less than or equal to _ the operating voltage of the signal processing circuit, the gate driving voltage is enabled, and the control voltage is equal to the working Voltage, when the input impurity is greater than the resident voltage, disable the voltage of the extreme pole, '5 hai control voltage is equal to the input liang; - the first Ρ type transistor, the first -! The first control end of the type transistor is connected to the voltage side unit to receive the gate driving voltage, and the second control end of the first p-type transistor is connected to the voltage The first source/secret of the 电-type transistor is connected to the pin, the second source/汲 terminal of the g-P type transistor is coupled to the type of circuit; and ▲-the first-N type transistor 'the first N-type The control terminal of the transistor is connected to the metastatic working voltage. The first source of the first transistor is connected to the first source/no terminal of the first P-type transistor, and the second source of the first N-type transistor is汲 Extreme _ The second source of the first-P-type transistor / no extreme. 2. The overvoltage protection circuit according to claim 1, wherein the voltage detecting unit comprises: a voltage generating unit coupled to the pin to input E according to the input voltage. 20 201223056 HM-2010- 0085-TW 36197twf.doc/I The control voltage and the -switch voltage are outputted, wherein when the wheel turns over the voltage, the control touches the working voltage, and the switching voltage is subtracted from the working voltage _ voltage, when the input is t voltage, the control voltage and the switch voltage are equal to the input power-gate drive unit, coupled to the pin and the voltage generates μ _ , !ί, the control voltage and the switch voltage Transmit two poles: When the input voltage is less than or equal to the servo voltage, the (four) pole drive voltage is enabled, when the input voltage is greater than the operating voltage of the working core S. 7: The overvoltage protection circuit described in the second paragraph of the patent b, the voltage generating unit in the basin includes: I (four)" - the first node outputs the switching voltage; a second node outputs the control voltage; a voltage unit that receives the input voltage and the buck unit end is coupled to the first node; J: a second P-type transistor, the first control end of the second P-type transistor receives the operating voltage, the second PS The first source/secret of the transistor receives the voltage, and the second source/secret of the second p-type transistor consumes the first point. The second control end of the first-P-type transistor is coupled to the first a second node; an off-type transistor, the first control terminal of the third p-type transistor is coupled to the first-_, and the first source/secret terminal of the third P-type transistor receives the voltage=the first The second source/secret of the three p-type transistor is lightly connected to the first node, and the second control end of the fifth p-type transistor is coupled to the second section 21 201223056 mvwi; i0-0085-TW 36197twf.doc /I point; and - a fourth P-type transistor, the first control terminal of the fourth P-type transistor receives the operating voltage, the fourth p-type transistor The first source is the second control terminal of the p-type::-type transistor: the second source of the transistor is not extremely lightly connected, and the second control terminal of the fourth 1>-type transistor_the second 4. The overvoltage protection circuit of the overvoltage protection circuit according to claim 3, wherein the control terminal of the first type of power supply (4) is coupled to the operating voltage, the second N The second source of the type transistor / the second source of the second N-type transistor is connected to the first defect. "5. Please refer to the third item of the patent scope. An overvoltage protection circuit, A1; comprising: a first resistor coupled to the input voltage and the (4) 2 (4) overvoltage circuit, a second node 'outputting the gate driving voltage; crimping the voltage generated The unit receives the control voltage and outputs a partial pressure according to the control voltage; the electric level ίί punching unit, the sub-county element, the recording _ partial pressure output one-fifth 电 type transistor 'the fifth ρ type electric The first control of the crystal == voltage generates a single it to receive the _ ^ connected to the buffer unit to receive the quasi-two aB, the first source / 汲 terminal is coupled to the third section Point, the fifth 22 201223056 HM-2010-0Q85.TW 36197twf.doc/I second control end of the crystal is coupled to the voltage generating unit to receive the control-sixth P-type transistor, the sixth p-type transistor The first - receiving the operating voltage, the sixth p-type transistor is connected, the sixth, the second and the second - the sixth reference voltage to the third node, the third Terminal coffee voltage generating unit to receive: control J Connected to the ^^-type transistor, the control end of the third N-type transistor is switched to the operating voltage, and the third N-type transistor is turned over to the source, and the second unit is used to receive the level voltage. The first/next pole of the N-type transistor is coupled to the third node. A source 7. The overvoltage protection circuit as described in claim 6 is composed of a plurality of N-type transistors connected in series. <8. The overvoltage protection unit of claim 6, wherein: the first voltage is coupled to the voltage generating element to receive the control voltage, The second end of the second resistor outputs the voltage divider; and the third resistor, the first end of the third resistor is coupled to the second end of the second resistor, and the second end of the third resistor is coupled to a ground a voltage, wherein a resistance value of the second resistor is less than a resistance value of the second resistor. 9. The overvoltage protection circuit of claim 6, wherein the buffer unit comprises a "first" inverter and a second inverter, the second 23 • 0085-TW 36197 twf. doc / I 201223056 An input end of the inverter is coupled to the voltage dividing unit to receive the voltage dividing unit, an input end of the second inverter is coupled to an output end of the first inverter, and an output end of the second inverter outputs the Level voltage. 10. The overvoltage protection circuit of claim 6, wherein the buffer unit comprises a comparator that compares the divided voltage with a comparison voltage to output the level voltage. twenty four