201220696 六、發明說明： 【發明所屬之技術領域】 以及應用該時間放大電路之鎖 本發明係關於時間放大電路 相迴路。 L无刖技術】 第Μ圖為習知時間放大器之示意圖。 係用以將輸入時間訊號⑶^的相位差 大二 將上述時間訊號轉換成具有較 •而 CKI⑽及CK2⑽。其t，該放^ ^差丁_的輸出時間訊號 Ατ = Ι^ 〇 ’、 V ^ Α的時間增益即可表示為： Τ,η 第圖則為習知時間放大器之詳細電 圖可知’該習知時間放大器係由兩铜SR閃鎖電路所構/ Α、Β分別接收時間訊號CK1盥 ’以、點 出時間訊號⑵一二 持性曲線。由於兩臼銘带扑 、電路之延遲 丁价，因而使得兩SR _電二自二時間偏移 :。第2:圖則為時間放大—特: = 圖中刀別向左右偏移的兩特性曲線相減而得。從』 =現’習知時間放大器操作的線性範圍是 ;二輕 而電路運作在、與^之外將會變得極不料。^間’ 因此’本發明提出-種具有更佳特性曲線的時間放大器。 【發明内容】 本發明提供一種時間放大電路，用以放大 第—時鐘訊號與 201220696201220696 VI. Description of the invention: [Technical field to which the invention pertains] and the application of the lock of the time amplifying circuit The present invention relates to a phase loop of a time amplifying circuit. L flawless technology] The figure is a schematic diagram of a conventional time amplifier. It is used to convert the phase difference of the input time signal (3)^ to two. The above time signal is converted into CKI(10) and CK2(10). The time gain of the output time signal Ατ = Ι^ 〇', V ^ Α of the ^ 差 、 、, V ^ 即可 can be expressed as: Τ, η The figure is a detailed electric diagram of a conventional time amplifier. The conventional time amplifier is constructed by two copper SR flash lock circuits / Α, Β respectively receive the time signal CK1 盥 'to, point out the time signal (2) one or two holding curve. Due to the delay of the two 臼明, the delay of the circuit, the two SR _ electric two are offset by two times: 2nd: The graph is time-magnification--: = The two characteristic curves of the knife in the figure are offset to the left and right. From the 』 = now, the linear range of the time amplifier operation is; the second is light and the circuit will operate unexpectedly and outside of ^ will become extremely unexpected. Therefore, the present invention proposes a time amplifier having a better characteristic curve. SUMMARY OF THE INVENTION The present invention provides a time amplifying circuit for amplifying a first clock signal and 201220696
-第二時鐘訊號間之相位差，包括：一輸入相位偵測器⑽说 detect⑴·），用以接收第一時鐘訊號及該第二時鐘訊號，並依據該第 一時鐘訊號與該第二時鐘訊號間之相位差，分別將該第—時鐘訊 號及該第二時鐘訊號轉換成具有不同脈寬之一第一脈衝訊號及一 第二脈衝訊號；以及-時間放大單元，更包括：—第—閘式環形 振盪器（gated ring osciilator)，耦接至該輸入相位偵測器，用以依 據該第一脈衝訊號之脈寬延遲該第—脈衝訊號；一第二閘式環开j 振盪器，耦接至該輸入相位偵測器，用以依據該第二脈衝訊號之 脈寬延遲該第二脈衝訊號；以及—輸出相位仙器，_接至該第 -及第二閘式環形振盛器，用以輸出—第三脈衝訊號及—第四脈 衝訊號，並依據該延遲後的第-脈衝訊號及第二脈衝訊號之位 準’輸出-重設訊號以重設該第—及第二閘式環形振堡器，以及 輸出相位偵測器。 本發明另提供-種鎖相迴路，包括：一時間放大電路，包括： 幸則入相位偵測器’用以接收第一時鐘訊號及該第二時鐘訊號， 並依據該第-時鐘訊號與該第二時鐘訊號間之相位差，分別㈣ 第里5孔5虎及該第二時鐘訊號轉換成具有不同脈寬之一第一臉 衝訊號及-第二脈衝訊號；以及至少—時間放大單^,更包括： :第-閘式環形振盪器，Μ接至該輸人相位偵翻1以依據該 弟—脈衝訊號之脈寬延遲該第—脈衝訊號；—第二閘式環形振盛 器’叙衫該輸人相㈣測器’用以依據該第二脈衝訊號之脈究 延遲（第二脈衝訊號；以及—輸出相位偵測器，_接至該第一及 第二閘式環形振i器，用以輪出—第三脈衝訊號及—第四脈衝訊 虓’亚依據該延遲後的第-脈衝訊號及第二脈衝訊號之位準，輸 出一重設訊號以重設該第-及第二閘式環形㈣器，以及輸出相 201220696 位偵測，充電泵，用以依據該時間放:大單元之輸出而調整一 充電泵電机，低通濾波器，用以受該充電泵電流之充放電而產 生乙制電愚1，一壓控振盪器，用以依據該控制電壓輸出一最終 乂及陈頻器，用以將該最終時鐘訊號之頻率除以一 數值而產生-除頻時鐘訊號，以供該輸入相位偵測器比較該第— 時鐘訊號及該第二時鐘訊號之用。 【實施方式] 下文為介紹本發明之最佳實施例。各實施例用以說明本發明 之原理，但非用以限制本發明。本發明之範圍當以後附之權利要 求項為準。 第3圖為依據本發明—實施例之時間放大電路示意圖。本發 明之時間放大電路300包括-輸入相位偵測器⑽咖侧 以及一時間放大單元320,其中該時間放大單元32〇更包括一第一 環形振魅（gated ring QSdllatQ1，)322、—第二環形振盈器似及一 輪出相位偵測器326。 本發明之時間放大電路目的在於放大—第—時鐘气號 CIO與一第二時鐘訊號CK2間之相位差。第4圖為本發明之時： 放大電路中各個訊號之時序圖。㈣便了解本發明，下文二 參照各S件之圖示以及第4圖說明本發明中時間放大電路3⑽之 各元件的電路動作。 如第3圖及第4圖所示’本發明之輸入相位偵測器η”用 =接收第一時鐘訊號ck】及該第二時鐘訊號CK2，並依據該:— 時鐘訊號CK]與該第二時鐘訊號CK2間之相 ^弟 笛—士 差Ti〗1 ’分別將該 第—％鐘訊號CK1及該第二時鐘訊號CK2轉換 、战具有不同脈寬之 201220696 -第-脈衝訊號UP0及—第二脈衝訊號DN〇。如第4圖所示，第 -脈衝訊號UP0具有較第二脈衝訊號腦大的脈寬。第5圖為本 發明-實施例之輸入相位伯測器31〇電路結構圖。在此實施例中， 本發明之輸入相位偵測器310包括一第一正反器312以及—第二 正反益〕14 ’兩者皆為㈣正反器，以D接腳_接至—高態的電 源，並以Q接腳作為輸出。第—正反器3]2係用以接收該第一時 鐘訊號CK1之致能而輸出該第-脈衝訊號upo;第二正反器314 係用以接收該第二時鐘訊號CK2 t致能而輸出該第二脈衝訊號 DN0更月確地& ’當該第—時鐘訊號CKi轉態為高態時，第— 正反态。12將被正緣觸發而使其Q接腳由低態轉變為高態·，而該 第二時鐘訊號C K2會在第—時鐘訊號c K i轉態為高態的l時間 後始轉態為高態’此時第三正反器314亦被正_發而使其ρ接 腳由低態轉變為高態。透過—邏輯閘（及閘）之作用，本發明之輸入 相位债測ϋ 310會在該第—脈衝訊號刪與該第二脈衝訊號細 均轉變至同-位準（此實施例中為高態）時重設該第—及第二正反 器312及314,因而使得第一及第二脈衝訊號up〇及卿同時轉 變回低態’如第5圖所示。在—較佳實施例中，本發明之輸 位偵測器310可另外包括一變容器316，其耗接至該第一及第二正 反器312及314，在_實施例中可為心元之_〇§變容器，可 接受-校正訊號Sc之控制而改變節點〗.丨上之負載，控制該變容 器316之方式將於後文詳述。 如第3圖及第4圖所示，該第一環形振盪器322及第二環形 ^器324分軸接至職人相位彳_31()，其_ —環形振 h 322可依據該第—脈衝訊號刪之脈寬延遲該第_脈衝訊號 而該第二環形振盪器324可依據該第二脈衝訊號刪之脈 201220696 寬延遲該第二脈衝訊號围。更明確地g，由於此實施中第—脈 衝訊號upo較該第二脈衝訊號DN〇有更大之脈寬，因而使環形振 盧器322輸出之訊號Vup較環形振盪器324輸出之訊號vj可更 快地上升至高位準(如第4圖所示，訊號Vup及Vdn分別耗費時間 乃及丁2上升至高位準）。然而，在訊號ν〇Ν被觸發後不久’環形 振盪器322及324會因為輸出相位偵、測器326所回授的重設訊號 如1而重設’使得訊號Vup及Vdn隨即下降而回到低位準。第1 圖為本發明-實施例之時間放大單元32〇 +—閘式環形振盛器 322或/24之電路結構圖。其中，該第—及第二閘式__器 322或3。24皆具有奇數個（此實施例中為三個）彼此串聯且首尾相連 的反相器311、3]3及315 ’以及墟至反相器如、阳及化 與兩電源的兩個電晶體317及319。舉例而言，該第一閘式環形振 盡器322之兩電晶體3 19與317分別可以其閘極接收該第—脈衝 Λ號UP0與UP0之反相訊號。如第6圖所示，上述的開式環形振 盛器322或324皆受—重設訊號如之控制而開啟或重設。關於 重設訊號ml之產生方式將於下文詳述。 、 ;如第3圖及第4圖所示，本發明之輪出相位偵測器概輕接 至該第一及第二間式環形振盪器322及324,可用以輸出_第三脈 衝5扎號UP1及-第四脈衝訊號削，並依據該延遲後的第一脈衝 訊號UP0及第二脈衝訊號麵之位準，輸出—重設訊號加以重 設該第―及第二閘式環形«器以及輸出相位偵測器。第7圖為 本發明—實施例之時間放大單元似中輸出相位制器似之電 路結構圖。本發明之輸出相位偵測器326包括一第三正反哭⑹ 及一第四正反器364,兩者皆μ型正反器，以__接至 南態的電源’並以Q接腳作為輸出。其中，該第三正反器泊可 201220696 文該延遲後的第一脈衝訊號Vup之致能:而輸出該第三脈衝訊號 UP1，而忒第四正反器364可受該延遲後的第二脈衝訊號V加之致 能而輸出該第四脈衝訊號DN1。更明確地說，當該延遲後的第一 脈衝訊號vUP轉態為高態時，第三正反器362將被正緣觸發而使 其Q接腳將由低態轉變為高態；而當該延遲後的第三脈衝訊號V⑽ 轉態為南態時’第二正反器364亦被正緣觸發而使其Q接聊由低 轉變為⑥態。透過_邏輯閘（及閘）之作用，本發明之輸出相位債 測器326會在該第三脈衝訊號up〗與該第四脈衝訊號削均轉變 至同一 /立準（此實施例中為高態）時重設該第三及第四正反器3 6 2 進而使得該第二脈衝訊號UP丨與該第四脈衝訊號DN1同 時轉變回低態，如第4圖所示。此時，由於本發明之時間放大電 路谓、作用’第—時鐘訊號CK1與第二時鐘訊號CM間之相位 、,,n被放大成該第二脈衝訊號UP1與該第四脈衝訊號DN1間 的!位差T°r達到時間放大之效果。值得注意的是，為了使前述 衣/层_1器。22及324可以適時停止振盈，該輸出相位谓測器 326可在該第三脈衝訊號υρι與該第四脈衝訊號腦均轉變至同 一位準味實施例中為高態）時輸出該重設訊號如。由於邏輯間 在即點rl上）為—短脈寬訊號’可能沒有足夠的時間The phase difference between the second clock signals includes: an input phase detector (10) said detect(1)·) for receiving the first clock signal and the second clock signal, and according to the first clock signal and the second clock a phase difference between the signals, respectively converting the first clock signal and the second clock signal into a first pulse signal and a second pulse signal having different pulse widths; and a time amplifying unit, further comprising: - a gated ring oscillator (gated ring osciilator) coupled to the input phase detector for delaying the first pulse signal according to a pulse width of the first pulse signal; and a second gate ring opening the j oscillator The second phase pulse signal is coupled to the input pulse phase detector for delaying the pulse signal according to the pulse width of the second pulse signal; and the output phase fairy device is connected to the first and second gate ring oscillators. For outputting a third pulse signal and a fourth pulse signal, and resetting the first and second gates according to the delayed first-pulse signal and the second pulse signal level output-reset signal Ring vibrator, and Output phase detector. The invention further provides a phase-locked loop, comprising: a time amplifying circuit, comprising: fortunately, the phase detector is configured to receive the first clock signal and the second clock signal, and according to the first clock signal and the first The phase difference between the two clock signals is respectively (4) the first 5 holes 5 and the second clock signal are converted into a first face signal and a second pulse signal having different pulse widths; and at least - time amplification unit ^, The method further includes: a first-gate ring oscillator connected to the input phase detection 1 to delay the first pulse signal according to the pulse width of the brother-pulse signal; the second gate type ring-shaped vibrator The input phase (four) detector is configured to delay according to the pulse of the second pulse signal (the second pulse signal; and the output phase detector, _ connected to the first and second gate ring oscillators, The second-pulse signal and the fourth-pulse signal are used to output a reset signal to reset the first and second gates according to the level of the delayed first-pulse signal and the second pulse signal. Ring (four), and output phase 201220696 bit detection, charging , according to the time release: the output of the large unit is adjusted by a charge pump motor, a low-pass filter for being charged and discharged by the charge pump current to generate a battery control, a voltage controlled oscillator, Outputting a final chirp and frequency detector according to the control voltage, and dividing the frequency of the final clock signal by a value to generate a frequency-divided clock signal for the input phase detector to compare the first clock signal with the first [Embodiment] The following is a description of the preferred embodiments of the present invention. The embodiments are intended to illustrate the principles of the invention, but are not intended to limit the scope of the invention. The third embodiment is a schematic diagram of a time amplifying circuit according to the present invention. The time amplifying circuit 300 of the present invention includes an input phase detector (10) and a time amplifying unit 320, wherein the time amplifying unit 32 The device further includes a first ring vibrating (Gated ring QSdllat Q1,) 322, a second ring vibrator and a round out phase detector 326. The time amplifying circuit of the present invention aims to enlarge - The phase difference between the first clock frequency CIO and a second clock signal CK2. Figure 4 is the timing diagram of each signal in the amplifying circuit at the time of the invention. (4) The present invention will be understood, and the second drawing will be referred to the following. 4 and 4 illustrate the circuit operation of each component of the time amplifying circuit 3 (10) of the present invention. As shown in FIGS. 3 and 4, the input phase detector η of the present invention receives the first clock signal ck. And the second clock signal CK2, and according to the: - the clock signal CK] and the second clock signal CK2, the first and second clock signals CK1 and the second The clock signal CK2 is converted, and the 201220696-the first pulse signal UP0 and the second pulse signal DN〇 have different pulse widths. As shown in FIG. 4, the first pulse signal UP0 has a larger pulse width than the second pulse signal. . Fig. 5 is a circuit diagram of an input phase detector 31 为本 according to the present invention. In this embodiment, the input phase detector 310 of the present invention includes a first flip-flop 312 and a second positive-reflex 14'. Both are (four) flip-flops, and the D-pin is connected to - High power supply with Q pin as output. The first flip-flop 3] 2 is configured to receive the first clock signal CK1 to output the first pulse signal upo; the second flip-flop 314 is configured to receive the second clock signal CK2 t enable The second pulse signal DN0 is outputted to be more positively & 'when the first clock signal CKi transitions to a high state, the first positive and negative states. 12 will be triggered by the positive edge to change its Q pin from a low state to a high state, and the second clock signal C K2 will start to transition after the first time of the first clock signal c K i transitions to a high state. In the high state, the third flip-flop 314 is also positively turned on and the ρ pin is changed from a low state to a high state. Through the action of the logic gate (and gate), the input phase debt test 310 of the present invention converts the first pulse signal and the second pulse signal to the same level (in this embodiment, the high state) The first and second flip-flops 312 and 314 are reset, thereby causing the first and second pulse signals up and down to simultaneously transition back to a low state as shown in FIG. In a preferred embodiment, the position detector 310 of the present invention may further include a varactor 316 that is consuming to the first and second flip-flops 312 and 314, which may be a heart in the embodiment. The method of controlling the varactor 316 will be described in detail later in the _ § § variable container, which can accept the control of the correction signal Sc and change the node. As shown in FIG. 3 and FIG. 4, the first ring oscillator 322 and the second ring oscillator 324 are connected to the employee phase 彳_31(), and the ring oscillator h 322 can be based on the first The pulse signal is pulsed to delay the _th pulse signal, and the second ring oscillator 324 can delay the second pulse signal according to the second pulse signal 201220696. More specifically, since the first pulse signal upo has a larger pulse width than the second pulse signal DN, the signal Vup outputted by the ring oscillator 322 is smaller than the signal vj output by the ring oscillator 324. Faster to higher level (as shown in Figure 4, the signals Vup and Vdn take time and rise to the high level respectively). However, shortly after the signal ν〇Ν is triggered, the ring oscillators 322 and 324 will be reset because the reset signal sent back by the output phase detector 326 is reset, so that the signals Vup and Vdn fall and then return. Low level. Fig. 1 is a circuit configuration diagram of a time amplifying unit 32 〇 + - gate type ring oscillating device 322 or /24 of the present invention. Wherein, the first and second gates __ 322 or 3.24 each have an odd number (three in this embodiment) of inverters 311, 3] 3 and 315 ' connected to each other in series and end to end. To the inverter, for example, the anode and the two transistors 317 and 319 of the two power sources. For example, the two transistors 3 19 and 317 of the first gate type ring resonator 322 can receive the inverted signals of the first pulse UP UP UP0 and UP0, respectively, by their gates. As shown in Fig. 6, the above-mentioned open-type annular vibrator 322 or 324 is turned on or reset by the control of the reset signal. The manner in which the reset signal ml is generated will be detailed below. As shown in FIG. 3 and FIG. 4, the wheel phase detector of the present invention is lightly connected to the first and second inter-ring oscillators 322 and 324, and can be used to output a third pulse 5 No. UP1 and - fourth pulse signal cutting, and according to the delayed first pulse signal UP0 and the second pulse signal surface level, the output-reset signal is used to reset the first and second gate type ring device And an output phase detector. Fig. 7 is a circuit diagram showing the circuit of the phase amplifying unit in the time-amplification unit of the present invention. The output phase detector 326 of the present invention includes a third forward-reverse crying (6) and a fourth flip-flop 364, both of which are μ-type flip-flops, and are connected to the south state power supply __ with a Q pin. As an output. The third flip-flop can be enabled by the delayed first pulse signal Vup: the third pulse signal UP1 is output, and the fourth flip-flop 364 can be subjected to the second delay. The pulse signal V is added to enable the fourth pulse signal DN1. More specifically, when the delayed first pulse signal vUP transitions to a high state, the third flip-flop 362 will be triggered by a positive edge such that its Q pin will transition from a low state to a high state; When the delayed third pulse signal V(10) is in the south state, the second flip-flop 364 is also triggered by the positive edge to change its Q chat from low to six states. Through the action of the _ logic gate (and gate), the output phase debt detector 326 of the present invention converts the third pulse signal up and the fourth pulse signal to the same/alignment (high in this embodiment). And resetting the third and fourth flip-flops 3 6 2 to further convert the second pulse signal UP丨 and the fourth pulse signal DN1 back to a low state, as shown in FIG. 4 . At this time, since the time amplifying circuit of the present invention acts to phase the phase between the first clock signal CK1 and the second clock signal CM, n is amplified to be between the second pulse signal UP1 and the fourth pulse signal DN1. The position difference T°r reaches the effect of time amplification. It is worth noting that in order to make the aforementioned clothing/layer_1 device. 22 and 324 can stop the oscillation at a timely time, and the output phase predator 326 can output the reset when the third pulse signal υρι and the fourth pulse signal are both converted to the same level in the embodiment. Signals such as. Since the logic is on the point rl, there may not be enough time for the short pulse width signal.
重設該等環形振盪51 π 9 B " 及324，因此在一較佳實施例中，本發明 之輪出相位偵測益326可另外包括—脈寬延長電路遍。舉例而 言，該脈寬延長電路366可包括—D型正反器⑹、—延遲線365, 其中該D型正反器3 6 3受到邏輯閉之輸出訊號之致能，而延遲線 365則可在適當的時間後將該D型正反器363重設，藉以延長重 ^訊號ml之脈寬。如第4圖所示，當重設訊號如轉變為高態 日"’幸則人相位偵測器310所輸出之訊號VUP及V⑽會被重設而轉 201220696 丨 ^低態’進而使得第一及第二環形振盈器322及324所輸出之 及第四脈衝訊號UP]及DN1亦轉變至低態。 八至此’本發明之時間放大電路的基本㈣及其運作原理皆已 =元畢，使用上述時間放大電路即可將兩時鐘訊號間之相位差 二放大°第8圖為本發明之時間放大電路3〇〇之特性曲線圖。 、本發明之4間放大電路3〇〇没有先前技術中所述兩個队閃鎖 電路之輸入時間偏移T〇ff，所以本發明之特性曲線上不會產生奇異 2亚且具有較寬廣的線性區間，因而增加了本發明之時間放大 電路可應用的範圍。 第9圖為本發明—較佳實施例之時間放大電路示意圖。在一 =施例中，本發明之時間放大電路_可另包括一時間增益 ^ =路_及-時間增益校正電路跡藉以增加本發明時間放 應用上的選擇性以及時間增益的準確性。除了相同於前文 所述的輸入相位偵測器310及時間放大單元3 外增加複數個時門放厂…l 卜，本發明尚另 數個寺間放大…提供多種相位差的時鐘訊號，如圖 ^斤不之時間放大單元32。，。同前述實施例，時間放大單元32〇, :文第三及第四脈衝訊號UP]及叫輸出較前述訊號有 、目立差的第五及第六脈衝訊號及DN2。 本發明之時間增益選擇電路91〇，舉例而言，可為一多工器， 第二、第三及第四、第五及第六脈衝訊號胸 ::二―及咖、贈及讀後，依據—選擇訊號町八 A °玄弟及第-脈衝訊號UP0及DN0、輸出哕第笫 脈衝訊號UP】及DN]，或是於4心二及弟四 一別出k第五及弟六脈衝訊號UP2及 間放1 ^以㈣^大單元為例，但本—用的時 、早兀之i:里不必以此為限。此外，須注意的是，由於時間 10 201220696 增益選擇電路㈣请出訊號υρ_及為短脈寬訊號， 直接輸㈣電路之外將耗費過大的功率，因此，在-實施例中， 本發明之時間放大電路9〇〇可另外將兩個正反器州及脱分別 麵接至該時間增益選擇電路_之輸出，使其最後輸出訊號u雨 及刪ff的工作周期接近5〇%，降低輸出緩衝器的頻寬需求。 本叙·月之時間增心正電路92Q可將—組脈衝訊號間之相位 差與一預定相位差作比較以作為校正時間增制依據。本實施例 中’《增盈校正電路920將第三及第四脈衝訊號υρι與間 之相位差與-預定相位差(參照第Μ圖比較，並輸出一校正 訊號Sc至輸入相則貞測器31()之變容器316⑥控制該變容器gw 之負載’進而控制該第—脈衝訊號up G及該第二脈衝訊號誦之 脈寬，藉此達成校正該時間放大電路_時間增益之效果。第ι〇 ，為本發明—貫施例中之時間增益校正電路㈣之電路結構圖。 j 11A、B圖則為該時間增益校正電路92G中之訊號時序圖，分別 。兄明時間心太大或太小之情形。在此實施例中，本發明之時間 增益校正電路920可包括一延遲線922、-第五正反器924以及一 連續逼近暫存器（successive appr〇ximati〇n吻咖，SA_6。當 几號SAR—STOP為低態而致能該時間增益校正電路92〇時，該延 遲線922可用以接收該第三脈衝訊號up卜並將該第三脈衝訊號 upl延€麵定相位差Td而產生延遲後的第三脈衝訊號狐。該 預定相位差又可由一訊號So進行調整，由於訊號產生及控制的實 方式m夕，故在此不再贅述。之後，該第五正反器924受訊號 _ K (此處同該第四脈衝D N丄）之致能而將該延遲後的第三脈衝訊 ^ 之位準幸刖出以作為一比較訊號compl。從第1 ] A圖可知， 當時間增益太大時，訊號_會使第五正反器咖輸出的比較訊 201220696 號compl為高態；而當時間增益太小時，丨訊號dni會使第五正反 器924輸出的比較訊號compl為低態。該sar 926可為—N位元 SAR，其可接收該比較訊號c〇mpl，並以一預定速度ck〜fsm產 生對應該比較訊號compl之該校正訊號Sc，其中該校正訊號& 具有多個大小不等之數值（在此實施例中為f個數值），可用以調 整同樣具有N位元之變容器。當校正訊號Sc為全“〇”時，將使輸 入相位偵測器310之變容器316關閉’使節點rl的負載達到最小 值，進而使第一脈衝訊號UP0及第二脈衝訊號DN0同時為高態的 區間最小’進而將時間增益最大化；當校正訊號Sc為全“丨”時， 將使輸入相位偵測器310之變容器3〗6全部開啟，使節點Η的負 載達到最大值，進而使第一脈衝訊號U Ρ 〇及第二脈衝訊號D ν 〇同 時為高態的區間最大，&而將時間增益最小化。此外，在一實施 例中，上述預定速度可為訊號CK一FSM之時鐘率㈨⑻匕u㈣，而 訊號CK—FSM可由用以致能第五正反器924的第四脈衝DN丨接上 一除頻器928而產生，然'而在其他實施例中，本發明不必以此為 限0The ring oscillations 51 π 9 B " and 324 are reset, so in a preferred embodiment, the wheeled phase detection benefit 326 of the present invention may additionally include a pulse width extension circuit. For example, the pulse width extension circuit 366 can include a -D type flip-flop (6), a delay line 365, wherein the D-type flip-flop 363 is enabled by a logic-closed output signal, and the delay line 365 is The D-type flip-flop 363 can be reset after an appropriate time to extend the pulse width of the weight signal ml. As shown in Fig. 4, when the reset signal is changed to a high state, the signal VUP and V(10) output by the human phase detector 310 will be reset and turned to 201220696 丨^ low state, thereby making the first And the fourth pulse signals UP] and DN1 output by the second ring oscillators 322 and 324 also transition to a low state.八至此' The basic (4) of the time amplifying circuit of the present invention and its operating principle are all = Yuan, the phase difference circuit between the two clock signals can be amplified by using the above time amplifying circuit. FIG. 8 is a time amplifying circuit of the present invention. 3〇〇 characteristic curve. The four amplification circuits 3 of the present invention do not have the input time offset T〇ff of the two team flash lock circuits described in the prior art, so that the characteristic curve of the present invention does not produce a singular 2 sub- and has a wide range. The linear interval thus increases the range in which the time amplifying circuit of the present invention can be applied. Figure 9 is a schematic diagram of a time amplifying circuit of the preferred embodiment of the present invention. In an embodiment, the time amplifying circuit of the present invention may further include a time gain ^ = path_ and - time gain correction circuit trace to increase the selectivity of the time shift application of the present invention and the accuracy of the time gain. In addition to the input phase detector 310 and the time amplifying unit 3 as described above, a plurality of time gates are added, and the present invention is further amplified by a plurality of temples to provide a plurality of phase difference clock signals, as shown in the figure. The time is not enlarged by the unit 32. ,. In the same embodiment as the foregoing, the time amplifying unit 32:, the third and fourth pulse signals UP] and the output of the fifth and sixth pulse signals and DN2 having the difference between the signals and the signals. The time gain selection circuit 91 of the present invention may be, for example, a multiplexer, the second, third, fourth, fifth, and sixth pulse signals: 2: and after the coffee, gift, and reading, According to the selection - signal Aocho A A Ao Dio and the first - pulse signal UP0 and DN0, output 哕 笫 pulse signal UP] and DN], or in the 4 heart two and the younger brother one out of k fifth and six pulse The signal UP2 and the inter-discharge 1 ^ take the (four) ^ large unit as an example, but the use of the time, the early i: does not have to be limited to this. In addition, it should be noted that since time 10 201220696 gain selection circuit (4) please send signal υρ_ and short pulse width signal, direct input (four) circuit will consume excessive power, therefore, in the embodiment, the present invention The time amplifying circuit 9 〇〇 can additionally connect the two positive and negative states and the decoupling face to the output of the time gain selecting circuit _, so that the working period of the final output signal u rain and ff is close to 5〇%, and the output is lowered. The bandwidth requirement of the buffer. The time incrementing positive circuit 92Q of the present time can compare the phase difference between the group of pulse signals with a predetermined phase difference as a basis for the correction time addition. In the present embodiment, 'the gain correction circuit 920 compares the phase difference between the third and fourth pulse signals υρι and the predetermined phase difference (refer to the first figure, and outputs a correction signal Sc to the input phase detector 31). The variable container 3166 of () controls the load of the variable container gw to further control the pulse width of the first pulse signal up G and the second pulse signal, thereby achieving the effect of correcting the time amplification circuit _ time gain. 〇, is the circuit structure diagram of the time gain correction circuit (4) in the present invention. j 11A, B diagram is the signal timing diagram in the time gain correction circuit 92G, respectively. The brother time is too big or too small In this embodiment, the time gain correction circuit 920 of the present invention may include a delay line 922, a fifth flip-flop 924, and a continuous approximation register (successive appr〇ximati〇n, SA_6). When the number of SAR_STOP is low and the time gain correction circuit 92 is enabled, the delay line 922 can be used to receive the third pulse signal upb and extend the third pulse signal upl to the phase difference Td. And after the delay Pulse signal fox. The predetermined phase difference can be adjusted by a signal So. Since the signal generation and control are performed in real time, it will not be described here. After that, the fifth flip-flop 924 receives the signal _ K (here). With the enablement of the fourth pulse DN丄), the level of the delayed third pulse signal is fortunately extracted as a comparison signal compl. As can be seen from the first graph, when the time gain is too large, The signal _ will make the fifth positive and negative device output comparison news 201220696 compl high; and when the time gain is too small, the signal dni will make the fifth signal of the fifth flip-flop 924 output compl low. 926 can be an N-bit SAR, which can receive the comparison signal c〇mpl and generate the correction signal Sc corresponding to the comparison signal comp1 at a predetermined speed ck~fsm, wherein the correction signal & The value (such as f values in this embodiment) can be used to adjust a varactor that also has N bits. When the correction signal Sc is all "〇", the varactor 316 of the input phase detector 310 will be enabled. Turn off 'to minimize the load on node rl, and then The interval between the first pulse signal UP0 and the second pulse signal DN0 being high at the same time is minimized to maximize the time gain; when the correction signal Sc is all "丨", the varactor 3 of the input phase detector 310 is caused 〖6 is all turned on, so that the load of the node 达到 reaches the maximum value, so that the first pulse signal U Ρ 〇 and the second pulse signal D ν 〇 are simultaneously the highest interval of the high state, and the time gain is minimized. In one embodiment, the predetermined speed may be a clock rate (9) (8) 匕 u (4) of the signal CK-FSM, and the signal CK-FSM may be coupled to a frequency divider 928 by a fourth pulse DN for enabling the fifth flip-flop 924. And produced, but in other embodiments, the invention does not have to be limited to zero.
本發明之時間放大電路即可應用於鎖相迴路（phase 1〇汰以 loop，PLL)及延遲鎖定迴路(delay 1〇cked 1〇〇p，DLL)之中。由於鎖 相迴路與延遲鎖定迴路具有相近之元件及架構，因此下文僅以鎖 相迴路為例作說明。第12圖為典型的鎖相迴路之方塊圖。典型的 鎖相迴路1200包括一相位頻率偵測器1202、一充電泵12〇4、一 -慮、波益1206、一壓控振盪姦及一除頻器]21〇，而本發 明之時間放大電路或·即可肋取代典型鎖相迴路讓中 立。頻率偵測裔1 202。第13圖為本發明—實施例之鎖相迴路示 思圖。本發明之鎖相迴路13〇〇除了前述之時間放大電路_外， 12 201220696 尚包括了-充電泵1304、一低通遽波器】3〇6、一麼控振盈器㈣ 及-除頻器⑶0,其中充電泵可依據時間放大電路_中時 間增益選擇電路910所選擇之輪出upmux及DNmux調整一充電 泵電流，並以該充電泵電流對該低通濾波器】306進行充電或放 電使仔該低通遽波器1306產生一控制電屋Vc，而該麼控振盈 器·即可依擄該控制M Ve輸出最終時鐘訊號CK_。此外， _器咖可將最終時鐘訊號之頻率除以一數值N而產生一除頻 時鐘訊號CKdlv，以供時間放大電路·中之輸人相位偵測器训 比較輸入時鐘訊號CKm之用。習知技術通常以增加充電泵電流之 方士改善充電泵之相位雜訊，然而’為了使充電泵的驅動電壓保 持常數.，充電泵電流的增加必定使其通道寬度相應增加，最後導 致充電粟的輸出雜訊頻譜密度亦隨之增加。藉由在鎖相迴路中應 =本發明之時間放大器，充電泵電流可因時間放大器的增益而提 间但尤電泵的輸出雜訊頻譜密度卻不會因此增加。由此可知， 本發明相對習知技術㈣更能有效地改善充電泵相位雜訊。 —本發明雖以較佳實施例揭露如上’然其並非用以限定本發明 t圍，钟熟習此項技藝者，在不脫離本發明之精神和範圍内， :可做注相更動與潤飾，因此本發明之保護範圍當視後附之中 請專利範圍所界定者為準。 201220696 【圖式簡單說明】 」 第1Α圖為習知時間放大器之示意圖。 第]B圖則為習知時間放大器之詳細電路結構圖。 第2A圖為兩個SR問鎖電路之延遲特性曲線。 第2B圖為時間放大器丁A整體之特性曲線。 第3圖駿據本發明_實施例之時間放大電路示意圖。 Γ圖為本發明之時間放大電路300中各個訊號之時序圖。 Γ圖為本發明—實施例之輪人相則貞測器3K)電路結構圖。 第6圖為本發明一實施例< _ μ ^ ， «器切或324之電路結構圖之時間放大早疋划中―閘式環形 測哭第96 =本發明—貫施例之時間放大單元320中輸出相位價 測tm ：>26之電路結構圖。 、 :8圖為本發明之時間放大電路300之特性曲線圖。 ^ 9圖為本發明—較佳實施例之時間放大電路示意圖。 結構圖第。10圖為本發明—實施例中之時間增益校正電路920之電路 第11Α、Β圖則為該時間增益校正電路 分別說明時間增益太大或太小之情形。中之㈣备 第]2圖為典型的鎖相迴路之方塊圖。 第η圖為本發明一實施例之鎖相迴路示意圖。 【主要元件.符號說明】 ΤΑ〜時間放大器； C1C10UI ' CK20UI〜輸出時間訊號 300〜時間放大電路； CKlin、CK2in〜輸入時間訊號; T〇fn時間偏移； 3 ]0〜輸入相位偵測器； Μ 201220696 3 20〜時間放大早元， 322〜第一環形振盪器； 324〜第二環形振盪器； 326〜輸出相位偵測器； CK1〜第一時鐘訊號； CK2〜第二時鐘訊號； UP0〜第一脈衝訊號； DN0〜第二脈衝訊號； 312〜第一正反器； 314〜第二正反器； 316〜變容器； Sc〜校正訊號； rstl〜重設訊號， 311、313、315〜反相器； 317、319〜電晶體； 362〜第三正反器； 364〜第四正反器； UP 1~第三脈衝訊號； DN1〜第四脈衝訊號； 366〜脈寬延長電路； 363〜D型正反器； 365〜延遲線； 910〜時間增益選擇電路； 920〜時間增益校正電路； 320’〜時間放大單元； DN2〜第六脈衝訊號； UP2〜第五脈衝訊號， UPmux、DNmux〜時間增益選擇電路910之輸出訊號 93卜932〜正反器； UPdff、DNdff〜最後輸出訊號 Td〜預定相位差； 922〜延遲線； 924〜第五正反器； 926〜連續逼近暫存器 comp 1〜比較訊號； UPK〜延遲後的第三脈衝訊號 DNK〜延遲後的第四脈衝訊號； 1200〜鎖相迴路； 1202〜相位頻率偵測器； 1204〜充電泵； 1206-低通濾波器； 1208〜壓控振盪器； 1210〜除頻器； 13 00〜鎖相迴路； 1304〜充電果； 1306〜低通濾波器； 1310〜除頻器。 1308〜壓控振盪器； 15The time amplifying circuit of the present invention can be applied to a phase locked loop (phase 1 looped in loop, PLL) and a delay locked loop (delay 1 〇cked 1 〇〇p, DLL). Since the phase-locked loop and the delay-locked loop have similar components and architecture, the following is only an example of a phase-locked loop. Figure 12 is a block diagram of a typical phase-locked loop. A typical phase-locked loop 1200 includes a phase frequency detector 1202, a charge pump 12〇4, a-when, a Bo Yi 1206, a voltage-controlled oscillation, and a frequency divider] 21〇, while the time of the present invention is enlarged. The circuit or rib can replace the typical phase-locked loop to make it neutral. Frequency detection 1 202. Figure 13 is a diagram showing the phase locked loop of the present invention. In addition to the aforementioned time amplifying circuit _, 12 201220696 includes a charging pump 1304, a low-pass chopper, a 3〇6, a controlled vibrator (4), and a frequency dividing circuit. (3) 0, wherein the charge pump can adjust a charge pump current according to the round upmux and DNmux selected by the time gain circuit selection circuit 910, and charge or discharge the low pass filter 306 with the charge pump current. The low pass chopper 1306 is caused to generate a control electric house Vc, and the control vibrator can output the final clock signal CK_ according to the control M Ve. In addition, the processor can divide the frequency of the final clock signal by a value N to generate a frequency-divided clock signal CKdlv for comparing the input clock signal CKm in the time-amplifier circuit. Conventional techniques generally improve the phase noise of the charge pump by increasing the charge pump current. However, in order to keep the drive voltage of the charge pump constant, the increase of the charge pump current must increase the channel width accordingly, and finally lead to the charging of the millet. The spectral density of the output noise also increases. By using the time amplifier of the present invention in the phase-locked loop, the charge pump current can be increased by the gain of the time amplifier, but the output noise spectrum density of the pump is not increased. It can be seen that the present invention is more effective in improving the phase noise of the charge pump than the prior art (4). The present invention has been disclosed in the above preferred embodiments, and it is not intended to limit the scope of the present invention. Those skilled in the art can, without departing from the spirit and scope of the invention, Therefore, the scope of protection of the present invention is defined by the scope of the patent application. 201220696 [Simple description of the diagram] The first diagram is a schematic diagram of a conventional time amplifier. The Fig. B is a detailed circuit diagram of a conventional time amplifier. Figure 2A shows the delay characteristics of the two SR challenge circuits. Figure 2B is a graph showing the overall characteristics of the time amplifier D. Figure 3 is a schematic diagram of a time amplifying circuit according to the present invention. The diagram is a timing diagram of each signal in the time amplifying circuit 300 of the present invention. The diagram is a circuit diagram of the wheel-to-human phase detector (3K) of the present invention. Figure 6 is an embodiment of the present invention < _ μ ^ , the circuit diagram of the "cutting or 324" time zooming in the early stage - the gate type ring measuring crying 96 = the present invention - the time amplifying unit of the embodiment In 320, the output phase price is measured by tm: > 26 circuit structure diagram. , Fig. 8 is a characteristic diagram of the time amplification circuit 300 of the present invention. Figure 9 is a schematic diagram of a time amplifying circuit of the preferred embodiment of the present invention. Structure chart. 10 is a circuit of the time gain correction circuit 920 in the present invention - the first embodiment of the present invention shows that the time gain correction circuit respectively indicates that the time gain is too large or too small. (4) Preparations Figure 2 is a block diagram of a typical phase-locked loop. FIG. 7 is a schematic diagram of a phase locked loop according to an embodiment of the present invention. [Main components. Symbol description] ΤΑ~time amplifier; C1C10UI 'CK20UI~ output time signal 300~ time amplification circuit; CKlin, CK2in~ input time signal; T〇fn time offset; 3]0~ input phase detector; Μ 201220696 3 20 ~ time to zoom in early, 322 ~ first ring oscillator; 324 ~ second ring oscillator; 326 ~ output phase detector; CK1 ~ first clock signal; CK2 ~ second clock signal; ~ first pulse signal; DN0 ~ second pulse signal; 312 ~ first flip-flop; 314 ~ second flip-flop; 316~ varactor; Sc~ correction signal; rstl~ reset signal, 311, 313, 315 ~ Inverter; 317, 319 ~ transistor; 362 ~ third forward and reverse; 364 ~ fourth forward and reverse; UP 1 ~ third pulse signal; DN1 ~ fourth pulse signal; 366 ~ pulse width extension circuit; 363~D type flip-flop; 365~delay line; 910~time gain selection circuit; 920~time gain correction circuit; 320'~time amplification unit; DN2~6th pulse signal; UP2~5th pulse signal, UPmux, DNmux~time gain The output signal 93 of the selection circuit 910 is 932~pronator; UPdff, DNdff~ final output signal Td~predetermined phase difference; 922~delay line; 924~5th flip-flop; 926~continuous approximation register comp 1~ Comparison signal; UPK~ delayed third pulse signal DNK~ delayed fourth pulse signal; 1200~ phase-locked loop; 1202~phase frequency detector; 1204~ charge pump; 1206-low-pass filter; 1208~ Voltage controlled oscillator; 1210~divider; 13 00~ phase-locked loop; 1304~charged fruit; 1306~low-pass filter; 1310~divider. 1308~ voltage controlled oscillator; 15