TW201218646A - Analog to digital converter - Google Patents

Abstract

An analog to digital converter comprising: an input channel for receiving said analog signal; a first sampling-integrating unit for receiving said analog signal from said input channel and for sampling a analog signal and integrating a superposition of a first feedback signal and a first sampled signal of said analog signal, and for generating a first output signal; a second sampling-integrating unit for receiving said first output signal and for sampling said first output signal and integrating a superposition of a second feedback signal and a sampled signal of said first output signal, and for generating a second output signal, wherein each of said first and second sampling-integrating units comprises a first energy storage unit and a first switch array for controlling said first energy storage unit; and a feedback circuit coupled to said first and second sampling-integrating units and for generating said digital signal according to said second output signal and for providing said first and second feedback signals indicative of a digital signal to said first and second sampling-integrating units respectively.

Description

201218646 VI. Description of the Invention: [Technical Field of the Invention] In particular, an analogy/presentation relates to a signal processing system digital converter. [Prior Art] In the field of data acquisition, a complex-to-signal signal can be captured simultaneously or in parallel' and converted into a digital signal in a predetermined time interval. In a conventional racking, each input channel requires a sample (sa_e) touch (10) d) module. All analog signals from the input channel will be sampled at the same time, and the money will be in a simple state. In the hold phase, the analog/digital converter (ADC) can convert the odd-to-continue conversion into a digital signal until all the input channels are converted to digital signals. This architecture has many shortcomings. For example, more regrets require more _like/maintaining pull groups' and this group is more sensitive to high-noise noise and does not have low-pass tear wave capability. In another traditional architecture, each input channel uses a separate analog/digital converter. A data acquisition system with multiple input channels requires a ship/number conversion $^ average ship/number of turns (four) available In this architecture, synchronization of multiple wheel channels is achieved. However, if multiple analog/digital converters are used, the sufficiency, area and cost increase. In addition, 'different analog/digital converters can cause multiple mismatches between the 201218646 incoming channels. SUMMARY OF THE INVENTION The technical problem to be solved by the present invention is to provide an analog/digital converter that converts a ratio signal into a digital signal. . In order to solve the above technical problem, the present invention provides that the type ratio/digital converter includes: - the input channel minus the signal; the U-shaped and integral unit subtracts the domain signal from the input channel for sampling, and the -: back The signal is integrated with an overlap of an ith signal of the analog signal and generates a first output signal; a second sample _ integration unit receives the sin-first output signal and performs the first output signal Sampling, and an overlapping P-knife of the -second feedback signal and the first-round signal-sampling signal, and generating a second output signal, wherein the first sampling_integrating unit and the second Each of the sampling and integrating units includes a first energy storage unit and a first-switch array that is input to the first-energy storage unit to control, a first energy storage element; and a feedback circuit, and the first a sampling · integral early 70 and the second sampling · integral single call, according to the second output signal generates a digital touch 'and provides the first feedback signal of the number of jobs and the second call (four) First-sampling and integrating unit and the second Sampling_integration σσ is 7C early. The present invention has a higher tester and a higher _ ratio/number (10) conversion accuracy than the analog/digital conversion piracy of the prior art. 8 201218646 The following is a detailed description of the technical solutions of the present invention in conjunction with the specific embodiments to make the features and advantages of the present invention more apparent. [Embodiment] Hereinafter, a detailed description will be given of an embodiment of the present invention. While the invention will be described in conjunction with the present invention, it should be understood that the invention is not limited to the embodiments. On the contrary, the invention is intended to cover various modifications, modifications and In addition, in the detailed description of the present invention, numerous specific details are provided to provide a comprehensive understanding of the invention. It will be appreciated by those of ordinary skill in the art that the present invention may be practiced without such ambiguous details. In other examples, for the Xi: method, process, 4 and circuit are not detailed, money to highlight the channel of the invention from a plurality of inputs _ switch to a digital output signal, such as minus (_ 咖咖e) Under the 'multiple analog input circuit ^ output electrical house. More analog/digital converters can be applied to each =:: one-, _, 峨: 22: __ conversion 圃 in the & example, multi-channel analog/digital converter

S 201218646 100 may be a first order delta-sigma analog-to-digital converter (delta-sigma ADC). In an embodiment, the multi-channel analog/digital converter 100 can have multiple input channels 'eg, four input channels include channel 1, channel 2, channel 3, and channel 4 to classify signals, for example, analog voltage signals Vl , v2, V3, and V4 are converted to digital signals in the interleaved mode, respectively. Each input channel is coupled to a switch. For example, switch S1A is coupled to channel 1; switch s2A is coupled to channel 2; switch S3A is coupled to channel 3; and switch Sm is coupled to channel 4. In one embodiment, the switches S1A, Sm, and Lv can be controlled by the system clock signal sCLK. In one embodiment, an input channel is selected during a clock cycle based on the system clock signal. In one embodiment, during a clock cycle, the switches coupled to the selected input channel will be turned "on" and the other switches will be turned "off". The multi-channel analog/digital converter 100 includes a modulator 11A to convert an analog signal, such as a voltage signal V], V2, V3 or v4, into a digital signal. The modulator 110 can receive an analog signal from the selected input channel and provide a corresponding digital signal to the filter coupled to the input channel, for example, a digital filter Fi, a digital ferrite F2, a digital chopper p3 And digital crossing waves. The analog signal can be various types of signals, such as current or voltage signals. In the modulator 110, the analog signal is input to the sample-integration unit 13A. In the sample-integration unit 130, the sampling circuit can sample the received analog signal at a preset sampling frequency, for example, the sampling frequency. Equivalent to Fs * 〇sr, where Fs is the Nyquist frequency' 〇SR is the oversampling rate for the Nyquist frequency ^ 201218646 For example 'When FS is 16 Hz, 0SR is 4 〇 96, the sampling frequency is 36 Hz . The analog signal can be converted into a digital signal by the female UG after sampling. In an embodiment, the number health key may be a continuous i-bit data string consisting of a sampling frequency, for example, Fs * OSR determining ratio _ logical i and logical 〇. The in-sense-sampling circuit includes an energy storage unit, for example, a sampling capacitor 12G, connected to the selected input port to store the f-charge from the selected input channel; the sampling circuit further includes (four) 122 , a switch 124, a switch 126 (four) off a switch array of 128 to control the energy storage unit 120. Switch 122 and switch 124 are controlled by signal pH2. Switch 126 and switch 128 are controlled by signal P%. In one embodiment, the signal ρΗι and the signal PH2 疋 are non-overlapping clock signals. For example, when signal |> only 2 is high potential, the signal PH! is low potential. The switch 丨 22 and the switch 124 are turned on, and the switch 126 and the switch 128 are turned off. When the signal PH1 is high, the signal Ph2 is low and the switch 122 and the switch 124 are turned off, and the switch 126 and the switch 128 are turned on. The sampling-integration unit 13 further includes an integrating circuit coupled to the sampling circuit to receive the sampling signal and the feedback signal 111' of the round-in analog signal and to overlap the overlapping portions of the sampling signal of the feedback signal 111 and the input analog signal. integral. The integrating circuit can generate an output signal 170 based on the integration result of the overlapping portion. In the embodiment shown in Figure ,, the integrating circuit includes a set of integrating capacitors (e.g., 'integrated capacitors Qi, Ci2, 〇3, Ci4) and an error amplifier 1〇2. 201218646 Integral capacitors Cu, C, 2, Q3, C; 4 series are coupled in parallel. The integral capacitor, Q2, cB, (^ can accumulate charge from the input channel respectively. Each integral capacitor q", Q2' ci3, cl4 can be connected in series with a switch, for example, the integral capacitor & is connected with the switch s1B, the integral capacitor Ci2 is connected to the switch S2B, the integrating capacitor 4 is coupled to the switch S3B, and the integrating capacitor Ci4 is coupled to the switch S4B. In an embodiment, the modulator 110 can successively perform analog/digital steps for each input channel in the conversion cycle. In one embodiment, at the beginning of the conversion cycle, the integrating capacitor can be randomly assigned to the input channel. For example, the integrating capacitor Cu can store the charge from channel 2 'integral capacitor Q2 can store the charge from channel 3, integrating Capacitor Q3 can store the charge from channel 4, integrating capacitor C; 4 can store the charge from channel 1. etc. The flexible composition of this input channel and the integrating capacitor can reduce the difference between the different channels due to the mismatch of the integral capacitor. Mismatch. In an embodiment, the output signal 170 of the sample-integral unit 13A represents that the corresponding integrated capacitor is stored during the previous conversion cycle. The result of integrating the charge, and the overlapping portion of the feedback signal 111 and the sampling signal of the input analog signal. The error amplifier 102 can receive the input signal through the inverting input terminal, receive the first reference signal through the non-inverting input terminal, and generate an error. The signal, for example, the input signal is the overlap of the sampled signal of the input analog signal with the feedback signal 111. In one embodiment the 'non-inverting input is grounded such that the voltage level of the first reference signal is substantially equal to zero. 201218646 Modulation The processor 110 further includes a feedback circuit for generating a digital signal from the output signal 170 of the sample-integration unit 130 and generating a feedback signal 111 representative of the digital signal of the integration circuit. In the embodiment illustrated in FIG. The feedback circuit further includes a comparator 1〇4, a multiplexer 1〇8, and a digital/analog converter (DAC) 106. That is, the 'integration circuit, the comparator 1〇4, the multiplexer 108, and The digital/analog converters together form a feedback loop that includes a feedforward consisting of an integrating circuit, a comparator 104, and a multiplexer 108. A (feed forward) path and a backward path including a digital/analog converter 106. The comparator 1〇4 coupled to the sample-integral unit 130 can output the output signal 17 of the sample-integration unit το 130〇 Comparing with the second reference signal and generating a comparison output signal according to a comparison result. Comparator 1〇4 can be controlled by signal PH2, and comparator 1〇4 operates when PH2 is high potential. In the example, the non-inverting input of comparator 104 is grounded. Therefore, the second reference signal voltage level is substantially equal to zero. Comparator 1〇4 can generate a one-bit digital signal based on the comparison result, for example, logic! Alternatively, the output signal of the logic comparator, for example, the 1-bit digital signal is further supplied to the multiplexer 1〇8. In an embodiment, the multiplexer 108 may be a cylindrical displacement register controlled by the system clock signal Sc^. The multiplexer 1 (10) is capable of causing a digital signal from the comparator 104, for example, a j-bit digital signal, to reach a corresponding output channel, such as a 'root-length signal ^, a digital chopping 201218646 combined with an input channel that is selected . The output channel may include digital filters F!, F2, F3, and F4 'eg, a subtraction filter that extracts a digital signal from the comparator 104, for example, a 1-bit digital k number into a multi-bit digital round-out signal (decimation) Filter). Thus, multiple digital output signals associated with multiple input channels can be derived from digital filters, for example, 匕, F2, h, and F4, respectively. Additionally, multiplexer 108 can latch (1-bit) a 1-bit digital signal associated with each input channel from comparator 1〇4. Therefore, in the current conversion period, the 丨 bit digital signal generated by each input channel in the previous conversion period is locked in multiplex H 108 ' until a new 1-bit number is generated. When an input channel is selected according to the system clock signal ScLK during the current conversion period, the multiplexer 108 can transmit the 1-bit digital signal of the previously input channel of the previous change to the digital/analog converter 1 〇 6. In one embodiment, multiplexer 1G8 may transmit a 丨 bit digital signal, for example, a logic 0, to digital/analog converter 1 在 6 during the first-to-conversion cycle. In one embodiment, the 'digital/analog converter 1〇6' may be a one-bit digital/analog converter. The digital/analog converter 1 可以 6 can receive the 1-bit τ number health symbol ' from the multiplexer 1 并 8 and convert the 丨 bit number key to an analog signal ', for example, a voltage signal. The analog signal generated by the digital/analog converter 1〇6 can be used as the feedback signal 111 transmitted to the integral 15G. In a real target example, the digital/analog converter 1〇6 can set the feedback signal 111 to -Vref' when the 1-bit digital signal is logic ^201218646. When the 1-bit digital signal is logically 将The feedback signal 111 is set to Vref. The digital/analog converter 106 can be controlled by the signal PH! and the signal PH2. Thus, the value of the feedback signal ln can be controlled based on the 1-bit digital signal from the multiplexer 108. Further, when the channel 1 is selected according to the system clock signal Sclk of each clock cycle of the current conversion period, the modulator 110 can receive an analog signal from the channel 1, for example, analog voltage signal % and from digital/analog The feedback signal 111' of the converter 106 produces a 1-bit digital signal. In one embodiment, the feedback signal 11 from the digital/analog converter 106 is generated based on the 1-bit digital signal and the reference voltage Vref generated during the previous conversion cycle in channel 1. The comparator 104 can generate a 1-bit digital signal to the multiplexer 1A8. Therefore, the previous 1-bit digital signal associated with channel 1 in multiplexer 1〇8 is replaced by a new 1-bit digital signal in the current conversion period. The multiplexer 1〇8 can output a 1-bit digital signal generated in the current conversion period to the corresponding digital filter F1. The next input channel, e.g., 'Channel 2, can be selected at the next clock cycle of the system clock signal SCLK, and the corresponding 1-bit digital signal can be received by the corresponding filter. For example, 'channel 1, channel 2, channel 3 and channel 4 are successively selected, and the corresponding 1-bit digital signals of channel 1, channel 2, channel 3 and channel 4 are successively digitally filtered, and the digital filter F2. The digital filter F3 and the digital filter F4 are received. A digital filter, for example, a digital filter Fi, a digital filter F2, a digital ferrite F3, and a digital filter f4 can accumulate the 1-bit number 彳5 of 13 201218646 in the corresponding input channel, and generate a multi-digit number. output signal. The multi-channel analog/digital converter excitation is shown in Fig. 1, but the present invention is not limited thereto. For example, tune _(10) can also be used to verify single channel analog/digital converters. The operation of the multi-channel analog/digital converter 100 will be described by way of example with reference to the waveform diagram 200A shown in Fig. 2A. 2A shows the waveform of the system clock signal sCLK, the state of the switch Sia, the heart, the ~, S4a, &, ^, and S4B, and the multi-channel analog/digital conversion $1〇〇 operation process in one embodiment. Signal PH2 and nickname PH! 2A is for illustrative purposes and the invention is not limited to the operation illustrated in Figure 2A. In the embodiment shown in Fig. 2A, 'when the corresponding state waveform is at the high potential switch is turned on', the switch is turned off when the corresponding state waveform is at a low potential. In the embodiment shown in FIG. 2A, the clock period of the system clock signal Sclk is divided into two (four) segments, which include the secret time domain - the low potential level & phase and system clock signal ScLK is High potential level & For example, each clock cycle, for example, Tl, A, A, %, A, etc., includes the s phase and the S2 phase. In the phase Si of each clock cycle, the signal ρΗι is set to a high potential quasi-signal PH! is set; t is a low potential quasi, like, in the S2 phase of each clock cycle '彳§# PH] Set to low potential, signal pH] is set to high potential. In the embodiment towel, because the signal term and signal pH2 are non-overlapping clock signals. The signal and the signal ph2_ wide-format clock 8 14 201218646 The pulse width of the signal sCLK is small to avoid overlap. In the embodiment, at the clock cycle T1, the 'channel' will be selected first when the multi-channel analog/digital converter 100 is activated. The switch associated with the channel] S1A and switch s1B will be turned on. Switches associated with other input channels, such as channel 2, channel 3, and channel 4, will be disconnected. In one embodiment, the switch = is turned on after being delayed by half a clock period. For example, the switch Sia is turned on during the clock period TjB on the switch s1B during the S2 phase of the clock cycle T1 and the phase of the clock cycle Τ2. The switch 122 and the switch 124 are turned on at the & stage of the clock period 1\ according to the high potential of the signal pH?. At the same time, switch 126 and switch 128 will be turned off in accordance with the low potential of the signal in the clock period. Shame, the analog signal from channel 1 'e.g., analog voltage signal Vi, through switch S1A, switch 124 and opening 122' can be transmitted to sampling capacitor 12A and sampled. The charge from channel 1 corresponding to the analog voltage signal Vi can be stored in the sampling capacitor 120. In the Si phase of the clock cycle D2, the switch 122 and the switch 124 are turned off according to the low potential of the signal PH2, and the ON_126 and the ON_128 are turned on according to the potential of the signal pH!. Therefore, the charge stored in the sampling capacitor 12G can be transferred to the integrating capacitor C" through the turned-on 126, the switch 128, and the switch & "The 'digital/analog converter 106' is based on 1 in the channel 1 in the previous conversion cycle. The bit digit apostrophe generates the feedback signal 111 to the integration circuit. In the clock cycle 15 201218646 D 2 S2 phase 'When the signal 嗥 is high potential, the comparator 1 〇 4 will pick (4) the early D0 output signal please Comparing with the second reference signal, generating a 1-bit digital signal of the channel, and locking it in the multiplexer lake. The digital ferrite F! receives the 1-bit digital signal. In the clock cycle I' channel The order of operation of channel 2 is similar to that of channel 1. The high potential level switch of signal pH2, switch 122 and switch 124 are turned on according to the heart phase of clock cycle I, switch 126 and switch 128 are open. The input analog signal of channel 2, for example, the analog voltage signal v2 is transmitted to the sampling capacitor 120 and sampled. At the & stage of the lion, the switch 122 and the switch 124 are turned off according to the high potential of the signal PH1, and the switch 126 with The switch 128 is turned on. Since the switch s1B is turned off after the & period of the clock cycle 1, the switch SZB is turned on during the heart phase and the clock cycle of the clock cycle Τ2, in the clock cycle In the & stage, the charge stored in the sampling capacitor 12G $ is transferred to the integrating capacitor Q2. Then the comparator 104 can operate in the 32-stage phase of the clock cycle 3 and generate a 1-bit 7L digit of the channel 2 to the multiplexer. The digital ferrite F! receives the i-bit digital signal. The class f can select channel 3 in the clock cycle I, and generate a 1-bit digital signal in the clock cycle D4 S2Mx, which can select the channel in the clock cycle. 4, and generate i-bit digital signal in the phase of the clock cycle □ 5. If there is a more input channel available, then the input channel can be selected successively in successive clock cycles. Thus, from these input channels The Laiby signal can be converted to a digital signal in succession 16 201218646 and loopback. For example, if there are 4 rounds of channels, then at least 4 clock cycles Τι, clock cycle I, clock cycle 3 And clocks around A loop that converts all input channels. A digital waver, for example, a digital filter Fl, a digital filter & a digital filter & or a digital wave $ Fd to receive and input channels in each conversion chat, for example Pass L 1 channel 2 channel 3 or channel 4 related 1-bit digital signal. Then the next conversion cycle starts from clock cycle Τ 5. Similarly, each input channel phase fiber selects 'each analog signal is sampled successively Therefore, each digital filter can accumulate the bit number of the input channel in multiple conversion cycles, and extract the bit 7L number to generate more at a preset speed (for example, Fs). Bit digital output signal. In the embodiment - the hypothesis - the oversampling rate is 0SR, the time required for a conversion cycle is N * OSR clock cycles 'where N represents the total number of channels. Advantageously, in an embodiment, the analog signal from the input channel can be sampled and converted to a bitwise number in one conversion cycle. Therefore, the multi-bit digital output signal of multiple input channels can be closed in multiple conversion weeks. As a result, the multi-channel digital/analog converter 100 can increase efficiency and reduce energy consumption. Fig. 2B is a waveform diagram of a signal of a multi-channel analog/digital converter 1 另 of another embodiment of the present invention. For example, the waveform plus represents the analog analog L number from the corresponding input channel. Waveform 204 represents the overlap of the 17 201218646 feedback signal 111 output from the digital/analog converter 1〇6 and the sampled signal of the input analog signal obtained from the sampling capacitor 120. Waveform 206 represents the output signal 170 of the integrating circuit. Waveform 208 represents the output signal of comparator 104. Waveform 210 represents an output signal representative of an input analog signal, such as a multi-bit digital signal, obtained from a corresponding digital filter. Waveform 212 represents the sampling rate of the input analog signal. In addition, in order to speed up the conversion, other switch arrays can be added (for example, similar to switches 122, 124, 126, and 128) and other sampling capacitors can be added (for example, similar to sampling capacitor 12〇), and complementary control is used. The clock signals PH1 and PH2 are used to implement a double sampling technique. With this topology, the conversion speed of a digital/analog converter can be doubled without increasing static power. Other sampling techniques, such as a triple sampling technique, can also be employed to achieve higher conversion speeds of the digital/analog converter 100. The figure shows a flow chart of a digital/analog converter, such as the operation of a multi-channel digital/analog converter (8), in accordance with an embodiment of the present invention. Figure 3 will be described in conjunction with Figure 1. The multi-channel digital/analog converter 1 selects one input channel to connect (four) to the signal in the system SGLK, and the input channel I = ' is channel 1, channel 2, channel 3 or channel 4. At step 302, the analog signal is received by the 310-saw early (13G-input channel-sampling signal. The sampling circuit in the step-by-step 5 single % 13G samples the analog signal in the ^_. 201218646

The sampling signal of the analog signal is transmitted to an integral capacitor, for example, a capacitor cii, Cu, Q3 or Cm, under the control of an associated switch, for example, switch SlB, Sm, s3B or S4B. The integrating circuit in the sampling-integration unit 13A can integrate the overlapping portion of the sampling signal of the input analog signal and the feedback signal 丨丨丨. The integrating capacitors can be randomly assigned to the input channels at the beginning of the conversion cycle. At step 330, the integrating circuit produces an output signal 170 based on the integration result of the overlapping portion. At step 340' the comparator, for example, comparator 1 〇 4 can generate a one-bit digital signal based on the round-out signal 170. More specifically, the comparator 〇4 compares the output signal Π0 with the reference signals to generate an i-bit digital signal and transmits the s-dimensional 1-bit digital signal to the multiplexer, for example, multiplexing. 1〇8. At step 350, the multiplexer 108 may output a 1-bit digital signal to the digital/analog converter and the subtraction domain filter, for example, a digital wave filter & a digital chopper f2, a digital test n f3, or The digital stitch ^ & also produces a feedback signal 1U representing a 1-bit digital signal. In step 36, the corresponding digital waveform can generate a multi-bit field output signal based on the 1-bit read signal. More specifically, the digital detector can be converted to a 1-bit touch field of the corresponding input channel, and the _ generates a digital output signal. Fig. 4 is a block diagram showing the architecture of an electronic system 400 according to an embodiment of the present invention. In the embodiment, the electronic system employs the multi-channel analog/digital bit described above. The 201218646 multi-channel analog/digital converter 100 has a plurality of input channels, such as converter 100. For example, channel 1, channel 2, finger q, , ^ channel ... channel N to receive analog signals from multiple devices, such as 'device 402, device 4〇4, device 406, device 408' And converting the analog signal into a digital output signal, for example, output Bu output 2 output 3 ·..··. Output N. The digital output signal can be received by various receivers, such as receiver 422, receiver-like, receiver gamma, and receiver 428. Multiple devices may be various types of devices that generate analog signals. For example, a multi-channel analog/digital converter can be used to convert analog voltages representing battery voltages to counties. Battery management money can receive digital signals and control the battery. Thus, in the "embodiment", a digital/analog converter for converting an analog signal into a digital signal, for example, a multi-channel analog/digital converter, includes: a multi-input channel, for example, a channel channel 2, a channel 3 , channel 4, etc., the sampling-integration unit 13〇' and the sampling and integration unit contact feedback circuit. One of the plurality of input channels is selected when the corresponding switch is turned on. The sample-integration unit 130 includes a sampling circuit that samples an analog signal of the selected input channel. The sampling rail contains a memory unit 12(). The sampling/integrating unit 13 further includes an integrating circuit that is connected to the sampling circuit to receive the sampling rhyme of the input analog signal (4), the powering U1, the sampling signal of the analog input signal of the lining input signal, and the weighting of the weighting signal portion of the lining signal. Integral circuit pack: A plurality of capacitors coupled in parallel, for example, an integrating capacitor and an error amplifier. Product 20 201218646 Knife Valley is connected with the switch. When the corresponding off is turned on, one of the integrating capacitors can store the charge from the energy storage unit 12G. The feedback circuit includes a multiplexer (10) that is connected to the integrating circuit of the sampling/integrating unit and is connected to the comparator 104, and is connected to a digit between the multiplexer and the secret-integral 7L 130. / analog converter. The comparator 1〇4 can compare the output signal m of the sampling/integrating unit 13G with the reference signal, and generate a comparison output signal H 1G8 according to the comparison result, and can provide a digital signal according to the comparison output L number. The multi-channel digital/analog converter 110 can further include an output channel to provide a nucleus digital output signal. The advantage is that the 'multi-channel analog/digital conversion H 100 can perform analogy to digital_variation in interleaved mode. In the embodiment, there is no need for multiple sample/hold Μ, and or analog analog/digital converters to customize the analog signal of multiple input channels. Therefore, the cost of the circuit line can be reduced and the circuit can be improved. System taxis;; additionally 'mismatch between multiple analog/digital converters can be reduced or avoided. FIG. 5 is not a schematic diagram of the architecture of the multi-channel analog/digital converter 500 according to an embodiment of the present invention. The multi-channel analog/digital converter 500 can be a multi-stage sigma-delta Μ/digital converter ’, for example, a 2 P Σ-Δ analog/digital converter. The same figure number as in Figure 1; Figure 5 will be described in conjunction with Figure 1. The 'modulator 51' shown in Figure 5 will come from the corresponding input channel, for example, packet 21 201218646 contains channel 1, channel 2, channel 3 complement; tone / ^ ^ and channel 4 analog channels of the four input channels, For example, 'analog voltage record V|, _f pressure %, analog voltage signal % or analog voltage signal V4 converted to the corresponding number of health can be multi-order Σ•△ modulator, for example, 2nd order Σ·△ adjustment Transformer. The modulator 510 includes a plurality of serially sampled and integrated materials, for example, a serial-to-sampling-integrating unit and a sampling-integrating unit-sampling-integrating unit 53A and a sampling-integrating unit 550 and a circle The sampling and integration unit can be similar. The sample_integration unit 530 receives an analog signal from the selected input channel, e.g., channel 丨 and associated switch ', ' switch SlA. At the sample-integration unit 530, the product 77 can sample the received analog signal at a predetermined sampling frequency. In the towel, the first-heteroelectric touch contains an energy storage list, such as a m capacitor, to store electricity from the selected wheel channel: 'Step 3 includes a switch 522, a switch 524, a switch 526, and an open switch array. Control the energy storage unit 52°. Similarly, switch 522 is broken, and switches 526 and 528 are controlled by signal ρΗι. In the consistent example, sister sampling, sub-single = * 2 is a non-overlapping clock signal. Further, the two circuits M coupled to the first sampling circuit receive the sampling signal and the feedback signal 111 of the wheel thief signal. f—Integral Wei is the finest part of the sampling money and the shouting signal m of the version _ domain. The integral result of the overlapping part of the first point produces an output signal circuit pack έ a set of integral capacitors, for example, an integral capacitor 8 201218646

GiA ' Ci2A ' Ci3A, Ci4A and error amplifier 502. The integrated cutter CUA, CM, CnA and CmA are coupled in parallel. Integral Capacitor CllA ' Ci2A, Ci3A, and CmA can accumulate charge from the input channel, respectively. Each integrating capacitor QlA, integrating capacitor 〇2A, integrating capacitor Q3A and integrating capacitor 14 can be connected in series with a switch. For example, integrating capacitor CUA and switch s1B are integrated with CuA and switch S1B, and integrating capacitor ci3A and switch S3B are used. Connect the 'integrated capacitor Q4A to the switch S4B. In a conversion cycle, the integral capacitor can be randomly assigned to the input channel at the beginning of the transition. In an embodiment, the output of the sample-integral unit 5, such as the output 57, the table 7F, is integrated in the overlap of the charge signal stored in the de-integration capacitor and the sample signal of the input-to-human ratio signal and the feedback signal (1). result. In one embodiment, the error amplifier 5〇2 can generate an error k number based on the input domain number and the first reference signal from the inverting and non-inverting input terminals, respectively. The input signal is the overlap between the sampled signal and the feedback signal U! In the implementation of the shot, the inverting input is grounded, so that the voltage level of the first reference signal is substantially equal to 〇. The sample-integration unit 550 receives an output signal 570 from the hybrid integration unit 53(). The sample-integration unit 55A has a similar architecture and function as the sample integration unit 53. Therefore, the output signal can be sampled by the second sampling circuit in the sampling_integration unit 55A with a preset sampling frequency. The second sampling circuit includes a 2012 23646 quantity storage unit 540 (e.g., sampling capacitor), and further includes a switch array including a switch 542, a switch 544, a switch 546, and a switch 548 to control the energy storage unit 540. In one embodiment, switch 542 and switch 544 are controlled by signal PH2, and switch 546 and switch 548 are controlled by signal PH!. In one embodiment, the sample-integration unit 530 and the sample integration unit 550 sample the input analog signal and the output signal 570 using the same sampling frequency, respectively. The sample integration unit 550 further includes a second integration circuit ‘ consuming the second sampling circuit to receive the sampled signal and the feedback signal of the output signal 570, for example, the feedback signal 111. The second integrating circuit integrates the overlapped portion of the sampled signal of the rounded signal 57A and the feedback of the reference number 111, and produces an output signal 572 based on the result of integrating the overlapped portion. The second integrating circuit includes a set of integral capacitors, for example, an integrating capacitor cilB, an integrating capacitor (: jia, an integrating capacitor Cbb, and an integrating capacitor ci4B, and an error amplifier 512 integrated electric valley Qib, an integrated electric valley Ci2B, an integrating capacitor Ci: 5B The integral capacitor cilB, the integrating capacitor Ci2B, the integrating capacitor Ci3B, and the integrating capacitor Q4B can accumulate the charges of the output signal 570 associated with the channel 丨, channel 2, channel 3, and channel 4, respectively. The integral capacitor CilB, the integral capacitor Qsb, the integral capacitor cDB and the integral capacitor ci4B are connected in series with a switch. For example, the integrated circuit Cgu B and the switch Sic are lightly connected; the integral capacitor Q2B is connected to the switch S; jc; the integral capacitor (: Lang and switch) Sk; coupling; integral capacitor ci4B is coupled to switch S4C. 8 24 201218646 As described above, integral capacitor Qi, integral capacitor Q2a, integral capacitor cw and integral power $ ci4A can be assigned to the input channel at the beginning of the cycle Similarly, the integrating capacitor CiiB, the integrating capacitor Ci2B, the integrating capacitor Cdb, and the integrating capacitor CWB can also be randomly assigned to the input pass at the beginning of the conversion cycle. In an embodiment, the integrating capacitor C core and ClkB '' assigned to the corresponding channel, for example 'n=Bu 2, 3 or 4; k=1, 2, 3 or 4, are turned on or off at the same time. For example, if The integrating capacitors Qia and Q3b are assigned to the channel. When the channel 1 is selected, the integrating capacitors CilA* ci3B are turned on. The similar 'error amplifier 512' can be based on inputs from the inverting wheel and the non-inverting input, respectively. The difference between the signal and the second reference signal produces an error signal. The input signal may be an overlap of the sampled signal of the output signal 570 and the feedback signal 111. In the embodiment, the non-inverting input is grounded, thus The voltage level of the two reference signals is substantially equal to 〇. Further, the feedback circuit includes a comparator 104, a multiplexer 108, and a digital/analog converter (referred to as a DAC). The feedback circuit can be based on the output of the sample-integrator unit 55〇. The signal 572 generates a digital signal, and generates a feedback signal 111 <5 representing the digital signal of the sampling and integrating unit 53A and the sampling-integrating unit 550. The comparator 1?4 coupled to the sampling_integrating unit 550 sets the sampling-integrating unit 55. The output signal 572 is compared to the third reference signal and produces a comparator output number based on the comparison. In one embodiment, the comparator 104 can be controlled by the signal pH2 and operates when PH2 is at zeta potential. In the example, the non-inverting 25 201218646 input of the comparator 1〇4 is grounded, so that the voltage level of the third reference signal is substantially equal to 〇. The comparator HH can generate a bit number key according to the ratio subtraction, for example, Logic 1 or Logic G. The wheeled signal of the comparator W, for example, the digital signal is delivered to the multiplexer 108. The eve 108 transmits the health signal from the comparator 1 to 4 according to the system s. (4) & lion_人_目_数赠(四)^, digital filter F2, digital filter, waver f3 and digital chopper & Thus, it is obtained with a plurality of input __ bit output signals, a time-of-care digital frequency device F1, a digital gift wave H F2, a digital tilt (four) F3, and a digital gift wave device F4. 550. In a new conversion cycle, a 1-bit digital signal generated by the previous conversion cycle of the input channel is transmitted to the digital/analog converter 1〇6 according to the system clock signal & The digital-to-average converter 6 converts the 1-bit read side number 5 into an analog signal, and the money can be transmitted as a feedback signal 丨11 to the sample/integration shirt and the sampling/integration unit. . For analog/digital converters with different ratios 'for example, 丨 analog/digit conversion Γ and 2 P white analog/digital converter 5〇〇' analog/digital converter bee ratio (s_biased ratio, _SNR) The maximum value of the ) varies with the oversampling rate and the order of the preset analog/digital converter. The SNR of the analog/digital converter with a preset order of l is determined by the formula (丨):

SNR

JIAX -\)2 〇SR{U+l^ (1) 26 201218646 where OSR represents the oversampling rate of the analog/digital converter, and 1^ represents the resolution of the digitization. Figure 6 shows an SNR plot 600 vs. oversampling rate OSR at different analog/digital converter orders. Analog/digit for fixed order

The converter, for example, has an order of 0 small 2, 3, 4 or 5, and the SNR increases as the 〇SR increases. For the same OSR 'for example, 〇SR=64, the higher the order of the analog/digital converter', the more noise will be suppressed during the analog/digital conversion of the input signal. Therefore, for higher order analog/digital Converter, the bandwidth of the input signal is increased, the daily shirt solution will also increase, and the output money will be enhanced. Further, in the embodiment, the output signal of the integrating circuit of the sampling/integrating unit 53A is not directly input to the integrating circuit of the sampling-integrating unit 55A, but is sampled by the sampling circuit of the track integrating unit S550. When the sampling circuit of the sampling_integrating unit 55〇 transmits the sampling signal to the integrating circuit of the sampling_integrating unit 550 controlled by the signal ρΗι, the sampling circuit of the sampling-integrating unit 550 and the signal Η: the secret-integral unit under control The 55-inch integration circuit is disconnected. Thus, the integration circuit of the same sampling and integration unit is operated independently, and the stability of the system is enhanced as shown in the present invention - an embodiment multi-channel analog/number architecture. More than 诵 翻 顺 / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / / 1 ° '2nd order Σ_△ analog/digital converter. Wei with the figures of Figure 1 and Figure 5 5'. Figure 7 will be described in conjunction with Figures 1 and 27 201218646 Figure 5. As shown in FIG. 7, the regulator 710 further forwards the packet to the input analog signal received from the selected round-in channel, := the integral circuit rhyme ^ 720 (^° ^ the charge from the selected input channel, the front_direction The circuit 73 is further advanced - there is a switch array 722, a switch 724, a switch 726, and a switch array of switches 728 to control the month (3) storage earlier than 72. The switch 722 and the switch η4 are controlled by signal items. Switching switch 728 is controlled by signal 。. Therefore, switch 722, switch 724 and switch 726, switch 728 will alternately conduct. During operation 'when the input channel, for example, channel i is selected, when switches 722 and 724 are turned on The energy storage unit stores the charge of the analog signal from channel i; when switches 726 and 728 are turned on, the charge stored in energy storage unit 720 is transferred to the integrating circuit of sample-integrator unit 55. Thus, sampling- The integrating circuit of the integrating unit 550 can integrate the sampling signal of the output signal 57〇, the sampling signal of the input signal, and the weight (four) of the signal to generate an output signal 572. Further, the regulator 710 includes a digit/class Ratio converter (10) 〇 t〇 (four) ton converter DAC) 706 and digital/analog converter 714 to generate feedback signal 711 and based on the 丨 bit digital signal of the selected input channel from the previous conversion period of multiplexed S 1G8 The signal 713 is returned. The feedback signal 711 and the back 8 28 201218646 are signaled 713 to be supplied to the sampling circuit of the hybrid integrating unit 53_like circuit and the sampling-integrating unit 550. The advantage is that the sampling circuit of the input money is supplied to the integrating circuit of the sampling-integrating unit wo through the feedforward forward circuit 73. The amplitude of the output signal 5?2 of the sampling integration sheet 疋5S0 is controlled within a specific range. Thus the stability of the multi-stage analog/digital converter has increased. In addition, the digital/analog conversion 3 706 and the digital/analog conversion n 714 can independently generate and provide the feedback signal 711 and the feedback 713, which helps to improve the stability of the freeze/digital converter 700. Figure 8 is a flow chart showing a multi-channel analog/digital converter, for example, a multi-channel analog/digital conversion (four), according to an embodiment of the present invention. Figure 8 will be described in conjunction with Figure 5. The multi-channel analog/digital converter selects one input channel for one clock cycle of the system clock signal ^, for example, channel 丨, channel 2, channel 3 or 迢 4 to receive an analog signal. In step 8〇2, the analog signal is input to the sampling and age unit', for example, the sampling commission unit W is in the step _, the ratio signal is under the control of the switch_ in the same (four) pulse is sampled-integrated early 530 sampling circuit Sampled. In step 806, the integrating circuit of the sampling-integrating unit 53A integrates the overlapping portion of the sampling signal and the feedback signal of the human-to-human ratio signal. In step _, the integration circuit produces an output signal for the integration result of the overlap portion. Step If the current sampling_integration unit is a multi-channel analog/digital conversion to the upper sampling-integration unit of the 201218646 converter, then the step is performed, otherwise step 812 is performed, in step 812, the output of the current sampling_integration unit The signal can be input to the next-sampling-integral material, for example, the sampling/pointing sheet is 50. Then, return to step 804. At step 814, a comparator, e.g., comparator 〇4, generates a 1-bit digital signal based on the output signal ’ of the last sample-integration unit', e.g., the output signal 572' of the sample-integration unit 55g. More specifically, the comparator (10) compares the output (four) 572 of the sampling and integrating unit 55A with a reference signal and generates a 1-bit 7G digital signal, and transmits the i-bit digital signal to the multiplexer, for example, a multiplexer 108. At step 816, the multiplexer should output the J-bit digital signal to the digital/analog converter 106 and the corresponding digital ferrite, for example, according to the waver Fi, the ferrite F2, the ferrite F3, or the newer & At the same time, a feedback signal U1 indicating an i-bit digital signal is also generated. At step 818, the corresponding digital filter produces a multi-bit recording output signal based on the 1-bit digital signal. More specifically, the corresponding digital filter accumulates the bit-bit signals of several conversion periods of the corresponding input channel and produces a multi-bit digital output signal. Thus, in accordance with an embodiment of the present invention, a multi-channel analog/digital converter converts a plurality of analog signals into corresponding digital signals through respective input channels. In one embodiment, the 'multichannel analog/digital converter includes a plurality of sample and integration orders 7C that are connected in parallel. By including multiple sample-integration units, the analog/digital converter can have a higher order, the signal-to-noise ratio of the analog/digital converter is improved, and the analogy/number 8 30 201218646 bit converter accuracy is improved. The above specific embodiments and _ are merely phase embodiments of the present invention. Obviously, various additions, modifications and substitutions are possible without departing from the spirit and scope of the invention as defined by the appended claims. It should be understood by those skilled in the art that the present invention may be modified in form, structure, arrangement, ratio, material, component, element, and other aspects without departing from the scope of the invention. Accordingly, the disclosure is to be construed as illustrative and not restrictive, and the scope of the invention BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing the architecture of a multi-channel analog/digital converter according to an embodiment of the present invention; FIG. 2A shows a multi-channel analog/digital converter signal according to an embodiment of the present invention. FIG. 2B is a waveform diagram of a multi-channel analog/digital converter signal according to another embodiment of the present invention; FIG. 3 is a flowchart showing an operation flow of a multi-channel analog/digital converter according to an embodiment of the present invention; FIG. 4 is a schematic structural diagram of an electronic system according to an embodiment of the present invention; FIG. 5 is a schematic structural diagram of a multi-channel analog/digital converter according to another embodiment of the present invention; The analog/digital converter of an embodiment of the invention differs from the signal to noise ratio curve of the oversampling rate of the order of 201218646; FIG. 7 is a schematic diagram showing the architecture of a multichannel analog/digital converter according to another embodiment of the present invention; FIG. 8 is a flow chart showing the operation of a multi-channel analog/digital converter according to an embodiment of the present invention. [Main component symbol description] 100: Multi-channel analog/digital converter 102: Error amplifier 104: Comparator 106: Digital/analog converter 108: Multiplexer 110: Modulator 111: Feedback signal 120: Sampling capacitor 122 ～128: Switch 130: Sampling-integrating unit 170: Output signals 200A to 200B: Waveforms 202 to 212: Waveform 300: Flowcharts 302 to 360: Step 400: Electronic systems 402 to 408: Devices 422 to 428: Receiver 500 : Analog/Digital Converter 8 32 201218646 502 : Error Amplifier 510 : Modulator 512 : Error Amplifier 520 : Energy Storage Units 522 528 528 : Switch 530 : Sampling - Integrating Unit 540 : Energy Storage Units 542 - 548 : Switch 550 : Sampling-integrating unit 570: output signal 572: output signal 600: graph 700: multi-channel analog/digital converter 706 · digital/analog converter 710: regulator 711: feedback signal 713: feedback signal 714: digital / Analog Converter 720: Energy Storage Units 722 to 728: Switch 730: Feedforward Forward Circuit 800: Flowchart 802 to 818: Steps Cil to Ci4: Integration Capacitance CilA to Ci4A: Integration Capacitor 33 201218646

CilB~Ci4B: Integral Capacitor Si~S2: Stage $1 VIII~§4 VIII: Switch

SlB~S4B: Switch Sic~S4C: Switch ScLK: Clock signal Fi-F#: Digital filter D1 to D5: Clock cycle PH^PHb: Signal v[~v4: Analog voltage signal Vref: Reference voltage 8 34

Claims (1)

201218646 Seven patent application scope: 1. An analog/digital converter, comprising: an input channel, receiving an analog signal; a first-sampling and integrating unit, sampling from the input channel _ class = class = signal ' Integrating a first feedback signal and an overlap portion of the 'two*-first-sampling signal into two first round-out signals; generating a second sampling-age unit to receive the _th output money number for sampling, And the _ second feedback signal and the first =. The secret of the 5th - overlap part is integrated, and ^ turns out (four) 'where' do-sampling integration unit and the second: with each / pure containing - the first - energy storage unit and - energy: connected - a first switch array to control the first: return = way 'and the first sample and integration unit and the second sample - integral ==:= number to generate a digital signal, and to mention the analogy/digit of the first item a converter, wherein the element further enters the i-packet m, the second sample_each unit in the integration unit = when the 〇umed(8) is turned on, the analogy of the first item from the first-energy storage unit is stored/ Digital converter, where 'the private sample_integration breaks into the step-inclusive-error amplification H, to -35 201218646 reference signal and the first return yield 4. Part '=:= secret two-: two:: In the analog/digital converter of item 1, the first smear-integral is further advanced - the reference signal and the second juice (9) are differentially amplified by 11' to the overlap of a 5. signal. In: The car one output relies on the sampling, such as the patent application scope 丨1§w, 'product difference signal. The feedback circuit includes a comparator coupled to the second converter, the first output signal and the reference signal are compared to the comparator output signal. (10) The m-seat ratio 6'f contains the multiplexer connected to the comparison_ to 7. Provide the Wei Jian according to the comparison n output money. For example, the analogy/digit of the patent scope 1IM. 8. Feedback, electricity. The circuit includes a digital/analog converter coupled to the first sampling-integrating unit and the first sampling unit 7C. ^Please refer to the analogy back-position converter of the first item of the patent range, the further step-step forward feed circuit, sample with the input channel and provide the number of the analog signal # _1 like integral unit through the confrontation: output And (4) integrating the sampling signal and an overlapping portion of the second signal of the analog signal to produce an analogy/digital converter according to item 8 of the patent application scope, wherein the 36 201218646 is forward-feeding The circuit includes a second energy storage unit and a second switch array, wherein the second switch array is coupled to the second energy storage unit to control the second energy storage unit. 37