201218170 六、發明說明： 【發明所屬之技術領域】 本發明係有關於一種液晶驅動裝置及其方法，尤指一種改善開 機延遲的液晶驅動裝置及其方法。 【先前技術】 請參照第1圖，第1圖係說明應用於閘極驅動電路中的移位暫 存器100之示意圖。如帛1圖所示，當液晶顯示器的掃描起始訊號 為高電位(液晶顯示器開機)時，掃描起始訊號輸入至間極驅動電路 中的移位暫存器100的輸入端IN卜此時薄膜電晶體丁！開啟，導 致節點m開始充電以及薄膜電晶體T2開啟。但由於此時輸入端 ㈤輸入的關時脈CK為低電位，所以移位暫存器卿的輸出端 =的輸出訊號(薄膜電晶體T2的源極端的電位)為低電位。當圖 二為高電位時’薄膜電晶體Τ2依然維持開啟(因為節 〜☆錢狀態）。因薄膜電晶體12的閘極端和源極端有-升 ，’夺c卜仙_N1的電壓她合圖脈 高。如此，將保持薄膜電晶體T2開啟，此時務捕^電位而更 端OUT的輸出m-心 開啟此時移位暫存器100輸出 Λ號為同電位’亦即高電位的 電晶體Τ2的源極端輸出。 、嫌CK經由_ 然而薄祺電晶體Τ2不僅要驅動 下-級移位暫存器以及重 4像素的開關，亦要設定 及重〜上〜級移位暫存器。因此，薄膜電晶 201218170 體 ^的寄生電容據㈣大，錢的狀時_Γ電因明此體 會使開機初期的節點N1的電4無法到達需求，而造成開機延遲。’ 【發明内容】 本發明的-實施織供—觀善開機延遲陳晶軸裝置。节 ^曰曰驅動裝置包含-閘極驅動電路、—源極驅動電路及—時序控制 電路。該·驅動電路包含複數個移位暫存器；娜極驅動電路係 ^將一顯^料轉換成—資料電壓，賴根據該資料電壓將相對 ^像素級電到姉應灰階的龍；及該鱗㈣電路係麵接 ㈣閑極_電路及該源極驅動電路’心在雜晶顯示器開機 時，达出低於該液晶顯示器的正常_時脈的—低頻_時脈 (tone rate⑽及高於雜晶顯示^的正常掃描啟始減的頻率的一 高頻掃描啟始訊號運作該閘極驅動電路―預定時脈數。 眷 林明的另一實施例提供一種用於改善開機延遲的液晶驅動裝 置之時序控制電路。該時序控制電路包含一計數器、一觸發器及一 調整頻率電路。該計數器係用以計數-預定時脈數；該觸發器係搞 ^於料數H ’用以根據該預定時脈數，產生一觸發訊號；及該調 整頻率電路係織於該觸發器，用以根據該觸發訊號，將一低頻圖 t貞時脈调整至絲晶顯示II的正常圖巾貞時脈以及將—高頻掃描啟始 訊號調整至該液晶顯示器的正常掃描啟始訊號。 5 201218170 本發明的另一實施例提俾一 法。該方法包含在一液晶續λ 顯示器開機延遲的方 正當圖碰rl 器開機時，根據低於該液晶顯示器的 正_械的-低_貞時脈以及高於 啟始訊號的頻率的一高頻播㈣正吊切田 定時脈數；根據該液晶顯示器的—時“ 路一預 低頻_魏咖= 描啟始訊號調整至該液晶_ 谁乂及將^崎 常_— 本發明所提供的一種改盖Ρϋ > 雷路Mm, 文相機延遲的液晶驅練置、時序控制 液晶鮮 ===^嫩，#~恤㈣開機時， 低頻_時脈以及高於液晶====示器的正常_時脈的 =敬始訊號’運作液晶顯示器的二：：=高 路，所以此時液晶顯示器的源極驅動電 :正常_時脈，頻:===:=:= :可：，晝*。如此，閘_電==尺 著變:開;rr延長一 ’因為知招起始訊號為高電位的時間增加且在_關 201218170 •期間輸出多次掃描起始訊號，所以可增加薄膜電晶體的開啟次數， 使得薄膜電晶體的溫度上升，提高薄膜電晶體的驅動能力。因此， 本發明可減少閘極驅動電路面積，以及減少開機延遲。 【實施方式】201218170 VI. Description of the Invention: [Technical Field] The present invention relates to a liquid crystal driving device and a method thereof, and more particularly to a liquid crystal driving device and method for improving the opening delay. [Prior Art] Referring to Fig. 1, Fig. 1 is a view showing a shift register 100 applied to a gate driving circuit. As shown in FIG. 1 , when the scan start signal of the liquid crystal display is high (the liquid crystal display is turned on), the scan start signal is input to the input terminal IN of the shift register 100 in the interpole drive circuit. Thin film transistor Ding! Turning on causes node m to start charging and thin film transistor T2 to turn on. However, since the off-clock CK input to the input terminal (5) is low, the output signal of the output terminal of the shift register (the potential of the source terminal of the thin film transistor T2) is low. When Figure 2 is at a high potential, the thin film transistor Τ2 remains open (because the section ~ ☆ money state). Since the gate terminal and the source terminal of the thin film transistor 12 have a liter, the voltage of the cull _N1 is high. In this way, the thin film transistor T2 is turned on, and at this time, the output potential of the more terminal OUT is turned on. At this time, the shift register 100 outputs the source of the transistor Τ2 whose nickname is the same potential, that is, the high potential. Extreme output.嫌 CK via _ However, the thin transistor Τ 2 not only drives the lower-level shift register and the 4-pixel switch, but also sets the ~~~ shift register. Therefore, the parasitic capacitance of the thin film transistor 201218170 is large according to (4), and the shape of the money is _ Γ 因 明 明 明 明 明 此 此 此 此 此 此 此 此 节点 节点 节点 节点 节点 节点 节点 节点 节点 节点 节点 节点 节点 节点 节点 节点 节点 节点 节点 节点[Description of the Invention] The present invention - the implementation of the woven - the good start-up delay Chen Jing axis device. The 曰曰 drive device includes a gate drive circuit, a source drive circuit, and a timing control circuit. The driving circuit comprises a plurality of shift registers; the nano-pole driving circuit converts a display material into a data voltage, and the light according to the data voltage is to be compared with the pixel level to the gray level; and The scale (4) circuit is connected (4) the idle pole _ circuit and the source drive circuit 'heart when the crystal display is turned on, reaching lower than the normal _ clock of the liquid crystal display - low frequency _ clock (tone rate (10) and high A high frequency scanning start signal at a frequency at which the normal scan starts decreasing of the crystal display operates the gate driving circuit - a predetermined number of clocks. Another embodiment of the present invention provides a liquid crystal for improving the turn-on delay. a timing control circuit of the driving device. The timing control circuit comprises a counter, a flip-flop and an adjusting frequency circuit. The counter is used for counting-predetermined clock number; the trigger is used to generate the number H' The predetermined number of clocks generates a trigger signal; and the adjusting frequency circuit is coupled to the trigger for adjusting a low frequency map t贞 clock to a normal picture clock of the silk crystal display II according to the trigger signal and Will be high The scan start signal is adjusted to the normal scan start signal of the liquid crystal display. 5 201218170 Another embodiment of the present invention provides a method for detecting the power-on delay of a liquid crystal display λ display. According to the liquid crystal display, the low-frequency (four) clock is lower than the frequency of the start signal, and the high-frequency broadcast (four) is used to hang the timing pulse number; _Wei coffee = tracing start signal adjustment to the LCD _ who will and will ^ sis often _ - the invention provides a modified cover gt > Lei Road Mm, text camera delay liquid crystal drive, timing control LCD fresh ===^嫩,#~shirt (4) When booting, low frequency _clock and higher than liquid crystal ==== normal _clock of the indicator = sequel to the operation of the LCD 2::= high road, so At this time, the source of the liquid crystal display drives electricity: normal _ clock, frequency: ===:=:=: can:, 昼*. So, __================================== The time when the start signal is high is increased and the scan start signal is output during the period of _ off 201218170 • Therefore, the number of times of opening the thin film transistor can be increased, the temperature of the thin film transistor is increased, and the driving ability of the thin film transistor is improved. Therefore, the present invention can reduce the gate driving circuit area and reduce the startup delay.
請參照第2圖，第2圖係本發明的一實施例說明改善開機延遲 的液晶驅動裝置2〇〇的示意圖。液晶驅動裝置2〇〇包含一閘極驅動 電路202、一源極驅動電路204及一時序控制電路206。閘極驅動電 路202包含複數個移位暫存器，複數個移位暫存器係以輸出端耗接 的方式相互連接。舉例來說，複數個移位暫存器包含依序耦接的一 第〜1級移位暫存器Gn-1、一第η級移位暫存器Gn、及一第n+1 級移位暫存器Gn+1，其中第n級移位暫存器Gn的輸出端的訊號另 做為第n+1級移位暫存器Gn+1的設定端SET的輸入訊號以及第 級移位暫存H Gri-l的重設定端reset的輸人訊號，其巾值得注意 ^是閘極驅動電路202最後附加的虛擬移位暫存器Gdummy的輸出 #端的峨不會做為虛擬移位暫存器Gdummy前面各級移位暫存器的 重設定端RESET的輸人職。每-級移位暫存器的輸出端的訊號係 用以控制祕於-像素腦的開關施的開啟與關閉。源極驅動 電路204係用以將一顯示資料轉換成一資料電a，然後根據資料電 壓將相對應的像素2024，充放姉目_灰階的電壓。時序控制電 路206係搞接於閘極驅動電路2〇2以及源極驅動電路辦，用以在 液晶顯示器開機時，送出低於液晶顯示器的正常_時脈CK的一 低頻圖㈣脈LCK以及高於液的正常掃贿始訊號贈V 201218170 的頻率的一高頻掃描啟始訊號HSTV，運作閘極驅動電路202 —預 定時脈數CP。 請參照第3圖，第3圖係本發明的另一實施例說明液晶驅動裝 置200中的時序控制電路206示意圖。時序控制電路206包含一計 數器2062、—觸發器2064及一調整頻率電路2066。在液晶顯示器 開機時’時序控制電路2〇6先設定液晶顯示器進入自我測試(buik_in self test，BIST)模式。此時，時序控制電路2〇6内的調整頻率電路施6 送出低於液晶顯示器的正常圖幀時脈CK的低頻圖幀時脈LCK以及 高於液晶顯示器的正常掃描啟始訊號NSTV的頻率的高頻掃描啟始 訊號HSTV，運作閘極驅動電路202。在以低頻圖傾時脈LCK運作 閘極驅動電路2〇2的同時，計數器2〇62 _計數以及時序控制電路 206送黑資料訊號給源極驅動電路2〇4，所以此時液晶顯示器呈現黑 色的圖巾貞。當計數器2〇62計數預定雜數cp後，祕於計數器細 的觸發器薦根據縱時脈數cp，產生—觸發織I _於觸 發器2064的調整頻率· 2〇66根據觸發訊號Tr，純頻_時脈 LCK 成驗晶顯示器的正常_時脈ck以及將高頻掃描啟始 訊號服V調整至液晶顯示器的正常掃描啟始訊號NSTV，且時序^ 控制電路施開始送出正常資料給源極驅動電路204，以顯示正常 的畫面。 •只I此爷 請參照第4圖，第4圖你 ,, ®係說明以低頻關時脈LCK以及高頻. 描啟始訊號HSTV，運作闡托K i 门屑 3極驅動電路202示意圖。本發明係 201218170 -常關時脈6紐、768條掃描線(每一條掃描線耦接於每一級移位暫 存裔的輸出端)的液晶顯示器為例，其正常掃描啟始訊號順^係為 一關出現-次。但本發明並不受限於正常_時脈舰、挪條 掃描線的液晶顯示器。當液晶顯示器開機時，係以遍z的關時 脈以及每192條掃描線產生—個掃描啟始訊號的高頻掃微始訊號 HSTV(亦即在―_中，出現四:欠掃概始訊舰衝），運作問極驅 $電路202。但本發明並不受限於使用3〇Hz的圖巾貞時脈和每I%條 籲掃描線產i個掃描啟始訊號脈衝的高頻掃描啟始訊號肌^開 機’、要疋利用低頻圖鴨時脈LCK以及高頻掃描啟始訊號hstv 開機，皆落入本發明的範疇。 由於非晶石夕薄膜電晶體在一般使用條件下，流過的電流I可由式 (1)決定： I=0.5x10'6xW/L(A) (1) • 其中狐係為非晶石夕薄臈電晶體的寬長比。將式(1)代入式(2)， 可得式(3): 0.5 X10 6 X — Jdt = C JdV (3) 其中赐為第1圖中的升壓電容Cl的充電電壓，C係為第1圖中的 電容C1的電容值。由式(3)可得式(4): (4) 201218170Referring to Fig. 2, Fig. 2 is a schematic view showing a liquid crystal driving device 2A for improving the turn-on delay according to an embodiment of the present invention. The liquid crystal driving device 2A includes a gate driving circuit 202, a source driving circuit 204, and a timing control circuit 206. The gate drive circuit 202 includes a plurality of shift registers, and the plurality of shift registers are connected to each other in such a manner that the output terminals are consumed. For example, the plurality of shift registers include a first-order shift register Gn-1, an n-th shift register Gn, and an n+1-th shift that are sequentially coupled. The bit register Gn+1, wherein the signal of the output end of the nth stage shift register Gn is used as the input signal of the set terminal SET of the n+1th stage shift register Gn+1 and the first stage shift Temporarily storing the input signal of the reset end of H Gri-l, the towel is worth noting ^ is the output of the last virtual offset register Gdummy of the gate drive circuit 202 is not used as a virtual shift The front end of the register Gdummy shift register reset terminal RESET. The signal at the output of each stage shift register is used to control the opening and closing of the switch that is secret to the pixel brain. The source driving circuit 204 is configured to convert a display data into a data power a, and then charge and discharge the corresponding pixel 2024 according to the data voltage. The timing control circuit 206 is connected to the gate driving circuit 2〇2 and the source driving circuit to send a low frequency picture (four) pulse LCK and high below the normal _clock CK of the liquid crystal display when the liquid crystal display is turned on. A normal high-frequency scanning start signal HSTV of the frequency of V 201218170 is given to the normal bribe-starting signal of the liquid, and the gate driving circuit 202 is operated - the predetermined clock number CP. Please refer to FIG. 3, which is a schematic diagram showing a timing control circuit 206 in the liquid crystal driving device 200 according to another embodiment of the present invention. The timing control circuit 206 includes a counter 2062, a flip flop 2064 and an adjustment frequency circuit 2066. When the LCD monitor is turned on, the timing control circuit 2〇6 first sets the liquid crystal display to enter the self-test (BIST) mode. At this time, the adjustment frequency circuit 6 in the timing control circuit 2〇6 sends out a low-frequency frame clock LCK lower than the normal picture frame clock CK of the liquid crystal display and a frequency higher than the normal scanning start signal NSTV of the liquid crystal display. The high frequency scanning start signal HSTV operates the gate driving circuit 202. While operating the gate driving circuit 2〇2 with the low frequency diagram, the counter 2〇62_counting and timing control circuit 206 sends the black data signal to the source driving circuit 2〇4, so the liquid crystal display is black at this time. Figure scarf. When the counter 2〇62 counts the predetermined number cp, the trigger of the counter is recommended according to the vertical clock number cp, and the triggering frequency of the trigger 2064 is generated according to the trigger frequency Tr, pure according to the trigger signal Tr, pure The frequency_clock LCK is the normal_clock ck of the crystal display and the normal scanning start signal NSTV of the liquid crystal display is adjusted to the liquid crystal display, and the timing control circuit starts to send the normal data to the source driver. Circuit 204 to display a normal picture. • Only I, please refer to Figure 4, Figure 4, you, ® shows the low-frequency off-clock LCK and high-frequency. The start-up signal HSTV, the operation of the K i shards 3-pole drive circuit 202 schematic. The invention is a liquid crystal display of 201218170 - normally off clock 6 New Zealand, 768 scanning lines (each scanning line is coupled to the output end of each stage shifting temporary storage), and the normal scanning start signal is Appears for one level - times. However, the present invention is not limited to the liquid crystal display of the normal_clock ship and the scanning line. When the liquid crystal display is turned on, the high frequency sweeping start signal HSTV of the scanning start signal is generated by the off clock of the z and the scanning lines of 192 (that is, in the _, the fourth appears: the underscan is started) The signal ship rushed), the operation asked the pole drive $ circuit 202. However, the present invention is not limited to the use of a 3 Hz reticle clock and every 1% of the scan lines to produce a scan of the start signal pulse of the high frequency scan start signal muscle ^ boot ', to use the low frequency map The duck clock LCK and the high-frequency scanning start signal hstv are turned on, all falling within the scope of the present invention. Due to the use of amorphous Aussie thin film transistor under normal use conditions, the current I flowing can be determined by equation (1): I=0.5x10'6xW/L(A) (1) • Where the fox is amorphous The width to length ratio of the germanium crystal. Substituting the formula (1) into the formula (2), the formula (3) is obtained: 0.5 X10 6 X — Jdt = C JdV (3) wherein the charging voltage of the boosting capacitor C1 in Fig. 1 is given, and the C system is the first 1 Capacitance value of capacitor C1. From equation (3), equation (4) is available: (4) 201218170
w _ 2VCw _ 2VC
l IrvT w 其中tw係為充電時間 。因此，由式(4)可4 使用正常_時舯⑺认^ )了知，如果錢晶顯示器 在理想上非晶㈣膜電充電時間增加— 但本翻辑晶體的寬的 口要县伽. 時脈CK的一半頻率開機， ^ 於正常_時脈CK的頻率開機，料人本發明的範 日請=照第1圖、第5A圖和第5B圖，第5A圖和第5B圖係說 月在正*圖鳩時脈CK(60Hz)和低頻圖Ί*貞時脈LCK(3〇Hz)運作閘極 驅動電路202時，移位暫存器觸中的節點N1充電過程的示意圖。 如第5B圖所示，使用低頻圖幀時脈LCK運作閘極驅動電路2〇2時， 知描起始訊號脈衝為高電位的時間也同步增加，所以節點N1的電 位可以較高，薄膜電晶體T2開啟更完全，使得薄膜電晶體T2溫度 上升。另外’在一圖幀期間輸出多次掃描起始訊號脈衝，則增加薄 膜電晶體T1的開啟次數，使得薄膜電晶體Τ1溫度上升。如此，可 增加缚膜電晶體T2的驅動能力，減少開機啓動不良、暖機時間及 薄膜電晶體T2的設計面積。 請參照第6圖，第6圖係本發明的另一實施例說明改善液晶顯 不器開機延遲的方法之流程圖。第6圖之方法係利用第2圖的液晶 驅動裝置200說明，詳細步驟如下： 201218170 步驟600 :開始； 步驟602 .在液日日顯不_機時，根據低於液晶顯示㈣正常_ =CK的低頻_時脈LCK以及高於液晶顯示器的正 ㊉掃私啟始峨NSTV的鮮的高頻掃微始訊號 HSTV ’運作’驅動電路2G2預定時脈數〇> ; 步驟_ :當已以低頻關時脈LCK和高頻掃描啟始訊細口運l IrvT w where tw is the charging time. Therefore, from equation (4), we can use normal _ 舯 (7) to know that if the crystal display is ideally amorphous (four), the film charging time increases - but the wide mouth of the crystal is required. The half frequency of the clock CK is turned on, ^ is turned on at the frequency of the normal_clock CK, and the person who is in the present invention is pleased to follow the maps of Fig. 1, Fig. 5A and Fig. 5B, Fig. 5A and Fig. 5B The graph of the charging process of the node N1 touched by the shift register is performed when the gate drive circuit 202 is operated by the clock CK (60 Hz) and the low frequency map Ί * 贞 clock LCK (3 Hz). As shown in FIG. 5B, when the gate driving circuit 2〇2 is operated by using the low-frequency frame clock LCK, the time at which the start signal pulse is high is also increased synchronously, so the potential of the node N1 can be high, and the thin film is electrically charged. The crystal T2 is turned on more completely, causing the temperature of the thin film transistor T2 to rise. Further, when a plurality of scanning start signal pulses are output during one frame period, the number of times of opening of the thin film transistor T1 is increased, so that the temperature of the thin film transistor Τ1 rises. In this way, the driving ability of the bonding film transistor T2 can be increased, and the startup failure, the warm-up time, and the design area of the thin film transistor T2 can be reduced. Please refer to FIG. 6. FIG. 6 is a flow chart showing a method for improving the power-on delay of the liquid crystal display according to another embodiment of the present invention. The method of Fig. 6 is illustrated by the liquid crystal driving device 200 of Fig. 2. The detailed steps are as follows: 201218170 Step 600: Start; Step 602. When the liquid day is not displayed, the liquid crystal display is lower than the liquid crystal display (4) Normal _ = CK The low frequency _ clock LCK and the high frequency sweeping start signal HSTV 'Operation' drive circuit 2G2 predetermined clock number 〇> of the NSTV is higher than the liquid crystal display. Step _: When Low frequency off-clock LCK and high-frequency scanning start message
作閘極驅動電路202預定時脈數〇>時，產生觸發訊號 Tr ； 步驟606 .當接收到觸發訊號Tr，將低頻圖帕時脈lck調整成為液 晶顯示器的正常圖_脈以以及將高頻掃描啟始訊號 STV調1至液晶顯示器的正常掃描啟始訊號nstv ; 步驟_ :根據正常_時脈CK以及正常掃減始訊號nstv， 運作閘極驅動電路202 ; 步驟610 :結束。When the gate driving circuit 202 determines the clock number 〇>, the trigger signal Tr is generated; Step 606. When the trigger signal Tr is received, the low frequency map clock lck is adjusted to be the normal picture of the liquid crystal display and the high value is high. The frequency scanning start signal STV is adjusted to 1 to the normal scanning start signal nstv of the liquid crystal display; Step_: The gate driving circuit 202 is operated according to the normal_clock CK and the normal scanning start signal nstv; Step 610: End.
、在步驟602中，時序控制電路2〇6送出黑資料至液晶顯示器的 源極驅動電路2〇4。在步驟_中，當計數器麗計數預定時脈數 CP後，耦接於計數器2062的觸發器2064根據預定時脈數CP，產 生觸發訊號Tr。在步驟606中，搞接於觸發器2064的調整頻率電 路2066根據觸發訊號Tr，將低頻圖幀時脈LCK調整成為液晶顯示 器的正常圖幀時脈CK以及將高頻掃描啟始訊號HSTV調整至液晶 顯示器的正常掃描啟始訊號NSTV。在步驟608中，根據正常圖幀 2〇1218170 時脈ck 時序控制始訊號NSTV，運作問極驅動電路202，且 正常的畫面。1送出正常資料給源極驅動電路綱，以顯示 π上觸’本剌峨供岐善職_驗晶驅 ’，控制電路如低頻關時脈以及高頻娜啟始訊號 電電路二同，時序控制電路送黑資料訊號給源極驅動 以此時液晶顯不器呈現黑色的關。當計數器計數預定時 至液晶顯不器的正常_時脈以及將高頻掃描啟始訊號調整 資料給源極驅動電===時序控制電路開始送出正常 ㈣電路，以顯不正常的畫面。因此，由式⑷可知，如 果备液日日.4不器使用低頻_時脈開機時，則在理想上非晶 電晶，的尺寸可因開機時充電時間延長而縮小，而薄膜電晶體的寄 生電今也跟著變小。另外，如第5B圖所示，因為掃描起始訊號為 高電位的時間增加且在一_期間輸出多次掃描起始訊號脈衝，所 以可曰加4膜電晶體的開啟次數，使得薄膜電晶體的溫度上升，提 高薄膜電晶體_動能力。因此，本發明上述優點，可減少閘 極驅動電路面積，以及減少開機延遲。 ，上所述僅為本發明之較佳實施例，凡依本發明申請專利範圍 所做之均㈣化與修飾’皆關本發明之涵蓋範圍。 12 201218170 【圖式簡單說明】 第1圖係說明應用於閘極驅動電路中的移位暫存器之示意圖。 第2圖係本發明的一實施例說明改善開機延遲的液晶驅動裝置的八 意圖。 、 第3圖係本發明的另一 示意圖。 實施例說明液晶驅動裝置中的時序控制電路In step 602, the timing control circuit 2〇6 sends the black data to the source driving circuit 2〇4 of the liquid crystal display. In step _, after the counter 丽 counts the predetermined number of clocks CP, the flip-flop 2064 coupled to the counter 2062 generates the trigger signal Tr according to the predetermined clock number CP. In step 606, the adjustment frequency circuit 2066 connected to the flip-flop 2064 adjusts the low-frequency frame frame clock LCK to the normal picture frame clock CK of the liquid crystal display and adjusts the high-frequency scan start signal HSTV according to the trigger signal Tr. The normal scanning start signal NSTV of the liquid crystal display. In step 608, the start signal NSTV is controlled according to the normal picture frame 2〇1218170 clock ck timing, and the gate drive circuit 202 is operated and the normal picture is displayed. 1 Send the normal data to the source drive circuit, to display the π touch 'Ben 剌峨 岐 岐 _ _ _ 验 验 , , , , , , , , , , 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制 控制The black data signal is applied to the source driver so that the liquid crystal display device displays a black level. When the counter counts to the normal _clock of the LCD display and the high-frequency scan start signal adjustment data is supplied to the source drive power === The timing control circuit starts to send out the normal (4) circuit to display an abnormal picture. Therefore, it can be known from the formula (4) that if the liquid preparation day 4 is not used, the low-frequency _ pulse is turned on, then the ideal amorphous crystal, the size can be reduced due to the extension of the charging time at the time of booting, and the thin film transistor Parasitic electricity is also getting smaller. In addition, as shown in FIG. 5B, since the time when the scanning start signal is high is increased and the scanning start signal pulse is outputted multiple times during one period, the number of times of opening the four film transistors can be increased, so that the thin film transistor The temperature rises and the film transistor _ mobility is improved. Therefore, the above advantages of the present invention can reduce the gate drive circuit area and reduce the turn-on delay. The above description is only the preferred embodiment of the present invention, and all the modifications and modifications made by the scope of the present invention are within the scope of the present invention. 12 201218170 [Simplified description of the drawings] Fig. 1 is a schematic diagram showing a shift register applied to a gate driving circuit. Fig. 2 is a view showing an eighth embodiment of the present invention for explaining a liquid crystal driving device for improving the turn-on delay. Figure 3 is another schematic view of the present invention. Embodiments illustrate a timing control circuit in a liquid crystal driving device
第4圖係說明以低頻圖幀時脈以及高頻掃描啟始訊號 動電路示意圖。 ’運作閘極驅 和第则係說明在正常_時脈和低頻_時脈 .轉電路時’移位暫存器中的節點充電過程的示意圖。 二 =本發明的另一實施例說明改善液晶顯示 移位暫存器 液日日驅動敦置 閘極驅動電路 源極驅動電路 時序控制電路 像素 開關 計數器 【主要元件符號說明】 • 100 200 202 204 206 2024 2026 2062 13 201218170 2064 觸發器 2066 調整頻率電路 Gn-1 第n-1級移位暫存器 Gn 第η級移位暫存器 Gn+1 第η+1級移位暫存器 Gdummy 虛擬移位暫存器 INI ' CK1 輸入端 ΤΙ ' T2 薄膜電晶體 CK 正常圖幀時脈 CP 預定時脈數 N1 節點 Cl 升壓電容 NSTV 正常掃描起始訊號 HSTV 高頻掃描起始訊號 LCK 低頻圖幀時脈 Tr 觸發訊號 OUT 輸出端 SET 設定端 RESET 重設定端 600-610 步驟 14Fig. 4 is a schematic diagram showing the start signal of the low frequency frame and the high frequency scanning start signal. The 'operational gate drive and the first section illustrate the diagram of the node charging process in the normal _clock and low frequency _clock. II=Another embodiment of the present invention is directed to improving liquid crystal display shift register liquid daily driving gate driving circuit source driving circuit timing control circuit pixel switching counter [main component symbol description] • 100 200 202 204 206 2024 2026 2062 13 201218170 2064 Trigger 2066 Adjusting frequency circuit Gn-1 Stage n-1 shift register Gn Stage n shift register Gn+1 Stage n+1 shift register Gdummy Virtual shift Bit register INI ' CK1 input terminal ΤΙ ' T2 thin film transistor CK normal picture frame clock CP predetermined clock number N1 node Cl boost capacitor NSTV normal scan start signal HSTV high frequency scan start signal LCK low frequency frame Pulse Tr trigger signal OUT output SET setting terminal RESET reset terminal 600-610 Step 14