201214938 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明係有關於一種功率因數修正電路，其係尤指 一種功率轉換器之功率因數修正電路。 【先前技術】 [0002] 按’現今電源供應器之業者追求高品質的電力供需 一直是全球各國所想要達成的目標，然而大量的興建電 廠並非解決問題的唯一途徑，一方面提高電力供給的能 ) 量’一方面提而電器產品的.功.率因數（power Factor)或 .... . ..：;： : 效率才能有效解爽.間題。.而功率因數修正器（power factor corrector)其主要作用是讓電器產品的輸入電 壓與輸入電流的相位相同，且使電器產品的負載近似於 電阻性負載，以達到供電的高功率因數α: 功率因數修正器主要分有三種，第一種為臨界傳導 模式功率因數修正器（Critical conduction mode，201214938 VI. Description of the Invention: [Technical Field] [0001] The present invention relates to a power factor correction circuit, and more particularly to a power factor correction circuit for a power converter. [Prior Art] [0002] According to the current supplier of power supply, the pursuit of high-quality power supply and demand has always been the goal of all countries in the world. However, the construction of a large number of power plants is not the only way to solve the problem. Can) the amount of 'on the one hand, and the electrical factor of the electrical product (power factor) or .... ..:;: : efficiency can effectively solve the problem. The main function of the power factor corrector is to make the input voltage of the electrical product and the input current have the same phase, and the load of the electrical product is similar to the resistive load to achieve the high power factor of the power supply α: power There are three main types of factor correctors, the first one is the critical conduction mode power factor corrector (Critical conduction mode,
CRM PFC)，第二種為非連續型功率因數修正器 (Discontinuous current Conduction Mode » DCM ) PFC)與第三種為連續型功率因數修正器（c〇nt i nuous current Conduction Mode CCM PFC)。 請參閱第一圖，係為習知技術之功率因數修正電路 的電路圖。如圖所示，習知技術之功率因數修正電路為 連續型功率因數修正器（CCM PFC)，其常用的控制方式 是所δ胃的平均電流（average current)控制模式，如第 一圖中’當交流電源AC經一橋式整流器10，整流成為波 形類似m形的輸入電壓Vin，一運算電路2〇，透過電壓迴 路補償電路30，取得電壓誤差訊號a或稱為電壓命令，輸 099132684 表單編號 A0101 第 3 頁/共 19 頁 0992057216-0 201214938 出電壓V〇ut*Kf與期待（參考）電壓Vref的差值經由一補 償電路而產生一電壓誤差訊號A，同時透過一前置電路4〇 由輪入電壓Vin取出一輸入訊號B與輸入電壓Vi η的平均 值C的平方訊號（即C~2訊號）。運算電路20，之一乘法 器22’進行處理電壓誤差訊號人與輸入訊號b的相乘，然 後再以運算電路20，之一除法器24，除以平方訊號c~2, 用以輸出一波形類似m形的電流命令訊號Iref。運算電路 2〇’中之所以要除以平方訊號C2,是因為不希望功率因 數修正器的功因值隨著輸入電壓Vin大小而改變，而電壓 誤差訊號A是考慮若在餘出雜壓變動情況下，仍能藉由控 制電路50，改變電晶體q的切換而達到穩壓效果。 凊一併參閱第二圖，係為第一圖之功率因數修正電 路的波形示意圖。如圖所示，閘極驅動脈波代是三角波 Ipwm和電流命令訊號Ic作比較運算後所得的結果。閘極 驅動脈波VG在電流命令訊號I c波谷附近的工作週期最寬 而在波峰附近最窄，在第二圖3中，可看出經由閘極驅動 脈波VG控制電晶體q而得到!電感[的電填波形況，此電流 波形iL經過輸入端的電容Cin婕波後即可在輸入端得到一 個近似弦波的電流波eiL(avg)。此近似弦波的電流波形 會與輸入電壓Vin同相位，而達到功因的修正。上述說明 中所提到利用運算電路2〇，的方式，產生近似弦波的輸 入電流波形與輸入電壓Vin同相位的結果，而達到功率因 數的修正。 惟查，由於運算電路2〇，中使用除法器24,，其個 別元件數目多、設計複雜。 因此，如何針對上述問題而提出一種新穎功率轉換 0992057216-0 099132684 表單編號A0101 第4頁/共ig頁 201214938 器之功率因數修正電路，’其可避免使用除法器，使功率 因數修正電路設計簡單，進而減少成本，使可解決上述 之問題。 【發明内容】 [0003] 本發明之主要之一，在於提供一種功率轉換器之功 率因數修正電路，其藉由一乘法器而避免使用除法器， 使功率因數修正電路結構簡單，進而達到縮小功率因數 修正電路的體積，並且使功率因數修正電路結構簡單， 進而減少成本的目的。 Ο ο 本發明之功率轉換器之功率因數修正電路耦接一功 率轉換器，用以調整功率轉換器之一功率因數，功率因 數修正電路包含一回授電路、一運算電路與一切換電路 。回授電路係耦接該功率轉換器之一輸出端，並依據該 功率轉換器之一輸出訊號，產生一回授訊號，運算電路 係耦接該功率轉換器之一輸入端與該回授電路，並接收 該功率轉換器之一輸入訊號與一感測訊號和該回授訊號 ，該運算電路依據該輸入訊號與該回授訊號產生一乘法 訊號，並依據該輸入訊號與一感測訊號產生一第一參考 訊號，該運算電路再依據該乘法訊號與該第一參考訊號 而產生一控制訊號，切換電路耦接該運算電路，並依據 該控制訊號與一第二參考訊號，而產生一切換訊號，用 以切換該功率轉換器之一開關。如此，本發明係藉由一 乘法器而避免使用除法器，使功率因數修正電路結構簡 單，進而達到縮小功率因數修正電路的體積，並且可達 到減少成本的目的。 099132684 表單編號Α0101 第5頁/共19頁 0992057216-0 201214938 【實施方式】 · [_] 紐貴審鱗貞料㈣之結構紐及所達成 之功效有更進-步之瞭解與認識，謹佐以較佳之實施例 及配合詳細之說明，說明如後·· 响參閱第_圖’係為本發明之_較佳實施例之電路 圖。如圖所示，本發明之功率轉換器之功率因數修正電 路1係麵接-功率轉換器2，用以調整功率轉換器2之一功 率因數，該功率因數修正電路丨包含一電壓回授電路1〇、 -運算電路12與-切換電路14/ „回授電路1G係輕接 功率轉換器2之一輸出螭，電壓回教電路1〇依據功率轉換 器2之一輸出訊號Vout而產生一電壓命令訊號Vea，即電 壓回授電路10係依據功率轉換器2之輸出訊號v〇ut與參考 電壓Vref之電壓差經由一補償電路（即電壓迴路補償器 100)而產生電壓命令訊號Vea，常見的補償電路實現方式 為一比例（Proportional，P)控制器，一比例積分 (Proport i ona卜Integra 1，P 1丨)傳制器或一比例積分 微分（Proport ional-Integral-m ff erental，PID) 控制器，運算電路12係耦接功率轉換器2之一電壓輸入端 ，電流輸入端與電壓回授電路1〇 ,運算電路12接收功率 轉換器2之一電壓輸入訊號Vin與一電流感測訊號I和電壓 命令訊號Vea，其中電壓輸入訊號Vin係為交流電源訊號 Vac經功率轉換器2之整流電路20整流後產生之輸入訊號 ’電壓輸入訊號Vin經由一第一調整器1 204產生信號B與 電壓命令訊號Vea相乘而產生一乘法訊號Iref，並運算電 路12依據輸入電壓訊號Vin與感測電流訊號I而產生一第 一參考訊號Isen，之後，運算電路12再依據乘法訊號 099132684 表單編號A0101 第6頁/共19頁 0992057216-0 201214938 一電流迴路補償器124而CRM PFC), the second is Discontinuous Current Conduction Mode (DCM) PFC) and the third is continuous continuous power factor corrector (CCM PFC). Please refer to the first figure, which is a circuit diagram of a power factor correction circuit of the prior art. As shown in the figure, the power factor correction circuit of the prior art is a continuous power factor corrector (CCM PFC), and the commonly used control mode is the average current control mode of the δ stomach, as in the first figure. When the AC power source AC is passed through a bridge rectifier 10, it is rectified into an input voltage Vin of a waveform similar to an m shape, and an operation circuit 2〇 is passed through the voltage loop compensation circuit 30 to obtain a voltage error signal a or a voltage command, and 099132684 is shown in Form No. A0101. Page 3 of 19 0992057216-0 201214938 The difference between the output voltage V〇ut*Kf and the expected (reference) voltage Vref generates a voltage error signal A via a compensation circuit, while passing through a pre-circuit 4 The input voltage Vin takes out a square signal (ie, C~2 signal) of the average value C of the input signal B and the input voltage Vi η . The arithmetic circuit 20, a multiplier 22' performs multiplication of the processing voltage error signal with the input signal b, and then divides the operation circuit 20, a divider 24, and divides the square signal c~2 to output a waveform. A m-like current command signal Iref. The reason why the arithmetic circuit 2〇' is divided by the square signal C2 is because it is not desirable that the power factor of the power factor corrector changes with the magnitude of the input voltage Vin, and the voltage error signal A is considered to be in the residual voltage fluctuation. In this case, the voltage stabilization effect can still be achieved by changing the switching of the transistor q by the control circuit 50. Referring to the second figure, it is a waveform diagram of the power factor correction circuit of the first figure. As shown in the figure, the gate driving pulse wave generation is a result obtained by comparing the triangular wave Ipwm and the current command signal Ic. The gate drive pulse VG has the widest duty cycle near the current command signal I c valley and the narrowest near the peak. In the second FIG. 3, it can be seen that the transistor q is controlled via the gate drive pulse VG to obtain the transistor q! In the case of the inductor's electric filling waveform, the current waveform iL is chopped by the input capacitor Cin to obtain an approximate sine wave current wave eiL(avg) at the input. The current waveform of this approximate sine wave will be in phase with the input voltage Vin, and the correction of the power factor will be achieved. As described in the above description, the operation circuit 2〇 is used to generate a waveform in which the input current waveform of the approximate sine wave is in phase with the input voltage Vin, and the power factor is corrected. However, since the divider 24 is used in the arithmetic circuit 2, the number of individual components is large and the design is complicated. Therefore, how to solve the above problems, a novel power conversion 0992057216-0 099132684 form number A0101 page 4 / total ig page 201214938 power factor correction circuit, 'which can avoid the use of dividers, make the power factor correction circuit design simple, In turn, the cost is reduced, so that the above problems can be solved. SUMMARY OF THE INVENTION [0003] One of the main aspects of the present invention is to provide a power factor correction circuit for a power converter, which avoids the use of a divider by a multiplier, so that the power factor correction circuit is simple in structure, thereby achieving power reduction. The factor corrects the volume of the circuit and makes the power factor correction circuit simple in structure, thereby reducing the cost. The power factor correction circuit of the power converter of the present invention is coupled to a power converter for adjusting a power factor of the power converter. The power factor correction circuit includes a feedback circuit, an operation circuit and a switching circuit. The feedback circuit is coupled to an output end of the power converter, and generates a feedback signal according to one of the output signals of the power converter, and the operation circuit is coupled to the input end of the power converter and the feedback circuit And receiving an input signal of the power converter and a sensing signal and the feedback signal, the operation circuit generates a multiplication signal according to the input signal and the feedback signal, and generates the signal according to the input signal and a sensing signal. a first reference signal, the operation circuit generates a control signal according to the multiplication signal and the first reference signal, the switching circuit is coupled to the operation circuit, and generates a switch according to the control signal and a second reference signal. A signal for switching one of the power converter switches. Thus, the present invention avoids the use of a divider by a multiplier, so that the power factor correction circuit is simple in structure, thereby reducing the size of the power factor correction circuit and achieving cost reduction. 099132684 Form No. 1010101 Page 5 / 19 pages 0992057216-0 201214938 [Embodiment] · [_] New structure of the ruthenium (4) structure and the effect achieved have a more advanced understanding and understanding, DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT(S) The following is a circuit diagram of a preferred embodiment of the present invention. As shown, the power factor correction circuit 1 of the power converter of the present invention is a surface-to-power converter 2 for adjusting a power factor of the power converter 2, and the power factor correction circuit 丨 includes a voltage feedback circuit. 1〇, -the arithmetic circuit 12 and the -switching circuit 14/ „the feedback circuit 1G is one of the output powers of the power converter 2, and the voltage feedback circuit 1〇 generates a voltage command according to the output signal Vout of one of the power converters 2 The signal Vea, that is, the voltage feedback circuit 10 generates a voltage command signal Vea according to the voltage difference between the output signal v〇ut of the power converter 2 and the reference voltage Vref via a compensation circuit (ie, the voltage loop compensator 100), common compensation The circuit implementation is a Proportional (P) controller, a proportional integral (Proport i ona Bu Integra 1, P 1丨) modulator or a Proportional-Integral-m ff erental (PID) control. The operation circuit 12 is coupled to one of the voltage input terminals of the power converter 2, the current input terminal and the voltage feedback circuit 1〇, and the operation circuit 12 receives a voltage input signal Vin and a voltage converter 2 The current sensing signal I and the voltage command signal Vea, wherein the voltage input signal Vin is an input signal generated by the AC power signal Vac after being rectified by the rectifier circuit 20 of the power converter 2, and the voltage input signal Vin is passed through a first regulator 1 204. The generating signal B is multiplied by the voltage command signal Vea to generate a multiplication signal Iref, and the operation circuit 12 generates a first reference signal Isen according to the input voltage signal Vin and the sensing current signal I, and then the operation circuit 12 further generates the multiplication signal according to the multiplication signal. 099132684 Form No. A0101 Page 6 / Total 19 Page 0992057216-0 201214938 A current loop compensator 124
。如此，本發”藉由運算祕12而避免❹除法器， 使功率因數修正電路i結構更為簡單，進而達到縮小功率 因數修正電路1的體積，並且可達到減少成本的目的。其 I ref與第一參考訊號15611經由一臂 λ \ λ 中，第二參考訊號Ipwm為一鋸齒波訊號。 . ..... 承上所述，本發明之薄算電2息食一第一參考訊 號產生電路120、一第一乘法器122與一電流迴路補償 124。第一參考訊號產生電路120係耦鉍功率轉換器2之輸 入端’並第一參考訊號產生電路120依據電壓輸入訊號 Vin與電流感測訊號I而產生乘法訊號1了^，第一乘法器 122係耦接功率轉換器2之輸入端與電壓回授電路10，並 第一乘法器122相乘電壓命令訊號Vea與電壓輸入訊號 Vin，其中，電壓輪入訊號Vin亦可經過第一放大器1204 ，而使第一乘法器122可相乘電壓命令訊號Vea與輸入訊 號（Vin*Kv)，而產生乘法訊號Iref電流迴路補償器124 耦接第一參考訊號產生電路120與第一乘法器122 ’電流 迴路補償器124係比較第一參考訊號I sen與乘法訊號 Iref ’而產生控制訊號Ic，以傳送至切換電路14。如此 ，本發明之運算電路12僅使用第一乘法器122 ’而未使用 除法器’使功率因數修正電路結構簡单’進而達到縮小 功率因數修正電路的體積’並減少其成本。 上述之第一參考訊號產生電路120包含一第二乘法器 099132684 表單編號A0101 第7頁/共19頁 0992057216-0 201214938 1 200、一第三乘法器1 202、第一調整器1204、一第二調 整器1 206與一低通濾波器1208。第一調整器丨2〇4係用以 調整電壓輸入訊號Vi η之強度，於此實施例中，第—調整 器12 0 4係用以放大/縮小電壓輸入訊號ν i η，並將調整後 之電壓輸入訊號Vin傳送至濾波器1208與第一乘法器 122。此外’第一調整器1204係更產生一訊號B，並將訊 號B傳送至第一乘法器122。第二調整器1206係用以調整 電流感測訊號I之強度’即放大/縮小該電流感測訊號I , 並將調整後之電流感測訊號I傳送至第二乘法器12〇〇。第 二乘法器1200係耗接機率轉換器2之輸入端，並相乘電壓 輸入訊號Vin之平均值C的平方訊號（即(Γ2訊號）與電流 感測訊號I ’而產生第一參考訊號lsen'，第三乘法器 1202係耦接於低通濾波器1208之輸出端，而產生電屋輸 入訊號Vin之平均值C的平方訊號（即(T2訊號），且傳送 電壓輸入訊號Vin之平均值C的平方訊號至第二乘法器 1200。低通濾波器1 208係耦接功率轉換器2之輸入端， 並過濾電壓輸入訊號Vin，而算出電壓輸入訊號Vin的平 均值。 此外’本發明可使用一運算單元12〇3取代第三乘法 器1 202(如第四圖所示），運算單元12〇3係耦接功率轉換 器2之輸入端’並依據一對應表而平方電壓輸入訊號Vin ’且傳送平方後之電壓輸入訊號Vin至第二乘法器1 200 , 於此實施例中，運算單元12〇3係耦接於低通濾波器12〇8 之輸出端’而產生電壓輸入訊號Vin之平均值C的平方訊 號（即C~2訊號），且傳送電壓輸入訊號Vin之平均值c的 平方訊號至第二乘法器12〇〇。 099132684 表單編號A0101 第8頁/共19頁 〇992丨 201214938 請復參閱第三圖，電壓回授電路1〇包含—希 補償器100與一第三調整器102。電壓迴路補償器丨〇〇人 耦接功率轉換器2之輸出端與運算電路12，拍 " “ 此电壓趣路補 償器100比較輸出訊號Vout與一門檻訊號v 1，而產生. In this way, the present invention avoids the erasure of the device by the operation secret 12, and makes the structure of the power factor correction circuit i simpler, thereby reducing the volume of the power factor correction circuit 1 and achieving the purpose of reducing the cost. The first reference signal 15611 is via a arm λ \ λ, and the second reference signal Ipwm is a sawtooth wave signal. ..... According to the above, the thin electrical power 2 of the present invention generates a first reference signal. The circuit 120, a first multiplier 122 and a current loop compensation 124. The first reference signal generating circuit 120 is coupled to the input end of the power converter 2 and the first reference signal generating circuit 120 according to the voltage input signal Vin and current sense The first multiplier 122 is coupled to the input of the power converter 2 and the voltage feedback circuit 10, and the first multiplier 122 is multiplied by the voltage command signal Vea and the voltage input signal Vin. The voltage input signal Vin can also pass through the first amplifier 1204, so that the first multiplier 122 can multiply the voltage command signal Vea and the input signal (Vin*Kv) to generate the multiplication signal Iref current loop compensator 12 The first reference signal generating circuit 120 is coupled to the first multiplier 122 'the current loop compensator 124 to compare the first reference signal I sen with the multiplication signal Iref ' to generate the control signal Ic for transmission to the switching circuit 14. Thus, The arithmetic circuit 12 of the present invention uses only the first multiplier 122' without using the divider 'to make the power factor correction circuit simpler', thereby reducing the volume of the power factor correction circuit and reducing its cost. The first reference signal described above The generating circuit 120 includes a second multiplier 099132684, a form number A0101, a seventh page, a total of 19 pages 0992057216-0 201214938 1 200, a third multiplier 1 202, a first adjuster 1204, a second adjuster 1 206 and a The low-pass filter 1208. The first adjuster 丨2〇4 is used to adjust the intensity of the voltage input signal Vi η. In this embodiment, the first adjuster 12 0 4 is used to amplify/reduce the voltage input signal ν i η, and the adjusted voltage input signal Vin is transmitted to the filter 1208 and the first multiplier 122. In addition, the 'first adjuster 1204 generates a signal B and transmits the signal B to the first multiplication method. 122. The second adjuster 1206 is configured to adjust the intensity of the current sensing signal I, that is, to amplify/reduce the current sensing signal I, and transmit the adjusted current sensing signal I to the second multiplier 12A. The second multiplier 1200 is connected to the input end of the probability converter 2, and multiplies the square signal of the average value C of the voltage input signal Vin (ie, (Γ2 signal) and the current sensing signal I' to generate the first reference signal lsen The third multiplier 1202 is coupled to the output of the low pass filter 1208 to generate a squared signal of the average value C of the electrical input signal Vin (ie, (T2 signal), and the average value of the transmitted voltage input signal Vin The squared signal of C goes to the second multiplier 1200. The low-pass filter 1 208 is coupled to the input of the power converter 2 and filters the voltage input signal Vin to calculate an average value of the voltage input signal Vin. In addition, the present invention can use an arithmetic unit 12〇3 instead of the third multiplier 1 202 (as shown in the fourth figure), and the arithmetic unit 12〇3 is coupled to the input end of the power converter 2 and according to a correspondence table. The squared voltage input signal Vin' and the squared voltage input signal Vin is transmitted to the second multiplier 1 200. In this embodiment, the arithmetic unit 12〇3 is coupled to the output end of the low pass filter 12〇8. A square signal (ie, C~2 signal) of the average value C of the voltage input signal Vin is generated, and a square signal of the average value c of the voltage input signal Vin is transmitted to the second multiplier 12A. 099132684 Form No. A0101 Page 8 of 19 〇992丨 201214938 Please refer to the third figure. The voltage feedback circuit 1A includes a compensator 100 and a third regulator 102. The voltage loop compensator is coupled to the output terminal of the power converter 2 and the arithmetic circuit 12, and the "the voltage circuit compensator 100 compares the output signal Vout with a threshold signal v1 to generate
電壓命令訊號Vea。第三調整器102係耦接於功率轉換$ 之輸出端與電壓迴路補償器100，第三調整器1〇2係用时2 調整功率轉換器2之輸出訊號Vout之強度，於此實施^ ，第三調整器102係放大/縮小功率轉換器2之輪出气號 Vout，並將調整後之輸出訊號Vout傳送至電壓迴路補产 器 100。 本發明之切換電路14可為第二比較器，其輕接運算 電路12與功率轉換器2，並比較嗶算電硌12輪出之控制訊 號Ic與第二參考訊號Ipwm ’而產生切換m號，以切換開 關Q，而達到功率轉換器2之功率因數的修正。Voltage command signal Vea. The third regulator 102 is coupled to the output of the power conversion $ and the voltage loop compensator 100, and the third regulator 1 2 is used to adjust the intensity of the output signal Vout of the power converter 2. The three regulators 102 amplify/reduce the wheel outlet Vout of the power converter 2 and transmit the adjusted output signal Vout to the voltage loop supplement 100. The switching circuit 14 of the present invention may be a second comparator, which is connected to the operation circuit 12 and the power converter 2, and compares the control signal Ic and the second reference signal Ipwm' that are calculated by the power circuit 12 to generate a switching m number. To switch the switch Q to achieve the correction of the power factor of the power converter 2.
由上述可知，由於乘法訊號Iref尊於電麼命令訊 號Vea乘上訊號B，第一參考訊號Isen等於調整後後之電 流感測訊號I乘上訊號C2 ’而電流感測訊號I等於功率轉 換器2之輸入電流I in，當系統穩定時第一參考訊號iSen 等於乘法訊號Iref，所以’功率轉換器2之輪入功率pin 等於電壓輸入電壓Vin乘上輸入電流Iin，即等於電壓輸 入電壓Vin乘上第一參考_訊號Isen除以訊號C2，也就是電 壓輸入電壓Vin乘上訊號B與電壓命令訊號Vea再除以訊號 c2，又，因為訊號β為調整後之電壓輸入電壓Vin ,所以 ，功率轉換器2之輸入功率pin等於電壓輸入電壓Vin的平 方乘上電壓命令訊號Vea，再除以訊號c2，並且平方訊號 C2相當於電壓輸入電壓Vin，或是數倍之電壓輸入電壓 099132684 表單編猇A0101 第9頁/共19頁 0992057216-0 201214938As can be seen from the above, since the multiplication signal Iref is used to command the signal Vea multiplied by the signal B, the first reference signal Isen is equal to the adjusted current sense signal I multiplied by the signal C2' and the current sense signal I is equal to the power converter 2 input current I in, when the system is stable, the first reference signal iSen is equal to the multiplication signal Iref, so 'the power input pin of the power converter 2 is equal to the voltage input voltage Vin multiplied by the input current Iin, which is equal to the voltage input voltage Vin multiplied The first reference_signal Isen is divided by the signal C2, that is, the voltage input voltage Vin is multiplied by the signal B and the voltage command signal Vea and divided by the signal c2, and since the signal β is the adjusted voltage input voltage Vin, the power is The input power pin of the converter 2 is equal to the square of the voltage input voltage Vin multiplied by the voltage command signal Vea, divided by the signal c2, and the square signal C2 is equivalent to the voltage input voltage Vin, or several times the voltage input voltage 099132684 A0101 Page 9 of 19 Page 0992057216-0 201214938
Vin，因此，輸入功率Pin即等於數倍之訊號Vea。如此 ，本發明藉由一乘法器而避免使用除法器，使功率因數 修正電路結構簡單較易實現，進而達到縮小功率因數修 正電路的體積，並可減少成本。 綜上所述，本發明之功率轉換器之功率因數修正電 路係由一回授電路依據功率轉換器之一輸出訊號，產生 一電壓命令訊號，運算電路接收功率轉換器之一電壓輸 入訊號與一電流感測訊號和電壓命令授訊號，並運算電 路依據電壓輸入訊號與電壓命令訊號產生一乘法訊號， 且依據電壓輸入訊號與電流感測訊號產生一第一參考訊 號，之後，運算電路再依據乘法訊號與第一參考訊號而 產生一控制訊號，切換電路依據控制訊號與一第二參考 訊號，而產生一切換訊號，用以切換功率轉換器之一開 關。如此，本發明係藉由乘法器而避免使用除法器，使 功率因數修正電路結構簡單，進而達到縮小功率因數修 正電路的體積，並且可達到減少成本的目的。 本發明係實為一具有新穎性、進步性及可供產業利 用者，應符合我國專利法所規定之專利申請要件無疑， 爰依法提出發明專利申請，祈鈞局早曰賜准專利，至 感為禱。 惟以上所述者，僅為本發明之一較佳實施例而已， 並非用來限定本發明實施之範圍，舉凡依本發明申請專 利範圍所述之形狀、構造、特徵及精神所為之均等變化 與修飾，均應包括於本發明之申請專利範圍内。 【圖式簡單說明】 [0005] 第一圖係為習知技術之功率因數修正電路的電路圖； 099132684 表單編號A0101 第10頁/共19頁 0992057216-0 201214938 第二圖係為第一圖之功率因數修正電路的波形示意圖； 第三圖係為本發明之一較佳實施例之電路圖；以及 第四圖係為本發明之另一較佳實施例之電路圖。 【主要元件符號說明】 [0006] 習知技術：Vin, therefore, the input power Pin is equal to several times the signal Vea. Thus, the present invention avoids the use of a divider by a multiplier, making the power factor correction circuit simple and easy to implement, thereby reducing the size of the power factor correction circuit and reducing the cost. In summary, the power factor correction circuit of the power converter of the present invention generates a voltage command signal by a feedback circuit according to one of the output signals of the power converter, and the operation circuit receives a voltage input signal of the power converter and a a current sensing signal and a voltage command signal, and the operation circuit generates a multiplication signal according to the voltage input signal and the voltage command signal, and generates a first reference signal according to the voltage input signal and the current sensing signal, and then the operation circuit is further multiplied according to the multiplication method. The signal and the first reference signal generate a control signal, and the switching circuit generates a switching signal for switching one of the power converters according to the control signal and the second reference signal. Thus, the present invention avoids the use of a divider by a multiplier, so that the power factor correction circuit has a simple structure, thereby reducing the size of the power factor correction circuit and achieving cost reduction. The invention is a novel, progressive and available for industrial use, and should meet the requirements of the patent application stipulated in the Patent Law of China, 提出 the invention patent application is filed according to law, and the prayer bureau gives the patent as early as possible. For prayer. However, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and the shapes, structures, features, and spirits described in the claims are equally variable. Modifications are intended to be included in the scope of the patent application of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS [0005] The first figure is a circuit diagram of a power factor correction circuit of the prior art; 099132684 Form No. A0101 Page 10 of 19 0992057216-0 201214938 The second figure is the power of the first figure BRIEF DESCRIPTION OF THE DRAWINGS FIG. 3 is a circuit diagram of a preferred embodiment of the present invention; and a fourth diagram is a circuit diagram of another preferred embodiment of the present invention. [Main component symbol description] [0006] Conventional technology:
10’橋式整流器 20’運算電路 22’乘法器 24’除法器 30’電壓放大器 40’前置電路 50’控制電路 本發明： 1 功率因數修正電路10' bridge rectifier 20' operation circuit 22' multiplier 24' divider 30' voltage amplifier 40' pre-circuit 50' control circuit The present invention: 1 Power factor correction circuit
10 電壓回授電路 100 電壓迴路補償器 102 第三調整器 12 運算電路 120 第一參考訊號產生電路 1200 第二乘法器 1 202 第三乘法器 1203 運算單元 1204 第一調整器 1 206 第二調整器 1208 低通濾波器 122 第一乘法器 099132684 表單編號A0101 第11頁/共19頁 0992057216-0 201214938 124 電流迴路補償器 14 切換電路 2 功率轉換器 20 整流電路 099132684 表單編號A0101 第12頁/共19頁 0992057216-010 voltage feedback circuit 100 voltage loop compensator 102 third regulator 12 arithmetic circuit 120 first reference signal generating circuit 1200 second multiplier 1 202 third multiplier 1203 arithmetic unit 1204 first adjuster 1 206 second adjuster 1208 Low Pass Filter 122 First Multiplier 099132684 Form No. A0101 Page 11 / Total 19 Page 0992057216-0 201214938 124 Current Loop Compensator 14 Switching Circuit 2 Power Converter 20 Rectifier Circuit 099132684 Form No. A0101 Page 12 of 19 Page 0992057216-0