TW201212319A - Composition of memory cell with resistance-switching layers - Google Patents

Abstract

A memory device in a 3-D read and write memory includes memory cells. Each memory cell includes a resistance-switching memory element (RSME) in series with a steering element. The RSME has first and second resistance-switching layers on either side of a conductive intermediate layer, and first and second electrodes at either end of the RSME. The first and second resistance-switching layers can both have a bipolar or unipolar switching characteristic. In a set or reset operation of the memory cell, an ionic current flows in the resistance-switching layers, contributing to a switching mechanism. An electron flow, which does not contribute to the switching mechanism, is reduced due to scattering by the conductive intermediate layer, to avoid damage to the steering element. Particular materials and combinations of materials for the different layers of the RSME are provided.

Description

201212319 VI. Description of the invention: [Technical field to which the invention pertains] The technology of the present invention relates to data storage. This application claims US Provisional Patent Application No. 61/356,327, filed on Jun. 18, 2010 ( file number: SAND-01478US0) and US Provisional Patent Application No. 61/467,936, filed on March 25, 2011 ( Archives: SAND-01478US1), the entire contents of each of which are incorporated herein by reference. [Prior Art] Various materials exhibit reversible resistance change or resistance switching behavior. The resistance of the material varies depending on the history of the current passing through the material and/or the voltage across the material. These materials include chalcogenides, carbon polymers, perovskites, and certain metal oxides (MeOx) and metal nitrides (MeN). Specifically, there are metal oxides and nitrides which contain only one metal and exhibit reliable resistance switching behavior. For example, the group includes nickel oxide (NiO), niobium oxide (Nb205), titanium dioxide (Ti02), hafnium oxide (Hf02) 'alumina (A1203), magnesium oxide (MgOx), chromium dioxide (Cr02), Vanadium oxide (VO), boron nitride (BN) and aluminum nitride (A1N), such as Pagnia and Sotnick in "Bistable Switching in Electroformed Metal-Insulator-Metal Device" (Phys. Stat. Sol. (A) 108, 11 As explained in 65 (1988)). A resistance switching layer (RSL), one of the materials, may be formed to be in an initial state, for example, a relatively low resistance state. When a sufficient voltage is applied, the material switches to a stable high resistance state and maintains the stable high resistance even after the voltage is removed. 156917.doc 201212319 state. This resistance switching is reversible so that subsequent application of an appropriate current or voltage can be used to return the RSL to a stable low resistance state, even after the voltage or current is removed. This conversion can be repeated multiple times. For some materials, this initial state is high resistance rather than low resistance. A setting procedure may refer to switching the material from a high resistance to a low resistance, and a reset procedure may refer to switching the material from a low resistance to a high resistance. A resistance switching memory element (RSME) can include an RSL positioned between the first electrode and the second electrode. The use of such reversible resistance-changing materials in non-volatile memory arrays has received considerable attention. For example, one resistance state may correspond to one data "〇" and another resistance state corresponds to a data "1". Some of these materials may have more than two stable resistance states. Moreover, in a memory cell, the RSME can be in series with a steering element, such as one of the diodes, that selectively limits the voltage across the RSME and/or the current through the RSME. For example, the diode can allow current to flow only in one direction along the RSME2 and substantially block one of the currents in the opposite direction. This—the steering element itself is usually not a resistance change material. Rather, the manipulation element allows writing to and/or reading from a memory unit without affecting the state of other memory units in an array. Non-volatile memory having a storage element or unit formed of a resistance change material is known. For example, U.S. Patent Application Publication No. 2006/0250836, the disclosure of which is incorporated herein by reference in its entirety in its entirety in the entire entire entire entire entire entire entire entire entire disclosure 156917.doc 201212319

MeOx or MeN) a rewritable non-volatile memory cell of a diode coupled in series. However, there continues to be a need for techniques that allow the size of the memory cells to be scaled down. [Embodiment] The present invention provides a delta-resonance system comprising a reversible resistivity switching memory element (RSME) having two or more resistance switching layers (RSL). In an exemplary embodiment, the RSME includes one of the first electrodes (E1) in series, a first resistance switching layer (RSL1), an intermediate layer (IL) that is considered to be a scattering layer or a coupling electrode, and a The second rsl (RSL2) and a second electrode (E2). In one method, the RSME has a mirrored configuration 'where the RSME configuration is symmetric on either side of the IL. However, this mirror configuration is not required. Generally, as the size of the RSME-based memory device is scaled down, one drawback is that one of the inrush currents during one of the RSME setting or resetting procedures can damage the operating element associated with one of the RSME series or even hinder extremes. The operation of the memory unit at a reduced size. Also, in general, many RSL-based memory devices require one of the steps to cause the initial insulation properties of the RSL to collapse during that step. This formation step is typically associated with a very short and very high discharge current peak that sets the on-resistance level of the rsl for subsequent switching events. If the on-resistance level is extremely low (e.g., '1 〇〇 kQ to 30 kQ), then the associated switching current is also extremely high and therefore the memory cell will not operate at the very small technology node. A setting or resetting procedure is for a type of RSL and RSME type I56917.doc -6- 201212319 blocking switching operation. To solve this problem, one of the RSELs comprising a separate RSL is provided on either side of the conductivity ratio. In particular, one of the memory cells, including one of the RSMEs provided herein, can limit the inrush current overshoot by actively reducing the operating current. For example, the ring-thin ILT prevents current overshoot and limits current flow, thereby making it easier to generate a large electric field across individual RSLs. As the current is reduced, the likelihood of damaging one of the unit's steering elements is reduced and a thinner steering element can be used, thereby facilitating scaling of the memory device and possibly reducing power consumption. Since an ion current is still allowed, the switching capability of the unit is maintained. The RSME is based on a certain rSl model, which describes several findings, including: an index-based E-field dependence and a measured current system based on one of electron/hole and ion conduction switching current, ion current. An inrush current is not used for the switching mechanism. Specifically, the qualitative model illustrates. (1) a sudden collapse type set current increase; (ϋ) why it is difficult to limit the set state to a high on-resistance state; (iii) the sensitivity of the cycle yield to the setting procedure; Iv) why the reset voltage can be higher than the set voltage; (v) why a higher reset voltage is required for a deeper reset; and (vi) why the reset current is higher for a deeper reset. The inrush current model can also be applied to any other "thin" storage material/ion memory, such as TiSi, CBRAM (conductive bridged RAM). » For one of the MeOx RSLs, these findings also indicate that the electron/hole current does not cause a switching effect. 'And the impact travels in MeOx to deliver heat only to the contacts, and this is different from thicker carbon or phase change materials in which the current is generated in the cell if the memory cell is sufficiently long heat. 156917.doc 201212319 FIG. 1 is a resistor-switching memory unit (RSMC) 100 comprising an RS ME 10 2 coupled between a first conductor ι 6 and a second conductor 108 in series with an operating element 104. One of the embodiments simplifies the perspective. RSME 1〇2 includes RSLs 130 and 135 on either side of a conductive intermediate layer (iL) 133. As mentioned, an RSL has a resistivity that can be reversibly switched between two or more states. For example, an RSL can be fabricated in an initial high resistivity (high resistance) state that can be switched to a low resistivity state when a first voltage and/or current is applied. Applying a second voltage and/or current returns the RSL to a high resistivity state. Alternatively, the RSL can be in an initial low resistance state at the time of manufacture. The RSL is reversibly switched to a high resistance state when a suitable voltage and/or current is applied. When used in a memory unit, each RSL

A resistance state (and one of the RSMEs corresponding to the electrical, resistive state) may represent the binary "0" of the RSME and another resistance state of each RSL (and 'one of the RSMEs corresponding to the resistance state" may represent the binary of the RSME "丨". However, more than two data/resistance states can be used. For example, the operation of a plurality of reversible resistance changing materials and memory cells employing reversible resistance changing materials is set forth in the above-referenced U.S. Patent Application Publication No. 2006/0250836. In one embodiment, the process of switching the RSME from a high resistivity state (eg, representing binary data "0") to a low resistivity state (eg, representing binary data "1") is referred to as setting or forming, and will The procedure for switching the RSME from a low resistivity state to a high resistivity state is called resetting. In other embodiments, the settings and resets and/or data encoding can be reversed. This setting or reset procedure can be performed for a 156917.doc 201212319 memory unit to be programmed to represent the desired state of one of the binary data. In certain embodiments, RSLs 130 and 135 may be formed of a metal oxide (MeOx), an example of which is Hf02. More information on the use of reversible resistance-changing materials to create a memory cell can be found in US 2009/, entitled "Memory Cell That Employs a Selectively Deposited Reversible Resistance Switching Element and Methods of Forming The Same", published on January 1, 2009. Found in 0001343, and the disclosure of which is hereby incorporated by reference in its entirety herein in its entirety, the <RTIgt; Electrode 132 is positioned between RSL 130 and a conductor 108 (e.g., a bit line or word line (control line)). In one embodiment, electrode 132 is made of titanium (Ti) or titanium nitride (TiN). The electrode : 134 is positioned between the RSL 133 and an operating element 104. In one embodiment, electrode 134 is made of titanium nitride (TiN) and acts as a bond and barrier layer. The steering element 104 can be a diode or other suitable steering element that exhibits non-ohmic conduction by selectively limiting the voltage across the RSME 102 and/or the current through the RSME 102. In one method, the steering element allows current to flow through the RSME in only one direction, such as from a bit line to a word line. In another method, a steering element (e.g., a feedthrough diode) allows current to flow through the RSME in either direction. The steering element acts as a one-way valve to allow current to conduct more easily in one direction than the other. A critical "on" current below one of the forward directions. 156917.doc 201212319 Pressure 'The diode conducts very little or no current. By using an appropriate biasing scheme, when a different rSME is selected for stylization, the voltage across the adjacent RSME does not exceed the diode's winter f-pass voltage when applied in the forward direction or when applied in the opposite direction. When the reverse breakdown voltage is not exceeded, the adjacent RSME diodes can be used to electrically isolate the adjacent RSMEs and thus prevent inadvertent resistance switching. Specifically, in a large cross-point RSME array, when a relatively large voltage or current is required, there is an RSME that shares the top or bottom conductor (eg, 'word line or bit line') with the rSME to be addressed. The voltage or current thus causes a risk of undesired resistance switching. Excessive leakage current across unselected cells can also be a problem depending on the biasing scheme used. This danger can be overcome by using diodes or other operating elements. In this way, the memory unit 1 can be used as part of a two-dimensional or three-dimensional memory array and can write data to the memory unit 100 under a barrier that does not affect the state of other memory cells in the array. / or read data from the memory unit 100. The steering element 104 can comprise any suitable diode, such as a vertical polycrystalline pn or a pin diode (or one of the diodes is located above the Ρ region or one of the diodes is located) The upper part of the η area refers to the lower part. Alternatively, even a through diode or a Zener diode can be used, which can operate in both directions. The steering element can be in the shape of a vertical column together with the RSME. In other methods, portions of rsmE2 are laterally configured with each other, as discussed further below. In some embodiments, the motor element 104 can be formed from a polycrystalline semiconductor material (e.g., polysilicon, a polysilicon-germanium alloy, polysilicon or any other suitable material). For example, the steering element 104 can include a heavily doped n+ polysilicon region 142, a lightly doped or an intrinsic (unintentionally doped) polysilicon region 144 over the n+ polysilicon region 142, and a heavily doped one over the intrinsic region 144. P+ polysilicon region 146. In some embodiments, a thin (eg, hundreds of angstroms or less) tantalum and/or tantalum-niobium alloy layer (not shown) may be formed on the n+ polysilicon region 142 (when a tantalum-niobium alloy layer is used) Having about 1% or more of ruthenium) to prevent and/or reduce migration of dopants from the n+ polysilicon region 142 to the intrinsic region 144 (for example, 5) as described under the heading "Deposited Semiconductor Structure To Minimize N-Type" The disclosure of U.S. Patent Application Publication No. 2006/0087005, the entire disclosure of which is incorporated herein by reference. It should be understood that the position of the ^ and P+ regions can be reversed. When the manipulating element 104 is fabricated from deposited germanium (e.g., amorphous or polycrystalline), a layer of wonderful layers can be formed on a pole body such that the deposited stone is in a low resistivity state at the time of manufacture. This low resistivity state allows for easier programming of the memory cell' because a large voltage is not required to switch the deposition to a low resistivity state. As described in "Memory Cell Comprising a Semiconductor Junction Diode Crystallized Adjacent to a Silicide", U.S. Patent No. 7,176,064, the disclosure of which is incorporated herein by reference. During the reaction with sedimentation, a telluride layer is formed. The lattice spacing of Shi Xihua and Shi Xihua's lead is close to the lattice spacing of 矽 and these bismuth layers appear to act as "crystal templates" or "seeds" adjacent to the sedimentary crystallization during deposition crystallization ( For example, the lithium layer enhances the crystalline structure of the ruthenium dioxide during annealing 156917.doc 201212319). This provides a lower resistivity. Similar results can be achieved for bismuth-tellurium alloys and/or ruthenium diodes. Conductors 106 and 108 comprise any suitable electrically conductive material, such as tungsten, any suitable metal, heavily doped semiconductor material, a conductive germanide, a conductive dopant-telluride, a conductive germanide or the like. In the illustrated embodiment, conductors 106 and 108 are rail shaped and extend in different directions (e.g., substantially perpendicular to each other). Other conductor shapes and/or configurations can be used. In some embodiments, barrier layers, adhesive layers, anti-reflective coatings, and/or the like (not shown) can be used with conductors 106 and 1 to improve device performance and/or aid device fabrication. Conductor 1〇6 can be a word line and conductor 1〇8 can be a bit line, or vice versa. Although the RSME 102 is shown in Figure 1 as being positioned above the steering element 1〇4, it will be understood that in alternative embodiments, the rSME 102 can also be positioned below the operating 7L member 104. Various other configurations are also possible. —RSL exhibits a single pole or bipolar resistance switching characteristic β with respect to a single pole resistance switching characteristic, and the voltages used to set and reset the program are of the same polarity, that is, both positive or negative. In contrast, with regard to a bipolar resistance switching characteristic, voltages of opposite polarity are used for setting and resetting procedures. Specifically, the voltage used to set the program can be positive, and the voltage used to reset the program is negative, or the voltage used to set the program can be negative, and the voltage used to reset the program is positive. . Figure 2 is a simplified perspective view of one of the portions of the first memory level 114 formed by a plurality of memory cells 1 of Figure 1. For the sake of simplicity, the RSME 102, the operating element 104 and the barrier layer 113 are shown separately from 156917.doc 201212319. The memory array 114 is an "interleaved" array comprising a plurality of bit lines (second conductors 108) and word lines (first conductors 106) to which a plurality of memory cells are coupled (as shown in the figure). Show). Other memory array configurations can be used, such as multiple memory levels. 2 is a simplified perspective view of one of a portion of a monolithic three-dimensional array 116 comprising a first memory level 118 positioned below a second memory level 12〇. In the embodiment of FIG. 3, each of the memory levels 126 and 120 includes a plurality of memory cells 100 in a cross-point array. It will be appreciated that additional layers (e.g., an inter-layer dielectric) may be present between the first memory level 118 and the second memory level 120, but are not shown in Figure 2 for simplicity. Other memory array configurations can be used, such as the use of additional memory levels. In the embodiment of FIG. 2, all of the diodes can be "pointed" in the same direction (eg, depending on whether a p_i_n diode having a p-doped region at the bottom or top of the diode is used, up or down) , thus simplifying the manufacture of the diode. In some embodiments, the memory levels can be formed as set forth in U.S. Patent No. 6,952,03, entitled "High-Density Three-Dimensional Memory Cell", which is incorporated herein by reference. For example, a first memory level upper conductor can be used to position one of the second memory level lower conductors above the first memory level, as shown in Figure 2C. In such embodiments, the dipoles adjacent to the memory level are preferably pointed in the opposite direction as in U.S. Patent 7,586,773, entitled "Large Array Of Upward Pointing PIN Diodes Having Large And Uniform 156917.doc 13 · 201212319 CUrrentj. As stated, the patent is incorporated herein by reference. For example, the diode of the first memory level ι 8 may be as indicated by the arrow A1 (eg, where the p region is located at The second body of the second memory layer 12' can be referred to as the lower diode as indicated by the arrow A2 (eg, where the n region is at the bottom of the diode), or vice versa. A monolithic three-dimensional memory array is one in which a plurality of memory levels are formed on a single substrate (eg, a wafer) without an intervening substrate. Several layers forming a memory level are directly deposited or grown in one Or three layers of existing tiers. In contrast, U.S. Patent No. 5,915,167 to Leedy, "Three Dimensional Structure"

"Memory" has been constructed by forming a plurality of memory levels on a separate substrate and bonding the memory levels to each other up and down. The patent is incorporated herein by reference. The substrates may be thinned or removed from the memory levels prior to bonding, but since the memory levels are initially formed over a separate substrate, such memory is not a true monolithic three dimensional memory array. According to the disclosed configuration, the above examples show a memory cell in the shape of a cylinder or a cylinder and a conductor in the shape of a track. However, the techniques described herein are not limited to any one particular structure of a memory unit. Other structures can also be used to form the memory unit containing the RSME. For example, 'US Patent Nos. 6,952,043, 6,951,780, 6,034,882, 6, 420, 215, 6, 525, 953, and 7, 081, 377, each of each of each of each of each of each of each of each of each of An example of the 201212319 structure. In addition, other types of memory cells can be used with the techniques described herein. 3 is a block diagram showing one example of a memory system 300 that can implement the techniques set forth herein. The memory system 3 includes an array of memory that can be one of two or three dimensional memory cell arrays as set forth above. In one embodiment, memory array 302 is a monolithic three dimensional memory array. The array terminal lines of the memory array 302 include various word line layers organized into columns and various bit line layers organized into rows. However, other orientations may be implemented. The memory system 300 includes a column control circuit 320 having an output 308 coupled to respective word lines of the delta memory array 302. Column control circuit 320 receives a group of one of a plurality of column address signals and one or more various control signals from system control logic circuit 330 and may typically include, for example, column decoder 322, array terminal driver 324, and block selection circuit. Circuitry 326 is used for both reading and stylizing (eg, 'set and reset') operations. The memory system 3A also includes a row control circuit 310 having input/output 306 coupled to respective bit lines of the memory array 3〇2. The row control circuit 306 receives from the system control logic 330 a group of one of the row address k numbers and one or more various control signals, and typically may include, for example, a row decoder 3 12, an array terminal receiver or a driver 3 14 The circuit of the block selection circuit 316 includes a sense amplifier 318 and a 1/(;) multiplexer ~ capture/write circuit. System control logic 33 receives data and data from a host and provides output data to the host. In other embodiments, system control logic 330 receives data and commands from a separate controller circuit and provides output data to the controller circuit, wherein the controller circuit communicates with the host 1569l7.doc •15-201212319. Control logic 330 may include one or more state machines, registers, and other control logic for controlling the operation of memory system 300. For example, write circuit 46A, read circuit 461, which is discussed further below, may be provided. And clamp control circuit 464. In one embodiment, all of the components illustrated in Figure 3 are configured on a single integrated circuit. For example, system control logic 33, row control circuit 310, and column control The circuit 320 can be formed on a surface of a substrate, and a memory array 3〇2 of a single-dimensional two-dimensional memory array is formed on the substrate (and thus, in the system control logic 33, the row control circuit 31) The column control circuit 320 is above. In some cases, a portion of the control circuit can be formed on the same layer as some of the layers of the memory array. The integrated circuit typically subdivides the array into a number of sub-arrays or blocks. The blocks can be further grouped together into a cell containing, for example, 16, 32 or a different number of blocks, as is commonly used, a sub- An array is a group of connected memory cells having connected word lines and bit lines that are typically not blocked by decoders, drivers, sense amplifiers, and input/output circuits. This is done for a variety of reasons. The signal delay (ie, RC delay) that traverses the lines down due to the resistance and capacitance of the word lines and bit lines can be significant in a large array. By using a larger array Subdividing into a smaller sub-array group to reduce the length of each word line and/or each bit line to reduce such RC delays. As another example, associated with accessing a memory cell group The upper limit of the number of memory cells that a power controllable can simultaneously access during a given memory cycle. Therefore, a large memory array is usually subdivided into smaller sub-arrays to drop 156917.doc -16 - 201212319 low simultaneous access Remember The number of body units. However, for ease of explanation, an array that is synonymous with a sub-array can also be used to refer to connected word lines and bits that are typically not blocked by decoders, drivers, sense amplifiers, and input/output circuits. One of the lines is connected to a group of memory cells. An integrated circuit can include one or more memory arrays. As described above, two or two can be switched by reversibly switching each of the RSLs of the RSME 102. The RSME 102 is reversibly switched between more than one state. For example, the RSME can be in an initial high resistivity state during manufacture, and the RSME can be switched to a low resistivity when a first voltage and/or current is applied. State. Applying a second voltage and/or current returns the RSME to a high resistivity state. Memory system 300 can be used with any of the RSMEs described herein. Figure 4A is a graph of voltage versus current for an exemplary embodiment of a monopole RSL. The X-axis shows an absolute value of the voltage, the y-axis shows the current and the lines are adjusted to meet at the origin of the graph. In the setup procedure, line 404 represents the I-V characteristic of RSL when in the high resistivity reset state, and line 406 represents one transition from the Vset down to the low resistivity set state. In the reset procedure, line 400 represents the I-V characteristic of RSL when in the low resistivity setting state and line 402 represents one transition from the Vreset to the high resistivity reset state. This example shows a unipolar mode of operation in which the polarity of the voltage is the same for both the set and reset switches. To determine the state of the RSL, a voltage can be applied across the RSL and the resulting current can be measured. A higher or lower measured current indicates that the RSL is in a low or high resistivity state, respectively. In some cases, the high resistivity state is substantially high in the low resistivity state, such as two or three orders of magnitude (100 to 1,000) times higher than the low resistivity state. Note that other variations of RSL with one of the different I-V characteristics can also be used with the techniques herein. When in the reset state, the RSME exhibits a resistive characteristic as indicated by line 404 in response to an applied voltage between 0 and Vset. However, when in the set state, the RSME exhibits a resistive characteristic as indicated by line 400 in response to an applied voltage between 0 and Vreset, where Vreset < Vset. Thus, depending on the resistance state of the RSME, the RSME thus exhibits different resistance characteristics in response to the same voltage in the same voltage range (e.g., between 0 and Vreset). In a read operation, a fixed voltage Vread < Vreset is applied in response to whether the sensed current is lb in the set state or the reset state. The state of the RSL or RSME can thus be sensed by identifying at least one point of the I-V characteristic of an RSL or RSME. In one approach, the RSME can include a plurality of RSLs each exhibiting substantially similar unipolar switching characteristics.

Figure 4B is a graph showing one of the different I-V characteristics of two exemplary unipolar RSLs. For two or more unipolar RSLs, the IV (current-voltage) characteristics may be substantially the same such that, for example, 1 increases with V at a common rate, and sets and/or resets the level Can be substantially the same. Alternatively, the I-V characteristics of the RSL may be different such that, for example, for one of the RSLs, the V may be increased or set faster and/or the level may be reset differently. In this example, "A" represents a first type of RSL and "B" represents a second type of RSL, wherein the RSLs have different unipolar resistance switching characteristics. X 156917.doc •18- 201212319 The axis shows the voltage (V) and the y-axis shows the current (I). The type "A" RSL' lines 400, 402, 404, and 406 are the same as in Fig. 4A. Also for type "A" RSL, VsetA sets the voltage, VresetA resets the voltage 'IresetA' resets the current and Iset_limitA sets the current limit. For type "B" RSL, lines 420, 422, 424, and 426 correspond to lines 400, 402, 404, and 406, respectively. Also for type "B" RSL, VsetB sets the voltage, VresetB resets the voltage, IresetB resets the current, and Iset_limitB sets the current limit. In the method shown here, 'VsetA>VsetB, VresetA>VresetB, IresetA>IresetB and Iset_limitA>Iset_limitB, but this is only an example and other alternative relationships can be applied. When two or more RSLs are in the same RSME, the switching characteristics of the RSME will be a function of the switching characteristics of each of the RSLs. During a setup procedure, for example, if the voltage is equally divided across each RSL, the type "B" RSL can be switched before the type "A" RSL as V increases. Similarly, during a reset procedure, for example, assuming that the same voltage is applied in each RSL, the type "B" RSL can be switched before the type "A" RSL as V increases. Alternatively, the type "A" and "B" RSLs may have different I-V characteristics of opposite polarities. For example, 'set VsetA> 0 V and VresetA> 0 V, and VsetB < 0 V and VresetB < 0 V. As an example, the characteristics of type "A" RSL may be as described in Figure 4A, and the characteristics of type "B" RSL may be as described in Figure 4C below. In theory, one RSL in an RSME can also have a unipolar characteristic and the other RSL in the RSME has a bipolar characteristic. However, using only one of all RSLs in an RSME 156917.doc -19- 201212319 switching characteristics (unipolar or bipolar) allows for a simplified control scheme. In some cases, one of the RSMEs reads the data state of one of the RSLs. For example, in the case where the first RSL is in a low resistance state and a second RSL is in a high resistance state, assuming that the high resistance state is several orders of magnitude higher than the low resistance state, a read operation will be substantially undetectable. Current. That is, the resistance of the RSME equal to the sum of the resistances of each RSL will be extremely high, so the current will be extremely low or substantially zero. A read operation can switch the second RSL to a low resistance state such that the resistance of the RSME is low and the current through it is relatively high and detectable " after switching the second RSL back to the high resistance state Then, you can perform a writeback operation. When a voltage is applied across the electrodes of an RSME, the voltage is divided proportionally across each RSL based on the resistance of each RSL. When the first RSL is in a low resistance state and the second RSL is in a high resistance state, the first RSL transfers the potential at the electrode to IL such that substantially all voltages are applied across the second RSL. If this voltage is of appropriate magnitude and polarity, it will switch the second RSL. In addition, an RSL can be used as a material for operation as a single or bipolar device, for example, in "Coexistence of the bipolar and unipolar resistive switching behaviours in Au/SrTi03/Pt cells" by Sun et al. (March 10, 2011)曰, J. Phys. D: Appl. Phys. 44, 125404), which is incorporated herein by reference. 4C is a graph showing one of the I-V characteristics of another exemplary monopolar RSL. Compared to the characteristics of Figure 4A, a negative voltage is used during the setup and reset procedure to replace the positive voltage with 156917.doc -20-201212319. In the setup procedure, line 434 represents the I-V characteristic of RSL when in the high resistivity reset state, and line 436 represents one transition from the Vset down to the low resistivity set state. In the reset procedure, line 430 represents the I-V characteristic of RSL when in the low resistivity setting state, and line 432 represents one transition from the Vreset to the high resistivity reset state. Vread, Vreset, Vset, and Vf are all negative voltages. In a read operation, a fixed voltage Vread>Vreset can be applied in response to the lb of the measured current system setting state or the reset state. 4D is a graph showing one of the I-V characteristics of an exemplary bipolar RSL. Here, the opposite polarity voltage is used to set and reset the program. In addition, a positive voltage is used to set the program and a negative voltage is used to reset the program. In this bipolar RSL, a setting procedure occurs when a positive voltage is applied and a reset procedure occurs when a negative voltage is applied. In the setup procedure, line 444 represents the I-V characteristic of RSL when in the high resistivity reset state, and line 446 represents one transition from the Vset down to the low resistivity set state. In the reset procedure, line 440 represents the I-V characteristic of RSL when in the low resistivity setting state, and line 442 represents one transition from the Vreset to the high resistivity reset state. Vset and Vf are positive voltages and Vreset is a negative voltage. 4E is a graph showing one of the I-V characteristics of another exemplary bipolar RSL. In this bipolar RSL, a reset procedure occurs when a positive voltage is applied and a setting procedure occurs when a negative voltage is applied. In the setup procedure, line 454 represents the I-V characteristic of RSL when in the high resistivity reset state, and line 456 represents one transition from the Vset down to the low resistivity set state. In the reset procedure, line 450 represents the Ι-V characteristic of RSL when in the low resistivity setting state, and 156917.doc •21 - 201212319 line 452 represents one transition from Vreset to high resistivity reset state ^Vset and Vf is a positive voltage and Vreset is a negative power. Although the lreset level in Figures 4D and 4C is higher than the iset level, it should be emphasized that it can be reversed. This means that for the opposite polarity, the Iset level in Figure 4D and Figure 4C can be higher than the lreset level. Figure 5 illustrates an embodiment of a circuit for reading a state of a memory cell. A portion of a memory array includes memory cells 55A, 552, 554, and 556. The figure shows two of the many bit lines and two of the many word lines. Bit line 559 is coupled to cells 550 and 554, and bit line 557 is coupled to cells 552 and 556. For example, bit line 559 selects a location line and can be at 2 V. For example, bit line 557 is an unselected location line and can be grounded. For example, word line 547 is the selected word line and can be at 〇 V. For example, word line 549 is the unselected word line and can be at 2v. One of the read circuits for one of the bit lines 559 is shown as being connected to the bit line via transistor 558, The transistor is controlled by a gate voltage supplied by the row de-energizer to select or deselect the corresponding bit line. The transistor 558 connects the bit line to a data bus 563. Write circuit 560, which is part of system control logic 330, is coupled to the data bus. Transistor 562 is coupled to the data bus and operates as a home device controlled by clamp control circuit 564, which is part of system control logic 33. The transistor 562 is also coupled to a sense amplifier 566 that includes a data latch 568. The output of sense amplifier 566 is coupled to a data wheel output terminal (to system control logic 330, a controller, and/or a host). Write circuit 560 is also coupled to sense amplifier 566 and data latch 568. 156917.doc •22· 201212319 When attempting to read the state of RSME, first bias all word lines with Vread (for example, approximately 2 v) and place all bit lines at ground. Then pull the selected word line to ground. For example, this discussion will assume that the selection memory unit 550 performs a read i-transmission data bus (by conducting a conductive crystal 558) and a bin device (the transistor 562' receives a ~2 V+Vth (transistor 562). Threshold voltage)) Pull one or more selected positioning elements 559 to Vread. The gate of the home device is higher than Vread but is controlled to keep the bit line close to Vread. In one method, a current is pulled from a sense node of the sense amplifier through the selected memory cell 550 through the transistor 562. The sense node can receive a high resistivity state current and a low resistivity state. A reference current between the currents. The sense node moves in response to a current difference between the cell current and the reference current. The sense amplifier 566 generates a data output signal by comparing the sensed voltage with a reference read voltage. If the memory cell current is greater than the reference current, the memory cell is in a low resistivity state and the voltage at the sense node will be lower than the reference voltage. If the reciprocal cell current is less than the reference current, the memory cell is in a high resistivity state and the voltage at the sense node will be higher than the reference voltage. The output data signal from sense amplifier 566 is latched into data latch 568. Referring again to Figure 4A, for example, when in a high resistivity state, if a voltage Vset and a sufficient current are applied, the RSL will be set to a low resistivity state. Line 404 shows the behavior when Vset is applied. The voltage will remain fairly constant and the current will increase towards Iset by a limit. At some point, rsl will be set and the device behavior will be based on line 406. Note that the first time you set rsl, you need to form a voltage) to set the device. After that, the second device is set to 156917.doc •23·201212319. The formation voltage Vf can be greater than Vset in absolute magnitude. » When in the low resistivity state (line 400), rSl will be reset to the high resistivity state if vsset and sufficient current (Ireset) are applied. Line 4〇〇 shows the behavior when Vreset is applied. At some point, the RSL will be reset and the device behavior will be based on line 402. In one embodiment, 'Vset is about 7 V, Vreset is about 9 V, Iset_limit is about 1 〇 μΑ and Ireset can be as low as 1 〇〇 μΑ. These voltages and currents are suitable for the circuit of Figure 5 in which an RSME is connected to a diode. 6A through 6 can be, for example, a cross-sectional view of a vertical or horizontal plane along an RSMEi. Figure 6A illustrates an exemplary memory unit having an RSME and one of the steering elements (SE) located below the RSME. This memory unit can have various configurations. A configuration is a stacked configuration in which each type of material is provided in a layer and each layer is positioned below the layer above it and typically has a similar cross-sectional area. In another possible configuration, one or more layers may be configured end-to-end with one or more other layers (see Figures 6F-6J). Note that in these figures, any two layers or materials that are adjacent to each other may be in contact with each other. However, this is not required unless otherwise stated, and any two layers or materials depicted as being adjacent to each other may be separated by one or a plurality of other layers of material that are not depicted. Further, in some cases, a material may be formed as a by-product of fabrication, for example, one of the Si?x layers formed on a Si layer, which is not necessarily shown in the drawing. In addition, several variations of the described embodiments are possible. For example, the order of the layers in each embodiment can be reversed such that, for example, the word line is on top and the 156917.doc -24 - 201212319 bit line is on the bottom. One or more intermediate layers may be provided between each of the illustrated layers. In addition, the position of the steering element can be varied such that it lies above or below other layers that comprise the RSL. The orientation of the layers can be modified from vertical to horizontal or any other orientation. Multiple layers or portions that may form a common conductive path are considered to be connected in series. The memory cell comprises a bit line contact (BLC) material such as W or NiSi. The bit line contact material is connected to a bit line of a memory device. The bit line is a type of control line such that the BLC is also tied to one of the first - control lines. After the BLC in a series path is, for example, one of the first adhesion layers (AL1) of TiN, which helps the bLC to adhere to the RSME and act as a barrier. A TiN layer can be deposited by any conventional method such as sputtering. An operating element (SE)', such as a diode, is placed after rSN1e in the series path. The steering element allows a signal (eg, a voltage or current) to be selectively applied to one or more memory cells via word lines or bit lines to individually control the cells to, for example, by switching their RSMe Change the status of its individual data. The resistance switching behavior of RSME is not dependent on SE. The SE itself can have a resistance switching behavior; however, this behavior will not be dependent on the resistance switching behavior of the RSME. A second adhesive layer (AL2), such as TiN, is placed after the SE in the series path. After the AL2 in the series path is, for example, a W or NiSi word line contact (WLC) material that is connected to a word line of a memory device. The word line is a type of control line such that the WLC is also tied to one of the second control lines. The depicted portions of the memory cells are arranged in series as such. 1569I7.doc • 25-201212319 Figure 6B illustrates an alternative configuration with one of the rsME memory cells 'where the steering element (SE) is located above the RSME. It is also possible to reverse the order of the other layers from top to bottom, from bottom to top. 6C illustrates an exemplary embodiment of the RSME of FIG. 6A as a mirrored resistive switch (MRS) in a vertical stack. The RSME includes a first electrode (E1) (which is a top electrode in some configurations), a first resistance switching layer (RSL1), and a conductive intermediate layer (Jiang) that acts as a scattering layer, coupled electrode Or face layer). The RSME also includes a second rsl (RSL2) and a second electrode (EL2). The second electrode is a bottom electrode in some configurations. For example, such RSLs may be reversible RSLs. A reversible RSL can switch from one state to another and switch back to that state. The IL is electrically connected between E1 and E2 and electrically connected in series with E1 and E2. The rsli is electrically connected between E1 and IL and in series with £1 and specific electricity. RSL2 is electrically placed between E2 and IL and electrically connected in series with E2 and IL. "Electrically located" or similar words may mean in a conductive path. For example, the IL can be electrically located between E1 and E2 and physically located or not between £1 and £2. For example, s ' can form an RSME by connecting two bipolar memristor (memory_resistor) elements in anti-series into a mirrored resistance switch (MRS). A memristor is a passive two-terminal circuit component in which the resistance varies according to the current through the device and the history of the voltage across the device. The MRS can be made of a first memristor element comprising, for example, an n-type ElEl, RSL1 (which can be a transition metal oxide such as hafnium oxide (Hf02) or nitrogen oxides HfSiON) and an IL (which can be 156917.doc •26·201212319 one of the chemical reactions with oxygen can oxidize the electrode (eg TiN)). The RSME comprises a second memristor element made of the same (or different) material but in reverse order, the second memristor element sharing the oxidizable electrode of the IL. Moreover, in one method, both the first memristor element and the second memristor 70 can have bipolar or monopolar I-V (current-voltage) characteristics. In the other method, one of the memristor elements has a unipolar characteristic and the other has a bipolar characteristic. By combining two memristor elements into one RSME, the RSME has one of the Ι-ν characteristics of the memristor element superimposed on one of the IV characteristics but with the RSME* being lower than the individual memristor elements Additional benefits of operation at multiple currents. More generally, 'RSME will have the characteristics of RSL - superimposing one of the I-V characteristics but enabling operation at low currents. The IL acts as a scattering layer by scattering electrons from the RSL into the germanium thereby slowing down the flow of electrons in one of the switching mechanisms to avoid damaging an operating element. Further, the 'IL acts as a coupling electrode or layer that is capacitively coupled to one of the voltages of the RSME by setting the potential of E1 & E2. Through this scatter 'IL' provides a resistor that reduces one of the peak currents during a set or reset procedure while achieving a low current operation. It is believed that this current limiting operation is derived from two aspects of the IL layer. First, the hot electrons are excellently scattered in the IL layer by an electron-electron interaction. Second, one of the rsl initially collapses and delivers an excess charge q to the ratio, and the voltage applied across the RSL effectively reduces V=q/C, where the c-line IL layer faces the electrode E. ', 1 and E2's electricity valley. At the same time 'a higher voltage is now at the second team' to induce a collapse of the second RSL. Since the amount of charge q available is limited to 156917.doc -27· 201212319, the current that can flow here is also extremely limited. In this way, the RSME achieves operation of the memory cell at low currents. It is believed that this resistance is based on IL scattering electrons and produces an extremely effective negative feedback to the applied bias voltage to form the ability to allow small conductive filaments to switch at low currents. In the absence of IL, when a voltage is applied, one of the filaments with a very low resistance will be formed, resulting in a high current peak in the memory cell (due to the relationship I=V/R) and the required switching current is also Will be extremely high. The RSME has a mirrored configuration relative to one of the ILs, since a sequence of rsl and one of the electrodes extends on either side of the IL. A mirrored configuration can also use the same material for the RSL and electrodes. The combination of El, RSL1 and IL forms a first memristor (memory-resistor) component, and the combination of E2, RSL2 and IL forms a second memristor component. The two memristor elements can be connected in series or in series to form a mirrored resistance switch (MRS) bipolar memristor element. In use, when a voltage is applied across E1 and E2, an electric field (E) is generated. 'The electric field is a voltage e il that is divided by the distance between e 1 and E 2 . 'This means that it is not caused by a voltage / The current signal is directly driven but can be electrically gated to directly drive one or more of the other electrodes (eg, Ε1 and/or Ε2) from a voltage/current signal. Due to capacitive fit, a portion of the voltage between Ε1 and Ε2 will be imposed from Ε1 to the light-to-layer layer and across RSL1, while another portion of the voltage between El and E2 will be imposed on the self-coupling layer and cross RSL2^ divides the voltage proportionally across each RSL based on the resistance of each RSL. In addition, the first memristor may have a first IV characteristic, and the second memristor 1569l7.doc • 28·201212319 has a second Ι-V characteristic such that the total characteristic of the memory cell is the first memristor The superimposing of one of the _v characteristics of the second memristor, but with the memory ## will have the added benefit of operating at a much lower current than the individual, hidden resistor elements. In one method, the first memristor and the second memristor have different "V characteristics, but have the same polarity. In the other method, the first memristor and the second memristor have opposite IV characteristics. Polarity. Figures 4A through 4E previously discussed provide an example of an RSL; [·v characteristics. Components of the RSME can be provided in a number of possible configurations as described in further detail below. Example materials for E1 include n+ Si (polysilicon) ), p+ Si (polycrystalline), TiN, TiSix, TiAIN, TiAl, W, WN, WSix, Co, CoSi, p+ Si, Ni, and NiSi. Exemplary materials for rsli and RSL2 include, for example, Me〇x And MeN metal materials. However, non-metallic materials can also be used, as discussed in some embodiments herein. The scales and scales are of the same type or different types. An RSL can also be a phase change. Unit, carbon-based, carbon nanotube-based, nano-ion memory, conductive bridge or a unit that changes its phase, spin, magnetic component, etc. RSL can have a range of ( Ω to 10 Μ Ω or More) One of the on-resistance (conductive state resistance). This and the programmable metal In contrast to a cell (PMC) (eg, a conductive bridge or CBRAM), the programmable metallization cell forms a quantum dot contact and has a much lower resistance of about 25 ΚΩ or less. This higher resistance provides a low current operation. And better scalability. Example materials for E2 include n+ si, n+ SiC, p+ SiC, and p+

Si (polysilicon), TiN, TiAIN, TiAl, w, WN Co, CoSi, p+

Si, Ni and NiSi. Specific material combinations in different layers may be advantageous 156917.doc -29- 201212319. The various configurations of β C·, . ' for 1L are discussed in further detail below, including TiN, TiN, Zr, La, Υ, Τι, ΤιΑΙΝ, TixNy, TiAl alloy, and p+ SiC. Thus, il may be an oxidizable material (eg, TiN, Ab Zr, La, γ 'Ti) or a non-oxidizable material (eg, TiA1N, TixNy, TiAl alloy, and carbon (including, for example, graphene, amorphous carbon, carbon) Made of nanotubes, carbon with different crystal structures and p+ SiC). Typically, the same material of £1 and £2 can be used for the river layer. In some cases, one or more oxide layers are intentionally or unintentionally formed as a by-product of the deposition and formation steps. For example, Sie or TiN can be oxidized by depositing MeOx on top of Si or other proposed metal can be oxidized on one side by Me〇x deposition and can be passed through the interface by 1^(^ and TiN One of the interface reactions is oxidized. As mentioned, El, E2, and IL are made of a conductive material. A conductive material may be characterized by its conductivity σ = 1 / ρ or its reciprocal, and its reciprocal resistivity P = E/J. Measure the conductivity per metre (s/m) of Siemens and measure the resistivity in ohm-meter (ω_ m) or Ω-cm. The magnitude of the electric field in volts/v is the system The magnitude of the current density in A/m2. For an insulator, p > 1 〇 8 or σ < 10-8 S/cm. For a semiconductor, 1 〇 · 3 icm < ρ < 1 〇 8 Ω. 103 S/cm >σ>1〇-8 S/cm. For a conductor, 1〇·3 Q_cm > p or 103 S/cm < σ. A semiconductor can be distinguished from a conductor in that a semiconductor is usually It is formed by doping an insulator into a p-type or n-type semiconductor, and a conductor does not rely on doping. A semiconductor is distinguished from a conductor in that a semiconductor allows current to be based on the polarity of an applied voltage. Flow so that current can flow strongly in one direction and not in the opposite direction. A semiconductor 156917.doc •30· 201212319 allows a forward current to flow along its direction depending on whether it is a p-type or an n-type semiconductor. In contrast, a conductor allows current to flow equally well in either direction. A conductive material is meant to comprise a semiconductor (semiconducting material) and a conductor. A conductor may also be referred to as a conductive material. A conductor has a higher than one One conductivity of a semiconductor. Note that RSME does not rely on a high bandgap three-layer stack (a relatively high bandgap material is located between several layers of a relatively low bandgap material), which is capable of receiving a coupling voltage. An electrically conductive material. Figure 6D illustrates an exemplary embodiment of the RSME of Figure 6A using a plurality of different types of IL between RSLs. Using a plurality of adjacent intermediate layers, including a first IL of type "1" ( IL1) and one of the types "2" second:: L(IL2). One advantage of this embodiment is that the ILs can have different scattering properties and different types of work functions to provide an additional measure of the performance of the rSME. can In addition, the use of multiple identical or different types of IL increases the scattering/resistance in the path, thereby reducing the current due to I=v/R. Multiple adjacent ILs can increase the scattering, as can be a thicker single IL. However, a thicker ratio presents the challenge of scaling up, that is, if the stack height is increased, the column-etch aspect ratio is increased. Therefore, manufacturing processes such as etching, cleaning, and gap filling become extremely challenging. Preferably, there may be two (or more) adjacent (or non-adjacent) thinner ILs (or similar or dissimilar properties/materials) in place of a thicker IL. For example, two ratios of 5 nm in thickness provide a scatter comparable to, for example, a single thicker il of 20 nm. For example, IL1 and IL2 can be of different materials having different resistivities and crystal structures. IL 1 and IL 2 may also be of the same material 'but may have different crystal structures or orientations or different grain sizes that will scatter charge carriers in different ways 156917.doc • 31 · 201212319. As another example, one IL may be composed of a fine grain material or nano particles (which may be the same or different from another IL). If RSL1 and RSL2 are different materials, and IL1 and IL2 are different materials and/or different material types, the optimal placement of these ILs relative to the RSLs will be material dependent. One possible embodiment uses a pn-junction where IL1 is n+Si and IL2 is p+Si. For example, IL1 and IL2 can each have a thickness of at least 20 nm. Another possible combination is to use one of the metals such as TiN for one of the ILs and n+ or p+ Si for the other of the ILs. For example, see Figure 10C. Figure 6E illustrates an exemplary embodiment of the RSME of Figure 6A using a repeating RSL/IL pattern. An RSL and an IL type or combination are repeated at least twice. For example, in addition to RSL2 and a second IL (IL2), RSL1 and a first IL (IL1) are provided. The third RSL (RSL3) is adjacent to E2. The RSLs may be the same or different types, and the ILs may be the same or different types. An advantage of this embodiment is that multiple scattering layers increase the amount of scattering/resistance in the path of the RSME. In addition, the ability to use different types of IL and RSL provides an additional capability to adjust the performance of RSME. The three RSLs can have a large number of characteristics (all identical, two identical and one different, all different, etc.). Using more than one IL with a different RSL will change the characteristics of the RSME and provide additional functionality to tune its performance. When a voltage is applied across the RSME, the voltage is divided proportionally across each RSL based on the resistance of each RSL. In one possible implementation, both of the RSLs of 156917.doc -32 - 201212319 have the same Ι-V characteristic, and the other RSL has a different IV characteristic such that, for example, when the other RSL is in a Both RSLs are in a low resistance state in the high resistance state, or both RSLs are in a high resistance state when the other RSL is in a low resistance state. Other variations are also possible. 6F illustrates an exemplary implementation of the RSME of FIG. 6A in which each layer of the RSME extends horizontally and one or more of the layers are configured end-to-end. Instead of a fully stacked (vertical) configuration, portions of the RSME are configured laterally (side) at other portions of the RSME, or are configured end-to-end with the other portions. For example, El, RSL1, and IL are in one stack, while RSL2 and E2 are in another stack, and RSL2 is configured side by side with the IL. Referring to FIG. 6A, BLC and AL1 may be provided on E1, and SE, AL2, and WLC may be provided under E2. In one possible approach, a non-conductive (NC) layer can be provided below the IL and configured side by side with E2. The parts/layers of the RSME are still arranged in series. In another possible embodiment, E2 is located on the side of RSL2 rather than below it, such that the three sections (IL, RSL2 and E2) are configured end to end. Other variations are also possible. Extending portions of the RSME end-to-end or otherwise laterally to each other provides an additional capability to adjust one of the RSME's layouts. For example, the height of the RSME can be reduced. In one method, BLC and AL1 can be provided on E1, and SE, AL2 and WLC can be provided below E2. 6G illustrates another exemplary implementation of the RSME of FIG. 6A in which each layer of the RSME is horizontally extended and one or more of the layers are configured end-to-end. Portions of the RSME are configured side-by-side with other portions of the RSME or 156917.doc -33.201212319 are configured end-to-end with the other portions. RSL1, IL and RSL2 are in one stack, while E2, a non-conductive layer (NC) and E2 are in another adjacent stack. E1 is disposed end-to-end at the side of RSL1 and E2 is disposed end-to-end at the side of RSL2. The portions may still be considered to be in series configuration, such as in series with one of El, RSL1, IL, RSL2, E2. In another option, for example, E1 is lateral to the RSL and extends above the RSL and E2 is lateral to the RSL and extends below the RSL. In one method, BLC and AL1 can be provided on E1, and SE, AL2 and WLC can be provided below E2. In general, at least one of El, E2, IL, RSL1, and RSL2 can be considered to be at least partially laterally disposed on at least one of El, E2, IL, RSL1, and RSL2. In Figures 6F and 6G, the lateral configuration is end-to-end. For example, RSL1 is laterally configured with E1 end-to-end and/or RSL2 and E2 end-to-side. Further, at least one of the IL and RSL1 and RSL2 is laterally disposed end to end. Figure 6H illustrates another exemplary embodiment of the RSME of Figure 6A in which each layer of the RSME extends vertically. Portions of the RSME are placed laterally or face to face with other portions of the RSME. For example, the BLC can be located above, below or to the side of E1, while the WLC is located above, below or to the side of E2. The BLC and WLC are in a series path with the RSME. Manufacturing may involve a repeating cycle of a layer of deposition and a spacer etch and a final CMP step. For example, the Ε1 layer can be deposited as a horizontally stretched layer, which is then etched to form the vertically extending portions shown. Next, the RSL1 layer can be deposited as a horizontally stretched layer, which is then etched 156917.doc • 34-201212319 to form the vertically extending portions shown. Repeat this for each of the IL, RSL2, and E2 sections. In one method, AL1 and BLC (Fig. 6A) extend vertically upward from E1 and SE, AL2, and WLC extend vertically downward from E2. 0 or more of the two layers may be laterally disposed face to face with each other. For example, RSL1, IL, and RSL2 can each be laterally configured face to face with each other. Further, El, RSL1, IL, RSL2, and E2 may each be laterally disposed face to face with each other. Compared to the L-shaped cross section of Fig. 61 and the U-shaped cross section of Fig. 6J, for example, the RSME portion of Figs. 6D to 6H has a rectangular cross section. 61 illustrates another exemplary embodiment of the RSME of FIG. 6A including the L-shaped portions of RSL1, IL, RSL2, and E2. For example, assume that the cross-sectional view is along a vertical or horizontal plane with one of the vertical axes X and y. In the X direction, E1 has a thickness tlx, RSL1 has a thickness t2x, IL has a thickness t3x, RSL2 has a thickness t4x and E2 has a thickness t5x. In the y direction, El has a thickness tly, RSL1 has a thickness t2y, IL has a thickness t3y, RSL2 has a thickness t4y and E2 has a thickness t5y. For each portion, the thickness in the X direction may be the same or different from the thickness in the corresponding y direction. The order of the layers may be reversed such that the layers extend in the order of E2, RSL2, IL, RSL1, E1 instead of E:1, RSL1, IL, RSL2, E2. For example, the BLC can be located above, below or to the side of E1, while the WLC is located above, below or to the side of E2. The BLC and WLC are in a series path with the RSME. By providing an L-shaped portion, conductive filaments can be formed in one of the RSME setting procedures, wherein the filaments extend in both X and y directions. Due to the relatively large area of filaments extending above 156917.doc -35 - 201212319, the formation of the filament is potentially promoted. The embodiments depicted may also be rotated by 9 〇 or 18 〇 °. In this method, 'similar to the concept of Figs. 6F to 6H', the same portions of the layers are disposed sideways to each other 'but the layers are nested L-shaped' having two portions extending at right angles to each other. For example, 'L-shaped RSL2 is nested within L-shaped E2, L-shaped IL is nested within L-shaped RSL2' and L-shaped RSL1 is nested within L-shaped IL. E1 is nested within L-shaped RSL1, but in this example it is not itself L-shaped. Each portion may be the same or different in one or more dimensions. Here, at least one of El, E2, IL, RSL1, and RSL2 may be considered to be at least partially laterally disposed at least one of El, E2, IL, RSL1, and RSL2. 6J illustrates another exemplary embodiment of the RSME of FIG. 6A including U-shaped portions of RSL1, IL, RSL2, and E2. For example, assume that the cross-sectional view is along a vertical or horizontal plane with one of the vertical axes X and y. In the X direction, E1 has a thickness tx, RSL1 has thicknesses t2xa and t2xb, IL has thicknesses t3xa and t3xb, RSL2 has thicknesses t4xa and t4xb, and E2 has thicknesses t5xa and t5xb. In the y direction, El has a thickness tly, RSL1 has a thickness t2y, IL has a thickness t3y ' RSL2 has a thickness t4y, and E2 has a thickness t5y » xa thickness which may be the same or different from the corresponding Xb thickness. Furthermore, the xy thickness may be the same or different than the corresponding xa and/or Xb thickness. The order of the layers may be reversed such that the layers extend in the order of E2, RSL2, IL, RSL1, E1 instead of El, RSL1, IL, RSL2, E2. For example, the BLC can be located above, below or to the side of E1, while Wlc is located above, below or to the side of E2. The BLC and WLC are in a series path with the RSME. By 156917.doc • 36· 201212319, by providing a U-shaped portion, conductive filaments can be formed in one of the rsme setting procedures wherein the filaments extend on either side of E1 in the X direction and in the y direction. The depicted embodiment can also be rotated by 9 turns. Or 180. . In this method, 'similar to the concept of Figures 6F to 6H, portions of the layers are arranged laterally to each other, but the layers are in a nested U shape having two parallel extending at right angles to a base portion section. For example, the u-shaped RSL2 is nested within the u-shaped E2, the U-shaped IL is nested within the U-shaped RSL2, and the U-shaped RSL1 is nested within the U-shaped IL. The E1 is nested within the U-shaped RSL1, but in this example it is not U-shaped. Each part may be the same or different in one or more dimensions. In general, any of the vertically stacked embodiments can be adapted to an L-shaped or U-shaped embodiment. Here, at least one of El, E2, IL, RSL1, and RSL2 may be considered to be at least partially laterally disposed at least one of El, E2, IL, RSL1, and RSL2. Figure 6K1 illustrates an exemplary embodiment of the RSME of Figure 6A using an RSL and a collapse layer located below the RSL. RSL1 is used as discussed previously, but a crash layer is used instead of an RSL2 between IL and E2. The collapse layer does not have a resistance switching behavior and can provide a material of one of the barrier layers between the turns. A material that has a resistance switching behavior typically toggles between the start and end resistance states. In contrast, a crash material has collapsed from an initial state with one of the associated characteristics by applying a relatively high voltage and/or current to a crash state with another associated Ι·ν characteristic and usually A material that can be changed only once from the initial state to the collapsed state. 156917.doc -37- 201212319 A material. A resistor-switching material can be considered to be a material that can be programmed multiple times, and a crash material can be considered to be a single-programmed material. This can be programmed to include the ability to change a resistive state. Although a resistive switching material can be paired with a dazzling or anti-solving filament to form a single-staged material, the resistive switching material itself can be programmed multiple times. For example, a single stylized material is useful when setting a unique identifier for a wafer or setting operational parameters such as a clock or voltage parameter. The example material used for the crash layer (and the associated resistivity P range for one of the instances before collapse in the initial state) contains: siN (for 25 c

Si3N4, p=i〇i4 Q-cm), SiO 2 (at 25 C, p=l〇14 to 1〇16〇-cm), SiC (p=l〇2 to 106 Ω-cm), SiCN, SiON or Any layer that can collapse, for example, changes from a higher resistance (typically a non-conductive state) to a lower resistance (conductive state), but is not itself referred to as a reversible resistance-switching material. The collapse layer can maintain a resistance of at least about one estuary to one of the 丨〇 Ω Ω while conducting one of the materials in the puddle state. The resistance in the initial state is typically one or more orders of magnitude higher than in the peer state. If the resistance of the layer is too low, it is less effective as a protective layer. The resistance of the material of the collapse layer is pl/A, the length of the material of the 1 series and the cross-sectional area of the A system. This length is the thickness of the collapse layer. After knowing p and R, you can use eight and 丨 to select the size of the material. The crash layer can be a single-programmed crash layer. It can be considered that this collapse layer is a non-switchable crash layer or a crash layer that can be switched once because the crash procedure is irreversible. That is, once the crash layer has collapsed from the beginning of the non-conducting state, the crash layer remains in the crash state and cannot be returned to the start state. In contrast, in some cases, a single pole or bipolar single 156917 .doc *38· 201212319 The unit can be operated in a single stylized mode, but usually does not actually crash and maintains at least about one of the resistances of i)^1 to 1〇. For example, one or more RSLs can be configured into a collapsed state by applying a relatively high voltage or current to the RSL. For example, an applied voltage can be significantly higher than the threshold voltage of the material. This crash procedure can be partly due to thermal effects. See Figure 6K2 and Figure 6K3 for further details. Figure 6K2 shows a graph of one of the collapse levels from an initial state to a collapsed state. This transition can be achieved by applying a current or voltage across the breakdown layer for a period of time that can be extended, for example, by a few minutes. At time tb', the current through one of the collapsed layers is gradually increased (due to the gradual decrease in the resistance), and a collapse event occurs at this time. In some cases, multiple crash events can occur. For an applied voltage, the voltage applied across the RSME is proportionally divided across the breakdown layer and RSL1 according to the breakdown layer and the respective resistors of RSL1. "rSL1 can be configured to a low resistance state so as to substantially cross the The breakdown layer applies all voltages. Figure 6K3 shows a graph of one of the I-V characteristics of a collapsed layer in an initial state (solid line) and a collapsed state (dashed line). For a given voltage, the current is higher in the collapsed state (and the resistance is lower). One of the crash layers is in an initial state. The RSME can be distinguished from one of the RSMEs in which the crash layer is in a crash state so that a data bit can be stored according to the state of the crash layer. The RSL can be further modulated between the two states to store a data bit. The state of the collapse layer and the RSL can be determined by applying an appropriate read voltage. Figure 6L illustrates an exemplary embodiment of the RSME of Figure 6A using a reversible RSL (RSL1) and one of the RSL1 156917.doc -39 - 201212319 crash RSLs. One of the configurations of this figure 6K1 replaces the configuration. Figure 6M illustrates an exemplary embodiment of the RSME of Figure 6A in which the resistance switching layer (rsl) is of a different type. rSL1 and RSL2 can be made of different types of materials having different switching characteristics, for example, to allow the RSme to store more than one data bit. Exemplary materials for RSL 1 and RSL 2 include: Ti02, NiOx, HfSiON, HfOx, Zr02, and ZrSiON. Figure 7A illustrates an exemplary embodiment of a steering element (SE) of the memory cell of Figure 6A as a Si diode. The redundancy has an n-type region, an intrinsic (i) region, and a p-type one Si dipole. As mentioned, a SE selectively limits the voltage across the RSME and/or the current through the rsmE. The SE allows writing to and/or reading from a memory unit without affecting the state of other memory cells in an array. Figure 7B illustrates an exemplary embodiment of an operational element (SE) of the memory cell of Figure 6A as a feedthrough diode. The punch-through diode includes an n+ region, a P-region, and an n+ region. The punch-through diode can operate in two directions. In particular, a pass-through diode allows for a bipolar operation of a cross-point memory array and can have a symmetric nonlinear current/voltage relationship. The feedthrough diode has a high current at high bias for selected cells and a low leakage current at low bias for unselected cells. Therefore, it is compatible with bipolar switching in a point-and-point memory array having a resistance switching element. The punch-through diode can be an n+/p-/n+ device or a p+/n-/p+ device. Although an example implementation involving a memory cell having a diode as a steering element is provided, in this context The technology provided is generally applicable to other devices and operating elements of 156917.doc -40· 201212319, including a transistor, a through-current crystal, a punch-through diode, a PN diode, an NP diode, and a PIN two. A polar body, a Zener diode, an NPN diode, a PNP diode, a Schottky diode, a MIN diode, a carbon polyoxynitride, a transistor layout, and the like. In another method, the steering element can be a transistor, such as a bipolar or CMOS transistor. In addition, in some configurations, it is not necessary to use a steering element. Figure 8 illustrates an exemplary embodiment of the memory cell of Figure 6A coupled between a bit line and a word line. The bit line contact (BLC) is W or NiSi, the first adhesive layer (AL1) is TiN, the first electrode (E1) is n+Si, RSL1 is MeOx (for example, Hf02), IL is TiN, and RSL2 is MeOx ( For example, Hf02) provides an additional adhesive layer (AL) for the Si diode of the system control element (SE), the second adhesive layer (AL2) is TiN and the word line contact (WLC) is W or NiSi. Alternatively, one or more cap layers may be provided using one selected from the group consisting of TiOx, A1203, ZrOx, LaOx, and YOx. Typically, the cap layer can be a metal oxide. In this example, the cap layers are adjacent to the IL and RSL. Specifically, a cap layer (〇 & 1) is located between 1181^1 and 11^ and adjacent to each of 118 [1 and 11^, and another cap layer (Cap2) is located at IL. It is adjacent to IL and RSL2 between RSL2. From the perspective of MeOx, a cap layer can act as an oxygen source or oxygen scavenger, which facilitates switching in an RSL. When used as an oxygen absorbing agent, for example, the cap layer can help provide oxygen from a MeOx RSL to an IL/electrode. When acting as an oxygen source, for example, the cap layer can help provide oxygen from a 156917.doc -41 · 201212319 - IL / electrode to a MeOx RSL. A getter is one in which a material such as oxygen is moved to a position. The getter is a program in which, for example, the material of oxygen moves to the position of the getter. The getter position is where one of the alternate locations will preferentially reside due to the oxygen being in a lower energy state. RSME consists of layers extending from E1 to E2. In an exemplary embodiment, for example, E1 and E2 each have a thickness or height of about 1 to 3 nm or about 1 to 1 〇 nm, and for example, jiang can have about 1 to 5 nm or about One thickness or height from 1 to 10 nm. Therefore, the total thickness of the rSME can be extremely small. 9A illustrates an embodiment of the RSME of FIG. 6C in which E1 is made of Co, CoSi, n+Si, p+Si, or p+ SiC and E2 is made of n+Si. The order from top to bottom is: El, RSL1, Capl, IL, Cap2, RSL2, E2. The RSME also comprises, for example, one of MeOx RSL 1, such as one of TiN, one of, e.g., one of MeOx, RSL2, and one of, for example, n+Si, a second electrode (E2). Further, a cap layer such as TiOx is provided between and between RSL^IL(Capl). This embodiment provides an asymmetric structure when £1 and £2 are made of different materials. For example, an El made of cobalt (c〇) is desirable because it has a relatively high work function of approximately _5 eV close to the work function of the guilt and can result in better switching. This is due to the fact that one of the benefits of one of the work functions can be tied to a higher barrier height. In another method, E1 made of Shi Xihua Gu (c〇Si) is also desirable because it also has a relative work function. In another method, E1 is made of n+si (polycrystalline germanium) which provides a high work function (about 4 丨 to 4 15 eV) and the benefits of oxidation. Other suitable materials include p+Si (polycrystalline germanium) having a work function of about 5" to 5 2 156917.doc -42 · 201212319 eV, and p + carbonized powder, which has a 6.6 to 6.9 eV from a high energy gap. ^· — ·*·, ^ Extreme work function. See Figure 9C. For example, for (4H polytype) the energy gap is about 3-23 eV and for the 6H alpha polytype, the energy gap is about 3·05 eV. These energy gaps are significantly higher than, for example, the energy gap of si, which is about ij eV for the Si' energy gap. In one embodiment, 'p+ SiC can be deposited and then doped with a dopant (eg, B', Be or Ga) by ion implantation to about 10E19 to 10E20 atoms per cubic centimeter, for example. A concentration. This is an example of in-situ doping. SiC is chemically inert and therefore resistant to oxidation. SiC does not actually melt due to a sublimation temperature of 27〇〇^, and has a high thermal conductivity of 3 6 to 49 w/(cm*K) (compared to 1.49 W (cm*K) of Si), This high thermal conductivity can benefit memory cell operation due to high current density. Figure 9B illustrates an embodiment of the RSME of Figure 6C in which E1 and IL are made of p+ SiC' and E2 is made of n+ Si, n+ SiC or p+ SiC. The order from the top to the bottom is: El (e.g., p+ SiC), RSL1, IL (e.g., 'p+ SiC), RSL2, E2. The high work function of El and IL can cause a decrease in cell current, where IL acts as a scattering layer. In addition, by adjusting the doping of the il's adjustable layer resistance to increase the scattering and reduce the current ❶ as the doping increases, the IL resistivity decreases, so that there is a small depletion width and a small amount on the depletion layer. Voltage drop. Further, E2 may be made of n+Si, n+ SiC or p+ SiC. When E2 is made of n+ SiC, there is a thin SiO 2 layer formed between E2 and RSL2 during fabrication. Since the voltage drop across one of the Si02 layers is avoided, the operating voltage is reduced. In contrast, in the case of an n+ Si bottom electrode, a thicker layer of 156917.doc •43·201212319 can be formed between E2 and RSL2. As an alternative to n+ Sia, 'E2 can be made of p+ siC. For example, rsli and RSL2 can be MeOx. In one method, 'IL can be provided, for example, by providing IL to one nanocrystal.

The SiC film is made of nano particles. For example, see w, discussed below, and Figure 0C shows one of the Fermi levels of p+ SiC versus other materials. It has been mentioned above that p+Sic has a very high work function of about 6.6 to 6.9 ev due to a high energy gap. To illustrate this fact, an energy diagram is provided for 4H-SiC. This figure shows the energy level (Evacuum) in the vacuum, the energy level (Ec) of the conduction band, the essential energy level (Ei), and the energy level of the valence band ( Εν). This illustration is from T. Ayalew's paper "SiC Semiconductor", incorporated herein by reference.

Devices Technology, Modeling And Simulation" (January 2004 'Institution for Microelectronics, Vienna, Austria). Other example materials and their Fermi level are also shown: Al (4.28 eV), Ti,

Zn (4.33 eV), W (4.55 eV), M〇 (4.60 eV) 'Cu (4.65 eV), Ni (5.10 eV), Au (5.15 eV), and Pt (5.65 eV). As mentioned, p+

SiC has a relatively high work function. In particular, the Fermi level will be close to the valence band. In practice, undoped SiC has a work function of about 4.5 to 4.8 eV or about 4.9 eV if covered by oxygen. However, for p+ SiC, the Fermi level will be closer to the valence band' to make the work function higher. Dependent on P+ doping level and SiC polytype (for 4H-SiC 'band gap Eg=3.23-3.26eV or for 611-8丨(:, £8=3.056¥)' work function £1(| )]^ can be as shown in the figure 6.6 to 6.9 156917.doc • 44 - 201212319 eV.

The siC can be applied by depositing at a temperature that is not too high. There are various techniques for depositing relatively low spills. For example, deposition at 750 C is set forth in the context of which it is incorporated herein by reference.

"Single-crystalline, epitaxial cubic SiC films grown on (100) Si at 750 °C by chemical vapor deposition" by Golecki (April 1992, Applied Physics Letter, Vol. 60 'No. 14 '1703 to 1705) In this method, the SiC film is formed by using decyl decane (SiCH3H3) (a single precursor having a ratio of 1:1 si:c) and H2 by low pressure chemical vapor deposition. In another exemplary method, molecular beam epitaxy has been used to deposit SiC at low temperatures, as described in reference herein by a Fissel et al., rLow-temperaturegrowthofSiCthinfilmson Siand6H-SiC by solid-source molecular beam epitaxy. (Applied Physics Letter, Vol. 66, No. 23, pp. 3182 to 3184, June 1995). The method involves the use of solid-state molecular beam epitaxy controlled by a quadrupole mass spectrometer-based flux meter at Si (lll) and 6° to 5° skew oriented 6H-SiC at a low temperature of about 800 to 1000 °C. (0001) Epitaxial growth of stoichiometric SiC on the substrate. In the case of SiC (0001), a film was obtained on the surface of the Si-stabilized surface exhibiting (3x3) and (2x2) superstructures. The reflection high energy diffraction (rheED) pattern and the resistive RHEED oscillation during growth at 6H-SiC (0001) at T > 900 °C indicate the two-dimensional nucleation system main growth procedure on the terrace. Another exemplary cryogenic process for depositing SiC is described in the reference to W. Yu et al., "Low temperature 156917.doc •45-201212319 deposition of hydrogenated nanocrystalline SiC films by helicon wave Plasma enhanced chemical vapor deposition" (September 3, 2010, J. Vac. Sci. Technol. A 28(5), American Vacuum Society, pages 1234 to 1239). Here, a hydrogenated nanocrystalline lanthanum carbide (nc-SiC:H) film is deposited at a low substrate temperature by using a spiral wave plasma enhanced chemical vapor deposition technique. The effects of radio frequency (rf) power and substrate temperature on the properties of the deposited nc-SiC:H film have been investigated. It has been found that a hydrogenated amorphous SiC film is fabricated at a low rf power, while an nc-SiC:H film having a microstructure of one of the SiC nanocrystals embedded in the amorphous equivalent portion can be used as the rf power. Deposited at 400 W or more. The plasma transition from self-capacitative dominant discharge to spiral wave discharge with high plasma strength affects the microstructure and surface morphology of the film. Analysis of the films deposited at various substrate temperatures revealed that the onset of SiC crystallization occurred at substrate temperatures as low as 150 °C. Figure 10A illustrates one embodiment of the RSME of Figure 6C illustrating an alternative IL material. The order of layers from top to bottom is: El (eg, TiN), E1 (eg, n+Si), RSL1 (eg, MeOx), cap 1 (eg, TiOx), IL (eg, TiN), cap2 (eg, TiOx), RSL2 (eg, MeOx), E2 (eg, n+Si). In one embodiment, El comprises a combination of one of the TiN layers on an n+ Si layer. Additionally, a cap layer, such as TiOx, is provided between RSL1 and IL and between IL and RSL2. A further Ti contact (not shown) may be located above E1. As an alternative, IL may be selected from the group consisting of Al, Zr, La, Y, Ti, TiAIN, TixNy and TiAl alloys. These materials are preferred coupling layers that enable lower V and I unit operation. This embodiment provides a mirror image structure for IL. 156917.doc -46-201212319 A cap layer, an RSL, and an electrode extend from both sides of the IL in the same order and are optionally the same material (eg, The same capping material above and below the IL, such as TiOx, followed by the same RSL material above and below the IL, such as MeOx, followed by the same electrode material above and below the IL, such as n+Si). Figure 10B illustrates an embodiment of the RSME of Figure 6C in an inverted mirror stack configuration. The order of layers from top to bottom is: El (eg, TiN), capl (eg, TiOx), RSL1 (eg, MeOx), IL (eg, 'n+Si), RSL2 (eg, MeOx), cap2 (eg, TiOx) ), E2 (for example, TiN). In one method, El is made of TiN, IL is made of n+Si, and E2 is made of TiN. For example, the IL layer can have n+Si having a thickness of 10 to 100 nm. This embodiment is an inverted mirror configuration that provides an inverted stack with respect to the embodiment of Figure 10A, since the n+ Si layer is now IL rather than the El or E2 layer, and the cap layer is located at the RSL and electrodes. Between the layers (capl is between RSL1 and E1; cap2 is between RSL2 and E2) instead of between RSL and IL. Specifically, an RSL, a cap layer, and an electrode extend from both sides of the IL in the same order and are optionally the same material (eg, the same RSL material above and below the IL, such as MeOx, followed by IL) And the same top cover layer material below, such as TiOx, followed by the same electrode material above and below the IL, such as TiN). Figure 10C illustrates one embodiment of the RSME of Figure 6C in an asymmetric, upright stack configuration. The order from top to bottom is: E1 (eg, TiN), capl (eg, TiOx), RSL1 (eg, MeOx), IL (eg, n+Si), IL (eg, TiN), cap2 (eg, TiOx) ), RSL2 (eg, 156917.doc -47 - 201212319 eg MeOx), E2 (eg, n+ Si). In one method, one of the n+ Si layers (e.g., 10 to 100 nm thickness) of the IL-based TiN layer is combined. A top cover layer such as TiOx is provided on top of the MeOx layer and adjacent to the MeOx layer. For example, capl is above RSL1 and ® is adjacent to RSL1, and cap2 is above RSL2 and adjacent to RSL2. The configuration is asymmetrical and is an upright stack with all layers vertically configured. Do not use a mirrored configuration. This configuration is asymmetrical because the layer extending over IL(n+Si) contains RSL1 followed by capl, while the layer extending below IL(TiN) contains cap2 followed by RSL2. The configuration is upright because capl is above RSL1 and cap2 is above RSL2. Figure 10D illustrates an embodiment of the RSME of Figure 6A in an asymmetric, inverted stacked configuration. The order of layers from top to bottom is: El (eg, TiN), E1 (eg, n+Si), RSL1 (eg, MeOx), capl (eg, TiOx), IL (eg, TiN), IL (eg, n+ Si), RSL2 (#J, eg, MeOx), cap2 (eg, TiOx), E2 (eg, TiN). Do not use a mirrored configuration. The configuration is asymmetrical because of the top of the IL, a top cover followed by an RSL, and below the IL, an RSL followed by a top cover. This configuration is inverted relative to the embodiment of Figure 10C because the n+ Si layer is now the E1 layer instead of the E2 layer, and the TiN layer is now the E2 layer rather than the lower E1 layer. For example, in one of the ways opposite to that of Figure 10C, the IL layer can have a combination of n+Si and TiN having a thickness of 10 to 100 nm. Other embodiments of IL use one or more metals, such as one selected from the group consisting of TiAIN, WN, W, NiSi, CoSi, and C. Figure 11A depicts an embodiment of 156917.doc-48-201212319 RSME of Figure 6C showing the growth of SiOx when E2 is n+Si. The order of layers from top to bottom is: El (eg, n+Si), RSL1 (eg, MeOx), cap 1 (eg, TiOx), IL (eg, TiN), cap2 (eg, TiOx), RSL2 (eg, MeOx), SiOx, E2 (for example, n+ Si). When E2 is made of Si and RSL2 includes a metal oxide, there is a large change in the formation voltage in the RSL due to the thickness variation of an SiOx layer formed between RSL2 and E2. For example, when RSL2 is a metal oxide and is deposited directly on one of n+Si and is in contact with E2, one of the top portions of the n+ Si layer is oxidized, thereby producing an SiOx layer. In an exemplary embodiment, a 1 to 2 nm SiOx layer may be formed between RSL2 and E2, wherein the RSLs are each made of one of 2 to 4 nm MeOx (eg, Hf02) and the E2 system is composed of Made of n+ Si. Alternatively, El and/or E2 may be made of p+Si, tungsten nitride (e.g., WN, WN2, N2W3), TiN or SiGe. Figure 11B depicts an embodiment of the RSME of Figure 6C showing the growth of a low band gap material such as TiOx when E2 is TiN. The order from the top to the bottom is: El (for example, n+ Si), RSL1 (for example, MeOx), capl (example ^, TiOx), 1 [({column, TiN), cap2 (#J, TiOx) , RSL2 (you J, eg MeOx), Ti/TiOx, E2 (for example, TiN). To prevent SiOx formation, the n+Si layer of E2 may be replaced by a material such as Ti deposited on a TiN electrode. The Ti layer can be considered to be part of the electrode. Specifically, during deposition of, for example, one of HfOx MeOx layers (RSL2) over the Ti layer, a top portion (about 1 to 5 nm) of the Ti layer is oxidized and converted into a TiOx layer. The thickness of the TiOx layer depends on the temperature at which the MeOx is deposited. In this case, the second electrode (E2) includes a Ti layer on a TiN layer, the second resistor cut 156917.doc -49 - 201212319 The change layer (RSL2) includes MeOx, and a TiOx layer is formed thereon. The Ti layer is in contact with the second resistance switching layer.

The band gap of Ti/TiOx is much lower than that of SiOx, so that large variations in voltage formation can be avoided. E1 may be n+ Si or a high work function material such as Ni or NiSi. In an exemplary embodiment, the RSLs are each made of one of 2 to 4 nm MeOx (eg, HfO 2 ). In addition, a high work function material can be used for E1 to reduce the operating current. For example, Ni having a work function of 5.1 eV can be used. NiSi is another alternative material. In comparison, a TiN has a work function of about 4.2 to 4.7 eV, and a work function of n+ Si is about 4.1 to 4.3 eV. Figure 11C illustrates one embodiment of the RSME of Figure 6C in which the RSLs are made of a doped metal oxide to reduce the operating voltage. The order of layers from top to bottom is: E1 (eg, n+ Si), RSL1 (eg, doped MeOx), capl (eg, TiOx), IL (eg, TiN), cap2 (eg, TiOx), RSL2 ( For example, it is doped with MeOx), SiOx, E2 (for example, n+Si). For example, a heavily doped MeOx layer such as HfOx or HfSiON can be used. Doping of MeOx can be achieved by implanting or diffusing a dopant such as Ti, Al or Zr into the MeOx layer at a concentration of about 0.01% to 5%. The test results indicate that these dopants provide good properties. For example, ion implantation or in situ atomic layer deposition (ALD) can be used. In an exemplary embodiment, the RSLs are each made of one of 2 to 4 nm MeOx (eg, HfO 2 ), and a 1 to 2 nm SiOx layer is formed on E2, which is an n+ Si 0 map. 1 ID depicts one of the RSMEs of Figure 11C in which E2 is a TiN instead of n+Si. 156917.doc -50 - 201212319 Embodiment. The order of layers from top to bottom is: El (eg, n+Si), RSL1 (eg, doped MeOx), capl (eg, TiOx), IL (eg, TiN), cap2 (eg, TiOx), RSL2 ( For example, doped with MeOx), Ti/TiOx, E2 (eg, TiN). In an exemplary embodiment, the RSLs are each made of one of 2 to 4 nm MeOx (e.g., HfO 2 ) and a Ti/TiOx layer is formed on E2. Figure 11E illustrates an embodiment of the RSME of Figure 6C in an asymmetric mirrored unit configuration, wherein the RSLs are made of different materials. The order of layers from top to bottom is: El (eg, n+Si), RSL1 (eg, type A MeOx), capl (eg, TiOx), IL (eg, TiN), cap2 (eg, TiOx), RSL2 (eg, , Type B of MeOx), SiOx, E2 (eg, n+ Si). Switching the RSME in both the positive and negative directions can be problematic, so switching at a certain polarity may be preferred. A viable solution uses different materials for RSL1 and RSL2. For example, RSL1 can be of type "A" and RSL2 of type "B". For example, two different types of MeOx can be used to control the switching polarity such that RSL1 is a MeOx of type "A" and RSL2 is a MeOx of type "B". Examples of MeOx include AlOx, TiOx, NiOx, ZrOx, CuOx, WOx such that RSL 1 can use one of these materials and RSL 2 can use the other of these materials. The RSL materials can be selected to achieve a desired switching effect, wherein the switching occurs under desired conditions such as the specified I-V conditions. For example, E1 and E2 can be made of n+ Si or TiN. Figure 11F illustrates one embodiment of the RSME of Figure 6C in an asymmetric mirror unit configuration that is free of SiOx. The layer order from top to bottom: e 1 (eg 156917.doc • 51· 201212319 eg 'n+ Si ), RSL1 (eg, MeOx of type a), capl (eg, TiOx), IL (eg, TiN), cap2 (eg, TiOx), RSL2 (eg, MeOx of type B), Ti/TiOx, E2 (eg, 'TiN). In this case, the second electrode (E2) is a material such as TiN instead of n + Si so that the SiO 2 layer is not formed during the fabrication. As discussed in connection with the figures, Ti is deposited on a TiN electrode and a top portion of the Ti layer is oxidized by depositing, for example, one of the HfOX Me〇x layers on the Ti, thereby producing a τί〇χ layer. Figure 12 is an energy diagram of one of the RSMEs of Figure 6C. Horizontal_shows a distance ' along RSME from E1 to E2' and the vertical axis represents an energy level. The Ec-based conduction band 'is located at a low level ec 1 from one of the junctions between the high level ec2 to E2 and the RSL2 at the junction between E1 and RSL1. Ee 1 is the energy level of E1, EIL is the energy of IL and EE2 is the energy level of E2. One of the notches in the conduction band indicates that one of the lower energy levels is achieved at the IL, as described below. An MRS relies on ion conduction as a switching mechanism. In ionic conductors, current is transported by the movement of ions and by the movement of electrons and holes. For example, s 'current transport via ions or ions and electrons/holes is present in an electrically conductive liquid called an electrolyte and an ionically conductive solid, also known as a solid electrolyte. In addition, ionic conductivity is available for many products (eg, j-type and π-type batteries (ie, 'regular and rechargeable), fuel cells, electrochromic windows and displays, solid state sensors), especially for reactive gases, conductive bridging Switching and bipolar MeOx switching as described in this document are important. . Compared to pure electron current transport, there is a chemical reaction associated with the current (eg, the system changes over time) that occurs anywhere where the ion current is converted into an electron current, ie, the contact or electrode 156917 .doc -52· 201212319. This is a significant difference compared to the current by means of electrons (or holes), in which the current across the contacts does not require a chemical reaction in the current through the electrons (or holes). Bipolar MeOx switching attempts to move the oxygen vacancies in Me〇x to form a metal filament whereby oxygen is stored at the interface. Electron conduction can be provided by mechanisms including: Fuller_Nordham, Schottky, Space Charge Limit Current (SCLC), SCLC together with Poole Frenkel (pF), PF and Hill's law . Ion conduction includes conductivity, diffusion, and field type. Typical ionic conductivity values are relatively low and depend on the oxygen supply, temperature and electric field from the air (in an exponential manner). Figure 13 illustrates the application of a high electric field in one of the RSL setting procedures. The scanning electron microscope image shows a left-hand electrode (EL) of n+si comprising one growth layer of SiO2, one of Hf02 RSL and one right-hand electrode (ER) of TiN. An electric field can be applied to move the oxygen into an RSL such as MeOx of Hf 〇 2 . Here, in an exemplary embodiment, a high electric field is present in one of the 3 to 5 nm wide Hf02 regions. When using a value of 5 nm, the electric field is therefore 5 V / 5 nm = 10 MV/cm. Figures 14A through 14D illustrate different stages in forming a conductive filament in one of the RSL setting procedures. The figure shows the typical collapse of a single MeOX film. For example, the left-hand electrode (EL) is set at 〇 V as a ground electrode. The middle region represents, for example, one of the Hf02 RSLs, and the right-hand edge region represents one of the 5 V-driven right-hand electrodes (ER). The 5 V system has no approximation of the current limiter (resistor). These figures indicate the expected behavior of an RSME with one or more of these RSLs. It should be noted that 156917.doc •53- 201212319 pays 'in an RSME' the right-hand electrode will receive a current-consuming voltage and is not directly driven. The RSL is initially non-conductive during a setup or formation process. An open or white circle indicates an oxygen ion, and a closed or black circle indicates a metal. The high electric field is coupled to the negatively charged oxygen ions, so that the oxygen ions are extracted from the excitation 2 and attracted to the ER. After the condition of Figure 14A, there is the condition of Figure 14B, in which some oxygen ions have been extracted and stored at the ER (as indicated by the open circles at the ER)' and the oxygen iHf〇2 region is changed from metallic to metallic (as indicated by a closed circle). This procedure continues so that after the condition of Figure 14B, the condition of Figure 14C is reached, where additional oxygen ions have been extracted and stored at the intermediate electrode, and the additional ^^^^ region from which oxygen is extracted becomes metal Sex. Finally, after the condition of FIG. 14C, the condition of FIG. 14D is reached, in which extra oxygen ions have been extracted and stored at the £11, and one of the Hf02 from which the oxygen is extracted is sufficiently partially metallic to form A conductive filament or path through one of the rsl acts as a short between the electrodes. Therefore, there is a self-off state (where the RSL is in a relatively high resistance state, similar to an open (non-conducting) path) to a conducting state (wherein the RSL is in a relatively low resistance state, similar to a short circuit (conductive) ) or closed circuit) one of the changes. 14E, 14F, and 14G illustrate energy diagrams of the setup procedure stages of Figs. 14A, 14B, and 14D, respectively. The y-axis shows the energy and the x-axis shows the distance in the RSME. The peak indicates the barrier to electron transport imposed by the oxygen in Hf〇2. These peaks follow the conduction band Ec, which is in the range from 丨 to jgC2. In Figures 14E to 14G, the conduction band maintains this fixed range. EEl 156917.doc •54- 201212319 is the energy of EL' and EER is the energy of Er. In addition, the figure shows one ideal case of linear band bending. At the beginning of the procedure, assuming that 5 V is applied across the EL and ER and the EL is separated from the ER by 5 nm, the electric field (E) is at one of the starting levels of 1 〇 MV/cm (5 V/5 nm). A relatively small amount of current flows, as indicated by a thin dashed arrow (Fig. 14E). As the procedure continues, oxygen is drawn from the RSL and the oxygen is replaced with a metallic region that is part of a growing filament. The metallic region essentially becomes "one extension of the electrode" such that the effective distance between EL and ER is reduced, for example from 5 nm to 4 nm, and the E field is correspondingly increased to 12 MV/cm (5 V/ 4 nm). Due to this higher field, a larger amount of current flows, as indicated by the thicker dashed arrow (Fig. 14F). Subsequently, additional oxygen is extracted from Hf02 to allow the filament to grow and between EL and ER The effective distance is reduced, for example from 4 rim to 1 nm, and due to the exponential relationship between the field and the distance, the e-field is increased to 50 MV/cm (5 V/1 nm). Because of even higher fields, even A larger amount of current flows into an inrush current, as indicated by an even thicker virtual arrow (Fig. 14G). Note that in Figs. 14E to 14G, the first energy peak is approximately the same as the height of the last energy peak. However, there are fewer peaks indicating a lower barrier to one of the electron transports. The proposed RSME can thus advantageously avoid an inrush current in one of the forming and setting commands by the current limiting effect of the IL layer. Figure 15A to Figure 15C Removing different stages of a conductive filament in an RSL reset procedure 15D, 15E, and 15F are energy diagrams illustrating the reset procedure stages of FIGS. 15A, 15B, and 156917.doc • 55-201212319 15C, respectively. The left-hand side area represents a ground electrode (EL), and the middle area represents, for example, Hf02. One of the RSLs and the right-hand side region represents a driven electrode (ER). The voltage and electrons are plotted as an approximation of the current limiting effect of IL. These figures indicate the expected behavior of an RSL. It should be remembered that An RSME consists of at least two series RSLs, and in an RSME, the right hand electrode will receive a coupling voltage without being directly driven and thus effectively reducing the current. The reset procedure is substantially the same as the settings of Figures 14A-14D. The procedure is reversed. At the beginning of the reset procedure (Fig. 15A and Fig. 15D), the E field is 50 MV/cm, and a relatively small number of oxygen ions are returned to a portion of Hf02 near the ER, thereby blocking the formation of filaments. Short circuit. For example, one of the opposite polarity is applied across the ER and EL and a voltage of -5 V is applied compared to the setting procedure. Therefore, during the reset, for example, it can start at -5 V. For example, Say, apply E across it One of the effective distances of the field is 1 nm, resulting in an E field of 50 MV/cm. Subsequently, a voltage of -7 V is applied across one distance of 1.3 nm, resulting in an E field of 53 MV/cm (Fig. 15B). And Figure 15E). Subsequently, a voltage of -9 V is applied across one distance of 1.6 nm, resulting in an E field of 56 MV/cm (Figure 15C and Figure 15F). This procedure is completely different in an RSME. It is therefore advantageous to avoid inrush currents in a reset procedure. In the case of a bipolar MeOx switch, an ion shift is provided in which ions are removed from the RSL to make the RSL more metallic. This is a self-amplifying effect, because as soon as one ion is removed, the other ions are accelerated as the field is removed, and the dependence of the movement on the field is exponential. Therefore, if an ion has been removed from 156917.doc •56-201212319, the field has increased and the mobility of ion mobility has increased exponentially. Therefore, the device has a faster sag effect. This explains the settings and forms a dependency. In addition to ion movement, electrons can move in the S-HSL by symbolically skipping energy peaks. Initially, only a small amount of electrons flowed. But as the electric field increases, more electrons can overflow the energy peak and it flows more easily. Finally, a large amount of electrons flow impingingly toward the IL. However, this electronic flow is undesirable because the electrons are not beneficial to the switching mechanism that relies on the movement of individual ions. In order to move the plasma, a sufficient electric field needs to be established. The associated electron flow is undesirable because if one has a steering element (eg, a diode) in series with the RSL, the diode needs to be able to not only source current from a small ion current but also from a larger electron current. The current continues. Further, during resetting, oxygen moves back to the resistance switching element, and therefore, the effective distance between 1L and E1 or E2 increases again. An electric field is generated that allows a large amount of electron flow. The RSME structure allows an electric field to be established that is sufficient to move the ions a little while not allowing the electrons to flow too much. The RSME basically provides a poor conductor that does not conduct much electrons. In addition, the IL provides a barrier to stopping electrons and reflecting electrons. Together with the capacitive coupling effect, the ions can thus be moved without causing too much electron current to flow. The RSME can be generally symmetrical (having an IL between RSLi and RSL2) so the switching mechanism can be followed at the IL (between the RSLs). The IL allows an electric field to be established at the center of the device such that the ions will move but do not cross the IL in the intermediate region. The IL is a conductor and is capable of storing oxygen ions at 156917.doc •57·201212319. The IL may be metallic, but it may also be non-metallic. The IL may be extremely thin' and should be capable of reflecting and/or holding electrons such that the electrons fall at the IL. The capacitance of the IL can be adjusted by varying its thickness. This can be especially important for scaled down devices. A target system provides one of the potential steps, such as one of the energy diagrams depicted in FIG. 12, and includes one of the potential steps of the electric field that is reflected but still exists in one of the fields. RSME can be used, wherein a symmetrical configuration can be used. And the ruler has the same thickness' or RSL1 and RSL2 may also have different thicknesses. One RSL can be slightly thicker than the other RSL so that a field can be established without inducing a switch. This will result in a band gap map as shown in Figure η based on the thickness shift of RSL1 and RSL2. If the thicknesses of the RSLs are the same, their fields will behave the same and will switch with the same electric field. On the other hand, by introducing an asymmetry, only one RSL can be modulated, in which case the other RSL becomes a barrier without switching. With regard to the inrush current, this phenomenon occurs because the distance between IL and E1 or E2 is so short that there is no opportunity to interact with the volume. In an electrical conductor, electrons accelerate in an electric field and travel in an average free path until they are scattered by electrons and electrons, electrons and photons, electrons and impurities, or electrons and interface mechanisms. For a typical conductor such as germanium or copper, a typical scattering mean free path is about 4 〇 nm. In a "scaled memory device" the current is shock sensitive because the typical dimensions are much smaller so that the electrons are overshooted and scattered deep inside the electrode and no energy is delivered to the switching region. FIG. 16A is a diagram showing a setting procedure of the ruler of FIG. At step 16〇〇 156917.doc •58· 201212319, the setup procedure is started for the -memory unit. In practice, a plurality of memory cells in a memory device can be simultaneously set or reset by applying an appropriate voltage to the appropriate bit line and word line. At step 1602, a set voltage is applied across the first electrode and the second electrode. The voltage is applied across the resistance-switching memory cell in series with the first and second electrodes of the memory switching device. The set voltage can have a desired waveform, such as, for example, one or several pulses of fixed amplitude, ramp-up or stair-type pulses. Thus, the voltage can be a voltage signal that varies over time, e.g., the magnitude increases over time. • For a pulse of a fixed amplitude, for example, the amplitude can be at or above one of the levels of Vset (Fig. 4A). For a ramp or floor ladder pulse, the set voltage can start at one level below Vset and increase to Vset or more. In one method, the set voltage is blindly applied for a predetermined period of time without determining whether the set state is actually achieved. In this case, the set voltage has a duration and/or magnitude that is sufficient to cause nearly 100% of all memory cells to reach a set state based on one of the prioritized statistical analyses of the memory device. In another method, 'the state of the memory cell is monitored when a set voltage is applied' and the set voltage is removed when the monitor indicates that the set state has been reached. Removing a voltage may mean allowing the first electrode and the second electrode to float. This method is further described, for example, on April 8, 2010, entitled "Set

And U.S. Patent No. 7,391,638, issued to U.S. Patent Application Serial No. No. No. No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No No. Both patents are incorporated herein by reference. At step 1604, a voltage is coupled to the intermediate layer (IL), and the IL scatters electrons from the RSL into the IL. At step 1606, one or more filaments are formed in the RSL. See also Figures 14A-14D. In different RSLs, filament formation can occur at different rates and at different times. For example, referring to Fig. 4B, when the set voltage reaches VsetB, the RSL of type "B" will first reach the set state, and then the RSL for type "A" reaches the set state when the set voltage reaches VsetA. The set voltage is sufficient to form a filament in each of the RSLs to provide a conductive path in the RSLs thereby providing a conductive path through the RSME and memory cells. Therefore, a low resistance state is reached in each of the RSLs and in the RSME. The low resistance state of RSME can be assigned to a first binary data state, for example, 0 or 1. At step 1608, the set voltage is removed and the memory cell (including the RSME) is discharged. Note that steps 1602 through 1606 occur at least partially simultaneously. Depending on the situation, only one of the RSLs may complete the setup procedure, or less than the RSL of all RSLs in the RSME to complete the setup procedure. Figure 16B illustrates a reset procedure for one of the RSMEs of Figure 6A. At step 1620, the reset procedure is initiated for a memory unit. At step 1622, a reset voltage (Vreset, see Figure 4A) is applied across the first and second electrodes. The voltage is applied across a first electrode and a second electrode of the memory cell by switching the memory cell in series with a resistor switching memory cell. The set voltage can have a desired waveform, such as a fixed amplitude 156917.doc • 60-201212319 pulse or a ramp-up pulse. Therefore, the voltage can be a time-varying voltage signal, for example, the magnitude increases with time. . As before, in one method, the set voltage is blindly applied without determining whether or not the set state is actually reached. In this case the 'reset voltage is enough to make it close! 00. All memory cells of /〇 reach a duration and/or magnitude of the reset state. In another method, the state of the memory cell is monitored when a reset voltage is applied and the reset voltage is removed when the monitor indicates that the reset state has been reached. This method is further described in the above-mentioned US 2010/008 5794 and US 7,391,638. At step 1624, a voltage is coupled to the intermediate layer, and IL scatters electrons from the RSL into the IL. At step 1626, one or more filaments are removed or destroyed in the RSLs. See also Figures 15A-15C. The removal of these filaments in different RSLs can be done at different rates and at different times. For example, referring to FIG. 4B, when the reset voltage reaches VresetB, the RSL of type "B" will first be reset, and then the RSL of type "A" reaches the reset state when the reset voltage reaches VresetA. . The reset voltage is sufficient to remove filaments in each of the RSLs to remove one of the conductive paths of the RSLs thereby removing a conductive path through the rSme and the memory cells. Therefore, a high resistance state is achieved in each of the RSLs and in the RSME. The high resistance state of the rSme can be assigned to a second binary data state opposite the low resistance data state, such as 1 or 0. At step 1628, the reset voltage is removed and the memory cell (including the RSME) is removed. Discharge. Note that steps 1622 through 1626 occur at least partially simultaneously. 156917.doc -61- 201212319 Depending on the situation, only one of the RSLs may complete the reset procedure, or less than the RSL of all RSLs in the RSME to complete the reset procedure. The method may include: applying a voltage across the first electrode and the second electrode of the resistance switching memory cell to set a first data state in the memory cell, wherein the voltage is capacitively coupled to a conductive intermediate layer, The conductive intermediate layer is electrically located between the first electrode and the second electrode and in series with the electrodes, and the voltage causes a resistance state to be switched in at least one of: (a) a first a resistance switching layer electrically disposed between the first electrode and the conductive intermediate layer and in series with the first electrode and the conductive intermediate layer, and (b) a second resistance switching layer electrically located at the first The second electrode is in series with the conductive intermediate layer and in series with the second electrode and the conductive intermediate layer, and the voltage is removed to allow the resistance switching memory cell to discharge. The resistive switching layers can be reversible or irreversible. The above method may further comprise: changing a resistance state of a resistor switching memory unit by: (a) increasing a voltage value of one of the voltage changes over time by switching the memory unit across the resistor until the Switching a resistance state to one of the first resistance switching layer and the second resistance switching layer of the resistance switching memory cell; and (b) subsequently increasing the time variation applied by switching the memory cell across the resistance The magnitude of the voltage is until a resistance state is switched in the other of the first resistance switching layer and the first resistance switching layer of the resistance switching memory cell. This switching of the resistance state can be reversible or irreversible. The method may further include: applying a voltage across the first control line and the second control line, wherein the first control line is connected to a resistance switching memory 156917.doc • 62·201212319 one end of the single 7C, the second The control line is connected to the control element connected in series with the resistance switching memory unit; and the first resistance switching layer and the second resistance switching layer of the memory unit are switched across the resistance and span the first resistance switching layer and the second A conductive inter-layer between the resistive switching layers applies the electric bunker; and the voltage is removed to allow the resistive switching memory cell to discharge. The dedicated resistance switching layer can be reversible or irreversible. - Thus, it can be seen that in one embodiment, a resistive switching memory cell comprises: a first electrode and a second electrode; electrically located between the first electrode and the second electrode and The electrode is connected in series with one of the conductive intermediate layers; electrically disposed between the first electrode and the conductive intermediate layer and with the first electrode and the conductive intermediate layer (four) - the first resistance switching layer; and electrically located at the first a second resistance switching layer between the second electrode and the conductive intermediate layer and in parallel with the second electrode and the conductive intermediate layer, the _ resistance switching layer and the second resistance switching layer both have a bipolar switching characteristic or All have a pole switching feature. In another embodiment, a resistance switching memory unit includes: a one-pole operating element; and a resistor switching memory element with the one of the diode operating elements, the resistor switching memory element An electrode and a second electrode; an electrically conductive or semiconductive intermediate layer electrically disposed between the first electrode and the second electrode and in series with the electrodes; electrically located at the negative, an electrode and the conductive or Between the semiconducting intermediate layers and one of the first and second layers of the conductive or semiconductive intermediate layer, and the y knife is layered; and electrically located in the second electrode and the conductive or semiconductive layer - The first pole and the armor layer are switched between the 156917.doc 63 · 201212319 layer and the second resistor. In another embodiment, a device 6 concealing device includes: a memory array, including a plurality of resistance switching memory cells, each of the resistance switching memory cells including the resistor-switching memory device in series An operating element, each of the resistance switching memory elements comprises: an intermediate layer between the resistance switching layers; a plurality of word lines and a bit mother-resistance switching memory unit having the same plurality of bit lines: each a terminal connected to the bit line, and another end connected to each of the plurality of word lines; and a control circuit connected to the plurality of word lines and the bit line, the control circuit via the control circuit Each of the bit lines and the word line adds an electric= to at least one of the resistance switching memory cells such that the resistance switching of the at least one of the = memory: memory cells The hidden component switches from one resistance state to another. In another embodiment, a resistor switching memory unit includes: a first electrode and a second electrode; electrically electrically located between the first electrode and the second electrode and electrically or semiconductively connected to the electrodes in series An intermediate layer; a first resistance switching layer electrically disposed between the first electrode and the conductive or semiconductive intermediate layer and in series with the first electrode and the conductive or semiconductive intermediate layer; and electrically located a second electrode and the conductive or semiconductive intermediate layer and the second electrode and the conductive or semiconductive intermediate layer are connected in series with a second resistor: a knife-changing layer, the first electrode, the second electrode, the conductive or half At least one of the conductive interlayer and the second resistive switching layer is at least partially at the first electrode, the second electrode, the conductive or semiconductive intermediate layer, and the first resistor In the switching layer and the second resistance switching layer, there is one other side configuration to 156917.doc -64 - 201212319. In another implementation, a resistor switches between the memory cell package pole and the second electrode; electrically located at the first electrode; and the conductive or semiconductive intermediate layer in series with the electrodes: electricity; Between the electrode and the conductive T-conserving inter-layer, the conductive or semi-conductive intermediate layer is connected in series with a -first resistance = layer and is connected in series with the second electrode and the conductive or semiconductive intermediate layer. The conductive or semiconductive intermediate layer and the first resistance switching layer and the first resistance switching layer are at least one of an L shape and a U shape. In another embodiment, a memory device includes: a memory array, and a plurality of resistor switching memory cells, each of which includes a control element for competing with the resistor-switching memory device. Each of the resistance switching memory elements includes an intermediate layer electrically disposed between the first resistance switching layer and the second resistance switching layer, and the first electrode and the second electrode; and the memory unit is switched for each resistor: the first Conducting at least one of an electrode, the second electrode, the conductive or semiconductive intermediate layer, the first resistance switching layer and the second resistance switching layer at least partially at the first electrode, the second electrode, and the first electrode Or at least one of the semiconductive intermediate layer, the first resistance switching layer, and the second resistance switching layer are laterally disposed; the plurality of word lines and the bit lines ·, each of the resistance switching memory cells having the complex number a control circuit for connecting the _ terminal of each of the bit lines and the respective word lines of the plurality of word lines and the plurality of word lines and the bit lines, the control The circuit applies a voltage to at least one of the resistance switching memory cells via the respective bit lines and the 156917.doc • 65·201212319 word lines such that the resistors switch to the memory cells At least one of the resistance switching memory elements switches from one resistance state to another. In another embodiment, a method for changing a resistance state of a resistance switching memory cell includes: applying a voltage across the first electrode and the second electrode of the resistance switching memory cell to the memory cell Providing a first data state, wherein the voltage is capacitively coupled to a conductive or semiconductive intermediate layer electrically disposed between the first electrode and the second electrode and The electrodes are connected in series, the voltage causing a resistance state to be switched in at least one of: (a) electrically located between the first electrode and the conductive or semiconductive intermediate layer and with the first electrode and The conductive or semiconductive intermediate layer is in series with one of the first resistance switching layers; and (b) is electrically located between the second electrode and the conductive or semiconductive intermediate layer and with the second electrode and the conductive or semiconductive The intermediate layer is in series with one of the second resistive switching layers, and the voltage is removed to allow the resistive switching memory cell to discharge. In another embodiment, a method for changing a resistance state in a resistance switching memory cell includes: increasing a value of a voltage that varies over time by switching a memory cell across the resistance until And switching one of the first resistance switching layer and the second resistance switching layer of the resistance switching memory unit to a resistance state; and subsequently, further increasing the voltage that is applied across the resistance switching memory unit The magnitude is until a resistance state is switched in the other of the first resistance switching layers 156917.doc • 66-201212319 and the second resistance switching layer of the resistance switching memory unit. In another embodiment, a method for changing a resistance state in a resistance-switching memory cell includes: crossing a first control line and a second control, a line: applying a voltage 'the first control line connection 4' to the resistance switching memory unit 4', the second control line is connected to the control element connected in series with the resistance switching memory unit, and the first resistance switching layer and the second resistance switching of the memory unit are switched across the resistance And applying a voltage across a layer of a (four) or semiconducting intermediate layer electrically between the second resistive switching layer; and removing the voltage to allow the resistive switching memory cell to discharge . In another embodiment, a resistive switching memory unit includes an operating element and a resistor switching memory element in series with the operating element, the resistive switching memory element comprising: a first electrode and a second electrode; a conductive or semiconductive intermediate layer between the electrode and the second electrode in series with the electrodes; between the first electrode and the conductive or semiconductive intermediate layer and with the first electrode and the conductive or semi a conductive first layer connected in series with the first resistance switch; and a second* resistor between the second electrode and the conductive or semiconductive intermediate layer and in series with the second electrode and the conductive or semiconductive intermediate layer Switch layers. In another embodiment, a resistive switching memory device includes: a first electrode and a second electrode; a conductive or semiconductive intermediate layer between the first electrode and the second electrode and in series with the electrodes a first resistance switching layer between the first electrode and the germanium conductive or semiconductive intermediate layer and in series with the first electrode and the conductive or semiconductive intermediate layer, the first resistance switching layer 156917.doc 201212319 includes Me〇x; a second resistance switching layer between the second electrode and the conductive or semiconductive intermediate layer and in series with the second electrode and the conductive or semiconductive intermediate layer, the first resistance switching layer comprising Me 〇x, · and a cap layer between the conductive or semiconductive intermediate layer and the first electrode, the cap layer is selected from the group consisting of TiOx, AI203, Zr〇x, La0x, 丫〇}{ The cap layer serves as an oxygen source or an oxygen absorbing agent from the perspective of the first resistance switching layer. In another embodiment, a memory device includes: a memory array including a plurality of memory cells, each memory cell including a steering element in series with a resistive switching memory component, each resistor switching memory The body element includes an intermediate layer between the first resistance switching layer and the second resistance switching layer; a plurality of word lines and a bit line; each memory cell has a different bit from the plurality of bit lines a terminal connected to the source line and another end connected to the respective word lines of the plurality of sub-lines t; and a control circuit connected to the plurality of word lines and the bit line, the control circuit via the respective bit line And the sub-line applies a voltage to at least one of the memory cells such that the at least one of the memory cells switches from the one resistance state to another resistance state . In another embodiment, a resistance switching memory cell includes: a first electrode and a first electrode ' electrically connected between the first electrode and the second electrode and a conductive intermediate layer in series with the electrodes; a resistive switching layer electrically disposed between the first electrode and the conductive intermediate layer and in series with the first electrode and the conductive intermediate layer; and electrically disposed between the second electrode and the conductive intermediate gate layer In conjunction with the third electrode and the conductive intermediate layer, one of the 156917.doc-68 - 201212319 collapse layers, the collapse; S name & π _ _ to Π) - the resistance is maintained at - conductive state at least about ιμΩ = In the embodiment, the “resistive switching memory unit includes a read-and-synchronized-switching memory element in series with the operating element, and the resistive switching memory element includes: the first electrode and the second electrode are electrically located at the first electrode and the Conducting an intermediate layer between the second electrodes and the electrodes; electrically located between the first electrode and the conductive; and electrically connected to the first electrode and the conductive interposed layer And = method is located in the first Electrode and the conductive intermediate layer twenty-one carry away from the shaped conductive layer, and the collapse of the layers in the conductive state is maintained at least about 1 Living Room resistor 10 to one. In the other - implementation of the ... resistance (four) record dragon single:: in series with the operating element - resistance switching memory components :::: recall; components include: the first electrode and the second ... electricity: = the first electrode and Between the second electrodes and the electric (four) = conductive inter-layer, electrically located in the first electrode and the conductive or layer series electrically or semi-conductive, between the second a collapsing layer between the electrode and the 4-electrode or +-conducting intermediate layer and in series with the second electrode and the conductive inter-layer 2, the collapsing layer being at least about 1 ΜΩ to 10ΜΩ when in a conducting state resistance. In the embodiment, a memory device includes a memory array including a plurality of memory cells, each memory cell including a steering element in series with a resistance switching memory cell. Each-resistance switch 156917.doc •69· 201212319 The memory component includes··the first electrode and the second electrode; the first electrode of the electric first electrode and the third electrode, and the electrodes of the main channel, j, and β Hai are connected in series a conductive or intermediate layer, electrically located in the first first electrode and the conductive or semiconductive intermediate layer: = resistive switching layer; and electrically located in the second electrode and the conductive or + conductive intermediate layer A breakdown layer between and in contact with the second electrode and the conductive or semiconductive layer: the breakdown layer maintains / resistance of about 1 Μ Ω to 10 Ω Ω when in a conductive state. The memory device also includes: a plurality of word lines and bit lines; each of the memory cells has one end connected to the respective bit lines of the (four) bit lines, and the plurality of word lines The other end of the respective word line connection; and the fourth circuit connected to the plurality of word lines and the bit line', the control circuit applies a voltage to the memory via the respective bit line and the word line At least one of the cells such that the at least one of the ones of the memory cells switch from one resistive state to another. The detailed description of the techniques herein is provided for the purposes of illustration and description. This document is not intended to be exhaustive or to limit the invention to the precise form disclosed. Many modifications and variations are possible in light of the above teachings. The embodiments described herein are chosen to best explain the principles of the present invention and its application, and thus, in the embodiments of the invention, Use this technology. The scope of the technology is intended to be defined by the scope of the accompanying claims. BRIEF DESCRIPTION OF THE DRAWINGS Figure 1 is a simplified perspective view of one embodiment of a memory unit comprising one of the RSMEs in series with a steering element. Figure 2A is a simplified perspective view of one of the first memory levels formed by a plurality of memory cells of Figure 1. Figure 2B is a simplified perspective view of one of the portions of a three dimensional memory array formed by a plurality of memory cells of Figure 1. Figure 2C is a simplified perspective view of one of the portions of a three-dimensional memory array formed by a plurality of memory cells of Figure 1. 3 is a block diagram of an embodiment of a memory system. 4A is a graph showing one of the I-V characteristics of an exemplary monopolar RSL. Figure 4B is a graph showing one of the different I-V characteristics of two exemplary unipolar RSLs. 4C is a graph showing one of the I-V characteristics of another exemplary monopolar RSL. 4D is a graph showing one of the I-V characteristics of an exemplary bipolar RSL. 4E is a graph showing one of the I-V characteristics of another exemplary bipolar RSL. Figure 5 illustrates an embodiment of a circuit for reading a state of a memory cell. Figure 6A illustrates an exemplary memory unit having an RSME and one of the steering elements (SE) located below the RSME. Figure 6B illustrates an alternate configuration of one of the memory cells having an RSME, wherein the steering element (SE) is located above the RSME. 6C illustrates an exemplary embodiment of the RSME of FIG. 6A as a mirrored resistive switch (MRS) in a vertical stack. Figure 6D illustrates an exemplary embodiment of 156917.doc-71 - 201212319 RSME of Figure 6A using multiple intermediate layers (IL) between RSLs. 6E illustrates an exemplary embodiment of the RSME of FIG. 6A using a repeating RSL/IL pattern. FIG. 6F illustrates that each layer of the RSME extends horizontally and one or more of the layers are configured end-to-end. An exemplary embodiment of the RSME of Figure 6A. 6G illustrates another exemplary implementation of the RSME of FIG. 6A in which each layer of the RSME is horizontally extended and one or more of the layers are configured end-to-end. Figure 6H illustrates another exemplary embodiment of the RSME of Figure 6A in which each layer of the RSME extends vertically. 61 illustrates another exemplary embodiment of the RSME of FIG. 6A including the L-shaped portions of RSL1, IL, RSL2, and E2. 6J illustrates another exemplary embodiment of the RSME of FIG. 6A including U-shaped portions of RSL1, IL, RSL2, and E2. Figure 6K1 illustrates an exemplary embodiment of the RSME of Figure 6A using an RSL and a collapse layer located below the RSL. Figure 6K2 shows a graph of one of the collapse levels from an initial state to a collapsed state. Fig. 6K3 is a graph showing one of the I-V characteristics of a collapsed layer in an initial state (solid line) and in a collapsed state (dashed line). Figure 6L illustrates an exemplary embodiment of the RSME of Figure 6A using an RSL and a collapse layer located above the RSL. Figure 6M illustrates an exemplary embodiment in which the RSLs are of a different type of RSME of Figure 6A 156917.doc-72-201212319. Figure 7A illustrates an exemplary embodiment of a steering element (SE) of the memory cell of Figure 6A as a Si diode. Figure 7B illustrates an exemplary embodiment of an operational element (SE) of the memory cell of Figure 6A as a feedthrough diode. Figure 8 illustrates an exemplary embodiment of the memory cell of Figure 6A coupled between a bit line and a word line. Figure 9A illustrates an embodiment of the RSME of Figure 6C in which E1 is made of Co, CoSi, n+ Si, p+ Si or p+ SiC and E2 is made of n+ Si. 9B illustrates an embodiment of the RSME of FIG. 6C in which El and IL are made of p+ SiC and E2 is made of n+Si, n+ SiC, or p+ SiC. Figure 9C is a graph showing one of the Fermi energy levels of p+ SiC relative to other materials. Figure 10A illustrates one embodiment of the RSME of Figure 6C illustrating alternative IL materials. Figure 10B illustrates an embodiment of the RSME of Figure 6C in an inverted mirror stack configuration. Figure 10C illustrates one embodiment of the RSME of Figure 6C in an asymmetric, upright stack configuration. Figure 10D illustrates an embodiment of the RSME of Figure 6A in an asymmetric, inverted stacked configuration. Figure 11A depicts an embodiment of the RSME of Figure 6C showing the growth of SiOx when E2 is n+Si. Figure 11B depicts an embodiment of the RSME of Figure 6C showing the growth of a low bandgap material (such as TiOx) 156917.doc -73 - 201212319 when E2 is TiN. Figure 11C illustrates an embodiment of the RSME of Figure 6C wherein the RSLs are made of a doped metal oxide to reduce the operating voltage. Figure 11D illustrates an embodiment of the RSME of Figure 11C, wherein E2 is TiN instead of n+Si. Figure 11E illustrates an embodiment of the RSME of Figure 6C in an asymmetric mirror unit configuration wherein the RSLs are made of different materials. Figure 11F illustrates an embodiment of the RSME of Figure 6C in an asymmetric mirror unit configuration without SiOx. Figure 12 is a diagram showing an energy diagram of the RSME of Figure 6C. Figure 13 illustrates the application of a high electric field in one of the RSL setting procedures. Figures 14A through 14D illustrate different stages in forming a conductive filament in one of the RSL setting procedures. 14E, 14F, and 14G illustrate energy diagrams of the setup procedure stages of Figs. 14A, 14B, and 14D, respectively. Figures 15A through 15C illustrate different stages in the removal of a conductive filament in one of the RSL reset procedures. 15D, 15E, and 15F are energy diagrams illustrating the reset procedure stages of Figs. 15A, 15B, and 15C, respectively. FIG. 16A illustrates one of the RSME setting procedures of FIG. 6A. Figure 16B illustrates one of the RSME reset procedures of Figure 6A. [Main component symbol description] 100 resistance switching memory unit 102 resistance switching memory element 156917.doc • 74· 201212319 104 steering element 106 first conductor 108 second conductor 113 barrier layer 114 first memory level 116 single three-dimensional Array 118 first memory level 120 second memory level 130 resistance switching layer 132 electrode 133 conductive intermediate layer 134 electrode 135 resistance switching layer 142 replay miscellaneous n. + polycrystalline stone: 144 lightly doped or essential (non-146 heavy Complementary P+ polycrystalline 300 memory system 302 memory array 306 input/output 308 output 310 row control circuit 312 row decoder 314 array terminal receiver 316 block selection circuit 156917.doc -75- 201212319 320 column control circuit 322 Column Decoder 324 Array Terminal Driver 326 Block Selection Circuit 330 System Control Logic 400 Line 402 Line 404 Line 406 Line 420 Line 422 Line 424 Line 426 Line 430 Line 432 Line 434 Line 436 Line 440 Line 442 Line 444 Line 446 Line 450 Line 452 line 454 line 156917.doc •76· 201212319 456 line 547 words 549 Word Line 550 Memory Unit 552 Memory Unit 554 Memory Unit 556 Memory Unit 557 Bit Line 558 Transistor 559 Bit Line 560 Write Circuit 562 Transistor 563 Data Bus 564 Clamp Control Circuit 566 Sense Amplifier 568 data latch A1 arrow A2 arrow AL adhesive layer AL1 first adhesive layer AL2 second adhesive layer BLC bit line contact Cap 1 one cap layer Cap2 another cap layer 156917.doc -77- 201212319

El first electrode E2 second electrode Ec conduction band energy level EE1 E1 energy level EE2 E2 energy level EEL EL energy EER ER energy Eg energy band gap Ei essential energy level EIL IL energy EL left hand side electrode ER right hand Side electrode Ev valence band energy level EV valence band IL intermediate layer IL1 first intermediate layer IL2 second intermediate layer IresetA reset current IresetB reset current Iset_limitA reset current limit Iset_limitB reset current limit NC non-conductive layer ςφΜ work function RSL1 First resistance switching layer 156917.doc -78- 201212319 RSL2 second resistance switching layer RSL3 third resistance switching layer RSME resistance switching memory element SE steering element tlx thickness tly thickness t2x thickness t2xa thickness t2xb thickness t2y thickness t3x thickness t3xa thickness t3xb Thickness t3y Thickness t4x Thickness t4xa Thickness t4xb Thickness t4y Thickness t5x Thickness t5xa Thickness t5xb Thickness t5y Thickness Vf Forming voltage Vread Fixed voltage -79- 156917.doc 201212319

Vreset

VresetA

VresetB

Vset

VsetA

VsetB

WLC Reset Voltage Reset Voltage Reset Voltage Set Voltage Set Voltage Set Voltage Word Line Contact -80- 156917.doc

Claims (1)

201212319 VII. Patent application scope: The resistance switching memory unit comprises: a resistor switching memory component, the resistor switching memory component package first electrode and the second electrode; - conductive or semi-conductive middle two electric... Located between the first electrode and the first electrode and associated with the electrodes; a semiconducting intermediate switching layer 'located between the first electrode and the conductive or intermediate layer string and the first electrode and the conductive or semiconductive And a two resistance switching layer between the second electrode and the conductive or electrical intermediate layer and in series with the second electrode and the conductive intermediate layer. 2. The switching of the memory cell as claimed, further comprising: manipulating the 7L member comprising a diode in series with the resistor switching memory element. 3. The resistance switching memory cell of claim 1, wherein: the conductive or semiconductive intermediate layer is non-oxidizable. 4. The resistor switching memory cell of claim 3, wherein: the conductive or semiconductive intermediate layer comprises carbon. 5. The resistor switching memory cell of claim 1, wherein: the conductive or semiconductive intermediate layer is oxidizable. 6. The resistance switching memory cell of claim 1, wherein: the conductive or semiconductive intermediate layer is selected from the group consisting of: 156917.doc 201212319 丽, A Bu Zr, La, γ, Ti, 备, Zhuangxin and η! alloy. 7. The resistance switching memory cell of claim 1, wherein: the conductive or semiconductive intermediate layer is selected from the group consisting of: n+Si, SiGe, and ZrOx. 8. The resistor switching memory cell of claim 1, wherein: the conductive or semiconductive intermediate layer comprises p+Sic. 9. The resistor switching memory cell of claim 1, wherein: the conductive or semiconductive intermediate layer comprises nanoparticle. 10. The resistance switching memory cell of claim 1, wherein: at least one of the first resistance switching layer and the second resistance switching layer is selected from the group consisting of: Hf〇j HfSiON. 11. The resistor switching memory cell of claim 1, wherein: at least one of the first resistance switching layer and the second resistance switching layer comprises a heavily doped metal oxide layer, wherein a dopant concentration It is from 0.01〇/〇 to 5%. 12. The resistance switching memory cell of claim 11, wherein: the metal oxide layer is selected from the group consisting of: Hf〇x and HfSiON; and the dopant is Ti, A1 or Zr. 13. The resistance switching memory cell of claim 1, wherein: at least one of the first electrode and the second electrode is selected from the group consisting of: W, WSix, WN, TiN, TiSix, SiGe, TiAIN, NiSi, Ni, Co, CoSi, n+Si, and p+Si. 14. The resistor switching memory unit of claim 1, wherein: 156917.doc -2- 201212319 at least one of the first electrode and the second electrode is selected from the group consisting of: n+n+ SiC and p+SiC. 1ί>_ The resistance switching memory cell of claim 1, wherein: the first electrode comprises n+Si; the conductive or semiconductive intermediate layer comprises TiN; and the a first first electrode comprises n+S i . 16. The resistance switching memory cell of claim 1, wherein: the first electrode comprises TiN; the conductive or semiconductive intermediate layer comprises n+Si; and the second electrode comprises .TiN. 17. The resistor switching memory cell of claim 1, wherein: the second electrode comprises a Ti layer on a TiN layer; the second resistance switching layer comprises MeOx; and a TiOx layer is formed in the Tiu' The second resistance switching layer contacts. 18. The resistor-switching memory cell of claim 1, wherein: the first electrode comprises n+Si; and the —SiOx layer is grown on the second electrode. 19. A resistance-switching memory device comprising: a first electrode and a second electrode; - a conductive or semi-conductive intermediate layer between the first electrode and the second electrode and in series with the electrodes; a first-resistive switching layer is disposed between the first electrode and the conductive or semi-conductive intermediate layer and in series with the first-f pole and the conductive or semi-conductive intermediate 156917.doc 201212319 layer, the first resistance switching layer includes Me〇x; a second resistance switching layer between the second electrode and the conductive or semiconductive intermediate layer and in series with the second electrode and the conductive or semiconductive intermediate layer, the second resistance switching layer comprises Me〇x ; and a cap layer between the conductive or semiconductive intermediate layer and the first electrode 'the cap layer is selected from the group consisting of Ti0x, AI2O3, ZrOx, LaOx, γ〇 From the perspective of one of the first resistance switching layers, the cap layer acts as an oxygen source or an oxygen absorber. 20. The resistor switching memory component of claim 19, wherein: the cap layer is adjacent to the conductive or semiconductive intermediate layer. 21. The resistor switching memory component of claim 20, further comprising: an additional cap layer between the conductive or semiconductive intermediate layer and the second electrode, the additional cap layer being selected from the group consisting of In the group: Ti〇x, Ti, αι2ο3, Zr〇x, La〇x, γ〇χ, the additional cap layer is adjacent to at least one of the conductive or semiconductive intermediate layer and the second electrode . 22. The resistor switching memory cell of claim 20, wherein: the cap layer comprises TiOx; and the conductive or semiconductive intermediate layer comprises TiN. 23. The resistor switching memory cell of claim 22, wherein: the first electrode comprises n+Si » 24. The resistor switching memory component of claim 19, wherein: the cap layer is adjacent to the first electrode. 25. The resistance switching memory cell of claim 24, wherein: 156917.doc 201212319 the cap layer comprises TiOx; and the first electrode comprises TiN. 26. The resistor switching memory cell of claim 25, wherein: the conductive or semiconductive intermediate layer comprises n+Si. 27. The resistor switching memory cell of claim 26, further comprising: an additional conductive or semiconductive intermediate layer adjacent to the intermediate layer comprising TiN. 28. The resistance switching memory component of claim 27, further comprising: an additional cap layer adjacent to the intermediate layer, the additional cap layer being selected from the group consisting of: TiOx, A1203, ZrOx, LaOx, Y〇x. 29. The resistor switching memory component of claim 19, wherein: the resistor switching memory component has a mirrored configuration. 30. The resistor switching memory component of claim 19, wherein: the resistor switching memory component has an inverted mirror configuration. 3 1. The resistor switching memory component of claim 19, wherein: the resistor switching memory component has an asymmetric upright configuration. 32. The resistor switching memory component of claim 19, wherein: the resistor switching memory component has an asymmetric inverted configuration. 33. A memory device, comprising: a memory array comprising a plurality of memory cells, each memory cell comprising one of a plurality of control elements in series with a resistance switching memory element. Included in the intermediate layer between the first resistance switching layer and the second resistance switching layer; 156917.doc 201212319 a plurality of word lines and bit lines; each memory unit has one of the plurality of bit lines a terminal connected to the other bit line and the other end connected to one of the plurality of word lines; and a control circuit connected to the plurality of word lines and the bit line, wherein the control circuit The bit line and the word line apply a voltage to the one of the memory cells a to be less than one such that the at least one of the # memory cells switches from the resistance state To another resistance state. 34. The memory device of claim 33, wherein: each of the steering elements comprises a diode. 35. The memory device of claim 33, wherein: the memory device comprises a plurality of memory intersection-and-point arrays, the memory array is a monolithic three-dimensional array, a unit level, and each memory level comprises a memory. Body unit. 156917.doc _ 6 -