201212206 六、發明說明： 【發明所屬之技術領域】 本發明有關於一種用來增加輸入至積體電路之信號之電壓操 作範圍之靜電保護電路(electrostatic discharge protection circuit)。 【先前技術.】 請參考第1圖。第1圖為說明先前技術之靜電保護電路100之 電路圖。靜電保護電路100輕接於積體電路101之第一端Τι、第二 端A與第三端丁3,以防止積體電路101受靜電損壞。積體電路101 透過第一端丁丨接收一輸入信號Srn ;積體電路1〇1之第二端丁2耦接 於一電壓源VDD(舉例而言，電壓源提供3.3V之電壓VDD);積 體電路ιοί之第三端τ'3耦接於一電壓源vss(舉例而言，電壓源Vss 提供0V之低電位之電壓Vss)。靜電保護電路10〇包括一 p型金氧 半導體(P-type channel metal oxide semiconductor, PM0S)電晶體 Qpi，以及一 N 型金氧半導體(N_type channel metal oxide semiconductor，NMOS)電晶體 Qni。PMOS 電晶體 QP1 包括一汲極 (D)、一源極⑸、一閘極(G)，以及一 N型井區(N-well)(W)。PMOS 電晶體Qpi之源極、閘極，以及N型井區皆搞接於積體電路ιοί之 第二端Τ'2 ’且PM0S電晶體Qpi之沒極麵接於積體電路ιοί之第一 端。NM0S電晶體QN1包括一》及極(D)、一源極⑸、一閘極(〇), 以及一 P型井區(Ρ-wellXW)。NM0S電晶體QN1之源極、閘極，以 及P型井區皆耗接於積體電路101之弟二端T?3，且NM0S電晶體 201212206201212206 VI. Description of the Invention: [Technical Field] The present invention relates to an electrostatic discharge protection circuit for increasing the voltage operating range of a signal input to an integrated circuit. [Prior Art.] Please refer to Figure 1. Fig. 1 is a circuit diagram showing a prior art electrostatic protection circuit 100. The electrostatic protection circuit 100 is lightly connected to the first end Τ, the second end A, and the third end 3 of the integrated circuit 101 to prevent the integrated circuit 101 from being damaged by static electricity. The integrated circuit 101 receives an input signal Srn through the first terminal D; the second terminal 2 of the integrated circuit 1〇1 is coupled to a voltage source VDD (for example, the voltage source provides a voltage VDD of 3.3V); The third terminal τ'3 of the integrated circuit ιοί is coupled to a voltage source vss (for example, the voltage source Vss provides a voltage Vss of a low potential of 0V). The electrostatic protection circuit 10A includes a p-type channel metal oxide semiconductor (PMOS) transistor Qpi and an N-type channel metal oxide semiconductor (NMOS) transistor Qni. The PMOS transistor QP1 includes a drain (D), a source (5), a gate (G), and an N-well (W). The source, gate, and N-well region of the PMOS transistor Qpi are connected to the second terminal Τ'2' of the integrated circuit ιοί and the immersed surface of the PM0S transistor Qpi is connected to the first circuit of the integrated circuit ιοί end. The NM0S transistor QN1 includes a "pole" (D), a source (5), a gate (〇), and a P-well (Ρ-wellXW). The source, gate, and P-type well regions of the NM0S transistor QN1 are both connected to the second terminal T?3 of the integrated circuit 101, and the NM0S transistor 201212206
Qni之汲極耦接於積體電路101之第一端Τι。如此’ pM〇s電晶踱 Qpi之寄生二極體1)(31>1耦接於積體電路101之第一端Τι與第二端 丁2之間，且NMOS電晶體W之寄生二極體〇_輕接於積體電絡 1之第知Τι與第二端丁3之間(如第1圖所示）^因此，當有主费 電於輸入端ENDrN產生時，寄生二極體Dqpi導通，使得正靜電玎逸 過導通之寄生二極體dqp1流向電壓源Vdd，如此，靜電保護電路1〇0 可消除正靜電。當有負靜電於輸入端ENE)in產生時，寄生二極體 φ DQni導通’使得負靜電可透過導通之寄生二極體Dqni流向電壓源 Vss，如此，靜電保護電路1〇〇可消除負靜電。 然而，當輸入信號SiN之電位較電壓vDD(3.3V)與寄生二極體 DQpi之導通電壓Vpw(約〇·7ν)之總和高時，寄生二極體D奶導通， 此時，輸入端£仙別與電壓源Vdd之間會產生一漏電流Iu，使得 輪入信號SrN從電壓源Vdd消散。同理，當電壓¥沾(3 3¥)減去寄生 •二極體Dqni之導通電壓Vfw(約0.7V)後之電位較輸入信號SiN高 寺寄生一極體DQN1導通，此時，輸入端ENDjn與電壓源之間 會產生一漏電流1L2，使得輸入信號Sin從電壓源vss消散。換句話 兒積體電路101之輸入信號Sw之電壓操作範圍被先前技術之靜 電保》蔓電路100限制在(VSS-VFW)〜(VDD+VFW)之間。此外，當輸入广 唬、之電位不在(vss-vFW)〜(vDD+vFW)之間時，在輸入端ENt^與 電壓源VDD(或vss)之間會產生漏電流。 /、 【發明内容】 5 201212206 本發明提供一種靜電保護電路。該靜電保護電路搞接於一積體 電路之一第一端與一第二端之間，以防止該積體電路受靜電損壞。 s亥靜電保護電路包括一第一 P型金氧半導體(P-typechannei metal oxide semiconductor, PMOS)電晶體，以及一深 N 型井區(Deep N-well)N 型金氧半導體(N-type channel metal oxide semiconductor， NMOS)電晶體。該第一 PMOS電晶體包括一汲極(D)、一源極(s)、 一閘極(G)，以及一 N型井區(N-well)。該第一 PMOS電晶體之該源 極耦接於該積體電路之該第一端。該第一 PM〇s電晶體之該閘極耦The first terminal of the integrated circuit 101 is coupled to the first end of the integrated circuit 101. Thus, the parasitic diode 1) of the 'pM〇s electro-crystal 踱 Qpi (1) is coupled between the first end 积ι of the integrated circuit 101 and the second terminal 2, and the parasitic diode of the NMOS transistor W The body 〇 is lightly connected between the first Τι of the integrated electrical system 1 and the second terminal ding 3 (as shown in Fig. 1). Therefore, when there is a main charge to the input terminal ENDrN, the parasitic diode Dqpi is turned on, so that the parasitic diode dqp1 that is positively discharged through the conduction current flows to the voltage source Vdd, so that the electrostatic protection circuit 1〇0 can eliminate positive static electricity. When there is negative static electricity generated at the input end ENE)in, the parasitic dipole The body φ DQni conducts 'so that the negative static electricity can pass through the parasitic diode Dqni which is turned on to the voltage source Vss, so that the electrostatic protection circuit 1 消除 can eliminate negative static electricity. However, when the potential of the input signal SiN is higher than the sum of the voltage vDD (3.3 V) and the turn-on voltage Vpw (about 〇·7ν) of the parasitic diode DQpi, the parasitic diode D milk is turned on, at this time, the input terminal is £ A leakage current Iu is generated between the fairy and the voltage source Vdd, so that the rounding signal SrN is dissipated from the voltage source Vdd. Similarly, when the voltage ¥3 (3 3¥) minus the parasitic diode Dqni's turn-on voltage Vfw (about 0.7V), the potential is higher than the input signal SiN high parasitic body DQN1, at this time, the input terminal ENDjn A leakage current 1L2 is generated between the voltage source and the voltage source so that the input signal Sin is dissipated from the voltage source vss. In other words, the voltage operation range of the input signal Sw of the integrated circuit 101 is limited by the prior art static protection circuit 100 between (VSS - VFW) ~ (VDD + VFW). In addition, when the input is wide and the potential is not between (vss-vFW) and (vDD+vFW), a leakage current is generated between the input terminal ENt^ and the voltage source VDD (or vss). /, [Summary of the Invention] 5 201212206 The present invention provides an electrostatic protection circuit. The electrostatic protection circuit is connected between the first end and a second end of an integrated circuit to prevent the integrated circuit from being damaged by static electricity. The shai electrostatic protection circuit includes a first P-type Channei metal oxide semiconductor (PMOS) transistor and a deep N-well N-type metal oxide semiconductor (N-type channel) Metal oxide semiconductor, NMOS) transistor. The first PMOS transistor includes a drain (D), a source (s), a gate (G), and an N-well. The source of the first PMOS transistor is coupled to the first end of the integrated circuit. The gate coupling of the first PM〇s transistor
接於該第一 PMOS電晶體之該汲極。該第一 PM〇s電晶體之該N 型井區耦接於該第一 PMOS電晶體之該汲極。該深n型井區nm〇s 電晶體包括一源極(S)、一汲極(D)、一閘極(G)、一 p型井區(p_well)， 以及一深N型井區。該深N型井區nmos電晶體之該源極耦接於 補體電狀該第二端。該㈣型井區丽⑽電晶體之該沒極麵 接於該第-PMOS電晶體之該没極。該深N型井區應〇§電晶體 之該閘極祕於該積體電路之料二端。該深N型井區丽〇§電 晶體之該P型井d祕於鱗N型井區丽〇;§電晶體之該源極。 該冰N型井區NM〇s電晶體之該㈣型井區絲涵蓋該p型井區。 該深N型井區NM〇S電晶體之該該㈣型井區祕至—第一賴 源。 【實施方式】 々。月參考第2 ®與第3 ®。第2圖為說明根據本發明第一實施例 之靜電保護電路200之示意圖。第3圖為靜電保護電路2〇〇之戴面 201212206 圖。在第3圖中’1ST1"表示N型摻雜(n-type doping)，P+表示P型摻雜 (P-type doping)。在第2圖中，靜電保護電路200耦接於積體電路101 之第一端乃與第二端T2之間’以防止積體電路受靜電損壞。積體 電路101之第一端1用來接收輸入信號Sw，積體電路1〇1之第二 端A耦接於電壓源Vss。靜電保護電路2〇〇包括一 PM0S電晶體 Qpi ’以及一深N型井區(deepN-well)NMOS電晶體QDN。PM0S電 晶體QP1包括一汲極(D)、一閘極(G)、一源極(S)，以及一 N型井區 隹（N_well)(W)。PM0S電晶體仏丨之源極耦接至積體電路1〇1之第一 端T〗’ PMOS電晶體QP1之汲極、閘極，以及N型井區皆耦接至深 N型井區NM0S電晶體QD^深]^型井區_〇；5電晶體Qdn包括 一汲極(D)、一閘極(G)、一源極⑻、一 p型井區(P_wdl)(w)，以及 一深N型井區。深N型井區電晶體Qdn之汲極耦接至pM〇s 電晶體QP丨之汲極。深N型井區NMO s電晶體Qdn之p型井區耦 接至深N型井區nmOS電晶體qdn之源極，深N型井區nm〇s電 _晶體QDN之源極與閘極皆耦接至積體電路1〇1之第二端A。如第3 圖所示冰N型井區電晶體qdn之深n型井區涵蓋p型井 區，且耦接至一高電位之電壓源(舉例而言，電壓源Vdd)。 、明參考第4圖與第5圖。第4圖與第5圖為說明靜電保護電路 〇〇 4除靜電之工作原理之示意圖。在第4圖中，假設正靜電那〇 自輸入端ENI^產生’由於正靜電侧之電位非常高，因此深n 尘井區NM0S電晶體qdn之寄生雙極性電晶體bTqdn導 通如此纟，正靜電+ESD透過導通的寄生二極體Don與導通的 201212206 寄生雙極性電晶體BTqDN流向電壓源Vss，使得靜電保護電路200 可消除正靜電+ESD。同理，在第5圖中，假設負靜電-ESD自輸入 端ENDjn產生，由於負靜電-ESD之電位非常高，因此PMOS電晶 體QdP1之寄生雙極性電晶體BTQDP1導通。如此一來，正電荷自電 壓源Vss透過導通的寄生雙極性電晶體BTqdpi與導通的寄生二極體 DqN流向輸入端ενΌϊν，以中和負靜電-ESD ’使得靜電保護電路2〇〇 可消除負靜電-ESD。 請參考第6圖與第7圖。第6圖與第7圖為說明靜電保護電路 20〇增加積體電路1〇1之輸入信號SlN之電壓操作範圍之示意圖。在 第6圖中，假設輸入信號Sw為1.5V，此時，PMOS電晶體Qpi之 寄生二極體DQP1導通。然而’由於深N型井區NMOS電晶體qdn 之寄生一極體Dqdn反向連接至寄生二極體DqP】，因此寄生二極體 Dqdn關閉。如此’輸入信號Sin透過第一端乃輸入至積體電路1〇1， 且不受靜電保護電路200影響。在第7圖中，假設輸入信號Sin為 •6V ’此時’深N型井區NMOS電晶體QDN之寄生二極體Dqdn導 通。然而，由於寄生二極體DqP1反向連接至寄生二極體£^咖，因 此寄生二極體Dqp1關閉。如此，輸入信號透過第一端丁1輸入至 積體電路101，且不受靜電保護電路200影響。由上述說明可知， 無哪輪入信號Sin之電位是高於或低於電壓源Vss所提供之電壓 Vss ’輪入信號SlN皆可透過第一端乃輸入至積體電路1〇1，且不受 靜電保護電路200影響。換句話說，相較於先前技術之靜電保護電 路1 〇〇 ’靜電保護電路200增加輪入信號之電壓操作範圍，此外， 201212206 還可避免積體電路101之第—端71與第二端了2之間產生漏電& 請參考第8圖、第9圖與第1〇圖。第8圖 第二實施例之靜電保護電路之電路圖。相較於=據本發明 圖^積體電路101之第二端τ2·至高電位之電壓源^在第8 〇 9 =2圖，在第9圖中，積體電路⑼之第二端τ =W電請之第—端Τι織至電壓源&。第= =月根據本發明第四實施例之靜電保護電路9〇〇之電路圖。相較 广2圖，在第1〇圖中’積體電路仙之第二端A用來接收輸入 域，且積體電路101之第—端Τι_至電壓源 護電路、_以及_之結構與工作原理與靜電保護電路2〇〇呆 類似’故不再贅述。靜電保護電路·、勘以及_可增加輸入信 旒Sw之電壓操作範圍，且可避免積體電路ι〇ι之第一端A與 端I之間產生漏電流。 。月參考第11圖。第11圖為說明根據本發明第五實施例之靜電 保護電路麵之示賴。相較於靜電保護電路2⑻，靜魏護電路 1000還包括-驅動電路麵雜接至深N型井區丽〇s電晶體如 之閘極。驅動電路誦包括-電容c，以及—電阻R。電容c之第 一端減至積體電路皿之第-端Τι，電容c之第二端耗接至深N 型井區NMQS電晶體QDN之閘極。飯端綠至深_ 井區NMOSt晶體QDN之閘極，電⑽之第二端耦接至積體電路 201212206 1〇1之第二端丁2。當正靜電+ESD自輸入端ΕΝΌϊν產生時，由於靜 電為高頻，因此電容C可視為短路。此時，深Ν型井區刪〇3電 晶體QDN之閘極可透過電容C接收一高電位之電壓。如此，深Ν型 井區NMOS電晶體qdn導通，而使得正靜電+ESD流向電壓源、 的速度增加。因此，相較於靜電保護電路2〇〇，靜電保護電路ι〇〇〇 可更快地消除正靜電+ESD。 請參考第12圖。第12圖為說明根據本發明第六實施例之靜電 保4電路1100之示意圖。相較於靜電保護電路2〇〇，靜電保護電路 _ 1100還包括-驅動電路1110·至深N型井區⑽ 之閘極。驅動電路1110包括一反相器_、一電容c，以及一電阻 R。反相器INV包括一 PM0S電晶體，以及一 電晶體Connected to the drain of the first PMOS transistor. The N-well region of the first PM〇s transistor is coupled to the drain of the first PMOS transistor. The deep n-type well region nm〇s transistor includes a source (S), a drain (D), a gate (G), a p-well (p_well), and a deep N-well region. The source of the deep N-type well region nmos transistor is coupled to the second end of the complement. The poleless face of the (4) well region (10) transistor is connected to the pole of the first PMOS transistor. The deep N-type well region should be the second end of the integrated circuit. The P-type well of the deep N-type well area is the secret of the scale N-type well area; § the source of the transistor. The (4) well zone wire of the NM〇s transistor of the ice N-type well region covers the p-type well region. The (N) type well region of the deep N-type well region NM〇S transistor is the first source. [Embodiment] 々. Refer to 2 ® and 3 ® for the month. Fig. 2 is a view showing the electrostatic protection circuit 200 according to the first embodiment of the present invention. Figure 3 is a diagram of the electrostatic protection circuit 2's wearing surface 201212206. In Fig. 3, '1ST1" indicates n-type doping, and P+ indicates P-type doping. In Fig. 2, the electrostatic protection circuit 200 is coupled between the first end of the integrated circuit 101 and the second end T2 to prevent the integrated circuit from being damaged by static electricity. The first terminal 1 of the integrated circuit 101 is used to receive the input signal Sw, and the second terminal A of the integrated circuit 101 is coupled to the voltage source Vss. The electrostatic protection circuit 2 includes a PM0S transistor Qpi' and a deep N-well NMOS transistor QDN. The PM0S transistor QP1 includes a drain (D), a gate (G), a source (S), and an N-well (N_well) (W). The source of the PM0S transistor is coupled to the first terminal of the integrated circuit 1〇1. The drain, gate, and N-type well region of the PMOS transistor QP1 are coupled to the deep N-well region NM0S. The transistor QD ^ deep ^ ^ type well _ 〇; 5 transistor Qdn includes a drain (D), a gate (G), a source (8), a p-type well (P_wdl) (w), and A deep N-type well area. The drain of the deep N-type well region transistor Qdn is coupled to the drain of the pM〇s transistor QP丨. The deep N-well NMO s transistor Qdn p-type well region is coupled to the source of the deep N-type well region nmOS transistor qdn, the deep N-type well region nm〇s electricity_crystal QDN source and gate are It is coupled to the second end A of the integrated circuit 1〇1. The deep n-well region of the ice N-type well region transistor qdn, as shown in Figure 3, covers the p-type well region and is coupled to a high potential voltage source (for example, voltage source Vdd). Refer to Figure 4 and Figure 5 for details. Fig. 4 and Fig. 5 are schematic diagrams showing the operation principle of the static electricity protection circuit 〇〇 4 in addition to static electricity. In Fig. 4, it is assumed that positive static electricity is generated from the input terminal ENI^ because the potential of the positive electrostatic side is very high, so the parasitic bipolar transistor bTqdn of the deep n-dwell region NM0S transistor qdn is turned on, and the static electricity is positive. +ESD flows through the turned-on parasitic diode Don and the turned-on 201212206 parasitic bipolar transistor BTqDN to the voltage source Vss, so that the electrostatic protection circuit 200 can eliminate positive static + ESD. Similarly, in Fig. 5, it is assumed that the negative electrostatic-ESD is generated from the input terminal ENDjn, and since the potential of the negative static-ESD is very high, the parasitic bipolar transistor BTQDP1 of the PMOS transistor QdP1 is turned on. In this way, the positive charge flows from the voltage source Vss through the turned-on parasitic bipolar transistor BTqdpi and the turned-on parasitic diode DqN to the input terminal ενΌϊν to neutralize the negative electrostatic-ESD', so that the electrostatic protection circuit 2 can eliminate the negative Static electricity - ESD. Please refer to Figure 6 and Figure 7. Fig. 6 and Fig. 7 are diagrams for explaining the voltage operation range of the input signal S1N of the integrated circuit 1〇1 by the electrostatic protection circuit 20〇. In Fig. 6, it is assumed that the input signal Sw is 1.5 V, and at this time, the parasitic diode DQP1 of the PMOS transistor Qpi is turned on. However, since the parasitic one body Dqdn of the deep N-type well region NMOS transistor qdn is reversely connected to the parasitic diode DqP, the parasitic diode Dqdn is turned off. Thus, the input signal Sin is input to the integrated circuit 1〇1 through the first terminal, and is not affected by the electrostatic protection circuit 200. In Fig. 7, it is assumed that the input signal Sin is ?6V' at this time, and the parasitic diode Dqdn of the deep N-type well region NMOS transistor QDN is turned on. However, since the parasitic diode DqP1 is reversely connected to the parasitic diode, the parasitic diode Dqp1 is turned off. Thus, the input signal is input to the integrated circuit 101 through the first terminal 1 and is not affected by the electrostatic protection circuit 200. It can be seen from the above description that the potential of no rounding signal Sin is higher or lower than the voltage Vss provided by the voltage source Vss. The rounding signal S1N can be input to the integrated circuit 1〇1 through the first end, and is not It is affected by the static electricity protection circuit 200. In other words, compared with the prior art electrostatic protection circuit 1 静电 'electrostatic protection circuit 200 increases the voltage operating range of the wheeling signal, in addition, 201212206 can also avoid the first end 71 and the second end of the integrated circuit 101 Leakage between 2 & Please refer to Figure 8, Figure 9, and Figure 1. Fig. 8 is a circuit diagram of the electrostatic protection circuit of the second embodiment. Compared with the voltage source of the second terminal τ2· to the high potential according to the present invention, in the eighth 〇9=2 diagram, in the ninth diagram, the second terminal τ of the integrated circuit (9) is W power please the first end - Τ woven to the voltage source & The == month circuit diagram of the electrostatic protection circuit 9A according to the fourth embodiment of the present invention. Compared with the wide 2 diagram, in the first diagram, the second terminal A of the integrated circuit is used to receive the input domain, and the first terminal Τι_ of the integrated circuit 101 is connected to the voltage source protection circuit, _ and _ It is similar to the working principle and the electrostatic protection circuit 2, so it will not be described again. The electrostatic protection circuit, the survey, and the _ can increase the voltage operation range of the input signal 旒, and can avoid leakage current between the first end A and the terminal I of the integrated circuit ι〇ι. . Refer to Figure 11 for the month. Fig. 11 is a view showing the surface of the electrostatic protection circuit according to the fifth embodiment of the present invention. Compared with the electrostatic protection circuit 2 (8), the static protection circuit 1000 further includes a driving circuit surface mixed with a deep N-type well region, such as a gate. The driving circuit 诵 includes a capacitor c and a resistor R. The first end of the capacitor c is reduced to the first end of the integrated circuit board, and the second end of the capacitor c is connected to the gate of the deep N-type well NMQS transistor QDN. The green end of the rice end is _ the gate of the QDN of the NMOSt crystal in the well area, and the second end of the electric (10) is coupled to the integrated circuit 201212206. When positive static + ESD is generated from the input terminal ΕΝΌϊν, since the static electricity is high frequency, the capacitance C can be regarded as a short circuit. At this time, the gate of the deep well type 3 transistor QDN can receive a high potential voltage through the capacitor C. Thus, the NMOS transistor qdn of the deep well region is turned on, and the velocity of the positive static +ESD flowing to the voltage source is increased. Therefore, the electrostatic protection circuit ι 〇〇〇 can eliminate positive static electricity + ESD faster than the electrostatic protection circuit 2 。. Please refer to Figure 12. Fig. 12 is a view showing the electrostatic protection 4 circuit 1100 according to the sixth embodiment of the present invention. The electrostatic protection circuit _ 1100 further includes a gate of the - drive circuit 1110· to the deep N-type well region (10) compared to the electrostatic protection circuit 2〇〇. The driving circuit 1110 includes an inverter _, a capacitor c, and a resistor R. The inverter INV includes a PM0S transistor, and a transistor
Qninv。PMOS電晶體QPINV之井區(weli)耦接至pM〇s電晶體仏請 之源極’ pmos電晶體(3歷之源極耦接至積體電路1〇1之第一端 ’ PMOS電晶體QP[NV之汲極耦接至深N型井區NM〇s電晶體 Qdn之閘極。NM0S電晶體QN騰之井區耦接至丽⑽電晶體qn腑 φ 之源極，NM0S電晶體QNINV之源極耦接至積體電路1〇1之第二端 丁2，NM0S電晶體Qnwv之汲極耦接至深N型井區電晶體 Qdn之閘極。電阻R之第一端耦接至積體電路1〇1之第一端Τι，電 阻R之第二端耦接至PMOS電晶體Qpnw之閘極與_〇§電晶體 Qninv之閘極。電容C之第一端耦接至PM〇s電晶體QprNv之閘極 與NM0S電晶體❽^^之閘極，電容c之第二端耦接至積體電路 101之第二端丁2。當正靜電+ESD自輸入端enDjn產生時，由於靜 10 201212206 電為高頻’因此電容c可視為短路。此時，PM0S電晶體Qpinv之 閘極與NMOS電晶體之閘極透過電容c接收電壓Vss(〇v)， 使得PMOS電晶體QPINV導通，且_〇8電晶體Qni^關閉。如此， 反相器INV輸出一尚電位之電壓，使得深：^型井區電晶體 Qdn導通。同理’此時深N型井區nm0S電晶體—增加正靜電 +ESD抓向電壓源vss的速度。也就是說，相較於靜電保護電路2〇〇， 靜電保護電路11〇〇可更快地消除正靜電+ESD。 綜上所述，本發明所提供之靜電保護電路雛於積體電路之第 -端與第二端之間’㈣止積體電路受靜f損壞。在積體電路之第 -端與第二端之中，-端用來讓積體電路接收—輸入信號，另一端 输至-糕源。本發明所提供之靜電保護電路包括—pM〇s電晶 體與-深N型井區_s電晶體。靜電保護電路透過觸§電曰^ 體與深N财區雇⑺f晶體之寄生二極酿寄生雙極性電^曰 2除靜電’且藉由PM〇S電晶體之寄生二極體反向連接於深_ 山品NMOS f晶體之寄生二極體，可避免積體電路之第—端與第二 m生r流。如此，靜電保護電路可防止積體電路受靜電損 壞’且增加輸人至麵桃之錢之賴操傾圍。 、 所做==7彻軸，膽她㈣專利範圍 所做之均料化與修飾，皆應屬本發明之涵蓋範圍。 【圖式簡單說明】 201212206 第1圖為說明先 ^ 第2圖為說明彳:之靜電保護電路之電路圖。 第3圖為說明第2固發明第—實施例之靜電保護電路之示意圖。 第4_第 ^靜電保護電路之截面圖。 之示意圖。說料2圖之靜電保護電關除靜電之工作原理 第二圖:第7圖為說明第2圖之靜 信號之電壓操作範圍之示意圖。 職電路之輸入 ==明根據本發明第二實施例之靜電保護電路之電路圖。 “明根據本發明第三實施例之靜電保護電路之電路圖。 第10圖為說日據本發邮四實施例之靜雜護電路之電路圖。 第11圖為說明根據本發㈣五實施例之靜絲護電路之示意圖。 第12圖為說明根據本發明第六實施例之靜電保護電路之示意圖。 【主要元件符號說明】 101 積體電路 100、200、700、800、 靜電保護電路 900、1000、1100 1010 、 1110 驅動電路 BTqdn、BTqdpi 寄生雙極性電晶體 c 電容 D 〉及極 Dqpi、Dqn1、Dqn 寄生二極體 12 201212206 END in 輸入端 G 閘極 Ili 、 Il2 漏電流 INV 反相器 Qpi、Qni、Qdn、 電晶體 Qpinv ' Qninv R 電阻 S 源極 Sin 輸入信號 乃、T2小2 端點 Vdd、Vss 電壓 W 井區 +ESD、-ESD 靜電 13Qninv. The well region (weli) of the PMOS transistor QPINV is coupled to the source of the pM〇s transistor, the pmos transistor (the source of the calendar is coupled to the first end of the integrated circuit 1〇1) PMOS transistor QP[NV's drain is coupled to the gate of NM〇s transistor Qdn in deep N-type well region. NM0S transistor QN is well connected to the source of MN(10) transistor qn腑φ, NM0S transistor QNINV The source is coupled to the second terminal of the integrated circuit 1〇1, and the drain of the NM0S transistor Qnwv is coupled to the gate of the deep N-type well region transistor Qdn. The first end of the resistor R is coupled to The first end of the integrated circuit 〇1 Τ1, the second end of the resistor R is coupled to the gate of the PMOS transistor Qpnw and the gate of the NMOS transistor Qninv. The first end of the capacitor C is coupled to the PM 〇 The gate of s transistor QprNv and the gate of NM0S transistor ,^^, the second end of capacitor c is coupled to the second end of integrated circuit 101. When positive electrostatic +ESD is generated from input terminal enDjn, Since the static 10 201212206 is high frequency, the capacitance c can be regarded as a short circuit. At this time, the gate of the PM0S transistor Qpinv and the gate of the NMOS transistor receive the voltage Vss(〇v) through the capacitor c, so that the PMOS transistor QPINV is turned on. And _〇8 transistor Qni^ is turned off. Thus, the inverter INV outputs a voltage of a potential, so that the deep Q: well type transistor Qdn is turned on. Similarly, 'the deep N-type well region nm0S transistor- increases Positive static + ESD captures the speed of the voltage source vss. That is, the electrostatic protection circuit 11 〇〇 can eliminate positive static + ESD faster than the electrostatic protection circuit 2 . In summary, the present invention The electrostatic protection circuit provided is between the first end and the second end of the integrated circuit '(4) The circuit of the integrated circuit is damaged by static f. Among the first end and the second end of the integrated circuit, the - end is used The integrated circuit receives the input signal and the other end is sent to the source of the cake. The electrostatic protection circuit provided by the invention comprises a -pM〇s transistor and a deep N-well _s transistor. The electrostatic protection circuit passes through the § Electric 曰 ^ body and deep N financial district employs (7) f crystal parasitic dipole brewing parasitic bipolar electric ^ 曰 2 static electricity ' and is connected to the deep by the parasitic diode of PM 〇 S transistor _ Yamamoto NMOS f The parasitic diode of the crystal can avoid the first end of the integrated circuit and the second m raw r flow. Thus, the electrostatic protection circuit can prevent The integrated circuit is damaged by static electricity' and increases the cost of the input to the face of the peach. The ==7 is the axis, and the uniformization and modification of the patent range is the invention. Coverage: [Brief Description] 201212206 Fig. 1 is a schematic diagram of the first embodiment. Fig. 2 is a circuit diagram illustrating the electrostatic protection circuit of Fig.: Fig. 3 is a diagram showing the electrostatic protection circuit of the second embodiment of the second invention. Schematic diagram of the 4th -th ^ electrostatic protection circuit. Schematic diagram. The working principle of static electricity protection and static elimination in the picture 2 is shown in the second figure: Figure 7 is a schematic diagram illustrating the voltage operating range of the static signal in Figure 2. Input of the job circuit == A circuit diagram of the electrostatic protection circuit according to the second embodiment of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 10 is a circuit diagram of a static protection circuit according to a fourth embodiment of the present invention. FIG. 11 is a diagram illustrating a fifth embodiment according to the present invention. Fig. 12 is a schematic view showing an electrostatic protection circuit according to a sixth embodiment of the present invention. [Description of Main Components] 101 Integrated Circuits 100, 200, 700, 800, Electrostatic Protection Circuits 900, 1000 , 1100 1010 , 1110 drive circuit BTqdn , BTqdpi parasitic bipolar transistor c capacitor D 〉 and pole Dqpi, Dqn1, Dqn parasitic diode 12 201212206 END in input terminal G Ili , Il2 leakage current INV inverter Qpi, Qni, Qdn, transistor Qpinv 'Qninv R resistance S source Sin input signal, T2 small 2 terminal Vdd, Vss voltage W well + ESD, -ESD static 13