TW201212131A - Methods of forming bonded semiconductor structures, and semiconductor structures formed by such methods - Google Patents

Abstract

Methods of forming bonded semiconductor structures include temporarily, directly bonding together semiconductor structures, thinning at least one of the semiconductor structures, and subsequently permanently bonding the thinned semiconductor structure to another semiconductor structure. The temporary, direct bond may be established without the use of an adhesive. Bonded semiconductor structures are fabricated in accordance with such methods.

Description

201212131, VI. Description of the Invention: [Technical Field of the Invention] Embodiments of the present invention generally relate to a method of forming a bonded semiconductor structure, and a resultant structure formed using the methods. [Prior Art] Three-dimensional (3D) integration of two or more semiconductor structures can yield many benefits for microelectronic applications. For example, the integration of microelectronic components can improve electrical performance and power consumption while reducing device footprint. 〇 See, for example, Ρ· Garr〇U et al. “The Handbook of 3D Integrati〇n”,

Wiley-VCH (2008). Connecting a semiconductor die to one or more semiconductor wafers (ie, die by attaching - semiconductor die to - or a plurality of other semiconductor die (ie, die to die (D2D)) To wafer (D2W), and to connect a semiconductor wafer to - or a plurality of other semiconductor wafers (ie, wafer to wafer (W2W)), or a combination thereof, to perform a semiconductor structure. Wafers can be relatively thin and difficult to process, so the so-called "carrier j grains or crystals" are included in the actual die or wafer.

Typically, individual semiconductor dies or dies or wafer devices are disposed of. The circle can be connected to the main pure and passive components of the actual die or wafer semiconductor H piece. The carrier grains or wafers typically do not include any active or passive components of the semiconductor device to be formed. The carrier dies and wafers are referred to herein as "carrier substrates." The bulk substrate increases the total thickness of the die or wafer and facilitates handling of the die or wafer by processing equipment for processing the active or/or passive components in the wafer or wafer to which it is attached, The die or wafer will include active and passive components for the fabrication of the 156587.doc 201212131 semiconductor device. Including the dies or wafers on which the active and/or passive components of the semiconductor device are to be fabricated, or which will ultimately include the active and/or passive components of the semiconductor device on which the semiconductor device is to be fabricated, upon completion of the fabrication process The die or wafer is referred to herein as a "device substrate." The carrier substrate is typically attached to the device substrate using an adhesive. A die or method for bonding an active component and/or a passive component including one or more semiconductor devices to another active component and/or passive component of one or more semiconductor devices may also be used using a similar bonding method. On the die or wafer. Adhesives commonly used to bond one die or wafer (eg, a carrier substrate) to another die or wafer (eg, a device substrate) can be fabricated in a die or wafer - or multiple semiconductors There are problems in the subsequent processing steps of the active and/or passive components of the device. SUMMARY OF THE INVENTION Embodiments of the present invention can provide methods and structures for forming semiconductor structures and, more particularly, methods and structures for forming bonded semiconductor structures. The present invention is provided to introduce a conceptual selection in a simplified form, which is further described in the embodiments of the embodiments of the invention. The present invention is not intended to identify key features or essential features of the claimed subject matter. In some embodiments of the invention, the method of forming a bonded semiconductor includes providing a direct atomic or molecular bond between a bonding surface of the first semiconductor structure and a bonding surface of the first 'body structure to make 156587.doc 201212131 A semiconductor structure is temporarily bonded to a second semiconductor structure. The first semiconductor structure can be selected such that it has an active surface on a first side of the first semiconductor structure and a back SUrface on a second, opposite side of the first semiconductor structure, and first The semiconductor structure includes at least one device structure formed over the 'substrate. The substrate of the first semiconductor structure can be thinned by removing the material of the substrate from the back surface of the first semiconductor structure. The first semiconductor, the back surface of the structure can be permanently bonded to the surface of the third semiconductor structure while the substrate of the first semiconductor structure is thinned while the first semiconductor structure is still temporarily bonded to the second semiconductor structure. The second semiconductor structure can then be separated from the first semiconductor structure. In other embodiments of the invention, a method of forming a semiconductor structure includes temporarily bonding a first semiconductor structure to a second semiconductor structure without using an adhesive between a bonding surface of the first semiconductor structure and a bonding surface of the second semiconductor structure . The first semiconductor structure can be selected such that it has an active surface on a first side of the first semiconductor structure and a back surface on the 〇=' opposite side of the first semiconductor structure and the first semiconductor structure comprises a substrate At least one device structure. The back surface of the first semiconductor structure can be permanently bonded to the surface of the second semiconductor structure while the first semiconductor. The structure is still temporarily bonded to the second semiconductor structure. The second semiconductor structure can then be separated from the first semiconductor structure. Embodiments of the present invention also include a package of a (four)-semi-four structure and a second semiconductor structure having a temporary bonding = a +-conductor structure (with no adhesive therebetween), and a structure of the first semiconductor structure. The first side has an active surface and has a 156587.doc 201212131 back surface on the second, opposite side of the first j^ jaiL > The first semiconductor structure includes a substrate and at least one device structure formed over the substrate. The bonding energy between the first semiconductor structure and the second semiconductor structure is about 1,000 mJ/m2 or 1, 〇〇〇mJ/m2 or less. The third semiconductor structure is permanently bonded to the back surface of the first semiconductor structure, and the bonding energy between the first semiconductor structure and the third semiconductor structure is at least about (9) mJ/m2 °. [Embodiment] Referring to the following embodiments of the present invention The detailed description of the embodiments of the invention can be more fully understood from the accompanying drawings. The illustrations provided herein are not intended to be an actual view of any particular material, device, system, or method, and are merely intended to describe an ideal representation of an embodiment of the invention. Any headings used herein are not to be construed as being limited to the embodiments of the invention as defined by the following claims. The concepts described in any special issue are generally applicable throughout the rest of the specification. The entire disclosure of the entire disclosure is hereby incorporated by reference in its entirety in its entirety in its entirety. In addition, the prior art of the subject matter of the present invention, which is hereby incorporated by reference, is hereby incorporated by reference. The term "semiconductor structure" means and includes a structure for forming a circle d (tetra) H (four), including, for example, a die and a wafer (10) such as a carrier substrate and a device substrate, and includes two mutually different ones, two or more A. ―, quasi-integrated die and/or wafer assembly or composite structure. The semi-conductor 156587.doc 201212131 also includes a fully fabricated semiconductor device and an intermediate structure formed during the fabrication of the semiconductor device. As used herein, the term "processed semiconductor structure" means and includes <> contains: or more (five) any semiconductor structure that at least partially shapes the t device structure. The processed semiconductor structure is a sub-structure of the semiconductor structure, and all of the processed semiconductor structures are semiconductor structures. As used herein, the term "bonded semiconductor structure" means and includes any structure comprising more than one semiconductor structure connected thereto. The bonded semiconductor structure is a subset of the semiconductor structure, and all bonded semiconductor structures are Semiconductor structure. In addition, bonded semiconductor structures including one or more processed semiconductor structures are also processed semiconductor structures. As used herein, the term "device structure" means and includes any portion of a processed semiconductor structure. The processed semiconductor structure includes or defines a semiconductor device to be formed on or in a semiconductor structure. Partial active or passive components. For example, the device structure includes active components and passive components of integrated circuits such as transistors, converters, capacitors, resistors, conductive traces, conductive vias, and conductive contact pads. As used herein, the term "through-wafer interconnect" or "top" means and includes any extending through at least a portion of the first semiconductor structure; electrical flux 2 for use in the first semiconductor structure and the second semiconductor structure Structural interconnections or electrical interconnections are provided across the interface between the first semiconductor structure and the second semiconductor organization. In this technology, the terms are used to interpenetrate, such as "through the hole", "through the substrate through hole", "== 156587.doc 201212131 ® through hole", or abbreviations of such terms, such as "τ TWi is usually in general The main main flaw with the semiconductor structure." In the straight direction (that is, in conjunction with the "2" :: face-down conductor structure. < million gates) extending through the half "such as: used" when using the active surface with respect to the processed semiconductor structure" means and includes Processed semiconductor: To a surface, the semiconductor structure that has been processed or to be processed by the processed semiconductor structure forms one or more device structures in the major surface of the exposed surface and/or the exposed major surface. As used herein, with respect to a processed semiconductor structure, the "back surface" means and includes the exposed surface of the processed semiconductor structure, the surface of the filament being on the opposite side of the active surface of the semiconductor structure on the processed semiconductor structure. The term "m_v semiconductor material" as used herein means and includes mainly one or more elements (BA Bu GaIn and T1) from Group IIIA of the periodic table and one or more elements from the periodic table family ( N, p, &,

Any material of Sb and Bi). As used herein, the term "thermal expansion coefficient" when used in reference to a material or structure means the average linear thermal expansion of the material (four) structure at room temperature. Embodiments of the invention include methods and structures for forming semiconductor structures and, more particularly, semiconductor structures including bonded semiconductor structures, and methods of forming such bonded semiconductor structures. Embodiments of the methods and structures of the present invention can be used for various purposes, such as for the 3〇 integration process 156587.doc 201212131 and for forming a 3D integrated structure. Exemplary embodiments of the present invention are described below with reference to Figures 1A-1E. Figure ia illustrates a processed semiconductor structure 100. The processed semiconductor structure 1 〇〇 can include a plurality of device structures HM. The device structure 1G4 is formed in the substrate 1 (6) and/or formed over the substrate 106. Substrate 1 6 may comprise one or more materials. The material 4 may comprise, for example, a semiconductor material such as germanium (8), germanium (Ge), m_v semiconductor material or the like. Further, the substrate 1〇6 may comprise a single crystal of a semiconductor material or a layer of a semiconductor material of a semiconductor material. In other embodiments, the substrate 〇6 may comprise one or more dielectric materials such as an oxide (eg, cerium (Si 2 ) or aluminum oxide (Al 2 〇 3)), a nitride (eg, tantalum nitride ( Si3N4) or boron nitride (7) N)) and the like. As shown in FIG. 1A, the device structure 1 〇 4 includes a plurality of Twi 1 〇 5. Each TWI 105 can comprise a generally cylindrical (e.g., cylindrical) structure comprising a conductive material such as one or more metals or metal alloys. Each Twi丨〇5 may also comprise a multi-layer or multi-region structure comprising, for example, a transition zone, a barrier zone, a Q-conducting zone, etc., each of which may comprise a different material. The processed semiconductor structure 100 includes an active surface 108 and a back surface 11A. The back surface 110 of the processed semiconductor structure 100 can comprise a substantially planar, exposed major surface of the substrate 1〇6. The active surface 108 of the processed semiconductor structure 100 may comprise a dielectric material 109 such as an oxide (eg, cerium (Si 2 ) or aluminum oxide (Al 2 〇 3)), a nitride (eg, tantalum nitride (Si 3 N 4 )). Or boron nitride (BN)). 1B illustrates a bonded semiconductor structure 12 that can be formed by temporarily bonding the processed semiconductor structure 100 of FIG. 8 to another semiconductor structure 122, 156587.doc 201212131. Semiconductor structure 122 can comprise, for example, a carrier substrate. For example, semiconductor structure 122 can comprise a semiconductor material such as germanium (si), germanium (Ge), πι-ν semiconductor materials, and the like. The semiconductor structure 122 may optionally comprise an epitaxial layer of a single crystal or semiconductor material of a semiconductor material. In other embodiments, the semiconductor structure 122 may comprise one or more dielectric materials such as an oxide (eg, yttrium oxide (Si 〇 2) or aluminum oxide (Al 2 〇 3)), a nitride (eg, tantalum nitride (Si 3 N 4 ) ), nitrided collar (BN) or aluminum nitride (A1N), and the like. Semiconductor structure I. The selected material is included such that the exhibited coefficient of thermal expansion is at least substantially equal to the coefficient of thermal expansion exhibited by the semiconductor structure 1 of FIG. 1A (eg, about twenty percent of the coefficient of thermal expansion exhibited by the semiconductor structure 100) Within (20%)). Continuing to refer to FIG. 1B, the processed semiconductor layer can be processed by direct bonding of atomic bonds or molecular bonds between the bonding surface of the semiconductor structure and the bonding surface of the semiconductor structure 丨22. The semiconductor structure 1 is temporarily bonded directly to the semiconductor structure 122. In other words, the processed semiconductor structure (10) can be temporarily bonded directly to the semiconductor structure 122 without the use of an adhesive or any other intermediate bonding material between the processed semiconductor structure loo (Fig. 1A) and the semiconductor structure 122. The atomic or molecular bond between the processed semiconductor structure and the semiconductor structure (IV) depends on the material composition of each of the semiconductor structure 100 and the semiconductor structure 122 to be processed. Thus, direct atomic or molecular bonds may be provided between at least one of, for example, cerium oxide and cerium oxide and at least one of cerium, lanthanum, cerium oxide and cerium oxide, according to some embodiments. The semiconductor structure 100 is exemplified by a conventional example and without limitation 156587.doc -10- 201212131 The moving surface 108 may comprise an oxide material (eg, cerium oxide (SiO 2 )), and the semiconductor structure 122 may at least substantially comprise The same oxide material (for example, cerium oxide (SiO 2 )). In such embodiments, the active surface 108 of the semiconductor structure 100 can be bonded to the bonding surface 124 of the semiconductor structure 122 using a yttria-yttria surface direct bonding process. Bond strength can be defined as the ability of a bonded semiconductor structure to undergo delamination of the interface caused by an external load. Bond strength can be characterized by specific bonding (surface) energy. Bonding energy can also be defined as the average specific surface energy of the two joined surfaces of the bonded semiconductor structure (designated symbol y) and equal to the energy required to separate the two joined surfaces, ie, where Y = 1 / 2 nEb, where η is the number of joints (joining density) formed per unit area and Eb is the energy of each joint. A common method of measuring joint strength is to test geometry using a double cantilever beam under constant wedge conditions. A wedge of thickness h is inserted at the joint interface between the two crystal circles of thickness t to disengage the region of the crack length L. The surface energy is then calculated using the following simple formula:

3h2Et3 V =- 32I4 Additional information on this common method can be found in the following publications: Maszara et al., J. Appl. Phys., 64, 4943 (1988) and Tong et al., Semiconductor Wafer Bonding: Science and technology, 27th Page, Wiley, New York (1999). The direct temporary bonding established between the active surface 108 of the semiconductor structure 100 and the bonding surface 124 of the semiconductor structure 122 can result in a relationship between about 10 156587.doc • 11·201212131 mJ/m 2 and about 1,000 mj/m 2 . The bonding energy between the active surface 108 of the semiconductor structure and the bonding surface 124 of the semiconductor structure 122. More specifically, the direct temporary bonding between the active surface 1 8 of the semiconductor structure 100 and the bonding surface 124 of the semiconductor structure can result in a semiconductor structure 1 between about 300 mJ/m 2 and about 700 mj/m 2 . The bonding energy between the active surface 108 of the crucible and the bonding surface 124 of the semiconductor structure 122. In some embodiments, the active surface 1 8 of the processed semiconductor structure 100 having a relatively smooth surface and the bonding surface 124 of the semiconductor structure can be formed, and then the active surface 1 8 and the bonding surface 124 can be formed. The direct temporary engagement between the active surface 1 8 of the semiconductor structure 100 and the bonding surface 124 of the semiconductor structure 122 is established adjacent to and maintaining contact between the active surface 1 8 and the bonding surface 124 during annealing. For example, the root mean square surface roughness (Rrms) can be formed to be about 2 nanometers (2.0 nm) or less, about 1 nanometer or less, or even about a quarter of nanometers. The active surface 108 of the semiconductor structure (0. 25 nm) or less than a quarter nanometer and the bonding surface 124 of the semiconductor structure 122. In some embodiments, the root mean square surface roughness (Rrms) may be formed between about one quarter nanometer (0-25 nm) and about 2 nanometers (2 〇 nm), or even about two The active surface 1 〇 8 of the semiconductor structure 100 and the bonding surface 124 of the semiconductor structure 122 between one nanometer (0.5 pm) and about 1 nanometer (1 〇 nm). The annealing system may be included in the furnace to heat the semiconductor structure 1 and the semiconductor structure 122 at a temperature between about 1 celsius and about 4 mils (about 4 Torr) for about 2 minutes (2 min). Approximately 15 hours (15 hr) of the time between 156587.doc •12·201212131. As described above, using at least one of the mechanical polishing process and the chemical remnant process, the active of each relatively smooth semiconductor structure 100 can be formed. The surface and the bonding surface 124 of the semiconductor structure 122. For example, a chemical mechanical polishing (CMP) process can be used to planarize each of the active surface 10 of the semiconductor structure 1 and the bonding surface 124 of the semiconductor structure 122. And/or reducing the surface roughness. At least one of the active surface 108 of the semiconductor structure and the bonding surface 124 of the semiconductor structure 122 may be activated to increase the active surface 108 and the semiconductor structure 122 of the semiconductor structure The bonding between the bonding surfaces ι 24 can then establish a direct temporary bonding along the bonding interface 126 therebetween. In other words, the main body of the semiconductor structure 100 can be selectively changed first. The surface chemistry of at least one of surface 1 〇 8 and bonding surface 124 of semiconductor structure 122 is followed by a temporary direct bond therebetween. Surface chemistry can be altered to bond semiconductor structure 1 active surface 108 to semiconductor structure 122 The bonding at the interface between the bonding surfaces 124 can be selectively adjusted to the extents mentioned herein. As a non-limiting example, a plasma activation process can be used to activate the active surface 108 and semiconductor of the semiconductor structure 1 At least one of the bonding surfaces 124 of the structure 122. The electricity activation process can be performed in the plasma chamber according to the following conditions: - gas of oxygen, nitrogen, argon or helium flows between 〇 and 1 〇〇 sccm (eg between 50 and 75 sccm); power between 25 and 2500 watts (eg between 150 and 1000 watts); pressure between 20 and 200 milliTorr (mTorr) (eg 50 and 100 mTorr 156,587. Doc •13·201212131); and the exposure time is between 5 and 5 minutes (eg between 〇 and 6 〇). In some embodiments, the processed semiconductor structure and semiconductor junction Only one of 122 may be subjected to a surface activation process as described above, and the other may not be subjected to a surface activation process to selectively adapt the bonding energy between the processed semiconductor structure 1 and the semiconductor structure 122 and/or The likelihood of inadvertently forming a permanent bond therebetween is reduced. Further, at least one of the active surface 108 of the processed semiconductor structure and the bonding surface 124 of the semiconductor structure 122 may be subjected to one or both prior to the annealing process. A plurality of cleaning processes. For example, the active surface 1 8 and the bonding surface 124 can be cleaned to remove organic contaminants and/or ionic contaminants. In embodiments where the active surface 108 and the bonding surface 124 comprise a material that is not an oxide but is susceptible to oxidation, the active surface 1 8 and the bonding surface 124 may be subjected to an oxide stripping process. As a non-limiting example, the processed semiconductor structure germanium and semiconductor structure 122 can be immersed in deionized (DI) water, which can then be at about 5 degrees Celsius (50 C) and about 80 degrees Celsius (80 ° C). At a temperature between them, it is immersed in a solution of 1:1:5 ammonium hydroxide (NH4〇H), hydrogen peroxide (H2〇2) and water (h2〇) for about 1 minute (1 min) ) with about 15 minutes (1 5 min). This first cleaning process can result in the formation of a thin layer of dioxide on the treated surface. The processed semiconductor structure 100 and semiconductor structure m can then be returned to a deionized (DI) water bath, which can then be between about 20 degrees Celsius (2 〇 = c) and about 3 degrees Celsius (30 C) Immerse it in a 1:5 氢 solution of hydrofluoric acid (hf) and water (H2 〇) at a temperature for about 1 〇 sec (1 〇 sec) and about 5 minutes (5 min) of 156587.doc -14 · 201212131. This cleaning process removes any of the dioxide layer formed by the first cleaning process and some ionic contaminants. The processed semiconductor structure 100 and semiconductor structure 122 can then be returned to a deionized (DI) water bath, which can then be at a temperature between about 50 degrees Celsius (5 (TC) and about 80 degrees Celsius (8 CTC). • It is immersed in a 1:1:6 solution of hydrochloric acid (HC1), hydrogen peroxide (h2〇2) and water (h20) for about 1 minute (i min) and about 15 minutes (15 min). This cleaning process removes any residual ionic contaminants (eg, metal ions). In some embodiments, the processed semiconductor structure 1 and semiconductor junctions

Only one of the II structures 122 can be subjected to the cleaning process as described above, and the other may not be subjected to the cleaning process, thereby reducing the likelihood of inadvertently forming a permanent joint therebetween. In other embodiments, a direct temporary bond can be established between the active surface 108 of the processed semiconductor structure 1 and the bonding surface 124 of the semiconductor structure 122 using the method described below with reference to Figures 3 and 4. In the method described with reference to Figures 3 and 4, a bonded interface region can be formed between the active surface 10 08 of the processed semiconductor structure 1 and the bonding surface 124 of the semiconductor structure 122, and the The bonded interface region is selected to be less than the total area of the bonding interface 26 between the active surface 108 of the processed semiconductor structure 1 and the bonding surface 124 of the semiconductor structure 122. The bonded interface region is defined as the region between the processed semiconductor structure 1 and the semiconductor structure 122, with direct atomic bonds and/or molecular bonds present thereon. For example, the bonded interface region between the active surface 108 of the processed semiconductor structure 1 and the bonding surface 124 of the semiconductor structure 122 can be selectively formed to be less than the active semiconductor structure. Table 156587.doc 201212131 Face 108 and semiconductor structure! The joint surface 124 of the joint surface 124 is between about eighty percent of the total area of the joint interface 126, less than about fifty percent (50%) of the total area, or even less than about two percent of the total area. Ten (20%) 减小 is to reduce the bonded interface region between the processed semiconductor structure 1 and the semiconductor structure m, which can be bonded to the active surface 108 and the semiconductor structure 122 of the processed semiconductor structure 1 A plurality of recesses are formed over or at least one of at least one of the surfaces 124. For example, Figure 3 illustrates a plurality of recesses 〇3〇 formed on the semiconductor structure 122. The recess 130 can be formed by patterning the semiconductor structure 122 or the material provided on the semiconductor structure 122. For example, a dielectric material 128 (eg, an oxide material layer such as cerium oxide (Si 2 )) may be formed over the semiconductor structure 122 and the dielectric material 128 may be patterned using a masking and etching process to A recess 130 is formed in the dielectric material 128. A patterned mask layer can be formed over the dielectric material 128 using a photolithography process known in the art. The patterned mask layer can include apertures that pass through locations where it is desired to form recesses 130 in the underlying dielectric material 128. Subsequently, the dielectric material 128 exposed through the holes in the overlying patterned mask layer can be subjected to an etchant using a wet chemical etch process or a dry reactive ion etch process. Optionally, a recess (such as a recess 13 on the semiconductor structure 122) may be formed in or on the active surface 1 8 of the processed semiconductor structure. Referring to FIG. 4, after the recess 130 is formed in or on one or both of the bonding surface 124 of the semiconductor structure 122 and the active surface 108 of the processed semiconductor structure 100, the processed semiconductor structure can be actively activated. Surface 156587.doc • 16 - 201212131 108 establishes a direct temporary engagement with the bonding surface 丨 24 of the semiconductor structure 122 as previously described with respect to FIG. As shown in FIG. 4, the bonded interface region between the processed semiconductor structure 100 and the semiconductor structure 122 is a region over which the dielectric material 128 abuts the active surface 108 of the processed semiconductor structure 1 ( This area is not covered by the recess 230).

As in Figure 4, the active surface 108 of the processed semiconductor structure may include exposed conductive features 1 (e.g., bonding turns, traces, etc.). The electrically conductive device features 1G4 may comprise, for example, a metallic material (i.e., a metal or metal alloy). In such embodiments, the plurality of recesses 130 can be patterned to select a mirror image of the pattern of conductive features. Thus, the recess (10) can be aligned with the conductive feature 104 when the temporary bonding between the processed semiconductor structure 1 and the semiconductor structure 122 is established. The bonding between the cured semiconductor structure (10) and the semiconductor structure (2) can be established. Between the dielectric material 128 of the semiconductor structure m surrounding the conductive device feature at the active surface 108 of the processed semiconductor structure 1 and the processed semiconductor gentleman conductor, the dielectric material 109 of the structure 100 Direct atomic or molecular bond. In these embodiments, the material of the conductive device feature 104 may not be in contact with the semiconductor structure 122 in any manner, such as during the bonding process, thereby preventing conduction. Device features 1 〇 4, 备 104 104 rolled and/or other forms of characteristic degradation, which may occur when the semiconductor structure 100 is bonded to the semiconductor structure 122. In other embodiments, the bonding surface 124 of the active semiconductor structure 1 and the semiconductor structure 156587.doc -17-201212131 122 may be used in the processed semiconductor structure 1 using the method described below with reference to FIGS. 5-7. A direct temporary engagement is established between them. In the method described with reference to FIGS. 5 through 7, as in the method described with reference to FIGS. 3 and 4, the bonding surface 124 of the active surface 1 8 and the semiconductor structure 122 of the processed semiconductor structure 1 can be A bonded interface region is formed therebetween, the bonded interface region being selected to be less than the bonding interface 126 between the active surface 1 8 of the cured semiconductor structure ι and the bonding surface Η* of the semiconductor structure 122 The total area. In addition, as described with respect to FIGS. 3 and 4, a plurality of at least one or at least one of the active surface 1 8 of the processed semiconductor structure 1 and the bonding surface 124 of the semiconductor structure 122 may be formed. The recess 130 reduces the bonded interface region between the processed semiconductor structure 1 and the semiconductor, -= structure 122. For example, Figure $ illustrates a recess 13 形成 formed in the semiconductor structure 122. The recess 130 can be formed as previously described with respect to Figure 3. A recess (such as a recess 130 on the semiconductor structure 122) may also be formed in or on the active surface 108 of the processed semiconductor structure, as appropriate, as shown in FIG. 5, at the bonding surface 124 of the semiconductor structure 122. Another dielectric material 129 is provided over the dielectric material 128 over a region other than the upper recess 130. Dielectric material 129 may be provided over dielectric material 128 prior to forming recess 13〇. In other words, a dielectric material can be provided (eg, deposited) over the dielectric material 128 on the bonding surface 124 of the semiconductor structure 122, and a plurality of recesses 130 can be formed through the dielectric material 129 and at least a portion of the dielectric material 128. . In other embodiments, the dielectric material 129 can be provided over the dielectric material 128 after the recess 13 is formed. In these embodiments, it may be only concave. A dielectric material 129 is provided over the surface of the dielectric material us other than 卩130, rather than over the surface of the dielectric material 128 within the recess "ο 156587.doc -18 - 201212131. In some embodiments, optionally a dielectric material 128 of a high temperature dielectric material, and optionally a dielectric material 129 comprising a low temperature dielectric material. As used herein, the term "low temperature dielectric material" means and includes heating to below & Any of the dielectric materials that will undergo at least one of degradation, decomposition, and deflation at the known temperature. As used herein, the term "high temperature dielectric material" means, and is included, heated to four degrees Celsius. (4 〇〇 (> c ) does not pass through any dielectric material that degrades, decomposes, and deflates. As a non-limiting example, the high temperature dielectric material 128 may comprise an oxide (eg, cerium oxide (Si) 〇 2) or alumina (A12〇3)) or nitride (such as tantalum nitride (Si3N4), boron nitride (BN) or aluminum nitride (A1N)). As a non-limiting example, low temperature dielectric material 129 It may contain TEOS or polymer materials. As shown in FIG. 6, a low temperature dielectric material 129 may also be provided over one or more regions of the active semiconductor structure 1 of the processed semiconductor structure. For example, the port is as mentioned in the prior art, in some implementations. In an example, the active surface 108 of the processed semiconductor structure can include exposed conductive features 1〇4 (eg, CT pads, traces, etc.). In such embodiments, masking and etching can be used. The process patterning the low temperature dielectric material 129 to form a recessed neighbor 104 in the dielectric materials 129 and 128. The patterned mask layer can be formed over the dielectric material 129 using a photolithography process known in the art. The patterned mask layer can include apertures that pass through locations where it is desired to form recesses 1 〇 4 in the underlying dielectric materials 129 and 128. Subsequently, wet chemical remnants can be used. The process or dry reactive ion engraving process exposes the dielectric materials 129 and 128 exposed through the vias in the overlying mask 156587.doc • 19_201212131 to the etchant. As shown in FIG. Materials 129 and 128 do not cover the exposed leads in any significant way Electrical device feature 104'. Referring to Figure 7 'after providing low temperature dielectric material 129 over at least one of active surface log of semiconductor structure 100 and bonding surface 124 of semiconductor structure 122' and at bonding surface 124 of semiconductor structure 122 And after forming the recess 130 in one or both of the active surface 108 of the processed semiconductor structure 100 or between the active surface 108 of the processed semiconductor structure and the bonding surface 124 of the semiconductor structure 122 Establish a direct temporary engagement as previously described with respect to Figure 3. As shown in FIG. 7, the bonded interface region between the processed semiconductor structure 100 and the semiconductor structure 122 is a region over which the dielectric material 128 abuts the active surface 108 of the processed semiconductor structure 1 ( That is, 'this area is not occupied by the recess 13〇). As previously described with respect to Figures 3 and 4, a plurality of recesses 丨3〇 can be patterned to select a mirror image of the pattern of conductive features 1〇4. Thus, the recess 130 can be aligned with the conductive features 1 〇 4 when a temporary bond is established between the processed semiconductor structure 1 〇〇 and the semiconductor structure 122. The bond established between the processed semiconductor structure 100 and the semiconductor structure 122 may comprise a direct atomic bond between the low temperature dielectric material 129 of the semiconductor structure 122 and the low temperature dielectric material 109 of the processed semiconductor structure 1 or Molecular bond. In such embodiments, the material of the features of the conductive features may not contact the semiconductor structure 122 in any significant manner during the bonding process, thereby preventing the conductive device features 104 from oxidizing and/or exhibiting other forms of characteristic degradation. These phenomena may otherwise occur when the machined semiconductor structure 150 is bonded to the processed semiconductor ide 156587.doc • 20-201212131. When the semiconductor structure 122 is temporarily bonded to the processed semiconductor structure 1 'the semiconductor structure 122 and the processed semiconductor structure 1 ' can be heated to at least a known temperature at which the low temperature dielectric material 129 will experience At least one of degradation, decomposition, and deflation. Thus, the low temperature dielectric material 129 will degrade, decompose, and/or deflate during the bonding process, which may result in a formation between the semiconductor structure 122 and the processed semiconductor structure 100 that is less than the degradation, decomposition, and/or When deflation occurs, the resulting joint is relatively weak. This weaker temporary bonding can facilitate subsequent separation of the semiconductor structure 122 from the processed semiconductor structure 100, as described in further detail below. Referring back to FIG. 1C, after the semiconductor structure 122 is temporarily bonded to the processed semiconductor structure 100, the substrate 106 of the processed semiconductor structure 1 can be thinned to form another semiconductor structure 140. The substrate 1〇6 can be thinned by, for example, removing the material of the substrate 1〇6 from the back surface 110 of the substrate 106. Material may be removed from the back surface 11 of the substrate ❹ 106 using at least one of a mechanical polishing process and a chemical etching process. For example, the material of the substrate ι 6 can be removed from the back surface 11 using a chemical mechanical polishing (CMP) process. As shown in FIG. 1C, the processed semiconductor structure ι can include a TWI 105 that extends partially through the substrate 106, and can expose the substrate 1〇6 through the processed semiconductor structure at TWI 105. The back surface 11〇 of the substrate 1〇6 is thinned. Figure 1D illustrates another semiconductor structure 16A that can be fabricated by forming a permanent bond between the semiconductor structure 140 of Figure 1C and another processed semiconductor structure 17A. The permanent bond established between the semiconductor structure 14A and the semiconductor structure 17A along the bonding interface therebetween 156587.doc -21 - 201212131 can produce at least about 1,2 〇〇 mJ/m 2 of the semiconductor structure 140 and the semiconductor structure 170 The bonding energy between the two. More specifically, the permanent bond established between semiconductor structure 140 and semiconductor structure 170 can result in bonding between semiconductor structure 140 and semiconductor structure 170 between about 1,600 mJ/m2 and about 3,000 mJ/m2. . The processed semiconductor structure 170 can be substantially similar to the processed semiconductor structure 100 of FIG. 8 and can include a plurality of device structures 1 74 formed in and/or over the substrate 176, although the processed semiconductor structure 17〇 The type and/or design may differ from the type and/or design of the processed semiconductor structure 101. Substrate 176 can comprise a semiconductor material such as any of those previously described with respect to substrate 106 of Figure 1A. The fabricated semiconductor structure 170 can also include a metal structure 175 that can be structurally coupled and/or electrically coupled to the TWI 105 of the semiconductor structure 140. Metal structure 175 can include one or more of conductive pads, traces, lines, and the like. Further, the metal structure 175 can comprise a multi-layer or multi-region structure including, for example, a transition zone, a barrier zone, a conductive zone, and the like, each of which can comprise a different material. In some embodiments 'TWI 105 and metal structure 175 may comprise the same material (e.g., a metal or metal alloy, such as a copper-based alloy), and a metal-to-metal bond may be established between Twi 1 〇 5 and metal structure 175. For example, a metal-to-metal thermocompression bonding process can be used to form the bond between TWI 1 〇 5 and metal structure 1 75. In such methods, pressure can be applied between the semiconductor structure 14 and the processed semiconductor structure 170 while heating the semiconductor structure 14 and the processed semiconductor structure 17 〇. The combination of pressure and heat results in the formation of a metal-metal bond between the TWI 105 and the metal structure 1 75. For example, 356587.doc -22 201212131, a pressure between about 0.14 MPa and about 1.43 MPa can be applied between the semiconductor structure 140 and the processed semiconductor structure ι7 , while the semiconductor structure 140 and the processed semiconductor structure are 17〇 is heated to about 2 〇 (rc and about 4 〇 (temperature between rc. To avoid oxidation during the bonding process, it can be between about 4% (4%) and about 100% by volume, such as nitrogen) The bonding process is performed in a reducing atmosphere of a mixture of hydrogen gas between ten (1%). In some embodiments, the TWI 105 and the metal structure 175 may comprise the same material (eg, a metal or metal alloy such as a copper-based alloy). And a metal-to-metal bond can be established between Twi 1 〇 5 and metal structure 175. For example, a metal-metal non-thermal bonding process can be used to form the bond between TWI 105 and metal structure 175. In the method, no external pressure is applied between the semiconductor structure ι4 〇 and the processed semiconductor structure 170. Further, non-thermobonding can be performed at room temperature and atmospheric pressure. Alternatively, the dielectric material 178 can be bonded to half The substrate structure 106 of the conductor structure is used to permanently bond the semiconductor structure 14 to the processed semiconductor structure 170. The dielectric material 178 may comprise, for example, an oxide (eg, SiO 2 or alumina (a12 二). 3)), nitride (such as tantalum nitride (si3N4), boron nitride (BN) or aluminum nitride (A1N)), etc. After the semiconductor structure 140 of FIG. 1C is permanently bonded to the processed semiconductor structure 17 The semiconductor structure 122 temporarily bonded to the semiconductor structure 100 is removed from the semiconductor structure 160 of FIG. 1D to form the semiconductor structure 180 shown in FIG. 1E. For example, by the semiconductor structure 122 and the rest of the semiconductor structure 160 A mechanical force is applied to remove the semiconductor structure 122 from the semiconductor structure 16 (Fig. 1D). 156587.doc • 23- 201212131 For example, a rotational torque can be applied between the semiconductor structure 122 and the rest of the semiconductor structure 16〇 To apply the rotational torque between the semiconductor structure i 22 and the remainder of the semiconductor structure 160, the first chuck device can be connected to the semiconductor structure 122 and the second chuck device can be connected to the half The remainder of the body structure 160, and torque can be applied between the semiconductor structure 122 and the remainder of the semiconductor structure 160 by applying a rotational torque between the first chuck device and the second chuck device. In the art Such chuck devices and devices are known. As other non-limiting embodiments, blades may be interposed between semiconductor structure 122 and the remainder of semiconductor structure 160, and may be guided between semiconductor structure 122 and the remainder of semiconductor structure 16G. The high pressure fluid is ejected, or a bending force can be applied to the semiconductor structure 160 to separate the semiconductor structure 122 from the remainder of the semiconductor structure 160. Embodiments of the invention described herein with respect to 1A to 1E are present in the processed semiconductor structure 1 before the processed semiconductor structure 1GG is bonded to the other-processed semiconductor structure 17A. In other embodiments of the invention, the TWI may be formed through at least one of the processed semiconductor structures after the at least one processed semiconductor structure is bonded to the at least one other processed semiconductor structure. Examples of such methods are described below with reference to Figures 2A through 2E. Figure 2A illustrates a processed semiconductor structure 2A comprising a plurality of horn structures. Device structure 204 is formed in and/or over substrate 2〇6. The substrate may comprise, for example, - or a plurality of semiconductor materials such as a ground (9), a wrong (tetra), a III-V semiconductor material, and the like. Further, the substrate 206 may comprise a layer of single crystal or semiconductor material of a semiconductor 156587.doc -24 - 201212131 material. In other embodiments, the substrate 206 may comprise one or more dielectric materials such as oxides (eg, SiO 2 or Al 2 〇 3), nitrides (eg, gasification fossils (§) "ν4), boron nitride (BN) or aluminum nitride (A1N), etc. As shown in Figure 2A, device structure 204 does not include TWI (such as TWI 105 of Figure 1A) during fabrication. The semiconductor structure 2 includes an active surface 208 and a back surface 210. The back surface 210 of the processed semiconductor structure 2 can comprise a substantially planar, exposed major surface of the substrate 206. The active surface of the processed semiconductor structure 200 208 may comprise one or more dielectric materials 209 such as an oxide (eg, cerium oxide (Si〇2) or oxidized (ΑΙζ〇3)), a nitride (eg, tantalum nitride (shN4), boron nitride (BN) Or aluminum nitride (A1N), etc. Figure 2B shows a bonded semiconductor structure 220 that can be formed by temporarily bonding the processed semiconductor structure 200 of Figure 2a to another semiconductor structure 222. 222 can comprise, for example, a carrier substrate. For example, semiconductor structure 222 Semiconductor materials may be included, such as germanium (Si), germanium (Ge), III-V semiconductor materials, etc. The semiconductor structure 222 may optionally comprise a single crystal or epitaxial layer of a semiconductor material of the semiconductor material. In other embodiments, the semiconductor Structure 222 can comprise one or more dielectric materials such as oxides (eg, SiO2 or SiO 2 or Zn 2 ), nitrides (eg, Zn (N3N4), Nib (bn), or nitrided. Aluminum (A1N)), etc. The semiconductor structure 222 can comprise a selected material such that the exhibited coefficient of thermal expansion is at least substantially equal to the coefficient of thermal expansion exhibited by the semiconductor structure 200 of FIG. 2A (eg, as exhibited by the semiconductor structure 1) The thermal expansion coefficient is about 156587.doc -25·201212131 (20%). With continued reference to FIG. 2B, the prior art may be used to temporarily bond the processed semiconductor structure 1 of FIG. 1a. Any of the methods described for semiconductor structure 122 of FIG. 1B temporarily bond the processed semiconductor structure 200 directly to semiconductor structure 222. For example, as described herein with respect to FIG. 1B and FIGS. 3-7 Any method of bonding the processed semiconductor structure 2 to the semiconductor structure 222. In other embodiments of the invention, the annealing process can be included in the furnace at about one hundred degrees Celsius (100 ° C) and about eight degrees Celsius Heating the semiconductor structure 200 and the semiconductor structure at a temperature between (8 〇〇. 〇) or at a temperature between about 10,000 Celsius (10 ° C) and about 40 ° C (4 ° ° C) 222 and lasts between about 2 minutes (2 minutes) and about 15 hours (15 hours). As shown in FIG. 2C, after the semiconductor structure 222 is temporarily bonded to the processed semiconductor structure 200, the substrate 206 of the processed semiconductor structure 2 can be thinned to form another semiconductor structure 24A. The substrate 2〇6 can be thinned by, for example, removing the material of the substrate 206 from the back surface 210 of the substrate 206. Material may be removed from the back surface 210 of the substrate 206 using at least one of a mechanical polishing process and a chemical etching process. For example, the material of substrate 206 can be removed from back surface 210 using a chemical mechanical polishing (CMP) process. Figure 2D illustrates another semiconductor structure 260 that may be formed by forming a permanent bond between the semiconductor structure 240 of Figure 2C and another processed semiconductor structure 27A. The permanent bond established between the semiconductor structure 24A and the semiconductor structure 27A along the bonding interface therebetween can produce a bonding energy between the semiconductor structure 240 and the semiconductor structure 270 of at least about 1,200 mJ/m2. More specifically, 156587. doc -26 201212131, permanent bonding between semiconductor structure 240 and semiconductor structure 270 can result in a semiconductor structure 240 between about 1,600 mJ/m2 and about 3,000 mJ/m2. Bonding energy with the semiconductor structure 270. The processed semiconductor structure 270 can be substantially similar to the processed semiconductor structure 200 of Figure 2A and can include a plurality of device structures 274 that are squared in and/or on the substrate 276. Substrate 276 can comprise a semiconductor material, such as any of those previously described with respect to substrate 206 of Figure 2A. The processed semiconductor structure 270 can also include a metal structure 275. Metal structure 275 can include one or more of conductive pads, traces, traces, and the like. In addition, metal structure 275 can comprise a multi-layer or multi-region structure including, for example, a transition zone, a barrier zone, a conductive zone, and the like, each of which can comprise a different material. The semiconductor structure 240 can be permanently bonded to the processed semiconductor structure 270 by bonding a dielectric material 278 (Fig. 2E) to the substrate 206 of the semiconductor structure 200. The dielectric material 278 can comprise, for example, an oxide (eg, cerium oxide (SiO 2 ) or aluminum oxide (A1203)) or a nitride (eg, tantalum nitride (Si 3 N 4 ), boron nitride (BN), aluminum nitride (A1N)). Wait for one or more. After the semiconductor structure 240 of FIG. 2C is permanently bonded to the processed semiconductor structure 270, a TWI 205 can be formed through the semiconductor structure 200 and up to the metal structure 275. For example, vias through the semiconductor structure 200 to the metal structures 275 can be formed by etching or laser ablation. One or more electrically conductive materials may then be provided in and through the vias and metal structures 275 using one or more electroplating processes (eg, an electroless plating process and/or an electroplating process) to form a structure to be interconnected with the metal structures 275 Electrically interconnected TWI 205. After the semiconductor structure 240 of FIG. 2C is permanently coupled to the processed semiconductor structure 270, 156587.doc -27-201212131, the semiconductor structure 222 temporarily bonded to the semiconductor structure 200 can be removed from the semiconductor structure 260 of FIG. 2D to form FIG. 2E. The semiconductor structure 280 is shown. The semiconductor structure 222 can be removed from the semiconductor structure 260 using, for example, the method previously described with respect to FIG. 1E. Embodiments of the present invention can be used in 3D integration of any type of semiconductor structure, including die-to-die (D2D) integration, die-to-wafer (D2W), wafer-to-wafer (W2W) integration, or such integration processes The combination. For example, in a die-to-wafer (D2W) integration process, a processed semiconductor wafer can be temporarily bonded directly to a carrier substrate wafer, as previously described herein for subsequent processing and processing of processed semiconductor wafers. description. The processed semiconductor wafer can then be separated from the carrier substrate wafer and mounted on the tape. The processed semiconductor wafer can then be diced to form individual dies that are adhered to the tape, which can then be tested under proper operation. The good die (KGD) can then be selected and permanently bonded to another processed semiconductor wafer using a permanent bonding process as previously described herein. In another example of a die-to-wafer (D2W) integration process, a good bare die (KGD) can be temporarily bonded directly to a carrier substrate wafer, as previously described herein for subsequent handling and processing (eg, thinning and/or Or forming a TWI) good bare die while bonding it to the carrier substrate wafer as described. The processed good die can then be permanently bonded to another processed semiconductor wafer while the carrier substrate wafer is still bonded to the good die on the opposite side of the other processed semiconductor wafer. . The good die (and another processed semiconductor wafer that is permanently bonded to it) can be separated from the carrier substrate wafer. 156587.doc • 28· 201212131 Other examples of non-limiting embodiments of the invention are described below. Embodiment 1 : A method of forming a bonded semiconductor structure, comprising: forming a first semiconductor structure by providing (iv) direct atomic bonds or molecular bonds of a bonding surface of the first semiconductor structure and a bonding surface of the second semiconductor junction Temporarily bonding to the second semiconductor structure; selecting the first semiconductor structure such that # has an active surface on a first side of the first semiconductor structure and a back surface on a second, opposite side of the first semiconductor structure, and first The semiconductor junction structure includes at least one device structure formed over the substrate; the substrate of the first semiconductor structure is thinned by removing the material of the substrate from the back surface of the first semiconductor structure; and the substrate of the first semiconductor structure is changed After thinning, the back surface of the first semiconductor structure can be permanently bonded to the surface of the third semiconductor structure while the first semiconductor structure is still temporarily bonded to the second semiconductor structure; and the second semiconductor structure is separated from the first semiconductor structure. Embodiment 2: The method of Embodiment 1, the method further comprising: selecting the first semiconductor structure to include at least one through-wafer interconnect, and wherein the substrate of the first 〇I conductor structure is thinned The method includes exposing at least a portion of at least one through-wafer interconnect through a back surface of the first semiconductor structure, and wherein the back surface of the first semiconductor structure is permanently bonded to a surface of the third body structure. - a through-wafer interconnect and at least one of the third semiconductor structures, the conductive structures being electrically interconnected. Embodiment 3: The method of embodiment i, further comprising forming at least one through-wafer interconnect of the first-semiconductor structure after the first semiconductor back surface is permanently bonded to the surface of the third semiconductor structure and causing the at least one The through-wafer interconnect is electrically interconnected with at least one of the conductive structures 156587.doc • 29- 201212131 of the third semiconductor structure. Embodiment 4: Embodiments i to 3 - the conductor structure is temporarily bonded to the first-half conduction /, /, so that the first semi-learn-conductor structure includes a helmet to be in the crucible body structure and the second semiconductor structure The first semiconductor is used to temporarily bond the first semiconductor to the second semiconductor structure by using the adhesive agent at the first + lead α μ + 吏. The method of any one of embodiments 1 to 4, wherein the bonding surface of the first π-body structure is bonded to the second semiconductor structure, and the direct bond or the good material is provided to provide oxygen cutting and nitrogen cutting. A direct atomic bond or molecular bond between at least one of the oxidative error to 7 and at least one of Shi Xi, Yan, Oxide, Nitride and Oxidation. The method of any of embodiments 1 to 5, wherein temporarily bonding the first constitutive structure to the second semiconductor structure comprises: forming surface rough joints each of about 2 nanometers (2 (four) or less) a bonding surface of the first semiconductor structure and a bonding surface of the second semiconductor structure; a bonding surface of the first semiconductor structure abutting the bonding surface of the second semiconductor structure; and maintaining the bonding surface of the conductor structure and the bonding surface of the semiconductor structure The time between about 2 degrees Celsius (200t:) and about 4 degrees Celsius (4 之 for about 2 minutes (2 minutes) and about 5 hours (j 5 hours). The method of embodiment 6, further comprising maintaining a pressure between the bonding surface of the first semiconductor structure and the bonding surface of the second semiconductor structure between about 0.14 MPa and about 1.43 MPa while maintaining the first semiconductor structure The bonding surface of the bonding surface and the second semiconductor structure is at a temperature between about two hundred degrees (20 (TC) and about four degrees Celsius (40 〇t) for about 2 minutes (2 minutes) and about 15 hours (15 h) The time between. I56587 The method of embodiment 6 or embodiment 7, further comprising activating the bonding surface of the first semiconductor structure prior to abutting the bonding surface of the first semiconductor structure adjacent the bonding surface of the second semiconductor structure and At least one of the bonding surfaces of the second semiconductor structure. The method of any one of embodiments 1 to 5, wherein temporarily bonding the first semiconductor structure to the second semiconductor structure comprises: Forming a bonded interface region between the bonding surface and the bonding surface of the second semiconductor structure, the bonded interface region being a bonding interface between the bonding surface of the first semiconductor structure and the bonding surface of the second semiconductor structure Approximately 80% (8%) or less than 80% of the total area. Embodiment 10: The method of Embodiment 9, further comprising bonding at a bonding surface of the first semiconductor structure and the second semiconductor structure A plurality of recesses are formed in at least one of the surfaces. Embodiment 11: The method of Embodiment 10, wherein the Q junction table of the first semiconductor structure Forming the plurality of recesses in at least one of the bonding surfaces of the second semiconductor structure includes: forming a plurality of recesses in a pattern on one of the bonding surface of the first semiconductor structure and the bonding surface of the second semiconductor structure; Selecting a pattern such that the crucible includes a bonding surface of the first + conductor structure and

Another of the joint surfaces of a semiconductor structure, X H, is now a mirror image of another metal feature pattern. The method of embodiment 10 or embodiment, wherein forming the plurality of recesses in at least one of the bonding surface of the first semiconductor structure and the bonding surface of the second semiconductor structure comprises: placing the first dielectric material Deposited in place 156587.doc • 31 201212131 over the second dielectric material on at least one of the bonding surface of the first semiconductor structure and the bonding surface of the second semiconductor structure; selecting the first dielectric material of the package s electrical material The low temperature dielectric material will undergo at least one of degradation, decomposition, and gassing when heated to a temperature below about four degrees Celsius (4 GG C ); and formed through at least a portion of the first dielectric material. A plurality of recesses. Embodiment η The method of Embodiment 12, further comprising heating the low temperature dielectric material to a temperature above a known temperature to attenuate the bond between the low temperature dielectric material and the other material. The method of any one of the preceding claims, wherein the temporarily bonding the first semiconductor structure to the second semiconductor structure comprises: forming a surface coarse rotation of about one quarter nanometer (10) 5 (four) and about 2 nanometers At least one of a bonding surface of the semiconductor structure and a bonding surface of the second semiconductor structure between meters (2.0 nm). Embodiment 15: The method of Embodiment 14, wherein a joint surface of the first conductor structure having a surface roughness of between about four quarters (0.25 nm) and about 2 nm (2 〇 nm) is formed At least one of the bonding surfaces of the two semiconductor structures comprises: a surface of the first semiconductor structure between the surface roughness and the thickness of each of the first semiconductor structures between about one-half of a nanometer and a nanometer (1. And a bonding surface of the first semiconductor structure. Embodiment 16: A method of forming a semiconductor structure, comprising: temporarily bonding a first semiconductor structure to a second bulk conductor structure using an adhesive between a bonding surface of the first semiconductor structure and a bonding surface of the second semiconductor structure Selecting a first semiconductor structure such that it has an active surface on a first side of the first semiconductor structure 156587.doc • 32-201212131 and a back surface on a second opposite side of the first semiconductor structure, and the first semiconductor structure Forming at least one device structure formed over the substrate; permanently bonding the back surface of the first semiconductor structure to the surface of the third semiconductor structure while the first semiconductor structure is still temporarily bonded to the second semiconductor structure; and the second semiconductor structure is The first semiconductor structure is separated.

The method of embodiment 16, wherein the temporarily connecting the first semiconductor structure to the first semiconductor structure comprises: forming a first surface having a roughness of about 2 nm (2 nm) or less. a bonding surface of the semiconductor structure and a bonding surface of the second semiconductor structure; causing the bonding surface of the first semiconductor structure to abut the bonding surface of the second semiconductor structure; and maintaining the bonding surface of the first semiconductor structure and the bonding surface of the second semiconductor structure The time between about 2 minutes (2 minutes) and about fifteen (15) hours at about two degrees Celsius (200 ° C) and about four degrees Celsius (400 ° C.) Example 18: Implementation The method of any one of embodiments 16 to 18, wherein the method of any one of embodiments 16 to 18, wherein the method of any one of embodiments 16 to 18, Wherein temporarily bonding the first semiconductor structure to the second semiconductor structure comprises: forming a bonded interface region between the bonding surface of the first semiconductor structure and the bonding surface of the second semiconductor structure The bonded interface region comprises about eighty percent (80%) or less than eighty percent of the total surface area of at least one of the bonding surface of the first semiconductor structure and the bonding surface of the second semiconductor structure In the first semi-conductive embodiment 20: the method of embodiment 19, a plurality of recesses are formed in at least one of the bonding surface of the bulk structure and the bonding surface of the second semiconductor structure. The method of embodiment 20, wherein forming the plurality of recesses in at least one of the bonding surface of the first semiconductor structure and the bonding surface of the second semiconductor structure comprises: bonding surfaces on the first semiconductor structure and second Forming a plurality of recesses in one of the bonding surfaces of the semiconductor structure; and selecting the pattern to include another metal feature on the other of the bonding surface of the first semiconductor structure and the bonding surface of the first semiconductor structure The embodiment of the method of claim 2, wherein the bonding method of the first semiconductor structure and the bonding of the second semiconductor structure Forming a plurality of recesses in the surface includes: depositing a first dielectric material over the second dielectric material on at least one of a bonding surface of the first semiconductor structure and a bonding surface of the second semiconductor structure Selecting a first dielectric material comprising a low temperature dielectric material that will undergo at least degradation, decomposition, and venting upon heating to a temperature below about four hundred degrees Celsius (400: (:)) And forming a plurality of recesses through at least a portion of the first dielectric material. Embodiment 23: The method of embodiment 22, further comprising heating the low temperature dielectric material to a temperature above a known temperature to cause a low temperature The method of embodiment 16 wherein the temporarily bonding the first semiconductor structure to the second semiconductor structure comprises: forming a surface roughness of between about one-quarter of a nanometer. At least one of a bonding surface of the first semiconductor 156587.doc-34-201212131 structure and a bonding surface of the second semiconductor structure between (0.25 nm) and about 2 nm (2.0 nm). Embodiment 25: A semiconductor structure comprising: a first semiconductor structure having an active surface on a first side of the first semiconductor structure and a back surface on a second, opposite side of the first + conductor structure, The first - semiconductor, -. Forming a substrate 3 and at least one device structure formed over the substrate; the second semiconductor structure 'having no adhesion between the first semiconductor structure and the first semiconductor structure; and temporarily bonding to the first semiconductor structure, at the first semiconductor The bonding energy between the structure and the first semiconductor structure is about 1 〇〇〇mj/m2*1〇〇〇mJ/m or less, and the second semiconductor structure is permanently bonded to the back surface of the first semiconductor structure, at the first The bonding energy between the semiconductor structure and the third semiconductor structure is at least about 1,2 〇〇mJ/m2. The embodiment 26: The semiconductor structure of embodiment 25, further comprising a bonding surface of the first semiconductor structure and the second semiconductor Direct atomic or molecular bonds between the bonded surfaces of the structure. The semiconductor structure of embodiment 26, wherein the bonding surface of the first semiconductor structure comprises at least one of yttrium oxide, lanthanum nitride and lanthanum oxide and the bonding surface of the first semiconductor structure comprises shi, wrong, oxidized At least one of 矽, nitrite and oxidization. The semiconductor structure of any one of embodiments 25 to 27, which advances I 3 to; >, a through-wafer interconnect, the at least one through-wafer interconnect from the first semiconductor structure At least one device structure extends through the substrate of the first semiconductor structure to at least one of the conductive structures of the third semiconductor structure. Embodiment 29: The semiconductor structure of Embodiment 25, wherein the surface of the first semiconductor junction 156587.doc-35-201212131 has a surface roughness and a junction surface of the second semiconductor structure of about 2 nm (2 nm) ) or below 2 nm. Embodiment 30: The semiconductor structure of Embodiment 25, wherein at least one of the bonding surface of the first semiconductor structure and the bonding surface of the second semiconductor structure has a surface roughness of about four quarters. Between m (10) nm). Embodiment 31: The semiconductor structure of Embodiment 30, wherein the bonding surface of the first semiconductor structure and the surface of the bonding surface of the second semiconductor structure are rough: each (four) one-half nanometer (10) (four) and about i nanometer (Η- Embodiment 32: The semiconductor structure of Embodiment 25 further comprising a plurality of recesses in at least one of a bonding surface of the first semiconductor structure and a bonding surface of the second semiconductor structure. Embodiment 33: Embodiment 32 a semiconductor structure, wherein the recesses of the plurality of recesses are disposed in a pattern on one of a bonding surface of the first semiconductor structure and a bonding surface of the second semiconductor structure, and wherein the pattern is included on a bonding surface of the first semiconductor structure And a mirror image of another metal feature pattern of the second semiconductor structure. The semiconductor structure of embodiment 32 or embodiment 33, wherein the recesses of the plurality of recesses extend at least partially Passing over at least one of the electrical materials of the first semiconductor structure and the bonding surface of the second semiconductor structure A low temperature dielectric material is provided. The semiconductor structure of Embodiment 35 is further comprising: a second dielectric material located under: a dielectric material, the first dielectric material being located on a bonding surface of a semiconductor structure and The second dielectric material comprises a high temperature dielectric material on at least one of the bonding surface 156587.doc • 36-201212131 of the second semiconductor structure. The embodiments of the invention described above do not limit the scope of the invention because The embodiments are merely examples of embodiments of the invention, which are defined by the scope of the appended claims and their legal equivalents. Any equivalent embodiments are intended to be within the scope of the invention. Various modifications of the present invention, such as alternative combinations of the elements, are apparent to those skilled in the art in the light of the scope of the accompanying claims. The title used in this article is only for clarity and convenience, and does not limit the scope of the following patent application. [Simplified Schematic] Figure 1A-1E is a semi-conductor BRIEF DESCRIPTION OF THE DRAWINGS FIG. 2A-2E are simplified schematic cross-sectional views of a semiconductor structure and illustrate other exemplary embodiments of the present invention for forming a bonded semiconductor structure; 3 and FIG. 4 are simplified schematic cross-sectional views of a semiconductor structure and illustrate a method for temporarily bonding a semiconductor structure (eg, a die or wafer) to another semiconductor structure (eg, another die or wafer). Examples; and Figures 5 through 7 are simplified schematic cross-sectional views of a semiconductor structure and illustrate another example of a method that can be used to temporarily bond one semiconductor structure to another semiconductor structure. [Major component symbol description] 100 Processed semiconductor Structure/Semiconductor Structure 100' Processed Semiconductor Structure 104 Device Structure 156587.doc -37· 201212131 104, 105 106 108 109 110 120 122 124 126 128 129 130 140 160 170 174 175 176 178 180 156587.doc Conductive Device Features / Recessed through wafer interconnect (TWI) substrate active surface 'processed semiconductor structure 1 主动 active surface / Active Surface Dielectric Material of Conductor Structure 100 / Processed Semiconductor Structure 1 介 Dielectric Material / Processed Semiconductor Structure 1 低温 Low Temperature Dielectric Material Back Surface / Processed Semiconductor Structure 100 Back Surface / Substrate The back surface of the hexagram is bonded to the semiconductor structure semiconductor structure semiconductor structure 122 the bonding surface bonding interface dielectric material / high temperature dielectric material dielectric material / low temperature dielectric material recess semiconductor structure semiconductor structure semiconductor structure / processed semiconductor structure device Structural Metal Structure Substrate Dielectric Material Semiconductor Structure - 38· 201212131 200 Processed Semiconductor Structure / Semiconductor Structure 204 Device Structure 205 Through Wafer Interconnect (TWI) 206 Substrate 208 Active Surface / Processed Semiconductor Structure 200 Active Surface 209 Dielectric Material 210 Back Surface / Back Surface of Processed Semiconductor Structure 200 / Back Surface 220 of Substrate 206 Bonded Semiconductor Structure 222 Semiconductor Structure 240 Semiconductor Structure 260 Semiconductor Structure 270 Processed Semiconductor Structure / Semiconductor Structure 274 Device Structure 275 metal structure 276 substrate 278 Dielectric material 280 Semiconductor structure 156587.doc 39·

Claims (1)

201212131 · VII. Patent Application Range: 1 - A method for forming a bonded semiconductor structure, comprising: providing a direct atomic bond or molecule between a bonding surface of a first semiconductor structure and a surface of a second semiconductor junction a bond temporarily bonding the first semiconductor structure to the second semiconductor structure; - the first semiconductor structure such that there is an active facet on a first side of the (four)-semiconductor structure and a second facet in the first I-conductor structure Having a back surface on the opposite side, and the first semiconductor structure includes at least one device structure formed over the germanium substrate; the first being removed by removing the material of the substrate from the back surface of the first semiconductor structure The substrate of the semiconductor structure is thinned; the back surface of the first semiconductor structure is permanently bonded to the surface of the third + conductor structure after the substrate of the first semiconductor structure is thinned, and at the same time the first semiconductor structure Still temporarily bonding to the second semiconductor structure; and ◎ separating the second semiconductor structure from the first semiconductor structure. 2. The method of claim 1, further comprising selecting the first semiconductor structure to include at least one through-wafer interconnect, and wherein thinning the substrate of the first semiconductor structure comprises causing the at least one to be worn At least a portion of the wafer interconnect is exposed through the back surface of the first semiconductor structure, and such that permanently bonding the back surface of the first semiconductor structure to a surface of the second semiconductor structure comprises causing the at least one to be worn The wafer interconnect is electrically interconnected with at least one electrically conductive structure of the third semiconductor structure. 3. The method of claim 1 further comprising forming at least one of the first semiconductor structure after the back surface of the first semiconductor structure 156587.doc 201212131 is permanently bonded to the surface of the third semiconductor structure A wafer interconnect and electrically interconnecting the at least one through-wafer interconnect with at least one conductive structure of the third semiconductor structure. 4. The method of claim 1, wherein temporarily bonding the first semiconductor structure to the semiconductor-semiconductor structure comprises: forming the first semiconductor structure having a surface roughness of about 2 nm (2 nm ht 2 nm or less) Bonding surface and the bonding surface of the second semiconductor structure; bonding the bonding surface of the first semiconductor structure to the bonding surface of the second semiconductor structure; and bonding the bonding surface of the first semiconductor structure to the second semiconductor The joint surface of the structure is maintained at a temperature between about two degrees Celsius (2 & > &gt; c ) and about four degrees Celsius (40 G C ) for about 2 minutes (2 _) and about 】 $ hour (1 5 5. The time between hr) 5. The method of claim 4, wherein the step further comprises maintaining about 0.14 MPa and about between the "sigma surface" of the first semiconductor structure and the bonding surface of the fourth semiconductor structure. M3 the pressure between them while maintaining the bonding surface of the first semiconductor structure and the bonding surface of the second semiconductor structure at about two degrees Celsius (2 〇〇 ° C) and about four degrees Celsius (4 〇 () Temperature between °C) Lowering the time between about 2 minutes (2 minutes) and about i5 hours hr); and activating the bonding surface of the first body structure adjacent to the second half prior to the bonding table of the first semiconductor structure Leading the semiconductor structure to the 156587.doc 201212131 &amp; surface and the bonding surface of the second semiconductor structure. 6. The method of claim </ RTI> wherein the first semiconductor structure is temporarily bonded k first The semiconductor structure includes a bonded interface region formed between the bonding surface of the first semiconductor structure and the bonding surface of the second semiconductor structure, the bonded interface region being the bonding surface of the first semiconductor structure and the The joint surface of the second semiconductor structure is between about eighty percent (8%) or less than eighty percent of the total area of the joint interface therebetween. 7. The method of claim 6 further Forming a plurality of recesses in at least one of the bonding surface of the first semiconductor structure and the bonding surface of the second semiconductor structure. 8. The method of claim 7 Forming a plurality of recesses in at least one of the bonding surface of the first semiconductor structure and the bonding surface of the second semiconductor structure comprises: ◎ the bonding surface of the second semiconductor structure and the bonding surface of the second semiconductor structure Forming the plurality of recesses in a pattern; and selecting the pattern to include the other surface of the bonding surface of the first semiconductor structure and the bonding surface of the second semiconductor structure 9. The method of claim 7, wherein the plurality of recesses are formed in at least one of the bonding surface of the first semiconductor structure and the bonding surface of the second semiconductor structure: 156587.doc 201212131 depositing a dielectric material over a second dielectric material on at least one of the junction surface of the first semiconductor structure and the bonding surface of the second semiconductor structure; selecting a material comprising a low temperature dielectric material The first dielectric material, the low temperature dielectric material will be heated to a temperature below about four degrees Celsius (4 liters) Li degradation, decomposition and the discharge gas is at least one; and the plurality of concave portions through at least a portion of the first dielectric material. Ίο 11. 12. The method of claim 9, further comprising adding the low temperature dielectric material to the temperature of the known/jn degree such that the low temperature dielectric material and the other material The joint between the weakened. A semiconductor structure comprising: a semiconductor structure having an active surface on a first side of the first semiconductor structure and a back surface on a second, opposite side of the first semiconductor structure 'the first semiconductor structure comprises a substrate and at least one device structure formed over the substrate; a second semiconductor structure temporarily bonded to the first semiconductor structure without an adhesive between the first semiconductor structure, and the first semiconductor structure The bonding energy between the second semiconductor structures is about 丨, (10) 〇mj/m2 or i, 〇〇〇mJ/m2 or less; the third semiconductor junction is bonded to the back of the first semiconductor structure The surface, the bonding energy between the first semiconductor structure and the third semiconductor structure is at least about 1,2 〇〇mj/m2. The semiconductor structure of claim 11, further comprising a direct atomic or molecular bond between the bonding table of the bulk structure and the bonding table of the semiconductor structure between the first semiconductor 156587.doc -4 _ 201212131; And wherein the bonding surface of the first semiconductor structure comprises at least one of cerium oxide, cerium oxide and oxidization, and the bonding surface of the second semiconductor structure comprises at least one of H-oxygen, nitrogen-cut and oxidization One. 13. Ο 14. The semiconductor structure of claim ,, further comprising at least one through-wafer interconnect, the at least one through-wafer interconnect from the at least one of the first semiconductor organizations The device structure extends through the substrate of the first semiconductor structure to at least one of the conductive structures of the third half of the structure. The semi-guide structure of claim U is further comprised of a plurality of recesses in at least one of a mating surface of the first semi-conductive structure and a bonding surface of the second semiconductor structure. 15. The semiconductor structure of claim 14, wherein the plurality of recesses are disposed in a pattern on one of the bonding surface of the first semiconductor structure and the bonding surface of the second semiconductor structure And wherein the pattern comprises a mirror image of another metal feature pattern on the other of the bonding surface of the first semiconductor structure and the bonding surface of the second semiconductor structure. 17. The semiconductor structure of claim 14, wherein the recesses of the plurality of recesses extend at least partially through at least the bonding surface of the first semiconductor structure and the bonding surface of the second semiconductor structure The first-dielectric material of the first dielectric material comprises a low temperature dielectric material. The semiconductor structure of claim 16, further comprising a second dielectric located in the first dielectric layer 156587.doc -5 - 201212131, a dielectric material of the second semiconductor structure, the dielectric material comprising a lower layer of high temperature dielectric material a second electrical material on the bonding surface of the first semiconductor structure and the at least one of the first surface. 156587.doc