201210193 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明涉及電子技術領域，特別涉及一種復位電路及電 子裝置。 【先前技術】 [0002] 復位電路被廣泛地應用於電子裝置中，以對電子裝置中 的主晶片進行初始化。通常，復位電路接收電源單元所 提供的供電電壓以上電工作，並輸出復位訊號給主晶片 ，從而使主晶片完成初始化。 [0003] 然而，當電源單元所提供的供電電壓不穩定時，復位電 路可能會異常工作。例如當電源單元所提供的供電電壓 低於一預定值時，可能導致復位電路無法輸出復位訊號 ，因而致使主晶片無法進行初始化。 【發明内容】 [0004] 鑒於此，有必要提供一種改進的復位電路。 [0005] 還有必要提供一種改進的電子裝置。 [0006] 一種復位電路，用於對主晶片進行初始化。該復位電路 包括保護單元、復位單元及用於提供供電電壓的電源單 元，該保護單元與復位單元相連。復位單元用於在供電 電壓正常時輸出第一電平訊號給主晶片，並在一預定時 間後輸出第二電平訊號給主晶片，該主晶片根據第一電 平訊號進行初始化，並在該預定時間後初始化完畢，該 主晶片根據第二電平訊號開始上電工作，該保護單元用 於在供電電壓低於一預定電壓值時輸出該第一電平訊號 099128045 表單編號A0101 第4頁/共11頁 0992049327-0 201210193 [0007] Ο [0008]201210193 VI. Description of the Invention: [Technical Field] [0001] The present invention relates to the field of electronic technology, and in particular to a reset circuit and an electronic device. [Prior Art] [0002] A reset circuit is widely used in an electronic device to initialize a main wafer in an electronic device. Generally, the reset circuit receives the power supply voltage supplied by the power supply unit and operates the power supply, and outputs a reset signal to the main chip, thereby completing the initialization of the main chip. [0003] However, when the power supply voltage supplied by the power supply unit is unstable, the reset circuit may operate abnormally. For example, when the power supply voltage provided by the power supply unit is lower than a predetermined value, the reset circuit may not output a reset signal, thereby causing the main chip to fail to initialize. SUMMARY OF THE INVENTION [0004] In view of the above, it is desirable to provide an improved reset circuit. It is also necessary to provide an improved electronic device. [0006] A reset circuit for initializing a main wafer. The reset circuit includes a protection unit, a reset unit, and a power supply unit for supplying a supply voltage, the protection unit being coupled to the reset unit. The reset unit is configured to output a first level signal to the main chip when the power supply voltage is normal, and output a second level signal to the main chip after a predetermined time, the main chip is initialized according to the first level signal, and After the predetermined time is completed, the main chip starts to operate according to the second level signal, and the protection unit is configured to output the first level signal 099128045 when the power supply voltage is lower than a predetermined voltage value. Form No. A0101 Page 4 / A total of 11 pages 0992049327-0 201210193 [0007] Ο [0008]
[0009] G —種電子裝置，其包括復位電路及主晶片，該復位電路 用於對主晶片進行初始化。該復位電路包括保護單元、 復位單元及用於提供供電電壓的電源單元，該保護單元 與復位單元相連，復位單元用於在供電電壓正常時輪出 第—電平訊號給主晶片’並在一預定時間後輸出第二電 平訊號給主晶片，該主晶片根據第一電平訊號進行初始 化，並在該預定時間後初始化完畢，該主晶片根據第二 電平訊號開始上電工作，該保護單元用於在供電電壓低 於一預定電壓值時輸出該第一電平訊號。 上述復位電路及電子裝置，由於設置了保護單元，當供 電電壓低於一預定電壓值時，保護單元輪出第一電平訊 號，不僅可使主晶片進行初始化，而且避免了主晶片在 供電電®不足時m作可能導致的錯誤操作。 【實施方式】 請參閱圖卜-較佳實射式的電子裝置刚包括復值電 路200及主晶片300。後位電路2〇〇用於對主晶片3〇〇進行 初始化。復位電路200包括電源單元1〇、復位單元2〇及保 護單元3G。電源單元1G詩給復位單元賊保護單元3〇 提供供電電壓。 [0010] 復位單元2G用於在供電電壓正常時輪出第—電平訊號給 明片300，並在一預定時間後輸出第二電平訊號給主』 片300。在一些實施例中，該正常的供電電壓可為3 3v 099128045 王曰b片300根據第一電平訊號進行初始化，並在該預定時 間後初始化完畢》主晶片300接收電源電壓並根據第二電 表單編號删1 第5頁/共11頁 0992049327-0 201210193 平訊號開始上電工作，所述電源電壓可以由電源單元1 ο 提供，也可以由其他的供電電源提供。在本實施方式中 ，該第一電平訊號為低電平電壓訊號，該第二電平訊號 為rfj電平電壓訊號。 [0011] 保護單元30用於在供電電壓低於一預定電壓值時輸出第 一電平訊號，並在供電電壓正常時停止工作。在一些實 施例中，該預定電壓可為2. 3V。由於在供電電壓低於一 預定電壓值時，保護單元30可輸出第一電平訊號給主晶 片300，使主晶片300進行初始化。因而當供電電壓恢復 正常時，主晶片300可正常上電工作，有效地避免了習知 技術中當供電電壓低於一預定電壓值時不能進行初始化 的缺陷。 [0012] 具體地，復位單元20包括第一電阻R1、第一電容C1及第 二電容C2。第一電阻R1的一端連接電源單元10，另一端 藉由第一電容C1接地。第二電容C2的一端連接於第一電 阻R1與第一電容C1之間，另一端接地。主晶片300包括用 於接收第一電平訊號及第二電平訊號的復位引腳302，復 位引腳302連接於第一電阻R1與第一電容C1之間。復位單 元20在一預定時間後輸出第二電平訊號給主晶片300，該 預定時間由第一電阻R1及第一電容C1所構成的充電時間 常數決定。 [0013] 保護單元30包括第二電阻R2、第三電阻R3、第四電阻R4 、第五電阻R5、第一三極體Q1及第二三極體Q2。第二電 阻R2的一端連接電源單元10，另一端藉由第三電阻R3接 地，第四電阻R4的一端連接於第二電阻R2與第三電阻R3 099128045 表單編號A0101 第6頁/共11頁 0992049327-0 201210193 之間，另一端連接第一三極體Q1的基極，第一三極體Q1 的集極藉由第五電阻R5連接電源單元1〇，第一三極體Q1 的射極接地。第二三極體Q2的基極連接第一三極體〇的 集極，第一二極體Q2的集極連接復位引腳3〇2，第二三極 體Q2的射極接地。在本實施方式中，第一三極體qi及第 二三極體Q2為NPN型三極體。 [0014] [0015] Ο ο [0016] 電子裝置100的工作原理如下： 當電子裝置100開機瞬間且電源單元1〇所提供的供電電壓 正常時，第二電阻R2及第三電阻共同對供電電壓進行 分壓所產生的電壓使得第一三極體Q1導通，第二三極體 Q2基於第一三極體Q1的導通而截止。由於電子裝置1〇〇開 機瞬間’電容C1相當於交流短路，因此複位引腳3〇2接收 到的為低電平電壓’主晶片300進行初始化。隨著供電電 壓對電容C1的持續充電，經過充電時間亨一及1本乙^ ’主晶片300初始化完畢’同時復位引腳3〇2將接收到高 電平電壓’主晶片300開始上電工作。 當電源單元10所提供的供電電壓低於一預定值時，第一 三極體Q1截止，第二三極體q2基於第一三極體〇1的截止 而導通。復位引腳302將接收到低電平電壓，主晶片3〇〇 進行初始化。當供電電壓恢復正常時，復位弓丨腳302將接 收到尚電平電壓’從而主晶片3〇〇可正常上電工作有效 地避免了習知技術中當供電電壓低於__預定電壓值時不 月6進行初始化的缺陷。另外，由於在供電電壓低於一預 定值時，主晶片300的復位引腳3〇2—直接收到的為低電 099128045 表單編號A0101 第7頁/共11頁 0992049327-0 201210193 平電壓，因而主晶片300不能正常上電工作，有效地避免 了主晶片300在供電電壓不足時因上電工作可能導致的錯 誤操作。 [0017] 综上所述，本發明符合發明專利要件，爰依法提出專利 申請。惟，以上所述者僅為本發明之較佳實施方式，舉 凡熟悉本案技藝之人士，在援依本案創作精神所作之等 效修飾或變化，皆應包含於以下之申請專利範圍内。 【圖式簡單說明】 [0018] 圖1為一較佳實施方式的電子裝置之具體電路圖。 【主要元件符號說明】 [0019] 電子裝置：100 [0020] 復位電路：200 [0021] 主晶片：300 [0022] 復位引腳：302 [0023] 電源單元：10 [0024] 復位單元：20 [0025] 保護單元：30 [0026] 電阻：Rl、R2、R3、R4、R5 [0027] 三極體：Ql、Q2 [0028] 電容：Cl、C2 099128045 表單編號A0101 第8頁/共11頁 0992049327-0[0009] G-electronic device comprising a reset circuit and a main chip for initializing a main wafer. The reset circuit includes a protection unit, a reset unit and a power supply unit for providing a supply voltage. The protection unit is connected to the reset unit, and the reset unit is configured to rotate the first level signal to the main chip when the power supply voltage is normal and After the predetermined time, the second level signal is outputted to the main chip, and the main chip is initialized according to the first level signal, and after the predetermined time is initialized, the main chip starts to operate according to the second level signal, and the protection is performed. The unit is configured to output the first level signal when the power supply voltage is lower than a predetermined voltage value. The reset circuit and the electronic device are provided with a protection unit. When the supply voltage is lower than a predetermined voltage value, the protection unit rotates the first level signal, which not only enables the main chip to be initialized, but also avoids the main chip being powered. When the ® is insufficient, m may cause incorrect operation. [Embodiment] Referring to the drawings, the preferred real-time electronic device includes the complex value circuit 200 and the main wafer 300. The post circuit 2 is used to initialize the main chip 3A. The reset circuit 200 includes a power supply unit 1A, a reset unit 2A, and a protection unit 3G. The power supply unit 1G provides a supply voltage to the reset unit thief protection unit 3A. [0010] The reset unit 2G is configured to rotate the first level signal to the chip 300 when the power supply voltage is normal, and output the second level signal to the main slice 300 after a predetermined time. In some embodiments, the normal supply voltage may be 3 3v 099128045. The slice 300 is initialized according to the first level signal and initialized after the predetermined time. The main chip 300 receives the power voltage and according to the second power. Form No. 1 Page 5 of 11 0992049327-0 201210193 The signal is started and the power supply voltage can be supplied by the power supply unit 1 or other power supply. In this embodiment, the first level signal is a low level voltage signal, and the second level signal is an rfj level voltage signal. [0011] The protection unit 30 is configured to output a first level signal when the power supply voltage is lower than a predetermined voltage value, and stop working when the power supply voltage is normal. 3伏。 In some embodiments, the predetermined voltage may be 2. 3V. Since the protection unit 30 can output the first level signal to the main wafer 300 when the supply voltage is lower than a predetermined voltage value, the main wafer 300 is initialized. Therefore, when the power supply voltage returns to normal, the main chip 300 can be normally powered up, effectively avoiding the drawback that the prior art cannot be initialized when the supply voltage is lower than a predetermined voltage value. [0012] Specifically, the reset unit 20 includes a first resistor R1, a first capacitor C1, and a second capacitor C2. One end of the first resistor R1 is connected to the power supply unit 10, and the other end is grounded by the first capacitor C1. One end of the second capacitor C2 is connected between the first resistor R1 and the first capacitor C1, and the other end is grounded. The main chip 300 includes a reset pin 302 for receiving the first level signal and the second level signal. The reset pin 302 is connected between the first resistor R1 and the first capacitor C1. The reset unit 20 outputs a second level signal to the main wafer 300 after a predetermined time, which is determined by the charging time constant of the first resistor R1 and the first capacitor C1. [0013] The protection unit 30 includes a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a first triode Q1, and a second triode Q2. One end of the second resistor R2 is connected to the power supply unit 10, and the other end is grounded via a third resistor R3. One end of the fourth resistor R4 is connected to the second resistor R2 and the third resistor R3 099128045. Form No. A0101 Page 6 / 11 pages 0992049327 -0 201210193, the other end is connected to the base of the first triode Q1, the collector of the first triode Q1 is connected to the power supply unit 1〇 via the fifth resistor R5, and the emitter of the first triode Q1 is grounded . The base of the second transistor Q2 is connected to the collector of the first transistor ,, the collector of the first diode Q2 is connected to the reset pin 3〇2, and the emitter of the second transistor Q2 is grounded. In the present embodiment, the first triode qi and the second triode Q2 are NPN type triodes. [0015] [0016] The operating principle of the electronic device 100 is as follows: When the electronic device 100 is powered on and the power supply voltage provided by the power supply unit 1 is normal, the second resistor R2 and the third resistor are collectively connected to the power supply voltage. The voltage generated by the voltage division causes the first triode Q1 to be turned on, and the second triode Q2 is turned off based on the conduction of the first triode Q1. Since the electronic device 1 is turned on, the capacitor C1 corresponds to an alternating current short circuit, so that the reset chip 3〇2 receives a low level voltage 'the main wafer 300 is initialized. As the power supply voltage continues to charge the capacitor C1, after the charging time and the first master wafer 300 are initialized, the reset pin 3〇2 will receive the high level voltage, and the main chip 300 starts to be powered. . When the supply voltage supplied from the power supply unit 10 is lower than a predetermined value, the first triode Q1 is turned off, and the second triode q2 is turned on based on the turn-off of the first triode 〇1. Reset pin 302 will receive a low level voltage and main chip 3〇〇 will be initialized. When the supply voltage returns to normal, the reset pin 302 will receive the still-level voltage 'so that the main chip 3 can be powered up normally to effectively avoid the conventional technique when the supply voltage is lower than the predetermined voltage value. Defects that are not initialized by month 6. In addition, since the power supply voltage is lower than a predetermined value, the reset pin 3〇2 of the main wafer 300 is directly received as a low power 099128045 form number A0101 page 7 / 11 pages 0992049327-0 201210193 flat voltage, thus The main wafer 300 cannot be normally powered on, effectively avoiding the erroneous operation that the main wafer 300 may cause due to power-on operation when the power supply voltage is insufficient. [0017] In summary, the present invention complies with the requirements of the invention patent, and submits a patent application according to law. However, the above description is only a preferred embodiment of the present invention, and those who are familiar with the art of the present invention should be included in the following claims. BRIEF DESCRIPTION OF THE DRAWINGS [0018] FIG. 1 is a detailed circuit diagram of an electronic device according to a preferred embodiment. [Main component symbol description] [0019] Electronic device: 100 [0020] Reset circuit: 200 [0021] Main chip: 300 [0022] Reset pin: 302 [0023] Power supply unit: 10 [0024] Reset unit: 20 [ 0025] Protection unit: 30 [0026] Resistance: Rl, R2, R3, R4, R5 [0027] Triode: Ql, Q2 [0028] Capacitance: Cl, C2 099128045 Form No. A0101 Page 8 of 11 0992049327 -0