201209838 "v…J802twf.doc/n 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種溶絲偵測裝置。 【先前技術】 在現今的積體電路中，常利用一種所謂的溶絲來完成 功能選擇或是輸出電壓準位調整等功效。簡單來說，就是 利用一個或多個的熔絲，並透過燒斷而形成斷路或是未被 燒斷而形成短路的狀態來產生超過一種的組合，並透過這 些組合來設定所要選用的功能或所要產生的輸出電壓準 位。這種熔絲的狀態的判斷一旦發生錯誤，就會使整個積 體電路運作不正確而產生無法弭補的錯誤。 以下請參照圖1，圖1綠示一種習知的溶絲债測裝置 。熔絲偵測裝置1〇〇包括作為開關的電晶體ρι及Nb 用以建構拾鎖器的電晶體P2、P3、N2及N3以及反向器 INV1所組成，用以偵測熔絲FUSE的短路斷路的狀態。熔 絲領測褒置100的動作細節則請同時參照圖2繪示的溶絲 積測裝置1GG的波形®。首先，熔絲偵測裝置⑽所接收 作為電源的參考電麼VINT被開啟並逐漸上升至穩定狀 態。，時，控制信號bFPUP被致能(保持邏輯低準位)並導 通，a日體Pi。此時由電晶體p2、p3、N2及建構的拾 ，益拾鎖其所接收到的等於參考電壓VINT的信號（邏輯 问準位）’並透過反向II INV1輸出邏輯低準位的偵測信號 肌ATS。接著，控制信號bFPUP轉態為邏輯高準位(禁能） 201209838 yywO 34802twf.doc/n f關閉電晶體PI，另一控制信號FPUN則致能(轉態為邏 輯兩準位)以導通電晶體N1。在熔絲FUSE未被燒斷(短路） 的狀態下’電晶體P2、P3、N2及N3建構的栓鎖器改拾 鎖到接地電壓vss並使偵測信號bFLATS轉態為邏輯高準 位信號。 在此請注意，熔絲偵測裝置100中的熔絲雖為短路的 狀態，但代表熔絲FUSE狀態的偵測信號bFLATS在時間 點τι間卻呈現代表溶絲FUSE已被燒斷的斷路狀態(邏輯 準位）。也就是說，此種習知的熔絲偵測裝置1〇〇是很容易 產生誤判斷的狀況的。 【發明内容】 本發明提供-種溶絲摘測裝置’有效避免溶絲 斷錯誤發生的可能。 本發明提出-種炫絲備測裝置，包括侧器 =及邏輯運算單元。制器中包括制開關模組以及_ ，器。侧開關模組串接第一參考電壓與溶絲間，接收 第二控制信號’並依據第-及第二控制信號以及溶 =短路錢路㈣產生初步❹说果。其♦，炫絲串接 於偵測開關模組與第二參考電壓間。偵·鎖 開關模組並接收初步_結果，依據 ^； ，結果的電壓值或保持其原來所儲存的=儲： ，拾鎖器魏據其所齡的電壓值產生校正前_^ 父正益則包括校正_模組以及校正拾脑1正^關模 201209838 "一” -.802twf.doc/n 組’串接該第一參考電壓與該第二參考電壓間，接收第一 及第二控制信號，並依據第一及第二控制信號產生校正結 果。校正拴鎖器耦接校正開關模組並接收校正結果，校正 拴鎖器儲存校正結果，並依據校正結果的反向以輸出校正 信號。邏輯運算單元耦接偵測器以及校正器，接收並依據 校正前偵測信號以及校正信號以進行邏輯運算，並藉以產 生校正後偵測信號。 為讓本發明之上述特徵和優點能更明顯易懂，下文特 舉實施例’並配合所附圖式作詳細說明如下。 【實施方式】 以下請參照圖3，圖3繪示本發明的一實施例的熔絲 偵測裝置300的示意圖。'溶絲偵測裝置300包括偵測器 310、校正器320以及邏輯運算單元330。偵測器310包括 偵測開關模組311以及偵測拴鎖器312。 偵測開關模組311串接在參考電壓viNT與熔絲 FUSE間’接收控制信號bFPUP以及控制信號FPUN。偵 測開關模組311依據控制信號bFpup、FPUN以及熔絲 FUSE的短路或斷路狀態產生初步偵測結果SIG1，其中， 熔絲FUSE串接於偵測開關模組3U與參考電壓vss間。 f本實施例中’偵測開關模組3U由電晶體？1以及N1所 分別構成的備測開關來實施，其中，電晶體P1的偵測開 關輕接至參考電壓VINT並受控於控制信 號bFPUP。電晶 體N1的偵測開關串接於熔絲1?1；5£與電晶體ρι間並受控 201209838 yy-wo 34802tw£d〇c/n 於控制信號FPUN。 另外，偵測拴鎖器312耦接偵測開關模組311並接 初步偵測結果SIG1。偵測拴鎖器312依據初步偵測結果 SIG1來儲存初步偵測結果的電壓值SI(}1或保持其原來 儲存的電壓值。偵測拾鎖器312並依據其所儲存的電壓值 產生校正前細信號SIG2e在此請注意，當偵測開關模組 311中的電晶體P1依據控制信號bFpup導通時，電晶體 φ N1必須被關閉。並且在此同時，初步偵測結果81(51會與 參考電壓VINT相同電壓準位，對的，#電晶體m ^ 據控制信號FPUN導通時，電晶體ρι必須關閉。而在此 同時’若熔絲FUSE的狀態是短路的’則初步偵測結果SIG1 會與參考電壓vss相同電壓準位。或若是溶,纟糸FUSE的狀 態是斷路的，則初步谓測結果SIG1會呈現高阻抗(雖 impendence)的狀態。而在當偵測拴鎖器312所接收到的初 步偵測結果SIG1是等於參考電壓vss或VINT時，偵測 拴鎖器312會拴鎖初步偵測結果SIG1對應的電壓準位。 • ❿若是初步債測結果SIG1呈現高阻抗的狀態時，镇測拴 鎖器312則保持原來所儲存的電壓值。 在本實施例中，偵測拾鎖器312包括由電晶體p2、 N2、P3及N3所組成的兩個串接的反向器來建構成的緩衝 器，其中，這個緩衝器的輸出端與輸入端相連接，並在其 輸出端產生校正前偵測信號SIG2。請注意，上述的緩衝器 由兩個反向器來建構僅只是一個範例，並不限制本發明的 偵測拴鎖器312中的緩衝器必須僅能使用兩個反向器來建 201209838 "“⑻)2twf.doc/n 構。 校正器320貝ij包括校正開關模組321以及校正拾鎖器 322。校正開關模組321串接參考電壓vint與參考電壓 VSS間校正開關模組321接收控制信號刪^以及控制 信號FPUN，並依據控制信號bFpup及FpuN產生校正結 果CR。校正拴鎖器322則輕接校正開關模组並接收 校正結果CR。校正拾鎖器322儲存校正結果cr並依據校 正結果CR的反向以輸出校正信號CRS。其令，校正開關 模組321依據控制信號bFpup及FpuN所產生校正結果 CR的電壓值會等於參考電壓乂贿及vss的其中之一。 簡單來說’當控制錢bFPUP致能時，校正結果cr的電 壓值等於參考電壓VINT，城的，當测錢FPUN致 能時，校正結果CR的電壓值等於參考電壓娜。 邏輯運算單元330贿偵測器31〇以及校正器似。 邏輯運算單元330接收並依據校正前偵測信號啦2以及 校正信號CRS以進行邏輯運算，並藉以產生校正後偵測信 號 bFLATS。 以下明參二、圖4 ’圖4矣會示本發明實施例的熔絲偵測 裝置300的-實施方式。其中，校正開關模組321包括由 電晶體P4及N4分別建構的校正開關。電晶體以的 祕參考電MvmT’其另1產生校正絲⑶並受控於 控制信號bmiPi晶體⑽的—料接於電晶體ρ4^ 考電壓VSS間’並受控於控制信號FPUN。另外，校正熔 絲雨SE串接於電晶體N4與參考電麗vss的域路徑 201209838 yy-υυο 34802twf.doc/n 間。 校正拴鎖器322則包括由電晶體P5、N5、P6及N6 所建構的多個反向器來串接而成的緩衝器。此緩衝器的輸 出端耦接到輸入端，其輸出端耦接至反向器INV2。校正拴 鎖器322接收並拴鎖校正結果CR，並透過反向器iNV2的 輸出端來產生與校正結果CR反向的校正信號CRS。 邏輯運算單元330則為反及閘NAND1。反及閘 φ NAND1的兩輸入端分別接收校正信號CRS以及校正前價 測k號SIG2 ’並在其輸出端產生校正後偵測信號bFLATS。 在整體的作動方面’請同時參照圖4以及圖5 ,其中 圖5繪示圖4繪示本發明的熔絲偵測裝置300實施方式的 波形圖。在當作為電源的參考電壓VINT被啟動並逐漸上 升至穩定狀態的同時，控制信號bFPUP維持在邏輯低準位 並導通電晶體P1以及P4，並使得校正結果CR以及校正 前偵測信號SIG2同樣等於邏輯高準位（等於參考電壓 V1NT的電壓準位）《>而此時’校正信號CRS則呈現與校正 鲁 結果CR反向的邏輯低準位ΰ並且因為校正信號CRS為邏 輯低準位，為反及閘NAND1的邏輯運算單元330則對應 產生邏輯高準位的校正後偵測信號bFLATS。 接著，控制信號bFPUP轉態為邏輯高準位後，控制信 號FPUN對應轉態為邏輯高準位並導通電晶體Ni 由於校正熔絲DFUSE永遠保持在短路狀態，所以在此時 的校正結果CR等於參考電壓VSS並呈現邏輯低準位，校 正信號CRS則為邏輯高準位。而反及的邏輯運 201209838 yy-υυο ^4802twf.doc/u 算單元330則維持其所產生的邏輯高準位的校正後偵測信 號 bFLATS。 由上述的說明及圖5的繪示可以得知，在本實施方式 中，不論控制信動FPUP及FPUN如何的作動，都不至於 會產生會導致誤判的邏輯低準位的校正後偵測作號 bFLATS。也就是說，炫絲偵測裝置3⑽有效 翌 知的熔絲偵測裝置的誤判現象。 、 附帶-提的，由於校正溶絲DFUSE永遠保持短路， 因此也可以不必要存在。也就是說，電晶體N4可以直接 連接到參考電壓VSS。 並且，在圖4繪示的邏輯運算單元33〇是利用反及閘 =ND1來建構’這個反及閘NANm也可以置換成為例如 是及閘的邏輯電路來建構。當然，在邏輯運算單元33〇利 用及閘來建構的情況下，校正後债測信號bFLATS的邏輯 準位所代表的熔絲FUSE的狀態的意義將會與利用反及閘 NAND1來建構的邏輯運算單元33〇所產生的校正後偵測 信號bFLATS相反。 另外，值得注意的是，控制信號bFPUp及FPUN傳送 到扠正器320的時間點需早於控制信號1)1；1>1^及FpuN傳 送到偵測器310的時間點，以確定校正信號CRS的產生時 間可以有效的早於校正前偵測信號SIG2並遮罩校正前偵 測信號SIG2所可能產生錯誤的部份。 請參照圖6，圖6繪示本發明的另一實施例的熔絲偵 測裝置600的示意圖。其中，熔絲偵測裝置6〇〇除了包括 201209838 yy-UUb 34802twf.doc/n 偵測器620、校正器610以及邏輯運算單元650外，還包 括多個擴充偵測器630〜640以及多個擴充邏輯運算單元 660〜670。在此，擴充偵測器與擴充運算單元的個數必須 相(相同等於N’N為正整數)。並且，各擴充偵測器630〜640 的内部電路都與偵測器620的内部電路相同，且各邏輯運 算單元660-670的内部電路都與邏輯運算單元650的内部 電路相同。' 在本實施例中，偵測器620以及擴充偵測器630〜640 透過利用共用的校正器610，再配合邏輯運算單元650以 及擴充邏輯運算單元660〜670進行邏輯運算，便可以得到 多個校正後偵測信號bFLATSl〜bFLATS3，並藉以獲知多 個熔絲的短路或斷路的狀態。而附帶一提的，控制信號 pFPUP及FPUN傳送到校正器610的時間點需早於控制信 號bFPUP及FPUN傳送到偵測器62〇以及擴充偵測器 630〜640的時間點。 、。综士所述，本發明利用校正器來提供校正信號以透過 邏輯運舁單年來遮罩校正前偵測信號所產生可能發生誤判 斷的部份。並且，這個校正信號由熔絲偵測裝置内部自行 產生，可以有效避免其他信號的干擾。 雖…;、本發明已以實施例揭露如上，然其並非用以限定 = 術領域中具有通常知識者，在不脫離 ^發明之精神和範_，當可作些許之更動與_ 發明之保護範㈣概附之申請專繼圍所界定者為準。 201209838—, .....J8〇2twf.doc/n 【圖式簡單說明】 圖1繪示-種習知的賴侧 圖2缘示炫絲偵測裝置100的波形圖。。 意圖圖3繪不本發明的一實施例的熔絲偵測裝置的示 圖4繪示本發明實施例的溶絲偵測裝置的-實施 方式° 圖5、’a示圖4續'示本發明的溶絲偵測裝置實施方 式的波形圖。 圖6繪不本發明的另一實施例的熔絲偵測裝置600的 开:意圖。 【主要元件符號說明】 100、300、600 :熔絲偵測裝置 321:校正開關模組 322 :校正拴鎖器 330、650 :邏輯運算單元 310、620 :偵測器 320、610 :校正器 330 :邏輯運算單元 311 :偵測開關模組 312 :偵測拴鎖器 630〜640 :擴充偵測器 660〜670 :擴充邏輯運算單元 201209838 yy-υυο 34802twf.doc/n SIGl :初步偵測結果 SIG2 :校正前偵測信號 CR :校正結果 CRS :校正信號 P1〜P6、N1〜N6 :電晶體 INV卜INV2 :反向器 bFPUP、FPUN :控制信號 bFLATS :偵測信號 FUSE、DFUSE :熔絲 VSS、VINT :參考電壓 NAND1 :反及閘201209838 "v...J802twf.doc/n VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to a dissolved wire detecting device. [Prior Art] In today's integrated circuits, a so-called dissolved wire is often used to perform function selection or output voltage level adjustment. In simple terms, one or more fuses are used, and a short circuit is formed by blowing or forming a short circuit without being blown to generate more than one combination, and the combination is used to set the function to be selected or The output voltage level to be generated. When an error occurs in the judgment of the state of the fuse, the entire integrated circuit is operated incorrectly and an error that cannot be compensated for is generated. Please refer to FIG. 1 below. FIG. 1 shows a conventional solution for measuring a solvent. The fuse detecting device 1 〇〇 includes a transistor ρι and Nb as switches for constructing the latches P2, P3, N2 and N3 and an inverter INV1 for detecting a short circuit of the fuse FUSE The state of the open circuit. For details of the operation of the fuse lead measuring device 100, please refer to the waveform® of the solvolysis device 1GG shown in Fig. 2 at the same time. First, the fuse detection device (10) receives the reference power as a power source, and VINT is turned on and gradually rises to a stable state. At the time, the control signal bFPUP is enabled (maintaining a logic low level) and turned on, a day Pi. At this time, by the transistors p2, p3, N2 and the constructed pickup, the signal (logic level) equal to the reference voltage VINT received by the pickup is detected and the logic low level is detected through the reverse II INV1. Signal muscle ATS. Then, the control signal bFPUP transitions to a logic high level (disabled) 201209838 yywO 34802twf.doc/nf turns off the transistor PI, and another control signal FPUN enables (transitions to logic two levels) to conduct the transistor N1 . In the state where the fuse FUSE is not blown (short-circuited), the latches constructed by the transistors P2, P3, N2, and N3 are reset to the ground voltage vss and the detection signal bFLATS is turned into a logic high-level signal. . Please note that although the fuse in the fuse detecting device 100 is in a short-circuit state, the detecting signal bFLATS representing the state of the fuse FUSE exhibits an open state indicating that the fuse FUSE has been blown at the time point τι . (logical level). That is to say, such a conventional fuse detecting device 1 is susceptible to misjudgment. SUMMARY OF THE INVENTION The present invention provides a solubilizing device for removing a wire to effectively avoid the possibility of a wire breakage error. The invention proposes a ray-preparing device, including a side device and a logic operation unit. The controller includes a switch module and a _, a device. The side switch module is connected in series between the first reference voltage and the dissolved wire, receives the second control signal and generates preliminary results according to the first and second control signals and the dissolved/short circuit (4). The ♦ is connected in series between the detection switch module and the second reference voltage. Detecting and locking the switch module and receiving the preliminary _ result, according to ^;, the voltage value of the result or keeping its original stored = stored:, the locker Wei according to the age of the voltage value to produce correction before the _^ father Zhengyi Then including the calibration_module and the correction of the brain 1 positive ^ ^ module 201209838 " a" -. 802twf.doc / n group 'series the first reference voltage and the second reference voltage, receive the first and second Controlling the signal, and generating a calibration result according to the first and second control signals. The calibration latch is coupled to the calibration switch module and receiving the calibration result, correcting the latch to store the calibration result, and outputting the correction signal according to the reverse of the calibration result The logic operation unit is coupled to the detector and the corrector, receives and performs a logic operation according to the pre-correction detection signal and the correction signal, and generates a corrected detection signal. The above features and advantages of the present invention can be more obvious. The following is a detailed description of the embodiment of the present invention. The following is a detailed description of the following description. [Embodiment] Referring now to FIG. 3, FIG. 3 is a schematic diagram of a fuse detecting apparatus 300 according to an embodiment of the present invention. The lysis wire detecting device 300 includes a detector 310, a calibrator 320, and a logic operation unit 330. The detector 310 includes a detection switch module 311 and a detection shackle 312. The detection switch module 311 is connected in series. The control signal bFPUP and the control signal FPUN are received between the reference voltage viNT and the fuse FUSE. The detection switch module 311 generates a preliminary detection result SIG1 according to the short circuit or open state of the control signals bFpup, FPUN and the fuse FUSE, wherein, the fusion The wire FUSE is connected between the detecting switch module 3U and the reference voltage vss. f In the embodiment, the detecting switch module 3U is implemented by a test switch composed of a transistor 1 and an N1, respectively, wherein the transistor is implemented. The detection switch of P1 is lightly connected to the reference voltage VINT and controlled by the control signal bFPUP. The detection switch of the transistor N1 is connected in series with the fuse 1?1; 5£ and the transistor ρι and controlled 201209838 yy-wo 34802tw The detection latch 312 is coupled to the detection switch module 311 and connected to the initial detection result SIG1. The detection latch 312 stores the preliminary detection result SIG1 according to the preliminary detection result SIG1. Detect the voltage value of the result SI(}1 or keep it original Storing the voltage value. Detecting the latch 312 and generating the pre-corrected fine signal SIG2e according to the stored voltage value. Please note that when the transistor P1 in the detecting switch module 311 is turned on according to the control signal bFpup, the battery is turned on. The crystal φ N1 must be turned off, and at the same time, the preliminary detection result 81 (51 will be at the same voltage level as the reference voltage VINT, and the transistor #m ^ according to the control signal FPUN is turned on, the transistor ρι must be turned off. At the same time, if the state of the fuse FUSE is short-circuited, the preliminary detection result SIG1 will be at the same voltage level as the reference voltage vss. Or if it is dissolved, the state of 纟糸FUSE is open circuit, and the preliminary prediction result SIG1 will exhibit a high impedance (although impendence) state. When the detection result SIG1 received by the detection latch 312 is equal to the reference voltage vss or VINT, the detection latch 312 will lock the voltage level corresponding to the preliminary detection result SIG1. • If the initial test result SIG1 is in a high impedance state, the ballast lock 312 maintains the original stored voltage value. In this embodiment, the detection latch 312 includes a buffer constructed by two serially connected inverters consisting of transistors p2, N2, P3, and N3, wherein the output of the buffer is The input terminals are connected and a pre-correction detection signal SIG2 is generated at its output. Please note that the above buffer is constructed by two inverters. It is only an example. It does not limit the buffer in the detection latch 312 of the present invention. Only two inverters can be used to construct 201209838 " "(8)) 2twf.doc / n. The corrector 320 ij includes a correction switch module 321 and a correction lock 322. The correction switch module 321 is connected to the reference voltage vnt and the reference voltage VSS between the correction switch module 321 receiving control The signal is deleted and the control signal FPUN is generated, and the correction result CR is generated according to the control signals bFpup and FpuN. The correction latch 322 is lightly connected to the calibration switch module and receives the correction result CR. The correction latch 322 stores the calibration result cr and corrects it according to the correction. As a result, the CR is inverted to output a correction signal CRS, which causes the correction switch module 321 to generate a correction result CR according to the control signals bFpup and FpuN, which is equal to one of the reference voltage, bribe and vss. When the control money bFPUP is enabled, the voltage value of the correction result cr is equal to the reference voltage VINT, and when the measurement FPUN is enabled, the voltage value of the correction result CR is equal to the reference voltage Na. The logic operation unit 330 receives and performs a logic operation according to the pre-correction detection signal 2 and the correction signal CRS, and generates a corrected detection signal bFLATS. 4, FIG. 4A shows an embodiment of a fuse detecting device 300 according to an embodiment of the present invention, wherein the correcting switch module 321 includes a correcting switch respectively constructed by transistors P4 and N4. The reference electric MvmT' generates the correction wire (3) and is controlled by the control signal bmiPi crystal (10) to be connected between the transistor ρ4^ test voltage VSS' and controlled by the control signal FPUN. In addition, the correction fuse rain SE string Connected to the domain path 201209838 yy-υυο 34802twf.doc/n of the transistor N4 and the reference battery Vs. The correction latch 322 includes a plurality of inverters constructed by the transistors P5, N5, P6 and N6. a buffer connected in series. The output end of the buffer is coupled to the input end, and the output end of the buffer is coupled to the inverter INV2. The correction latch 322 receives and latches the correction result CR and passes through the inverter iNV2. Output to generate a reverse of the correction result CR Correction signal CRS. The logic operation unit 330 is the inverse gate NAND1. The two input terminals of the gate φ NAND1 respectively receive the correction signal CRS and the calibration price k number SIG2 ' and generate a corrected detection signal bFLATS at the output end thereof. In terms of overall operation, please refer to FIG. 4 and FIG. 5 simultaneously, wherein FIG. 5 is a waveform diagram of an embodiment of the fuse detecting device 300 of the present invention. When a reference voltage VINT is used as a power source, it is activated. And gradually rising to a steady state, the control signal bFPUP is maintained at a logic low level and the transistors P1 and P4 are turned on, and the correction result CR and the pre-correction detection signal SIG2 are also equal to a logic high level (equal to the reference voltage V1NT). Voltage level) > At this time, the correction signal CRS presents a logic low level 反向 opposite to the corrected Lu result CR and because the correction signal CRS is at a logic low level, the logic operation unit 330 of the NAND gate NAND1 Corresponding to the corrected detection signal bFLATS that generates a logic high level. Then, after the control signal bFPUP transitions to the logic high level, the control signal FPUN corresponds to the transition state to the logic high level and conducts the crystal Ni. Since the correction fuse DFUSE is always kept in the short circuit state, the correction result CR at this time is equal to The reference voltage VSS assumes a logic low level and the correction signal CRS is a logic high level. The opposite logical operation 201209838 yy-υυο ^4802twf.doc/u unit 330 maintains the corrected high-level corrected detection signal bFLATS. It can be seen from the above description and the illustration of FIG. 5 that in the present embodiment, regardless of the operation of the control signaling FPUP and FPUN, the detection of the logic low level which causes the false positive will not occur. No. bFLATS. That is to say, the sinus detecting device 3 (10) effectively recognizes the misjudgment of the fuse detecting device. , Inc. - As mentioned, since the calibration solution DFUSE is always short-circuited, it may not be necessary. That is, the transistor N4 can be directly connected to the reference voltage VSS. Further, the logic operation unit 33A shown in Fig. 4 is constructed by using the inverse gate = ND1. This reverse gate NANm can also be replaced by a logic circuit such as a gate. Of course, in the case where the logic operation unit 33 is constructed by using the gate and the gate, the meaning of the state of the fuse FUSE represented by the logic level of the corrected debt signal bFLATS will be logically constructed using the inverse gate NAND1. The corrected detection signal bFLATS generated by unit 33A is reversed. In addition, it is worth noting that the timing at which the control signals bFPUp and FPUN are transmitted to the fork controller 320 is earlier than the control signal 1) 1; 1 > 1 and the time point at which the FpuN is transmitted to the detector 310 to determine the correction signal. The generation time of the CRS can be effectively earlier than the pre-correction detection signal SIG2 and mask the portion of the pre-correction detection signal SIG2 that may cause an error. Please refer to FIG. 6. FIG. 6 is a schematic diagram of a fuse detecting apparatus 600 according to another embodiment of the present invention. The fuse detecting device 6 includes a plurality of extended detectors 630 640 and 640, in addition to the 201209838 yy-UUb 34802 twf.doc/n detector 620, the corrector 610, and the logic operation unit 650. The logical operation units 660 to 670 are expanded. Here, the number of extended detectors and extended arithmetic units must be the same (the same is equal to N'N being a positive integer). Moreover, the internal circuits of the extension detectors 630-640 are the same as the internal circuits of the detector 620, and the internal circuits of the logic operations units 660-670 are identical to the internal circuits of the logic operation unit 650. In the present embodiment, the detector 620 and the extension detectors 630-640 can obtain multiple operations by using the common corrector 610 and performing logical operations together with the logic operation unit 650 and the expansion logic operation units 660 to 670. After the correction, the signals bFLATS1 to bFLATS3 are detected, and the state of short circuit or open circuit of the plurality of fuses is known. Incidentally, the control signals pFPUP and FPUN are transmitted to the corrector 610 at a point in time earlier than the control signals bFPUP and FPUN are transmitted to the detector 62 and the detectors 630 to 640 are extended. ,. As described in the above, the present invention utilizes a corrector to provide a correction signal to mask a portion of the pre-correction detection signal that may be misjudged by a logical operation for a single year. Moreover, the correction signal is generated by the fuse detection device internally, which can effectively avoid interference of other signals. Although the present invention has been disclosed in the above embodiments, it is not intended to limit the general knowledge in the field of technology, without departing from the spirit and scope of the invention, when a slight change can be made and the protection of the invention is (4) The application for the purpose of the application shall be subject to the definition. 201209838—, ..... J8〇2twf.doc/n [Simplified Schematic Description] Fig. 1 shows a conventional waveform. Fig. 2 shows a waveform diagram of the glare detecting device 100. . FIG. 4 is a view showing a fuse detecting device according to an embodiment of the present invention. FIG. 4 illustrates an embodiment of a solution detecting device according to an embodiment of the present invention. FIG. 5 and FIG. A waveform diagram of an embodiment of a dissolved filament detecting device of the invention. Figure 6 depicts the opening of the fuse detection device 600 in accordance with another embodiment of the present invention. [Main component symbol description] 100, 300, 600: fuse detecting device 321: correction switch module 322: correction latch 330, 650: logic operation unit 310, 620: detector 320, 610: corrector 330 : Logic operation unit 311: detection switch module 312: detection 拴 locker 630 640 640: expansion detector 660 ~ 670: expansion logic operation unit 201209838 yy-υυο 34802twf.doc / n SIGl: preliminary detection result SIG2 : Pre-correction detection signal CR: Correction result CRS: Correction signals P1 to P6, N1 to N6: Transistor INV INV2: Inverter bFPUP, FPUN: Control signal bFLATS: Detection signal FUSE, DFUSE: Fuse VSS, VINT: reference voltage NAND1: reverse gate