201206038 六、發明說明： 【發明所屬之技術領域】 本發明一般係有關電源，更具體地說，係有關開關變 換器。 【先前技術】 大多數電子產品，諸如筆記型電腦、桌上型電腦、 PDA等，需要直流（DC )電源向各個功能模組提供經過 調節的功率。DC-DC同步降壓式變換器具有效率高、體積 小等優點，而獲得到了廣泛的應用。低的電壓波紋和快速 的暫態響應是DC-DC同步降壓式變換器最基本的要求。201206038 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates generally to power supplies, and more particularly to switch converters. [Prior Art] Most electronic products, such as notebook computers, desktop computers, PDAs, etc., require a direct current (DC) power supply to provide regulated power to each functional module. The DC-DC synchronous buck converter has many advantages such as high efficiency and small size, and has been widely used. Low voltage ripple and fast transient response are the most basic requirements for DC-DC synchronous buck converters.
滯環控制電路具有暫態響應速度快、結構簡單等優點 ，可以作爲DC-DC同步降壓式變換器的控制電路，如圖1 所示，輸入電壓經由電晶體1 〇 1和1 02的調變，被耦合到 由電感器103和電容器104所組成的輸出濾波器，濾波之 後的電壓被輸出到負載電阻105，輸出電壓VQUl經由由電 阻器1 0 6和1 0 7所構成的電壓取樣電路而將電壓取樣信號 FB反饋到滯環比較器1 08的輸入端，與上限閾値電壓VH 和下限閩値電壓Vl相比較，滯環比較器1 〇8的輸出信號 係耦接到驅動電路109，驅動電路109產生相應的驅動信 號，以控制電晶體1 01和1 02的導通和關斷，電晶體1 〇 1 和1 02的閘極驅動信號是互補的。圖1的示例示出，電晶 體101和102爲金屬氧化物半導體場效電晶體（MOSFET )，在其他示例中，可以使用諸如雙極接面電晶體（BJT 201206038 )或絕緣閘雙極電晶體（IGBT )之類的其他適當電子設備 來加以實現》圖2示出了圖1中之電壓取樣信號FB、電 晶體1 〇 1和1 02的閘極驅動信號波形。反饋信號FB達到 上限閩値VH時，電晶體101被關斷，電晶體102被導通 ，當反饋信號FB達到下限閾値Vl時，電晶體1〇2被關斷 ，電晶體101被導通。但滯環控制電路過分依賴輸出電壓 諧波，經由將電壓諧波與上下兩個閎値電壓相比較來產生 上下兩個電晶體的控制信號，變換器的輸出電壓諧波無法 被控制在理想範圍內，變換器的切換頻率也會因週邊元件 和操作條件的改變而發生變化。 圖3示出了採用恒定導通時間（COT )控制電路的 DC-DC同步降壓式變換器電路。輸出電壓V。^經由電壓 取樣電路而將電壓取樣信號FB反饋到比較器3 08的輸入 端，與參考電壓信號VREF相比較，比較器3 08的輸出信 號被耦接到驅動電路109，同時導通計時電路310也被耦 接到驅動電路1 09，經由將電壓取樣信號FB與參考電壓 信號VREF相比較來產生電晶體101的導通信號，電晶體 1 0 1的導通時間是固定的，由導通計時電路3 1 0所控制。 這種方法減小了輸出電壓的諧波，但是電晶體1 〇 1的關斷 時間是可變的，變換器的切換頻率也會相應變化。由於採 用恒定導通時間控制，省略了上限閾値電壓，如果在電晶 體1 0 1導通時刻產生負載跳變的情況，電路無法做出迅速 的暫態響應，必須等到導通時間結束才能關斷電晶體1 0 1 ，這會導致輸出電壓有較大幅度的變化。圖4示出了圖3 -6- 201206038 中之電壓取樣信號FB和電晶體1 〇 1閘極驅動信號的波形 。當反饋信號FB達到參考電壓信號VREF時’電晶體101 被導通，導通時間Τπ係由導通計時電路3 1 0所控制。採 用恒定導通時間（COT)控制電路的DC-DC同步降壓式變 換器電路，輸出電壓諧波獲得到了改善’但切換頻率仍然 會因週邊元件和操作條件的改變而發生變化’並且惡劣情 況下的暫態響應速度會受到限制。 【發明內容】 本發明的目的在於提供一種開關變換器的裝置，使其 輸出電壓波紋控制在小的範圍內，具有快速的暫態響應速 度，開關管的切換頻率穩定。 本發明的目的在於提供一種開關變換器的方法，將該 開關變換器的輸出電壓波紋控制在小的範圍內，使其具有 快速的暫態響應速度，以確保開關管的切換頻率穩定。 爲了實現上述發明目的，開關變換器電路包括：輸入 端子，以接收輸入電壓；輸出端子，係耦接到負載電路， 而爲所述負載電路提供輸出電壓；反饋電路，係與輸出電 壓相耦接，以提供反饋信號給驅動電路；驅動電路，係與 反饋電路相耦接，以輸出驅動信號；開關電路，基於驅動 電路輸出的驅動信號而切換開關管導通或關斷。 在一個實施例中，所述反饋電路包括電壓取樣電路， 對所述輸出電壓進行取樣，以產生電壓取樣信號。 在一個實施例中，所述反饋電路還包括導通計時電路 201206038 ，所述導通計時電路輸出導通計時信號。 在一個實施例中，所述反饋電路還包括自適 所述自適應模組接收所述驅動信號和導通計時信 出上限閩値電壓和下限閩値電壓。 在一個實施例中，所述反饋電路還包括比較 所述比較器電路將所述電壓取樣信號與所述上限 和所述下限閾値電壓相比較，以產生所述反饋信 在一個實施例中，所述導通計時電路係耦合 入電壓，包括一個由至少一個鏡像電流源和一個 器所耦接而成的充電電路，和一個比較電路；所 容器的一端係耦接到所述比較電路，與一個參考 較，以產生所述導通計時信號。 在一個實施例中，所述自適應模組包括一個 個第一電晶體和一個第一電流源所耦接而成的放 和一個由至少一個第二電晶體和一個第二電流源 成的充電電路。 在一個實施例中，所述第一電晶體的閘極係 述驅動電路輸出的驅動信號，所述第二電晶體的 接到所述導通計時信號。 在一個實施例中，所述自適應模組還包括一 電路' 充電電路相耦接的第二電容器’所述第一 導通時，第一電流源給所述第二電容器放電；所 晶體被導通時，所述第二電流源給所述第二電容 在一個實施例中，所述自適應模組還包括參 應模組， 號，以輸 器電路， 閾値電壓 0|^ 疏。 到所述輸 第一電容 述第一電 電壓相比 由至少一 電電路， 所耦接而 耦接到所 閘極係耦 個與放電 電晶體被 述第二電 器充電。 考電壓源 -8 - 201206038 ，輸出所述下限閾値電壓；所述參考電壓源與一個滯環電 壓源相耦接後，與所述第二電容器相耦接；所述參考電壓 源、滯環電壓源和第二電容器三者的電壓相加後，輸出所 述上限閾値電壓。 在一個實施例中，所述自適應模組還包括參考電壓源 ，輸出所述上限閩値電壓；所述參考電壓源與負的一個滯 環電壓源相耦接後，與所述第二電容器相耦接；所述參考 電壓源電壓減去滯環電壓源電壓、第二電容器電壓後，輸 出所述下限閾値電壓。 在一個實施例中，所述開關電路包括第一開關管和第 二開關管，其中，第一開關管的源極與第二開關管的汲極 相耦接作爲輸出端，再經濾波電路而與輸出端子相耦接。 在一個實施例中，所述驅動信號爲兩路互補的脈衝信 號，係分別耦接到第一開關管、第二開關管的閘極。 本發明採用上述結構的裝置和/或方法，經由電壓取 樣電路取樣開關變換器輸出電壓信號，經由反饋電路而被 提供給驅動電路，以控制開關管的導通與關斷，可以對輸 出電壓進行調節；自適應控制電路提供上下限閾値電壓， 使開關變換器具有快速的暫態響應速度，即使是最惡劣的 情況也能快速響應；另外，自適應控制電路能夠根據開關 變換器的實際操作情況，調節上限閾値電壓和/或下限閩 値電壓，以使開關管的切換頻率穩定。 【實施方式】 s -9 - 201206038 揭示一種用於開關變換器的方法和裝置。在以下描述 中，爲了提供對本發明的透徹理解，闡述了許多特定細節 。然而，對於本領域普通技術人員顯而易見的是：不必採 用這些特定細節來實行本發明。在其他實例中，爲了避免 混淆本發明，並未具體描述公知的材料或方法。 在整個說明書中，對“ 一個實施例”、“實施例”、 “ 一個示例”或“示例”的提及意謂：結合該實施例或示 例描述的特定特徵、結構或特性被包含在本發明至少一個 實施例中。因此，在整個說明書的各個地方出現的短語“ 在一個實施例中”、"在實施例中”、“一個示例”或“ 示例”不一定都指同一個實施例或示例。此外，可以以任 何適當的組合和/或子組合而將特定的特徵、結構或特性 組合在一個或多個實施例或示例中。此外，本領域普通技 術人員應當理解，在此提供的示圖都是爲了說明的目的， 並且示圖不一定是按比例來予以繪製的。 圖5爲根據本發明的一個實施例，輸入電壓被耦合到 輸入電容器和開關電路，開關電路係由電晶體101和102 所組成，電晶體1 〇 1和1 02的公共點係耦接到由電感器 103和電容器104所構成的濾波器，而濾波器的輸出係耦 合到負載電路。自適應滯環控制電路5 1 1的一個輸入端係 耦接到電晶體1 〇 1的閘極，以接收其驅動控制信號HS， 自適應滯環控制電路5 1 1的另一個輸入端係耦接到導通計 時電路510，以接收其導通計時信號。自適應滯環控制電 路5 1 1的輸出信號係分別耦接到滯環比較器508的兩個輸 -10- 201206038 入端，而爲其提供上限閾値電壓VH和下限閾値電眉 由電阻器106和107所構成的電壓取樣電路，對輸 VQUt進行取樣，將電壓取信號FB反饋到滯環比較 的另一個輸入端。滞環比較器508將電壓取樣信號 上下限閾値電壓相比較，將比較結果耦接到驅動電 ，驅動電路1 〇 9根據比較結果而輸出互補的驅動信 控制電晶體1 〇 1和1 02的導通和關斷。 圖6爲本發明中導通計時電路510的一個實施 通計時電路5 1 0係鍋接到輸入電壓V i n，鏡像電流 以電流I給電容器602充電，電容器602上的電壓 到比較器6 0 3的輸入端，藉由設定鏡像電流源6 0 1 器602就可以確定導通計時信號。參考電壓信號A 耦接到比較器603的另一個輸入端，與電容器602 相比較，比較器6 0 3根據比較結果而輸出導通計時 導通計時信號係耦接到自適應滯環控制電路5 1 1的 入端。 圖7爲本發明中自適應控制電路511的一個實 電晶體70 1的閘極係耦接到電晶體1 0 1的閘極驅 HS，電晶體702的閘極係耦接到導通計時信號。當 號爲高位準時，電晶體701被導通，電流源704經 體701而以電流II給電容器703放電；當導通計 爲高位準時，電晶體702被導通，電流源705經由 7 02而以電流12給電容器703充電。參考電壓信弱 下限閾値電壓，與一個滯環電壓相加，例如圖7中 ! V l ° 出電壓 器 508 FB與 路 1 09 號，以 例。導 源601 係耦接 與電容 'R E F 係 上電壓 信號， 一個輸 施例。 動信號 HS信 由電晶 時信號 電晶體 ί V L爲 所示的 -11 - 201206038 1 5 mV，但具體應用中可以根據實際情況而調整，將求和 後的電壓與電容器703上的電壓Vc相加，獲得到的電壓 爲上限閩値電壓VH，VH = VL+15mV + Vc(可以經由加法器電 路來予以實現）。圖8爲圖7中上限閩値電壓和下限閾値 電壓之關係的示意圖，下限閾値電壓乂1^是固定的，滯環 電壓提供穩定操作時上限閩値電壓VH與下限閾値電壓VL 之間的差値，而這個差値又與電容器703上的電壓Vc相 疊加，這樣上限閾値電壓V η會根據實際操作狀況而進行 調整，以實現自適應控制。例如11 =12的情況，電晶體 701的導通時間爲T^-hs，電晶體702的導通時間爲T^-cot ，如果 TwhpTw.cot，電容器 703上的電壓 Vc = 0， VH = VL+15mV;如果 Ton.Hs<Ton-c〇T，電容器 703 上的電壓 Vc>0，VH>VL+15mV，電晶體101的導通時間Tm-hs會變 大，以達到更高的上限閾値VH;如果T^hPT^.cot，電 容器703上的電壓Vc<0，VH<VL+15mV，電晶體101的導 通時間T^.hs會變小，因爲上限閾値電壓VH變小了。自 適應控制電路會根據開關變換器實際操作情況而對上限閾 値電壓進行調節，確保切換頻率在很小的範圍內變化。並 且自適應控制電路輸出上限閩値電壓和下限閾値電壓，能 夠確保開關變換器在最惡劣情況下的暫態響應速度。 圖9爲根據本發明進行模擬而獲得到的波形圖。下限 閾値電壓Vl爲固定値800 mV，輸入電壓Vin在5 V到16 V 之間變化，上限閩値VH也相應的在8 1 0 mV到8 1 5 mV之 間變化，上限閩値會根據實際操作情況而進行自適應調節 -12- 201206038 圖10爲根據本發明自適應控制電路511的另一個實 施例。參考電壓信號VH爲上限閩値電壓，VH是一個固定 的電壓’與一個滯環電壓相減，例如圖1 0中所示的15 m V ’但具體應用中可以根據實際情況而調整，將求差後的電 壓與電容器703上的電壓Vc相減，獲得到的電壓爲下限 閩値電壓V L ’ V L= V Η -1 5 m V - V c (可以經由減法器電路來 予以實現）。 以上對本發明的示出示例的描述，包括摘要中所描述 的，並不希望是毫無遺漏的或者是對所揭示的精確形式的 限制。儘管出於說明性目的而在此描述了本發明的特定實 施例和示例，但是在不偏離本發明的更寬的精神和範圍的 情況下，各種等同修改是可以的。實際上，應當理解，特 定電壓、電流、頻率、功率範圍値、時間等被提供用於說 明目的，並且其他値也可以用在根據本發明教導的其他實 施例和示例中。 根據以上詳細描述，可以對本發明的示例進行這些修 改。以下申請專利範圍中所使用的術語不應該被理解爲將 本發明限制於說明書和申請專利範圍中所揭示的特定實施 例。而是，範圍完全由以下申請專利範圍所確定，申請專 利範圍要根據已制定的申請專利範圍解釋原則來加以理解 。因此，本說明書和圖式被視爲說明性的而非限制性的。 【圖式簡單說明】 -13- 201206038 圖1是經由滯環控制電路來控制DC-DC同步降壓式 變換器的示意圖。 圖2是圖1中電晶體閘極驅動信號和電壓取樣信號波 形。 圖3是經由恒定導通時間控制電路來控制DC-DC同 步降壓式變換器的示意圖。 圖4是圖3中電晶體閘極驅動信號和電壓取樣信號波 形。 圖5是本發明經由自適應控制電路控制DC-DC同步 降壓式變換器的一個實施例的示意圖》 圖6是圖5中導通計時電路一個實施例的示意圖。 圖7是圖5中自適應控制電路一個實施例的示意圖。 圖8是圖7中上限電壓閾値和下限電壓閾値的示意圖 〇 圖9是圖5中電路模擬結果的示意圖。 圖10是圖5中自適應控制電路另一個實施例的示意 圖。 【主要元件符號說明】 1 〇1 :電晶體 ·‘電晶體 1〇3 :電感器 104 :電容器 1 〇 5 :負載電阻器 -14- 201206038 1 Ο 6 :電阻器 107 :電阻器 108 :滞環比較器 1 〇 9 :驅動電路 3 08 :比較器 3 1 0 :導通計時電路 5 08 :滯環比較器 5 1 0 :導通計時電路 5 1 1 :自適應滯環控制電路 6 0 1 :鏡像電流源 602 :電容器 603 :電容器 701 :電晶體 7 0 2 :電晶體 703 :電容器 704 :電流源 705 :電流源 FB :電壓取樣信號 H S :驅動控制信號The hysteresis control circuit has the advantages of fast transient response speed and simple structure. It can be used as the control circuit of the DC-DC synchronous buck converter. As shown in Figure 1, the input voltage is adjusted via the transistors 1 〇1 and 102. The output is coupled to an output filter composed of an inductor 103 and a capacitor 104. The filtered voltage is output to a load resistor 105, and the output voltage VQU1 is passed through a voltage sampling circuit composed of resistors 106 and 107. The voltage sampling signal FB is fed back to the input end of the hysteresis comparator 168, and compared with the upper threshold 値 voltage VH and the lower 闽値 voltage V1, the output signal of the hysteresis comparator 1 〇8 is coupled to the driving circuit 109, The drive circuit 109 generates corresponding drive signals to control the turn-on and turn-off of the transistors 101 and 102, and the gate drive signals of the transistors 1 〇1 and 102 are complementary. The example of FIG. 1 shows that the transistors 101 and 102 are metal oxide semiconductor field effect transistors (MOSFETs), and in other examples, such as bipolar junction transistors (BJT 201206038) or insulated gate bipolar transistors can be used. Other suitable electronic devices such as (IGBT) are implemented. FIG. 2 shows the gate drive signal waveforms of the voltage sampling signal FB, the transistors 1 〇1 and 102 in FIG. When the feedback signal FB reaches the upper limit 闽値VH, the transistor 101 is turned off, and the transistor 102 is turned on. When the feedback signal FB reaches the lower limit threshold 値V1, the transistor 1〇2 is turned off, and the transistor 101 is turned on. However, the hysteresis control circuit relies too much on the output voltage harmonics. By comparing the voltage harmonics with the upper and lower 闳値 voltages to generate the control signals of the upper and lower transistors, the output voltage harmonics of the converter cannot be controlled within the ideal range. Within this, the switching frequency of the converter also changes due to changes in peripheral components and operating conditions. Figure 3 shows a DC-DC synchronous buck converter circuit employing a constant on-time (COT) control circuit. Output voltage V. The voltage sampling signal FB is fed back to the input terminal of the comparator 308 via the voltage sampling circuit. Compared with the reference voltage signal VREF, the output signal of the comparator 308 is coupled to the driving circuit 109, and the timing circuit 310 is also turned on. Being coupled to the driving circuit 109, the conduction signal of the transistor 101 is generated by comparing the voltage sampling signal FB with the reference voltage signal VREF, and the on-time of the transistor 101 is fixed, and the conduction timing circuit 3 1 0 is controlled. This method reduces the harmonics of the output voltage, but the turn-off time of the transistor 1 〇 1 is variable and the switching frequency of the converter changes accordingly. Since the constant on-time control is adopted, the upper threshold 値 voltage is omitted. If the load jump occurs when the transistor 1 0 1 is turned on, the circuit cannot make a rapid transient response, and the transistor 1 must be turned off after the on-time is over. 0 1 , this will cause a large change in the output voltage. Figure 4 shows the waveforms of the voltage sampling signal FB and the transistor 1 〇 1 gate driving signal in Figure 3-6-201206038. When the feedback signal FB reaches the reference voltage signal VREF, the transistor 101 is turned on, and the on-time Τπ is controlled by the turn-on timing circuit 310. DC-DC synchronous buck converter circuit with constant on-time (COT) control circuit, the output voltage harmonics are improved 'but the switching frequency will still change due to changes in peripheral components and operating conditions' and in the worst case The transient response speed is limited. SUMMARY OF THE INVENTION An object of the present invention is to provide a device for a switching converter that has its output voltage ripple controlled within a small range, has a fast transient response speed, and has a stable switching frequency of the switching transistor. SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of switching a converter that controls the output voltage ripple of the switching converter to a small range to provide a fast transient response speed to ensure stable switching frequency of the switching transistor. In order to achieve the above object, a switching converter circuit includes: an input terminal for receiving an input voltage; an output terminal coupled to the load circuit to provide an output voltage for the load circuit; and a feedback circuit coupled to the output voltage To provide a feedback signal to the driving circuit; the driving circuit is coupled to the feedback circuit to output the driving signal; and the switching circuit switches the switching tube to be turned on or off based on the driving signal outputted by the driving circuit. In one embodiment, the feedback circuit includes a voltage sampling circuit that samples the output voltage to generate a voltage sampling signal. In one embodiment, the feedback circuit further includes a turn-on timing circuit 201206038, and the turn-on timing circuit outputs a turn-on timing signal. In one embodiment, the feedback circuit further includes adaptively receiving the driving signal and the on-time signal upper limit voltage and the lower limit voltage. In one embodiment, the feedback circuit further includes comparing the comparator circuit to compare the voltage sampling signal to the upper limit and the lower threshold 値 voltage to generate the feedback signal. In one embodiment, The conduction timing circuit is coupled to the voltage, comprising a charging circuit coupled by at least one mirror current source and a device, and a comparison circuit; one end of the container is coupled to the comparison circuit, and a reference In order to generate the conduction timing signal. In one embodiment, the adaptive module includes a first transistor coupled to a first current source and a charge coupled by at least one second transistor and a second current source. Circuit. In one embodiment, the gate of the first transistor is a driving signal output by the driving circuit, and the second transistor is connected to the conduction timing signal. In one embodiment, the adaptive module further includes a circuit 'the second capacitor coupled to the charging circuit'. When the first is turned on, the first current source discharges the second capacitor; the crystal is turned on. The second current source is provided to the second capacitor. In one embodiment, the adaptive module further includes a component, a number, and a driver circuit, and the threshold voltage is 0. The first capacitor is coupled to the first capacitor by at least one electrical circuit, coupled to the gate coupled to the second transistor, and the second transistor is coupled to the discharge transistor. Test voltage source -8 - 201206038, output the lower threshold threshold ; voltage; the reference voltage source is coupled to a hysteresis voltage source, coupled to the second capacitor; the reference voltage source, hysteresis voltage After the voltages of the source and the second capacitor are added, the upper threshold 値 voltage is output. In one embodiment, the adaptive module further includes a reference voltage source that outputs the upper threshold voltage; the reference voltage source is coupled to a negative hysteresis voltage source, and the second capacitor The phase voltage is coupled to the reference voltage source voltage minus the hysteresis voltage source voltage and the second capacitor voltage, and the lower threshold threshold voltage is output. In one embodiment, the switching circuit includes a first switching transistor and a second switching transistor, wherein a source of the first switching transistor is coupled to a drain of the second switching transistor as an output terminal, and then is filtered by the circuit. It is coupled to the output terminal. In one embodiment, the driving signals are two complementary pulse signals coupled to the gates of the first switching transistor and the second switching transistor, respectively. The present invention adopts the above-mentioned structure device and/or method, and samples the switching converter output voltage signal via a voltage sampling circuit, and is supplied to the driving circuit via a feedback circuit to control the switching transistor to be turned on and off, and the output voltage can be adjusted. The adaptive control circuit provides upper and lower threshold 値 voltage, so that the switching converter has a fast transient response speed, which can respond quickly even in the worst case; in addition, the adaptive control circuit can be based on the actual operation of the switching converter. The upper threshold 値 voltage and/or the lower 闽値 voltage are adjusted to stabilize the switching frequency of the switching tube. [Embodiment] s -9 - 201206038 discloses a method and apparatus for a switching converter. In the following description, numerous specific details are set forth in order to provide a thorough understanding of the invention. However, it will be apparent to those skilled in the art that the present invention may be practiced without these specific details. In other instances, well-known materials or methods have not been specifically described in order to avoid obscuring the invention. Reference throughout the specification to "one embodiment", "an embodiment", "an" or "an" or "an" In at least one embodiment. Thus, the appearances of the phrase "in one embodiment", ",",,,,,,,, Specific features, structures, or characteristics may be combined in any suitable combination and/or sub-combination in one or more embodiments or examples. In addition, one of ordinary skill in the art will appreciate that the illustrations provided herein are for The purpose of the description, and the drawings are not necessarily drawn to scale. Figure 5 illustrates an input voltage coupled to an input capacitor and a switching circuit, the switching circuit being comprised of transistors 101 and 102, in accordance with one embodiment of the present invention. The common points of the transistors 1 〇 1 and 102 are coupled to a filter formed by the inductor 103 and the capacitor 104, and the output of the filter is coupled to the load circuit. The adaptive hysteresis control circuit 51 1 An input is coupled to the gate of the transistor 1 〇1 to receive its drive control signal HS, and the other input of the adaptive hysteresis control circuit 51 1 is coupled to the conduction meter The circuit 510 receives the turn-on timing signal. The output signals of the adaptive hysteresis control circuit 51 are respectively coupled to the two inputs of the hysteresis comparator 508, and the upper limit threshold is provided. Voltage VH and lower threshold threshold The voltage sampling circuit formed by resistors 106 and 107 samples the input VQUt and feeds the voltage take signal FB back to the other input of the hysteresis comparison. The hysteresis comparator 508 samples the voltage. Comparing the signal upper and lower thresholds 値 voltage, the comparison result is coupled to the driving power, and the driving circuit 1 〇9 outputs the complementary driving signal control transistors 1 〇 1 and 102 according to the comparison result. In the invention, one implementation of the on-time circuit 510 of the on-time circuit 510 is connected to the input voltage V in , the mirror current is charged to the capacitor 602 by the current I, and the voltage on the capacitor 602 is input to the input of the comparator 603. The turn-on timing signal can be determined by setting the mirror current source 601. The reference voltage signal A is coupled to the other input of the comparator 603, and compared to the capacitor 602, the comparator 605 is based on The output turn-on timing turn-on timing signal is coupled to the input of the adaptive hysteresis control circuit 51. Figure 7 is a gate coupling of a real transistor 70 1 of the adaptive control circuit 511 of the present invention. To the gate drive HS of the transistor 101, the gate of the transistor 702 is coupled to the turn-on timing signal. When the number is high, the transistor 701 is turned on, and the current source 704 is supplied to the capacitor via the body 701 with the current II. 703 discharge; when the conduction meter is high, the transistor 702 is turned on, and the current source 705 charges the capacitor 703 with the current 12 via 702. The reference voltage weak lower threshold 値 voltage is added to a hysteresis voltage, for example, FIG. Medium! V l ° Output voltage 508 FB and road No. 09, for example. The source 601 is coupled to a voltage signal on the capacitor 'R E F , an embodiment. The signal HS signal is -11 - 201206038 1 5 mV, but it can be adjusted according to the actual situation, and the summed voltage is compared with the voltage Vc on the capacitor 703. Add, the obtained voltage is the upper limit 闽値 voltage VH, VH = VL + 15mV + Vc (can be realized by the adder circuit). 8 is a schematic diagram showing the relationship between the upper limit 闽値 voltage and the lower limit threshold 値 voltage in FIG. 7. The lower limit threshold 値 voltage 乂1^ is fixed, and the hysteresis voltage provides a difference between the upper limit 闽値 voltage VH and the lower limit threshold VL voltage VL during stable operation.値, and this difference is superimposed on the voltage Vc on the capacitor 703, so that the upper threshold 値 voltage V η is adjusted according to the actual operating conditions to achieve adaptive control. For example, in the case of 11 = 12, the on-time of the transistor 701 is T^-hs, the on-time of the transistor 702 is T^-cot, and if TwhpTw.cot, the voltage on the capacitor 703 is Vc = 0, VH = VL + 15 mV If Ton.Hs <Ton-c〇T, the voltage Vc > 0, VH > VL + 15 mV on the capacitor 703, the on-time Tm-hs of the transistor 101 becomes larger to reach a higher upper threshold 値VH; T^hPT^.cot, the voltage Vc < 0, VH < VL + 15 mV on the capacitor 703, the on-time T^.hs of the transistor 101 becomes smaller because the upper limit threshold voltage VH becomes smaller. The adaptive control circuit adjusts the upper threshold 値 voltage according to the actual operation of the switching converter to ensure that the switching frequency varies within a small range. Moreover, the adaptive control circuit outputs an upper limit voltage and a lower threshold voltage, which can ensure the transient response speed of the switching converter under the worst conditions. Figure 9 is a waveform diagram obtained by simulation in accordance with the present invention. The lower threshold 値 voltage Vl is fixed at m800 mV, the input voltage Vin varies between 5 V and 16 V, and the upper limit 闽値VH also varies between 8 1 0 mV and 8 15 mV. The upper limit 根据 is based on the actual Adaptive adjustment by operation -12-201206038 Figure 10 is another embodiment of an adaptive control circuit 511 in accordance with the present invention. The reference voltage signal VH is the upper limit 闽値 voltage, VH is a fixed voltage 'subtracted from a hysteresis voltage, such as 15 m V ' shown in Figure 10, but the specific application can be adjusted according to the actual situation, will be The difference voltage is subtracted from the voltage Vc on the capacitor 703, and the obtained voltage is the lower limit 闽値 voltage VL ' VL = V Η -1 5 m V - V c (can be implemented via a subtractor circuit). The above description of the illustrated examples of the invention, including the description of the present invention, is not intended to be exhaustive or to limit the precise form disclosed. Although the specific embodiments and examples of the invention have been described herein for illustrative purposes, various equivalent modifications are possible without departing from the spirit and scope of the invention. In fact, it should be understood that specific voltages, currents, frequencies, power ranges, time, etc. are provided for illustrative purposes, and other aspects may be used in other embodiments and examples in accordance with the teachings of the present invention. These modifications can be made to the examples of the invention in light of the above detailed description. The terms used in the following claims should not be construed as limiting the invention to the specific embodiments disclosed in the specification and claims. Rather, the scope is determined entirely by the scope of the patent application below, and the scope of the patent application is to be understood in accordance with the principles of interpretation of the scope of the patent application that has been established. Accordingly, the specification and drawings are to be regarded as [Simplified illustration] -13- 201206038 Figure 1 is a schematic diagram of controlling a DC-DC synchronous buck converter via a hysteresis control circuit. Figure 2 is a waveform diagram of the transistor gate drive signal and voltage sample signal of Figure 1. Figure 3 is a schematic diagram of a DC-DC synchronous buck converter controlled via a constant on-time control circuit. Figure 4 is a waveform diagram of the transistor gate drive signal and voltage sample signal of Figure 3. Figure 5 is a schematic diagram of one embodiment of a DC-DC synchronous buck converter controlled by an adaptive control circuit of the present invention. Figure 6 is a schematic diagram of one embodiment of the turn-on timing circuit of Figure 5. Figure 7 is a schematic illustration of one embodiment of the adaptive control circuit of Figure 5. Figure 8 is a schematic diagram of the upper limit voltage threshold 下限 and the lower limit voltage threshold 图 in Figure 7 〇 Figure 9 is a schematic diagram of the circuit simulation result of Figure 5. Figure 10 is a schematic illustration of another embodiment of the adaptive control circuit of Figure 5. [Main component symbol description] 1 〇1: transistor · 'Cell crystal 1〇3: Inductor 104: Capacitor 1 〇5: Load resistor-14- 201206038 1 Ο 6 : Resistor 107: Resistor 108: Hysteresis Comparator 1 〇9: Drive circuit 3 08: Comparator 3 1 0 : On-time timer circuit 5 08 : Hysteresis comparator 5 1 0 : On-time timer circuit 5 1 1 : Adaptive hysteresis control circuit 6 0 1 : Mirror current Source 602: capacitor 603: capacitor 701: transistor 7 0 2 : transistor 703: capacitor 704: current source 705: current source FB: voltage sampling signal HS: drive control signal