TW201203520A - Transistor having an adjustable gate resistance and semiconductor device comprising the same - Google Patents

Abstract

A memory device comprises an array of memory cells each capable of storing multiple bits of data. The memory cells are arranged in memory strings that are connected to a common source line. Each memory cell includes a programmable transistor connected in series with a fixed resistance. The transistor includes a gate dielectric that is switchable between a plurality of different resistance values. The threshold voltage of the transistor changes according to the resistance value of the gate dielectric. Memory states of the memory cells can thus be associated with respective resistance values of the dielectric layer of the transistor.

Description

201203520

I W5964PA VI. Description of the Invention: [Technical Field of the Invention] The present invention relates to an electronic memory element for use as a non-volatile sputum--from the singularity of the previous two, semiconductor memory components . electronic. The hidden parts are known as electronic components that are widely known and can be found in different electronic systems. For example, 'electronic memory components (sometimes referred to as computer memory) can be found in computers & other computer components. Different removable electronic memory components or stand-alone electronic memory components are also known, such as memory cards or solid state data access systems. For example, 'like using a removable memory card to access a photo from a digital camera, or using a digital video recorder to access a recorded movie. Most electronic memory components can be distinguished as volatile or non-volatile. A typical volatile electronic memory component is a type of power source that is required to maintain the stored information. The volatile electronic memory component can be, for example, a static random access device, a body (SRAM), or a dynamic random access memory (DRam). The memory component is SRAM or DRAM only when the computer is turned on. In order to retain the stored data, when the computer is turned off or the power is turned off, the previously stored data will be lost. In contrast, a generally non-volatile electronic memory component has this force that retains stored data without an external power source. The non-volatile memory is, for example, a memory card, and the memory card is widely used in digital cameras. The memory card can store photos taken by the camera, and the memory card retains the photo data even if the memory card has been removed from the camera. As systems using electronic memory components become more powerful, the requirements for data storage capacity for 201203520 also increase. ,, 'a large number of random access records, J 2nd generally with:: higher resolution camera manufacturing more =:= 榀 就 要 要 要 要 要 要 要 要 要 要 要 找出 找出 找出 找出 找出 找出 找出 找出 找出 找出 找出 找出 找出 找出 找出 找出 找出 找出 找出 找出Storage and ^: It is not enough to just increase the capacity. Tongguan also hopes to increase the data storage capacity while the size of the component is the same as its $-available. The size of the π piece is reduced. Therefore, increasing the data storage capacity under the size of 2 and 7 is the trend of the electronic memory S piece = another trend, in other words, the trend toward a larger bit density: There are cost considerations. For example, when the bit density of several electronic brothers is increased, it is hoped to maintain or reduce the manufacturing cost. In other words, it is hoped to reduce the bit cost of electronic memory components. (per-bit manufacturing cost). Another consideration is the related performance', for example, to provide faster data storage on electronic memory components and faster storage of data access. The method is to reduce Don't remember the size of the cell. For example, when the process is improved, a smaller structure can be formed, which allows a smaller memory cell to be fabricated. However, some points indicate that the bit cost in the future when using this method. It will start to increase, because the process cost will start to increase more rapidly than the speed of memory cell reduction. SUMMARY OF THE INVENTION The present invention discloses a memory device and a memory device for a memory element 201203520 I wjy〇 According to the aspect of the disclosure, a memory device can include a memory cell array, wherein at least one of the plurality of memory cells has a first end, a second end, and a gate structure. The transistor, and the gate structure comprises a gate dielectric layer. The memory cell further comprises a resistor connected in series with the gate structure of the transistor. The gate dielectric layer is switchably corresponding to the -first resistance The value and the _second resistance value, the first resistance value and the second resistance value respectively correspond to the first-memory state and the second memory state.

The gate-resistance value of the gate' electrical layer corresponds to a soft collapse state of the transistor. The second resistance value of the gate dielectric layer corresponds to at least partially reversing the soft collapse state of the transistor. This transistor may further include a well region endpoint. A read operation, a programming #, and a - erase operation may include applying a predetermined power i: to the well region H. The programming operation includes applying a predetermined voltage to the gate structure 'and the erase operation includes A predetermined voltage is applied to the end of the well. This series

(4) It can induce the soft collapse state of the transistor. This erase operation reverses the soft collapse state of the transistor at least minutely. The gate dielectric layer may include at least one of SiO2 (Si〇2), oxidized (Hf〇2), zirconia (zroj, and TiO 2). 0 The resistance may include a high The resistor value layer, and the gate structure may comprise a low resistance layer ' and wherein 6 the resistor layer may be disposed between the gate dielectric layer and the low resistance layer. According to another aspect of the disclosure, a The memory component can include a bit line, a word line, a memory string including a memory cell, and a common source line connected to the memory string. The memory string is connected to the bit 201203520 line. The system is connected to the common source line and the bit 绫, ^ includes a first end point, and a bit: between the t springs. The memory cell 曰俨 曰俨 , , , , , , , , , , , , , The gate structure includes a gate dielectric layer. The memory cell is also two-two and the resistor is electrically connected in series between the transistor layer and the sub-reader of the transistor. The dielectric layer can be switched to the opposite side to a = resistance value and - the second resistance value, the first resistance value and the second resistance value / knife Corresponding to - the first memory state and the second memory state. The first resistance value of the gate dielectric layer corresponds to the soft breakdown of the transistor. The second resistance value of the gate dielectric layer is One of the crystals corresponds at least partially to a soft collapse state. The transistor further includes a well end point. At least one of a read operation, a program operation, and an erase operation may include applying a predetermined voltage to the well The end point of the zone. This programming operation can include applying a predetermined voltage to the gate structure, and the erasing operation can include applying the predetermined voltage to the end of the well region. This singulation can induce a soft collapse state of the transistor. In addition to the operation, the soft collapse state of the transistor can be at least partially reversed. The gate dielectric layer can include cerium oxide (SiO 2 ), hafnium oxide (Hf 〇 2 ), zirconium dioxide (Zr 〇 2 ), and titanium dioxide ( At least one of Ti〇2). The resistor may include a high resistance layer 'and the gate structure may include a low resistance layer' and wherein the high resistance layer is disposed on the gate dielectric layer and the low resistance Between the value layers. This memory cell can be tied The first memory cell, and the memory component, may further include a second memory cell formed on the first memory cell in a stacking direction such that the first memory cell and the second memory cell are included in a Three-dimensional memory array. 201203520

The above and other features, aspects, and embodiments of the present invention are described in detail in the following section [Implementation]. [Embodiment] FIG. 1 is a block diagram of a memory array 100 according to an embodiment of the present invention. The memory array 100 includes a plurality of memory cells 1 〇 2 'plurality of bit lines BL1_Bl3 , a plurality of word lines WL1 - WL3 , a series selection line SSL · , a ground selection line GSL , and a common source line • SL . The configurable memory array 100 is such that the memory cells 102 are arranged such that the array of mxn s memory cells ’2 and the n systems are natural numbers, respectively. More specifically, the memory array 100 can be configured in such a manner that the memory cell 1〇2 is a plurality of MIMO strings MSI-MS3. Each memory string MS includes a serial selection transistor SST, a group of 11 memory cells 102, and a ground selection transistor GST connected in series. The memory strings MS1-MS3 are connected to the bit line bli_BL3, respectively. Memory String • MS1-MS3 are connected to the common source line SL. FIG. 2 is a schematic diagram of a memory string MS1. The memory string MS is an example of a memory string, and the memory string can be any one of the pictures shown in FIG. The singular string MSI includes a series selection transistor SST, a first memory cell to a fourth memory cell 〇2a-i 〇 2c, and a ground selection transistor GST. The serial selection transistor SST, the first memory cell to the third memory cell 102a-102c, and the ground selection transistor GST are connected in series between the bit line BL1 and the common source line SL. Although the memory string MS includes three memory cells 102a-102c, the actual implementation may include an additional increase

» I 201203520 Recall: for example, 16, 32, 64 or more memory cells. The first to third memory cells 102a-102c include transistors 1a8a_1〇8c, respectively. The electro-crystals _- positions include the polarity of the adjustable resistance value ma_u〇c. The memory cells 102a-102c also include resistors U2a_n2c, respectively. In addition, in some real cases, adjacent transistors 108 may share a common source and/or a common drain to reduce memory cell size. If the source or the drain are not shared in a neighboring transistor, it is difficult to achieve a design rule that is desired, and the design rule to be achieved will not be greater than 4F2. The gate of the serial selection transistor SST is connected to the serial selection line SSL. The source of the serial selection transistor SST is connected to the bit line]. The spurt of the series selection transistor SST is connected to the first memory cell 1 〇 2a. The gate of the ground selection transistor GST is connected to the ground selection line GSL. The source of the ground selection transistor GST is connected to the last memory cell 102c. The drain of the ground selection transistor GST is connected to the common source line SL. FIG. 3 is a schematic diagram showing a memory cell 102 according to an embodiment of the invention. The memory cells 1a-102c can be configured as shown in Fig. 3. The memory cell 102 includes a transistor 1〇8 and a resistor 112. The transistor ι 8 includes a gate 110 of an adjustable resistance value. The transistor 108 can be a field effect transistor (FET), such as a metal oxide half field effect transistor (MOSFET). The transistor 108 can include a semiconductor substrate 114, a source 116, a drain 118, and a gate 11A. The gate 110 includes a gate dielectric layer 120 and a gate electrode 122. The source 116 of the transistor 108 is connected to the bit line bl by a serial selection transistor SST and any memory cell 1〇2 located therebetween as shown in Fig. 2. 201203520 1 WjyuHr/Λ The drain 118 of the transistor 108 is connected to the common source line SL through the ground selection transistor GST and any memory cell 1〇2 located therebetween as shown in FIG. The gate electrode 122 of the transistor 1 is connected to the word line WL through a resistor 112. The semiconductor substrate 114 is connected to an array of well contact leads. The resistor 112 can be a fixed resistor having a fixed resistance value Rp. The resistor 112 is connected in series with the gate 11 ,, and the gate 11 〇 has a variable gate resistance value Rg'. Here, the resistance value Rg is a variable memory of the singular cell 1 〇 2 Receives the % of electricity from the word line applied to the memory cell. One of the generated differential voltages (Va_Vg) is across the resistor 112, and this gate voltage vg is applied to the gate 11A of the transistor 108. According to the following equation (1), the gate voltage Vg has a corresponding relationship with the applied voltage Va. & Therefore, the gate voltage Vg and the gate resistance value Rg are dependent. Therefore, if the gate resistance value Rg is controlled to change from a resistance value to another resistance value, the effective gate voltage Vg also changes, resulting in a different current. Fig. 4 is a graph showing the simulation result of a MOSFET. When the gate resistance Rg changes from 1 GQ to 丨ΜΩ, the curve changes from the solid line 134 to the broken line 136. In this example, an M〇SFET has a 3 nm gate oxide, a p-type well region doping of about 2E17 cm·3, and a resistor 112 having a fixed resistance value. Figure 4 shows the resistance value Rg& i (10) converted to i ΜΩ, resulting in a threshold voltage vth from a lower threshold voltage 1 201203520

Vthlow drift to high threshold voltage ^ electric monitoring vt^igh. Therefore, the transistor 108 of the adjustable resistance changes the gate Ryang resistance value Rg, thereby causing the threshold voltage t to be shifted to the bottom of the cell. (d) Vth drift is caused by the charge it stores. (4) The transistor (10) of the resistance value does not need to have a stored charge to limit the drift of the voltage Vth. The gate dielectric layer 20 can be formed by a thin dioxometer-2). The change in the resistance value at the gate no can be implemented by utilizing the well-known soft crash _ breakdown, SBD state, which is a situation that was not desired in the past. As shown in Fig. 5, in the newly fabricated MOS device, the gate dielectric layer has an arbitrary number of defects 130 in the epitaxial oxide. Over time, due to the operating stress, more defects 13G are formed, so that minute conductive circuits are generated and passed through the oxide. During this process, the conductive path formed by the defects of the oxide and the gate oxide through the gate dielectric layer 12G cause current conduction. The formation of these conductive paths is considered a soft collapse. These conductive paths may be repaired due to the high current density generated at the defect location. High temperatures may reset some of the oxide defects 13 〇, destroying the conductive path. The thin dielectric layer 120 may be replaced by a high dielectric constant material to form the gate dielectric layer 120. The high dielectric constant material has a high dielectric constant or a dielectric constant higher than that of the germanium dioxide. The ruler value. Examples of suitable high dielectric constant materials include ruthenium dioxide ruthenium 2), ruthenium dioxide (Zr 〇 2), and titanium dioxide (Ti 〇 2). High dielectric constant materials generally have more defects than ruthenium dioxide, thus providing a simpler operation in changing the gate resistance value Rg. 201203520 Figure 6 shows a graph of a transistor 108 before soft collapse and after a soft crash =!!,: asks the pole voltage %, where the transistor (10) is represented by a line 138, the transistor 1〇8 is represented by a broken line M0 in the soft collapse. For example, before the soft collapse, the interlayer leakage current of the oxide layer of the thin gate dielectric layer 12G having a thickness of less than ^, is usually less than 1 nA ', and its corresponding gate resistance value Rg is greater than 丨 (8). In the hall

L can induce a soft collapse of the open-layer layer m by applying a gate voltage % of about +4.3 V. After the soft breakdown of the gate dielectric layer (10), the gate leakage current becomes about 丨μΑ, and its corresponding (four) pole resistance value is about 1 ΜΩ | humanity collapse/bebey general phase change random access memory (卩(3) flat ) or phase change memory (PRAM) uses lower power consumption.

The characteristics of the transistor 108, which can adjust the resistance value, can be modified in accordance with the above description. For example, the thickness of the gate oxide and the doping of the p-type well region can be varied according to the above numerical values. Further, the resistance value of the fixed resistance ι ΐ 2 can also be changed from the above-described resistance value 丨 Mq. For example, Fig. 7 shows a relationship between an alternative embodiment of a memory cell 1 对 for a gate leakage current Ig and a gate voltage Vg. The transistor 108 is an N-channel m〇sfet having a gate oxide of 1 nm thick. The resistor 112 has a fixed resistance value of 2 〇 μω. The relationship between the gate leakage current ig and the gate voltage Vg before the soft collapse is indicated by the solid line 144, and the relationship after the soft collapse is indicated by the broken line 146. In this embodiment, the initial gate oxide resistance value Rg before the soft collapse is about 1 = Ω. Use for about time! The 4 4 3 v pulse voltage can induce a soft collapse of 7 Å. After the collapse of the weight, the gate oxide resistance value Rg is lowered and fixed by the fixed resistor 112. In this embodiment, the oxide resistance value Rg of the 201203520 is reduced to about 1 Μ Ω between the soft collapses. 1 .. trace 2 shows the relationship between the source of the transistor 108 of the memory cell 1〇2 of this embodiment θί, the source current Is before the collapse, and the gate voltage % line, the line M8 represents: The relationship after the soft collapse is virtual ground... As shown in Fig. 8, after the soft collapse, the source current drops significantly, because the gate resistance value of the gate is higher than that of the gate 10 plus the gate voltage difference is large. Most of the relationship across the fixed resistance of the resistor 112 is 值^. Therefore, the soft collapse causes a significant drop in the secret/source current of the transistor (10). In this embodiment, the difference between the source current [s and the source current ism after the soft collapse is more than two orders of magnitude or more before the soft collapse. Therefore, the (four)/source current of the significantly different transistor (10) can be used as the different memory state of the memory cell 102. Fig. 9 and Fig. 10 show simulation results showing the effect of the change in the resistance value Rp of the memory cell 1〇2. More specifically, Fig. 9 shows that the gate current of the transistor 108 is specific to the fixed resistance value 对应 corresponding to different values, and Fig. 10 shows the transistor 108 under the fixed resistance value Rp corresponding to different values. Source/drain current characteristics. In Fig. 9, curve 16 〇 shows the result of the state before the soft collapse; curve 161 shows the result when Rp = 4.7 Μ Ω; curve 162 shows the result when Rp = 20 Μ Ω; curve 163 shows The result when Rp = 40 Μ Ω; and the curve 164 shows the result when Rp = 8 〇Μ Ω. In the figure, curve 170 shows the result of the state before the soft collapse; curve 丨71 shows the result when Rp = 4.7MQ; curve 172 shows the result when Rp = 20MQ; curve 173 shows when Rp = The result is 40 ΜΩ; and curve 174 shows the result when Rp = 80 ΜΩ. Therefore, it can be seen from the simulation results in Fig. 9 with 201203520 I wjy〇nr/\ and Fig. 10 that when the resistance value of the fixed resistance value Rp is increased, both the gate current and the drain/source current are lowered. In some embodiments, memory cell 102 can be used as a One Time Program memory component. Figure 11 is a graph showing the relationship between the gate current Ig of the transistor 108 and the number of soft burst induced (SBD-inducing) voltage pulses applied to the gate 100 of the transistor 108. When a soft breakdown induced pulse voltage is applied to the transistor 108, the gate current Ig is gradually changed. When the number of applied soft-induced pulse voltages increases, the gate current Ig at a given +2 V read voltage increases. This occurs because of the relationship between the progressive mechanisms of gate oxide collapse. Therefore, memory cell 102 can be used as a multi-layer, one-time programming memory component. In such an embodiment, the desired gate current Ig can be selected by applying a corresponding predetermined number of soft crash induced voltage pulses to the gate 110 of the transistor 108. In other embodiments, memory cell 102 can be used as a memory component for repeated writes. Fig. 12 is a graph showing the gate characteristics of the electromorph 108 obtained from the simulation results of the state before the soft collapse (curve line 180) and the soft collapse state (curve 182). The collapsed state, represented by curve 182, can be induced by applying a gate pulse voltage for a predetermined period of time. In this simulation example, a collapse state is induced by applying a pulse voltage of 4.3 V having a pulse width of about 1 ps. However, the soft collapse state can be at least partially inverted by applying a pulse voltage having a polarity opposite to that induced the soft collapse state voltage. In addition, the pulse width of the soft burst inversion (SBD-reversing) pulse voltage may be different from the pulse width of the soft crash induced pulse voltage. Under partial reversal 201203520 soft breakdown voltage conditions, the gate characteristics of the transistor (10) are represented by the curve and line 184 in Fig. 12. Here, the exemplary embodiment is shown to achieve a partial inversion soft state by applying a pulse voltage of 4.3 v with a width of =ir. . The soft collapse state of the transistor 108 can be at least partially reversed to distinguish the gate characteristics of the transistor (10) in a soft collapse state and the degree of gate reversal of the transistor (10) in a collapsed state. This =, by applying the appropriate pulse voltage, the transistor 〇8 can make multiple iterations between the dimorphic collapse state and the reversal soft collapse state (or at least partially reverse the soft crash). Therefore, the soft crash state and at least part 8: the soft crash state can be regarded as individual; it has been recalled. For example, the soft collapse state of the curve 182 table * can be regarded as the "program" state of the 5 memory cell 102, and the at least partially inverted soft collapse state indicated by the curve 184 can be regarded as the memory cell 1 〇 2 An "erase" Next, referring to Fig. 13, the operation of the rewritable memory embodiment of the memory array 100 will be described herein in the same manner as in Figs. 1 and 2. In general, the voltage levels of the word line WL1_WL3, the bit lines BL1-BL3, and the source line SL, and the states of the ground selection transistor GST and the series selection transistor SST can be controlled to the memory array 1 Any memory cell that is programmed, erased, or read. A more detailed description will be specifically referenced to one or more special memory cells of the memory array 1 随着 as the memory array operates; however, those skilled in the art should understand that such descriptions can be applied. Equivalent to other memory cells of the memory array 100, and may also be equivalent to other alternative embodiments of the application memory array 201203520 100, including additional memory cells, bit lines, word lines, ground selection transistors, strings Select the transistor, and / or other components. Memory array 100 can be part of memory component 200, and memory component 200 is organized from a plurality of blocks 202, each block 202 being organized from a plurality of pages 204. For example, in one embodiment, a 2-Gbit embodiment of memory element 200 can include 2048 blocks 202, with 64 pages 204 in each block 202 and 2112 • each page 204. The bits cause the memory element 200 to consist of a series of 128-kbyte blocks 202. Other embodiments may include additional or fewer bits of memory, block 202, page 204, and/or bits of each page 204. The memory component 100 can also include a multi-bit interface (not shown) for data transmission or reception of the memory array 100, such as an 8 or 16 bit interface. The received data can be written to the memory as binary data, and the binary data is stored as a logic level 1 or a logic level 0. The memory component 200 can be initialized such that a plurality of memory cells 102 are initially set to a logic level 1 or a logic level 0. After initialization, data can be written to the memory cells 102 using erase and program operations. The erase operation stores a logic level 1 into the memory cell 102. The programming operation stores a logic level 0 into the memory cell 102. In some embodiments, an erase operation is performed sequentially in one of the blocks 202 of the memory element 200, and a program operation is sequentially performed on the bits of the memory. The programming operation changes the state of the erased bit to a state of logic level 0. The programming operation induces a state of rotation of the transistor 102 of the memory cell 102 to be programmed to complete the transition of the state by the soft state of the memory cell 102 201203520 4 text 3 Vi?: brother 'in the embodiment described above' The state is induced by applying a λ voltage to the selected memory cell. The remaining memory cells (8) of the memory array 100 can be kept below the soft crash induced voltage level. A; ^ example to 5 brothers ' ^ reference to the first }, a selected memory cell 102 (shown by a dashed box) can be used to increase the word line and "voltage to 4.3 v - and the line BL3 Set to 〇v to complete programming. At this time, the remaining lines WL2 and WL3 are raised to 3 3 v 1 and the remaining bits ‘: 2? It was upgraded to 3·3 V. Because of other unselected notes: the potential across _L is less than the voltage that induces a soft collapse state: the text, his unselected 忆 忆 忆 1 〇 2 will not be programmed. Further, the serial selection of the transistor SST is turned on, for example, by raising the voltage of the series selection line SSL to (or greater than) the serial selection voltage threshold Vth' such as 3.3 V. Since the voltage of the bit line BL3 is 〇v, and the voltage of the bit lines BU and BL2 is 3 3 v, only the serial selection transistor SST of the third memory string is turned on; the first memory string MS1 and the first memory The serial connection of the string MS2 selects the transistor as if it remains off. The ground selection transistor GST of the third memory string MS3 remains closed, and the source line SL is floating. Therefore, the voltage across the selected memory cell 1, 〇2 is at least sufficiently high at the intersection of the word line wu and the bit line to induce the weight of the selected memory cell 1〇2. The crash state, so the selected memory cell 1〇2 is programmed. π - As another example, please still refer to Figure 1, the bit line BL3 can be set to 0V, by raising the voltage of the word line WL1 to 4·3 v, to the selected memory cell 1〇2 (displayed by a dashed box) for programming. Meanwhile, 201203520

I W5V04PA The remaining characters, lines WL2 and WL3 are boosted to 3 v, and the remaining bit lines BL1 and BL2 are also boosted! v. Since the electric dust system across other unselected memory cells 102 is less than the requirement to induce a soft collapse state voltage, other unselected memory cells 1〇2 will not be programmed. In addition, the serial selection memory SST of the third memory string MS3 is turned on, for example, by raising the voltage of the series selection line SSL to (or greater than) the threshold voltage of the serial selection transistor sst, for example, 1 v, The threshold voltage of the serial selection of the electro-optic crystal in the SST is 0.7 V. Since the voltage of the bit line BL3 is 〇, and the voltage of the bit lines BL1 and BL2 is! v, so only the serial selection transistor SST of the third memory string lake is turned on; the serial selection transistor SST of the remaining first-memory string MS1 and the second memory string MS2 remains off. The ground selection transistor GST of the second memory string MS3 can be kept off, and the source line SL can be floating. Therefore, the voltage across the selected memory cell ι 2 is at least sufficiently high at the intersection of the sub-line W1 and the bit line BL3 to induce softness of the transistor 1 〇 8 of the selected memory cell 102. Crash_state, so the selected memory cell 1〇2 is programmed. The erase operation changes the state of the programmed bit to a state of a logical level i. The erase operation completes the transition of this state by at least partially inverting a soft collapse state of the transistor 108 that selects the memory cell 102 to be erased. For example, in the embodiment described above, the soft collapse state can be partially reversed by applying a • 4.3 V word line WL voltage across the selected memory cell 1〇2. In other words, the programmed word line of the memory cell 1 〇 2 is set to the -potential, which is lower than the potential of the substrate well region of the transistor 108 of the memory cell 102 that is programmed. 3 v. The remaining memory cells 102 of the memory array 100 can be kept below the soft crash induced voltage level. For example, 'please refer to the first item】, a selected memory cell 102 (shown by a dashed box) can be used - including the block erase step of erasing the memory cells 〇〇 the whole memory cell 102 Wipe the process and erase it. After this block is erased, any memory cell (10) that should have a logic level Q can be reprogrammed to a logic level of zero. The erase process includes setting the power of the word lines WL1-WL3 to 〇 V, and the voltage of the substrate well region is set at 43 volts. Further, the serial selection of the first memory string MSI to the third memory string MS3 and the ground selection f crystal GST are turned off, for example, by raising the voltage of the series selection line SSL and the ground selection line GSL to approximately

Same as the well voltage of 4.3 V' - generated across the series selection transistor SST and the ground selection transistor GST. The bit lines BL1-BL3 and the source line SL may be floating. Therefore, the negative word line milk potential across the plurality of memory cells 1〇2 of the memory array 100 is at least sufficiently high to soften the softness of the transistor 1〇8 at least partially inverting the memory cells 102. State, so these memory cells 1 〇 2 are erased. It should be possible to do this. If an insufficient number of memory cells 102 are erased, then one or two erases can include erase state verification and the block erase process described above. The item fetch operation detects a selected state of the memory cell 102 to determine whether the selected memory cell 102 is set to a logic level or a logic level 1. The read operation can detect the logical reference of the selected memory pack 102 by applying a read voltage Vread to the character ^, which is tied to , ',. The selected 5 cells are 1 〇 2, which in this example is the word line WL1. As shown in Fig. 4, the threshold voltage Vth of the transistor 108 and the transistor 1〇8 are 201203520

I W^y〇4t"A is set in a soft crash state or is set in an at least partial reversal soft crash state. When the transistor 108 is in a soft collapse state, the gate resistance value Rg is relatively low, so the threshold voltage Vth is set to a relatively high threshold voltage Vthhigh. On the other hand, when the transistor 108 is in at least partially inverted soft collapse state, the gate resistance value Rg is relatively high, so the threshold voltage Vth is set to a relatively low threshold voltage VthlQW. Therefore, the state of the transistor 108 and the similar memory state on the memory cell 102 can be detected by detecting the threshold voltage of the transistor 108 as a high threshold voltage Vthhigh or a low threshold voltage Vthlow. Therefore, the logic level of the selected memory cell 102 can be detected by applying a gate voltage to the transistor 108 of the selected memory cell 102, so that the transistor 108 is only set at the threshold voltage Vth of the transistor. The low threshold voltage VthlQW will be turned on. Therefore, the applied gate voltage should be selected to be greater than or equal to the low threshold voltage VthlQW and less than the high threshold voltage Vthhigh. For example, the memory state of the selected memory cell 102 can be detected by applying a read voltage Vread to a word line spanning the memory cell 102. • The read voltage Vread is selected such that the Vqs of the transistor 108 of the selected memory cell 102 is less than the south threshold voltage Vthhigh' and greater than or equal to the low threshold voltage Vthlow. The remaining memory cells 102 in the memory string MS3 are operated in a pass-through mode. Since the memory state of the remaining memory cell 102 of the memory string MS3 can be a logic level 1 or a logic level 0, the VGS applied to these memory cells 102 should be greater than or equal to the high threshold voltage Vthhigh to operate in the transparent mode. The transistor 108 does not need to pay attention to the memory state of these memory cells 102. In addition, the series selection transistor SST and the ground selection transistor GST of the memory string MS3 are turned on, and the voltage level of the line 19 201203520 line BL3 is boosted, so that the transistor 108 of the selected memory cell 102 is turned on. At this time, the VDS of the transistor 108 of the selected memory cell 102 will be boosted to a sufficiently high voltage to pass a perceptible drain current Id. The series connection selection transistor SST and the ground selection transistor GST of the remaining memory strings MSI and MS2 are off. The following table (Table 1) summarizes the operation of the memory array 100 by a method using a voltage level paradigm according to one embodiment of the memory array 100. For different embodiments, the exact voltage levels listed in Table 1 may vary, particularly those of transistor 108 characteristics and resistance 112 characteristics. · Write erase read BL1 BL2 BL3 BL1 BL2 BL3 BL1 BL2 BL3 ον IV IV OPEN OPEN OPEN IV ον ον SSL IV 4.3 V IV WL1 4.3 V ον 3 V WL2 3 V ον Vread WL3 3 V ον 3 V GSL ον 4.3 V IV SL ον OPEN ον WELL ον 4.3 V ον 20 201203520

I W:>y〇4PA Please refer to Fig. 14, and structure 220 shows the embodiment. As shown in Figure 3, the memory cell 1〇2 includes and

The resistance value Rp in series. Structure 220 can provide the resistance of resistor value Rp in series to gate 11 of transistor 108. Structure 22 includes an ancient and 112 layer 222 is disposed over gate dielectric | 120. The structure 22 is also valued. The resistance value layer 224 is disposed on the high resistance layer. The low resistance U can be formed from a low resistance material such as a metal germanide \ low resistance layer 224 which can be used as a low resistance gate electrode. The value layer 222 can be composed of a low-doped cermet material. A layer 222 of the polysilicon material is formed to provide a parasitic resistance Rp, for example, in the range of two Μ Ω to 1 〇 Ω.疋 —1 Figure 15 shows the type of p-type polycrystalline stone material that can be used to provide the desired low-resistance layer 224 ~ 丨 and half. As shown in Fig. 15, the p-type polysilicon material can be doped to a concentration lower than 1017 cm3 to obtain a higher resistivity. Therefore, for the high resistance layer 222, a resistance value Rp greater than i 〇 m = can be obtained at the 15 nm node. Fig. 6 shows a three-dimensional memory array 250 of an embodiment having a three-dimensional memory array. The three-dimensional memory array 25A includes a memory array 252 formed on the substrate 254 in a lamination direction. Memory array 252 is formed between conductive source line barriers 256 and a series of vertically spaced bit line conductors 258a-258c. A series of conductive series select lines 260a-260b are formed on the memory array 252 in a lamination direction. The series select lines 260a-260b can be connected to the series select transistor region 266 by conductive turns 260c and 260d. 21 201203520 ···一··-- * * . . . The substrate 2 5 4 may be formed by a wafer, such as a wafer or other form of wafer. In some embodiments, substrate 254 can include a buried oxide layer. For example, substrate 254 can include an insulating silicon-on-insulator (SOI) material. The power supply line bar 256 can provide a common source line for the memory array 250. The bit line conductors 258a-258c can be provided as bit lines BL1-BL3, respectively. Conductor line stop 256, bit line conductors 258a-258c, and series select lines and conductive posts 260a-260d may be formed of a conductive material, such as tungsten. The φ memory array 252 includes a ground selection transistor region 262, a memory region 264, and a series select transistor region 266. A plurality of conductive vias 268 provide a conductive interconnect between the ground select transistor region 262, the memory cell region 264, and the series select transistor region 266. The conductive vias 268 may be formed of a conductive material, such as tungsten. The ground selection transistor region 262 includes a plurality of memory columnar semiconductor layers 270. A plurality of memory gate insulating layers 272 are respectively formed as sidewalls of the memory columnar semiconductor layers 270. A plurality of gate structures 274 are formed on the sidewalls of the memory gate insulating layer 272. The memory columnar semiconductor layer 270 and the gate structure 274 are formed of a polysilicon. A portion of the memory columnar semiconductor layer 270 may be formed of p+ and n+ doped smectite. The memory gate insulating layer 272 may be formed of a gate dielectric material such as oxidized oxide. The memory cell region 264 includes a plurality of memory pillar semiconductor layers 280. The memory gate insulating layer 282 is formed as a sidewall of the memory columnar semiconductor layer 280, respectively. A plurality of gate structures 284 are formed on the sidewalls of the memory gate 22 201203520 insulating layer 282. The memory columnar semiconductor layer 28A and the gate structure 284 may be formed of a polysilicon. A portion of the memory columnar semiconductor layer 280 may be formed of p and n-doped polysilicon. The memory gate insulating layer 282 may be formed of a gate dielectric material such as cerium oxide (si〇2) or a lanthanum dielectric constant material such as cerium oxide (Hf〇2) or a cerium dioxide (Zr02). And titanium dioxide (Ti〇2). The series select transistor region 266 includes a plurality of memory columnar semiconductor layers 290. The memory gate insulating layer 292 is formed as a sidewall of the memory columnar semiconductor layer 290, respectively. A plurality of gate structures 294 are formed on the sidewalls of the 5 memory gate insulating layer 292. The memory columnar semiconductor layer 290 and the gate structure 294 may be formed of a germanium. A portion of the memory columnar semiconductor layer 290 may be formed of p+ and n+ doped germanium. The memory gate insulating layer 292 may be formed of a gate dielectric material such as hafnium oxide. Thus, in accordance with the present disclosure, a 1T MOSFET memory is provided and the threshold voltage drift of the memory transistor is caused by a change in the gate resistance value Rg. The change in the gate resistance value Rg results in a significant drift of the threshold voltage Vth by a series connected resistance value Rp. Preferably, Rg (after soft collapse) and Rp are between a similar range of resistance values. The difference between the drain current Id and the threshold voltage Vth is used to define the memory state of the memory cell as a logic level 1 or a logic level. The memory cell can operate as a four-terminal component, including gate/resistance values Rp and Rg, source, drain, and well regions. Different high dielectric constant materials or materials similar to phase change memory can be used as the material of the gate resistance value Rg. An array structure similar to the NAND gate can be used as the memory component of the present invention. The memory cell can be made by a 4F2 design rule. A three-dimensional structure similar to the gate can also be used to provide a high memory density of 23,035,035, for example, the capacity of the it bit. Compared with the phase change memory, the memory cell disclosed in the present invention can use the phase memory material on the gate dielectric layer of a MOSFET, and the memory cell disclosed in the present invention uses the gate resistance change. For programming/erasing operations, instead of using charge storage for operation. Since the memory cell of the present invention transmits the measurement current through the source of the transistor, it is not necessary to obtain a large current to make the material collapse. Therefore, the programming current of the memory cell of the present invention can be lower than the phase transition. The programming current of the memory. Since the present invention uses the resistance value change of the gate instead of the charge storage for data storage, the φ memory cell of the present invention does not encounter the problem of charge storage. The memory cell of the present invention can include an ultra-thin gate oxide (~1 nm) MOSFET in a memory array having 4F2 memory cells. Since the ultra-thin gate oxide MOSFET can be shrunk to less than 10 nm, a plurality of extremely miniature components (e.g., channel aspect ratios less than 10 nm) are possible with the memory array of the present invention. In the above, the present invention has been described in terms of the preferred embodiments, and is not intended to limit the invention. Those skilled in the art can make various changes and modifications without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram of a memory array in accordance with an embodiment of the present invention. Fig. 2 is a view showing a memory string of one of the memory elements shown in Fig. 1. 24 201203520

In the VV-figure diagram, the memory of the memory device shown in Fig. 1 is not intended. Figure 4! A graph showing the relationship between the sense resistor value and the threshold voltage of the memory cell resistance shown in Fig. 3. Fig. 5 is a schematic diagram of a transistor of a memory cell not shown in Fig. 3. Fig. 6 is a graph showing the relationship between the terminal leakage current Ig and the gate voltage Vg of the transistor shown in Figs. 3 and 5. Fig. 7 is a graph showing the relationship between the gate leakage current Ig and the gate voltage Vg of an alternative embodiment of the memory cell shown in Fig. 3. Fig. 8 shows the source characteristic curves of the transistors shown in Figs. 3 and 5. Fig. 9 and Fig. 1 show the simulation results showing the effect of the change in the resistance value of the memory cell. Fig. 11 is a graph showing the relationship between the open current Ig of the transistor shown in Figs. 3 and 5 and the number of soft breakdown induced voltage pulses applied to the gate. ... Figure 12 shows the gate characteristics of the transistor shown in Figures 3 and 5 in a pre-soft collapse state, a soft collapse state, and at least a partial reversal soft collapse state. Figure 13 depicts a block diagram of a memory component, including the memory array shown in the second figure. Fig. 14 is a view showing a memory cell of an embodiment of the memory array shown in Fig. 1 and the memory string shown in Fig. 2. Fig. 15 is a schematic diagram showing the resistivity characteristics of the double crystal 25 201203520 which can be used for the memory cell shown in Fig. 14. Fig. 16 is a view showing an embodiment of a memory array having a three-dimensional structure shown in Fig. 1. [Description of main component symbols] 100, 252: Memory arrays 102a-102c · Memory cells 108a-108c: Transistors 110a-110c: Gates 112a-112c: Resistors 114, 254: Semiconductor substrate 116: Source 118: 汲Pole 120: gate dielectric layer 122: gate electrode 130: defects 134, 138, 144, 148: solid lines 136, 140, 146, 150: dashed lines 160, 161, 162, 163, 164, 170, 171, 172 , 173 , 174 , 180 , 182 , 184 : Curve 200 : Structure 202 . Block 204 : Page 222 : High Resistance Value Layer 224 : Low Resistance Value Layer 250 : Three Dimensional Memory Array 26 201203520

IW^y〇-4rA 2 5 6 . Conductor power line shed 258a-258c: bit line conductor 260c-260d: conductive post 262: ground selection transistor region 264. memory cell region 266: serial selection transistor region 268 : Conductive path 270, 280, 290: Memory columnar semiconductor layer • 272, 282, 292: Memory gate insulating layer 274, 284, 294: Gate structure BL1-BL3: Bit line GSL: Ground selection line MS1 -MS3: memory string

Rg : fixed resistance value Rp : variable gate resistance value SL : source line SSL ' 260a-260b : series connection line Va : applied voltage Vg : gate voltage Vth threshold voltage

Vthhigh: high threshold voltage VthlQW: low threshold voltage WELL: well area WL1-WL3: word line 27

Claims (1)

201203520 VII. Patent application scope: 1. A memory component, comprising -I ', a p-car array having a plurality of memory cells, at least one of the memory cells comprising: a soap-transistor having a first end a gate, a second terminal, and a pole structure, the gate structure including a gate dielectric layer; and a resistor 'in series with the gate structure of the transistor, wherein the gate dielectric layer can be (4) Corresponding to and a second resistance value, the first ray and the 丨 丨 value and the third resistance value respectively correspond to the deer and the second memory state. ... 2. The memory device according to claim 1, wherein the first resistance value of the gate dielectric layer corresponds to a collapse state of the transistor. 3. According to the memory profile described in claim 2, the second resistance value of the interpolar dielectric layer corresponds to the m-inversion soft collapse state of the electric day and day. call ...4. (4) The memory component described in item 3 of the patent scope, wherein the circuit further includes a well end point. 5. The memory component of claim 4, wherein at least two of the basin-read operation, the -program operation, and the erase operation comprise applying a predetermined voltage to the end of the well region. 6. The memory component of claim 5, wherein the programming operation comprises applying the shape t to the structure, and the erasing operation comprises applying the predetermined voltage to an end of the well region. ??? 7. The memory component of claim 6, wherein the programming operation induces the soft collapse state of the transistor. 8. The memory element of claim 7, wherein the erasing operation at least partially reverses the soft collapse state of the transistor. The memory device of claim 1, wherein the inter-electrode layer comprises cerium dioxide (Si〇2), oxidized (Hf〇2), and dioxed (ZrOJ, And a memory element according to the above-mentioned claim, wherein the resistor comprises a high resistance layer, and the idle structure comprises a low resistance a value layer 'and wherein the high resistance layer is disposed between the gate dielectric layer and the low piano resistance layer. - The memory component comprises: a bit line; a word line; a memory cell; and a common source line connected to the memory string; wherein the memory string is connected to the bit line; wherein the memory cell is connected between the common source line and the bit line The memory cell includes: a transistor having a first terminal, a second terminal, and a gate structure, the gate structure including a gate dielectric layer; and a resistor electrically connected in series Connected between the interposer of the transistor and the word line, wherein The gate dielectric layer is switchably coupled to a first resistance value and a second resistance value, the first resistance value and the second resistance value respectively corresponding to a first memory state and a second memory state. For example, in the memory component described in claim U, the resistance value of 29 201203520 corresponds to the collapse state of the gate dielectric layer in one of the softness of the transistor. The memory device of claim 2, wherein the second resistance value of the gate dielectric layer corresponds to at least partially inverting a soft collapse state of the transistor. 14. The patent application scope is 13 workers. The memory component, wherein the germanium transistor further comprises a well region end point. ^ The memory component as described in the patent application 帛 14 workers, wherein the beard is a private operation, and the erase operation At least one of the methods includes applying a predetermined voltage to the end of the well region, such as the memory component of the patent application, wherein the programming operation includes applying the voltage to the gate structure, and the erasing Operation includes The memory element of claim 16, wherein the programming operation induces the soft collapse state of the transistor. 18. Patent Application No. 17 The memory component of the item, wherein the erasing operation at least partially reverses the soft collapse state of the transistor. ▲ 19. The memory component of claim n, wherein: The electric layer includes at least one of oxidized 7 (Sl 〇 2), oxidized (Hf 〇 2), cerium oxide (Zr 〇 2), and titanium dioxide (Ti 〇 2). The memory device of claim 11, wherein the resistor comprises a high resistance layer, and the gate structure comprises a low resistance layer, and wherein the high resistance layer is disposed on the gate dielectric layer And 5 litres between low resistance layers. 201203520 I W^y〇4KA ...Ο M The memory component described in Item 11 of the patent range, °H. The memory cell is a - memory cell, and wherein the memory component further comprises a second memory cell formed on the first memory cell in a lamination direction, such that the first memory cell and the second memory The cell line is included in a three-dimensional array of memory. 31