201145491 六、發明說明： 【發明所屬之技術領域】 [0001] 本發明涉及一種發光二極管，尤其涉及一種能夠直接使 用交流電源供電的多晶封裝發光二極管。 【先前技術】 [0002] 目前，發光二極管（Light Emi tt ing Diode，LED)因 具有功耗低、壽命長、體積小及亮度高等特性已經被廣 泛應用到很多領域。 [0003] 在發光二極管封裝技術中，多晶封裝（Multi-Chip 〇201145491 VI. Description of the Invention: [Technical Field] The present invention relates to a light emitting diode, and more particularly to a polycrystalline package light emitting diode capable of directly supplying power from an alternating current power source. [Prior Art] [0002] At present, light-emitting diodes (LEDs) have been widely used in many fields due to their low power consumption, long life, small size, and high brightness. [0003] In the LED packaging technology, polycrystalline package (Multi-Chip 〇
Module，簡稱：MCM)是指複數個半導體發光二極管晶 片封裝成為一顆發光體。先前多晶封裝發光二極管採用 直流驅動。一般地，為發光二極管供電的驅動電路方案 有兩種，一種是藉由傳統的交流變壓、整流、串聯穩壓 等環節來獲得直流驅動；一種是採用較先進的開關電源 直接產生所需的直流穩壓電源。前者因為使用了變壓器 、限流電阻等裝置，具有成本高、能耗大、品質重等缺 ^ 點，後者應用較為普遍，雖然具有較低的能耗，但結構 複雜，成本也較高。 【發明内容】 [0004] 下面將以實施例說明一種能夠直接使用交流電源供電的 多晶封裝發光二極管。 [0005] —種多晶封裝發光二極管包括多個發光二極管晶片，一 個封裝基板，以及一個封裝體。每個發光二極管晶片具 有一個正極以及一個負極。該封裝基板上形成有電路層 ，該電路層包括多個焊接點，每個發光二極管晶片的正 099117885 表單編號A0101 第3頁/共19頁 0992031736-0 201145491 極與負極分別與一個焊接點電連接，以使該多個發光二 極管晶片形成至少兩個分別正向串聯的晶片組，該至少 兩個晶片組反向並聯，該封裝體設置在該封裝基板上， 用以覆蓋該多個發光二極管晶片。 [0006] 相對於先前技術，所述多晶封裝發光二極管所包括的多 個發光二極管晶片形成反向並聯的晶片組，因此，該多 晶封裝發光二極管可以直接由交流電源供電，而無需設 置橋式整流器，電路結構簡單。 【實施方式】 [0007] 下面將結合附圖對本發明實施例作進一步的詳細說明。 [0008] 請參閱圖1、圖2與圖3，本發明第一實施例提供一種多晶 封裝發光二極管10，其包括：一個封裝基板20，多個設 置在該封裝基板20上的發光二極管晶片30，以及一個用 於覆蓋該多個發光二極管晶片30的封裝體40。 [0009] 每個發光二極管晶片30包括一個外延基底31，依次形成 在該外延基底31上的緩衝層32，以及多層磊晶結構33。 在本實施例中，該外延基底31通常為藍寶石（Sapphire) 、碳化矽（SiC)、矽（Si)、珅化鎵（GaAs)、偏鋁酸鋰 (LiA102)、氧化鎂（MgO)、氧化鋅（ZnO)、氮化鎵（GaN) 、氮化鋁（A1N)、或氮化銦（InN)等單晶基底。 [0010] 該多層磊晶結構33依次包括形成在該缓衝層32上的N型半 導體層34，半導體活性層35，P型半導體層36，以及透明 電極層37。該多層磊晶結構33形成一個平台結構（Mesa Pattern)，以使該N型半導體層34具有一個暴露在外的 099117885 表單編號A0101 第4頁/共19頁 0992031736-0 201145491 表面381 ^該Ν型半導體層34上形成一個Ν型電極34ι，該 透明電極層37上引出一個ρ型電極371。 [0011] ❹ ο 在本實施例中，該封裝基板2〇上形成有電路層21。該電 路層21上具有多個焊接區域22，每個焊接區域22包括一 個Ν型焊接點23以及一個Ρ型焊接點24。該多個焊接區域 22包括的Ν型焊接點23以及ρ型焊接點24分別藉由連接金 屬25相互連接。該ν型焊接點23以及該ρ型焊接點24分別 與發光一極管晶片30的Ν型電極341與Ρ型電極371相配合 具體地’該發光二極管..晶、片.3:0分別藉由該ν型電極mi 與該Ρ型電極371與該電漆層21上的Ν型焊_點23以及該Ρ 型焊接點24電連接，從而將該發光二極管晶片3〇覆晶封 震在該封裝基板2〇上。並且，該多個發光二極管晶片3〇 形成一個正向串聯的第一晶片組26與一個正向串聯的第 二晶片組27，且該第一晶片組26與第二晶片組27反向並 聯。請一併參見圖4所示’該多個發光二辞管晶片3〇封裝 在該封裝基板20上形成的多晶封裝發光二極管1〇的等效 電路圖。在本實施例中’該兩個晶片組所包括的發光二 極管晶片30的數量相同。該^ 一晶片組26與第二晶片組 27相互並聯後與一個交流電源（圖未示）電連接。該第 一晶片組26與第二晶片組27所包括的發光二極管晶片30 的數量取決於該交流電源的電壓》—般地，為了保證該 多個發光二極管晶片30在額定電壓下正常工作，該第一 晶片組26或者第二晶片組27包括的發光二極管晶片30的 工作電壓相加等於該交流電源的峰值電壓。 [0012]Module, abbreviation: MCM, refers to a plurality of semiconductor light-emitting diode wafer packages packaged into one illuminant. Previous polycrystalline package LEDs were driven by DC. Generally, there are two kinds of driving circuit schemes for powering LEDs. One is to obtain DC driving by means of conventional AC voltage transformation, rectification, series voltage regulation, etc. One is to directly generate required signals by using a relatively advanced switching power supply. DC regulated power supply. Because the former uses transformers, current limiting resistors and other devices, it has the disadvantages of high cost, high energy consumption, and heavy quality. The latter is more common, although it has lower energy consumption, but the structure is complicated and the cost is higher. SUMMARY OF THE INVENTION [0004] A polycrystalline package light emitting diode capable of directly using an alternating current power source will be described below by way of example. A polycrystalline package light emitting diode includes a plurality of light emitting diode chips, a package substrate, and a package. Each of the LED chips has a positive electrode and a negative electrode. A circuit layer is formed on the package substrate, the circuit layer includes a plurality of solder joints, each of the LED chips is positive 099117885 Form No. A0101 Page 3 / 19 pages 0992031736-0 201145491 The pole and the cathode are respectively electrically connected to a solder joint The plurality of light emitting diode chips are formed into at least two wafer groups respectively connected in a forward direction, the at least two wafer groups being connected in anti-parallel, the package being disposed on the package substrate to cover the plurality of light emitting diode chips . [0006] Compared with the prior art, the plurality of light emitting diode chips included in the polycrystalline package light emitting diode form an anti-parallel chip group, and therefore, the polycrystalline package light emitting diode can be directly powered by an alternating current power source without setting a bridge. Rectifier, the circuit structure is simple. [Embodiment] Hereinafter, embodiments of the present invention will be further described in detail with reference to the accompanying drawings. Referring to FIG. 1 , FIG. 2 and FIG. 3 , a first embodiment of the present invention provides a polycrystalline package LED 10 comprising: a package substrate 20 , and a plurality of LED chips disposed on the package substrate 20 . 30, and a package 40 for covering the plurality of LED chips 30. Each of the light emitting diode chips 30 includes an epitaxial substrate 31, a buffer layer 32 sequentially formed on the epitaxial substrate 31, and a multilayer epitaxial structure 33. In the present embodiment, the epitaxial substrate 31 is typically sapphire, tantalum carbide (SiC), germanium (Si), gallium antimonide (GaAs), lithium metaaluminate (LiA102), magnesium oxide (MgO), and oxidation. A single crystal substrate such as zinc (ZnO), gallium nitride (GaN), aluminum nitride (A1N), or indium nitride (InN). The multilayer epitaxial structure 33 sequentially includes an N-type semiconductor layer 34, a semiconductor active layer 35, a P-type semiconductor layer 36, and a transparent electrode layer 37 formed on the buffer layer 32. The multilayer epitaxial structure 33 forms a mesa pattern such that the N-type semiconductor layer 34 has an exposed 099117885. Form No. A0101 Page 4 / 19 pages 0992031736-0 201145491 Surface 381 ^ This type of semiconductor A germanium electrode 34i is formed on the layer 34, and a p-type electrode 371 is drawn on the transparent electrode layer 37. [0011] In the present embodiment, the circuit board 21 is formed on the package substrate 2 . The circuit layer 21 has a plurality of soldering regions 22, each of which includes a meandering solder joint 23 and a tantalum solder joint 24. The Ν-type solder joint 23 and the p-type solder joint 24 included in the plurality of soldering regions 22 are connected to each other by a connection metal 25, respectively. The ν-type solder joint 23 and the p-type solder joint 24 are respectively matched with the Ν-type electrode 341 and the Ρ-type electrode 371 of the light-emitting diode wafer 30, specifically, the light-emitting diode: crystal, sheet, and 3:0 respectively The ν-type electrode mi and the Ρ-type electrode 371 are electrically connected to the Ν-type soldering point 23 on the enamel layer 21 and the Ρ-type solder joint 24, thereby squeezing the LED chip 3 The package substrate 2 is mounted on the substrate. Moreover, the plurality of LED chips 3A form a first wafer set 26 in a forward series and a second wafer group 27 in a forward direction, and the first wafer group 26 is connected in reverse to the second wafer group 27. Referring to Fig. 4, an equivalent circuit diagram of the polycrystalline package light-emitting diode 1A formed on the package substrate 20 is shown. In the present embodiment, the number of the light emitting diode chips 30 included in the two wafer groups is the same. The chip group 26 and the second chip group 27 are connected in parallel to each other and electrically connected to an AC power source (not shown). The number of the LED chips 30 included in the first chip group 26 and the second chip group 27 depends on the voltage of the AC power source. Generally, in order to ensure that the plurality of LED chips 30 operate normally under the rated voltage, the The operating voltage of the LED chip 30 included in the first wafer group 26 or the second wafer group 27 is added equal to the peak voltage of the AC power source. [0012]
優選地’在本實施例中，該N型電極341與電路層21上的N 099117885 表單編號A0101 第5頁/共19頁 0992031736-0 201145491 [0013] [0014] [0015] 099117885 型焊接點23之間設有N型連接材料38，該p型電極川盘 電路層21的P型焊接點24之間設有p型連接材料⑽。” 該封裝體40設置在該封裝基板20上，以用於覆蓋該多個 發光二極管晶片30以及該連接金屬25。該封裝體4〇可以 避免該發光二極管晶片30及該連接金屬25與外界水氣相 接觸而被氧化。該封裝體40的外表面41可為平面、凸曲 面或凹曲面，以改變發光二極管晶片3〇發出的光線經由 外表面41出射的角度，從而可以改變多晶封裝發光二極 管10的照射範圍及光型。在本實施例中，該封裝體40的 外表面41為一個凸曲面。該封裝體4〇所用材料可為環氧 樹脂、矽樹脂或其他電絕緣的透明材料。當然，該封裝 體40中也可進一步包含有擴散粒子，例如二氧化矽微粒 ，用以散射該發光二極管晶片30發出的光線《當然，該 封裝體4 0内也可以設置光波長轉換物質，使該多晶封裝 發光二極管1〇產生所需要的光顏色，例如螢光粉。 ' 本實施例中，該多晶封裝發光二锅管1〇進一步包括一個 承載該封裝基板20上並遠離鱗封裝體4〇 —側的散熱基板 5〇 ’該散熱基板50用於散發該多個發光二極管晶片3〇工 作時導出的熱量。可以理解的是，該散熱基板5〇與該封 裝基板20的材料可以相同也可以不同。 該多晶封裝發光二極管1〇所包括的多個發光二極管晶片 30形成反向並聯的兩個晶片組。因此，在交流電源接通 時’該交流電源在任意半個週期内，該第一晶片組26與 第二晶片組27中有一個晶片組點亮，而另一個晶片組熄 滅。因此’該多晶封裝發光二極管丨〇可以直接使用交流 表單編號A0101 第6頁/共19頁 0992031736-0 201145491 [0016] [0017] Ο 〇 [0018] 099117885 電源供電1無需設置橋式整流器，電路結構簡單。 可以理解的是，❹轉接區域22在該封裝基板2〇上的 排列不限於本實施例所示，還可以為其他_方式，如 交錯排列，不對稱排列，只要相_焊接區型焊 接點23與和其相鄰的焊接區域22咐型焊接點湖由連接 金屬25相互連接即可。 請參見圖5，本㈣提供第二實_提供的多晶封裝發光 。該多晶封裝發光二極管7()與該多晶封裝發光 二極管10基本相同，不同之處在於：在本實施例中該 多晶封裝發光二極管7〇所包括的第—晶片組加以及第二 晶片組702分別與一個滑動電阻7〇&、？〇7串聯。因此， 在本實施例中，該第-晶片組7〇1以及第二晶片組？〇2分 別串聯的發光二極管晶片71的數量可以不葙同其分別 藉由該滑動電阻706、707控制處於工作狀態的其中一個 晶片組的電壓’以保證該多個發光二極管晶片Η均處於 額定電壓下工作。由於轉多晶封震發光二極管7〇每個晶 片組中所包㈣制二極管晶片71的數量以及工作電壓 分別可以調節，若發光二極f晶片的數量不同時，可利 用滑動電阻調節工作電®。因此，該多晶㈣發光二極 管70的設計更具靈活性。 明參見圖6本發明提供第三實施例提供的多晶封裝發光 一極s 8G胃多Ba封裝發光：極管㈣與該多晶封裝發光 二極管7G基本相同，不同之處在於：該多晶封裝發光二 極管80僅包括-個滑動電阻8Q6。該第—晶片組8〇1與該 第二晶片組802反向並聯後再與該滑動電阻議串聯。 表單編就A0101 第7頁/共19頁 0992031736-0 201145491 [0019] 請參見圖7，本發明提供第四實施例提供的多晶封裝發光 二極管90。該多晶封裝發光二極管90與多晶封裝發光二 極管80基本相同，不同之處在於：該多晶封裝發光二極 管90包括四個並聯的晶片組，其中，相鄰的兩個晶片組 反向並聯。該四個晶片組並聯後再與一個滑動電阻串聯 〇 [0020] 可以理解的是，在本實施例中，該四個並聯的晶片組， 也可以僅將其中一個晶片組與另外三個晶片組反向並聯 。每個晶片組所包括的發光二極管晶片91的數量可以不 同，也可以相同。優選地，同向並聯的晶片組所包括的 發光二極管晶片91的數量相同，因此，當同向並聯的晶 片組均處於工作狀態時，其每一個晶片組的電壓相等， 並且藉由調節該滑動電阻906，從而使發光二極管晶片91 在額定電壓下工作。 [0021] 當然，在本實施例，並聯的晶片組也不限於四個，可以 為三個或者四個以上，並且，也可以在每個晶片組上串 聯一個滑動電阻，從而同向並聯的晶月組所包括的發光 二極管晶片91的數量也可以不相同。 [0022] 綜上所述，本發明符合發明專利要件，爰依法提出專利 申請。惟，以上所述者僅為本發明之較佳實施例，舉凡 熟悉本案技藝之人士，在爰依本發明精神所作之等效修 飾或變化，皆應涵蓋於以下之申請專利範圍内。 【圖式簡單說明】 [0023] 圖1是本發明第一實施例的多晶封裝發光二極管的立體示 意圖。 表單編號A0101 099117885 第8頁/共19頁 0992031736-0 201145491 [0024] 圖2是圖1的發光二極管晶片覆晶封裝在封裝基板上的結 構示意圖。 [0025] 圖3是圖1中封裝基板上的焊接區域示意圖。 [0026] 圖4是圖3中的電路等效示意圖。 [0027] 圖5是本發明第二實施例提供的多晶封裝發光二極管的等 效電路示意圖。 [0028] 圖6是本發明第三實施例提供的多晶封裝發光二極管的等 效電路示意圖。 〇 [0029] 圖7是本發明第四實施例提供的多晶封裝發光二極管的等 效電路示意圖。 【主要元件符號說明】 [0030] 多晶封裝發光二極管：10、70、80、90 [0031] 封裝基板：20Preferably, in the present embodiment, the N-type electrode 341 and the circuit layer 21 on the N 099117885 Form No. A0101 Page 5 / 19 pages 0992031736-0 201145491 [0013] [0015] [0015] 099117885 type solder joint 23 An N-type connecting material 38 is provided between them, and a p-type connecting material (10) is provided between the P-type solder joints 24 of the p-type electrode tray circuit layer 21. The package body 40 is disposed on the package substrate 20 for covering the plurality of LED chips 30 and the connecting metal 25. The package body 4 can avoid the LED chip 30 and the connecting metal 25 from the outside water. The outer surface 41 of the package body 40 may be a flat surface, a convex curved surface or a concave curved surface to change the angle at which the light emitted from the LED chip 3 is emitted through the outer surface 41, thereby changing the polycrystalline package light. The illumination surface and the optical type of the diode 10. In the embodiment, the outer surface 41 of the package 40 is a convex curved surface. The material of the package 4 can be epoxy resin, enamel resin or other electrically insulating transparent material. Of course, the package 40 may further include diffusion particles, such as cerium oxide particles, for scattering the light emitted by the LED chip 30. Of course, the wavelength conversion substance may also be disposed in the package 40. The polycrystalline package light-emitting diode 1 〇 produces a desired color of light, such as phosphor powder. In this embodiment, the polycrystalline package is illuminated by a two-pot tube. The heat dissipating substrate 50 is disposed on the package substrate 20 and away from the side of the scale package. The heat dissipating substrate 50 is used to dissipate heat generated when the plurality of LED chips 3 are operated. It can be understood that The heat dissipation substrate 5 〇 may be the same as or different from the material of the package substrate 20. The plurality of light emitting diode chips 30 included in the polycrystalline package light emitting diode 1 形成 form two wafer groups in anti-parallel. Therefore, the AC power supply is connected. When the AC power supply is in any half cycle, one of the first chip set 26 and the second chip set 27 is lit, and the other chip set is extinguished. Therefore, the polycrystalline package LED 丨〇 Can be used directly AC form number A0101 Page 6 / 19 pages 0992031736-0 201145491 [0016] [0017] Ο 〇 [0018] 099117885 Power supply 1 No need to set up a bridge rectifier, the circuit structure is simple. Understandably, twirling The arrangement of the connection region 22 on the package substrate 2 is not limited to that shown in this embodiment, and may be other methods, such as staggered arrangement, asymmetric arrangement, as long as the phase is soldered. The solder joint 23 and the solder joint 22 adjacent thereto are connected to each other by the connection metal 25. Referring to Fig. 5, the present invention provides the polycrystalline package illumination provided by the second embodiment. The LED 7() is substantially the same as the poly-package LED 10, except that in the embodiment, the poly-package LED 7A includes a first chip set and a second chip set 702 respectively. A sliding resistor 7〇&,?7 is connected in series. Therefore, in the present embodiment, the number of the LED chips 71 connected in series between the first wafer group 7〇1 and the second wafer group 〇2 may be different. The voltages of one of the chipsets in the operating state are controlled by the sliding resistors 706, 707, respectively, to ensure that the plurality of LED chips are all operating at the rated voltage. Since the number of the diode chips 71 and the operating voltage of the package (4) in each of the wafer groups can be adjusted, respectively, if the number of the light-emitting diodes is different, the sliding resistor can be used to adjust the working power. . Therefore, the design of the poly (tetra) light emitting diode 70 is more flexible. Referring to FIG. 6 , the present invention provides a polycrystalline package light-emitting one-pole s 8G gastric multi-Ba package light-emitting device provided by the third embodiment: the pole tube (4) is substantially the same as the poly-storage light-emitting diode 7G, and the difference is that the polycrystalline package The light emitting diode 80 includes only one sliding resistor 8Q6. The first wafer group 8〇1 is connected in anti-parallel with the second wafer group 802 and then connected in series with the sliding resistor. Forms A0101 Page 7 of 19 0992031736-0 201145491 [0019] Referring to FIG. 7, the present invention provides a polycrystalline package LED 90 according to a fourth embodiment. The polycrystalline package LED 90 is substantially identical to the poly package LED 80, except that the poly package LED 90 includes four parallel wafer sets, wherein adjacent two wafer sets are connected in anti-parallel. The four wafer sets are connected in parallel and then connected in series with a sliding resistor. [0020] It can be understood that in the embodiment, the four parallel chipsets can also have only one of the chipsets and the other three chipsets. Reverse parallel. The number of light emitting diode chips 91 included in each wafer group may be different or the same. Preferably, the same-parallel series of wafers includes the same number of light-emitting diode chips 91, so that when the wafer groups in the same direction are in operation, the voltage of each of the wafer groups is equal, and by adjusting the sliding The resistor 906 is such that the LED chip 91 operates at the rated voltage. [0021] Of course, in the embodiment, the parallel chip sets are not limited to four, and may be three or more, and a sliding resistor may be connected in series on each wafer group, so that the crystals are connected in parallel in the same direction. The number of LED chips 91 included in the month group may also be different. [0022] In summary, the present invention complies with the requirements of the invention patent, and submits a patent application according to law. However, the above description is only the preferred embodiment of the present invention, and equivalent modifications or variations made by those skilled in the art of the present invention should be included in the following claims. BRIEF DESCRIPTION OF THE DRAWINGS [0023] FIG. 1 is a perspective view of a polycrystalline package light emitting diode according to a first embodiment of the present invention. Form No. A0101 099117885 Page 8 of 19 0992031736-0 201145491 [0024] FIG. 2 is a schematic view showing the structure of the flip-chip package of the LED chip of FIG. 3 is a schematic view of a soldering region on the package substrate of FIG. 1. 4 is an equivalent schematic diagram of the circuit of FIG. 3. 5 is a schematic diagram of an equivalent circuit of a polycrystalline package light emitting diode according to a second embodiment of the present invention. 6 is a schematic diagram of an equivalent circuit of a polycrystalline package light emitting diode according to a third embodiment of the present invention. 7 is a schematic diagram of an equivalent circuit of a polycrystalline package light emitting diode according to a fourth embodiment of the present invention. [Main component symbol description] [0030] Polycrystalline package light-emitting diode: 10, 70, 80, 90 [0031] Package substrate: 20
[0032] 電路層：21 ❹ [0033] 焊接區域：22 [0034] N型焊接點：23 [0035] P型焊接點：24 [0036] 連接金屬：25 [0037] 第一晶片組：26、701、801 [0038] 第二晶片組：27、702、802 [0039] 發光二極管晶片：30、71、81、91 099117885 表單編號A0101 第9頁/共19頁 0992031736-0 201145491 [0040] 外延基底：31 [0041] 緩衝層：32 [0042] 多層磊晶結構：33 [0043] N型半導體層：34 [0044] N型電極：341 [0045] 半導體活性層：35 [0046] P型半導體層：36 [0047] 透明電極層：37 [0048] P型電極：371 [0049] N型連接材料：38 [0050] P型連接材料：39 [0051] 封裝體：40 [0052] 散熱基板：50 [0053] 滑動電阻：706、707、806、906 [0054] 表面：381 [0055] 外表面：41 099117885 表單編號A0101 第10頁/共19頁 0992031736-0[0032] Circuit layer: 21 ❹ [0033] Soldering area: 22 [0034] N-type solder joint: 23 [0035] P-type solder joint: 24 [0036] Connecting metal: 25 [0037] First chip set: 26, 701, 801 [0038] Second chip set: 27, 702, 802 [0039] LED chip: 30, 71, 81, 91 099117885 Form No. A0101 Page 9 / 19 pages 0992031736-0 201145491 [0040] Epitaxial substrate : 31 [0041] Buffer layer: 32 [0042] Multilayer epitaxial structure: 33 [0043] N-type semiconductor layer: 34 [0044] N-type electrode: 341 [0045] Semiconductor active layer: 35 [0046] P-type semiconductor layer :36 [0047] Transparent Electrode Layer: 37 [0048] P-type Electrode: 371 [0049] N-type connection material: 38 [0050] P-type connection material: 39 [0051] Package: 40 [0052] Heat-dissipating substrate: 50 Sliding resistance: 706, 707, 806, 906 [0054] Surface: 381 [0055] Outer surface: 41 099117885 Form number A0101 Page 10 / Total 19 page 0992031736-0