201145452 六、發明說明： 【發明所屬之技術領域】 本發明是有關於一種半導體製程，且特別是有關於一種内 連線結構的製造方法。 【先前技術】 銅雙鑲嵌(dual damascene)技術搭配超低介電(uUra w_k) 材料為目前所知商積集度、高速(high-speed)邏輯積體電路晶片 製造以及0.18微米以下半導體製程之最佳金屬内連線解決方 案。其原因在於銅具有低電阻值(比鋁低30%)以及較佳抗電致 遷(electromigration resistance)等特性，而超低介電材 降低金屬導線之間的RC延遲(RC她y)，由 電材料搭配銅金屬雙鑲嵌内連線技術在積體電路製程中顯得 曰益重要。 β 銅金屬雙鑲嵌内連線製程約可分為三種：溝渠先形成 (trench first)式、介層洞先形成(via first)式及自行對準式 (self-aligned)式。在溝渠先形成式的雙鑲嵌製程中，由於其^ 先形成溝渠，再移除溝渠底部的部分超低介電材料，以形^介 • 層洞。因此，往往會在介層洞的側壁及底部（也就是銅金屬的 表面）殘留製程中所生成的聚合物，造成電阻值提高及RC延 遲效應等瑕疵。為解決此問題，目前是在將銅金屬填入介層洞 之則，先對溝渠及介層洞進行清洗製程，以去除殘留在溝渠及 介層洞的側壁及底部的聚合物。 習知常見的清洗製程大多是採用乾式清洗，也就是利用電 漿清洗製程來移除溝渠及介層洞内的聚合物。然而，由於超低 介電材料層會與氫離子產生反應，並增大超低介電材料層介電 吊數，因此傳統的反應式預清洗(reactive pre_clean，Rp〇製程 並不適用於具有超低介電材料層的雙鑲嵌結構中。為此，習知 201145452 另提出一種以氩氣進行電漿清洗的製程，其雖然可避免超低介 電材料層在製程中發生介電常數偏移的問題，但以此種作法所 產出的雙鎮嵌結構卻有信賴度(reliability)不足的問題。 在美國專利第6,713,402號「清除蝕刻停止層之蝕刻後聚 & 物的方法(Method for polymer removal following etch-stop layer etch)」中，其係揭露在形成介層洞之後，將基底傳送至 工作溫度約為3l〇〇C的電漿清洗室中，並通入含氫之電漿以移 除殘留之聚合物。然而，在此種高溫清洗製程中所釋放出的有201145452 VI. Description of the Invention: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor process, and more particularly to a method of fabricating an interconnect structure. [Prior Art] Dual damascene technology combined with ultra-low dielectric (uUra w_k) materials is currently known as commercial integration, high-speed logic integrated circuit chip fabrication and semiconductor processing below 0.18 micron. The best metal interconnect solution. The reason is that copper has low resistance (30% lower than aluminum) and better resistance to electromigration resistance, while ultra-low dielectric reduces the RC delay between metal wires (RC her y). The combination of electrical materials and copper metal dual damascene interconnect technology is of great importance in the integrated circuit process. The β-copper metal dual damascene interconnect process can be divided into three types: trench first (form first), via first (self first) and self-aligned. In the double damascene process in which the trench is formed first, since the trench is formed first, a part of the ultra-low dielectric material at the bottom of the trench is removed to form a layer hole. Therefore, the polymer formed in the process of the sidewall and the bottom of the via hole (that is, the surface of the copper metal) is often left, resulting in an increase in resistance value and an RC delay effect. In order to solve this problem, the copper metal is currently filled into the via hole, and the trench and the via hole are first cleaned to remove the polymer remaining on the sidewall and bottom of the trench and the via hole. Conventional cleaning processes are mostly dry cleaning, which uses a plasma cleaning process to remove the polymer from the trenches and vias. However, since the ultra-low dielectric material layer reacts with hydrogen ions and increases the dielectric suspension of the ultra-low dielectric material layer, the conventional reactive pre-cleaning (reactive pre_clean, Rp〇 process is not suitable for super In the dual damascene structure of the low dielectric material layer, for this reason, the conventional 201145452 further proposes a plasma cleaning process using argon gas, which can avoid the dielectric constant shift of the ultra low dielectric material layer during the process. Problem, but the double-town embedded structure produced by this method has the problem of insufficient reliability. In U.S. Patent No. 6,713,402, "Method for the removal of the etch stop layer after etching" In the following etch-stop layer etch), after exposing the formation of the via hole, the substrate is transferred to a plasma cleaning chamber having a working temperature of about 3 〇〇C, and a hydrogen-containing plasma is introduced to move Except for residual polymer. However, what is released in this high temperature cleaning process
機氣體除了影響各層間之界面的附著力外，亦容易與氫離子發 生化學反應並生成副產物。此時，屬於多孔性材料(p〇r〇us material)的超低介電材料將容易吸附這些副產物，使得這些副 產物附著在介層洞的側壁及底部，導致雙鑲嵌結構的製程良率 下降。 因此如何以更簡便及有效之方式去除餘刻超低介電材料 層後所產生之聚合物，且*會在清除過程巾破壞雙鑲嵌結構， 仍然是業界亟待研究改良之課題。 【發明内容】 有鑑於此’本發明的目的就是在提供一種内連線結構的製 造方法’其可在*損壞内輯結制前訂，有 所產生的副產物，以提高製程良[ f 本發明提出-種内連線結構的製造方法 底，其中此基底上已形成有第-導電層。接著，在基 ==移除部分的超低介電材料層，以形成二 以清洗開口所暴露出之第—導騎的表面。其巾，此 製程的工作溫度介於室溫至卿。c之間。 乾式心先 201145452 在本發明之—實關中，上述m包括氣氣。 的本發明之—實施例中’上述之氣體中氫氣含4佔總含量 ，本發明之一實施例中，上述之氣體更包括情性氣體，例 如IL範。 例為發明之—實施例中，上述之氣體中之氫氣與氦氣的比 sc!本發明之—實關中，上述之氣體中，氫氣之流量為 200sccm，虱氣之流量為80〇sccm。 介於=二==之乾式清洗製程的工作溫度 作溫度银〇是耽 丨纽’上叙乾式清洗製程的工 前，之—實㈣巾’在形成上述超财電材料層之 二、tit底上形成第—阻障層覆蓋第—導電層，且在移 介電材料層時’更包括移除對應之部分第-阻障 層’以形成上述開口而暴露出部分之第—導電層。 ▲$之—實施例巾’在移除部分之超低介電材料層之 超低介電材料層上形成硬罩幕層，接著再移除部 =更罩幕層’以暴露出上述超低介電材料層欲形成上述開口 之處。 在本㈣之—實關巾，形成上賴σ的方法包括先移除 上逑超低介電材料層的第—部份’⑽成溝渠。接著再移除超 ^電材料層位於溝渠⑽第二部份，以形成介層洞而與溝渠 構成上述開口。 在本發明之-實施例中，更包括在上述開口内填入第二導 電層，以使第二導電層與第一導電層電性連接。 201145452 在本發明之-實施例中’在填入上述第二導電層之前，更 包括形成第二阻障層，以覆蓋上述開口之侧壁。 在本發明之-實施例中’上述超低介電材料層的介電係數 ;ι於1.9至2.5之間。舉例來說，上述超低介電材料層的介 係數例如是2.0。 。本發明是在超低介電材制巾形賴_，在介於室溫至 100C之間駐作環境下進行乾式清洗製程，以減少清洗製程 中所使用的氣體與殘留在開口内的副產物反應生成的廢氣，進 Φ而避免過多的廢氣無法完全從開口内抽離而影響後續形成之 内連線結構的電性。 為讓本發明之上述和其他目的、特徵和優點能更明顯易 下文特舉較佳實施例，並配合所附圖式，作詳細說明如下。 【實施方式】 圖1為本發明之一實施例中内連線結構在部分製程中的 剖面不意圖。請參照圖卜首先提供基底110,其中基底110 上已形成有介電層112與第—導電層114，且第一導電層114 • 例如，嵌於介電層112中。具體來說，第-導電層114的材質 =如疋銅。接著’在基底11()上形成超低介電材料 120而覆蓋住第—導電層114。在本實施例中，超低介電材 2層，的材質例如是AMAT的BlackDiam〇nd π，而其介電 吊數是”於1.9至2·5之間’且較佳為2.G，但本發明不限於此。 此外，本實施例還可以在形成超低介電材料層120之前， ，在基底11G上形成第—阻障層115，其例如是由氮化石夕 用以避免第—導電層114的金屬原子擴散至超低介 廣120内。 了 接績’移除部分之超低介電材制12G以及對應之第—阻 201145452 障層115，以形成暴露出第一導電層114的開〇 。詳細來 說’開口 122例如是利用圖案化光阻層（圖未示）作為遮罩， 並透過餘刻的方式製成。而且’在將圖案化光阻層移除後，為 避免在關製程巾所產生的副產钱留在開口 122内而影響 後續製程的良率，接著即是進行乾式清洗製程，而本實施例是 利用電漿清洗製程來去除殘留在開σ 122内的副產物。由於 Aktivpre-dean (簡稱為APC)製程具有高清洗效率，且經此 清洗製私的内連線結構可具有足夠的電子遷移信賴度 φ (eleCtr〇migrati〇nreliabiHty)，因此本實施例例如是以APC來清 洗開口 122。詳細來說，本實施例是通入氣體〇來進行電漿清 洗製程’其中氣體G中例如是包括氫氣。由於氫氣所釋放出 的氫氣自由基(hydrogen radical)可與殘留在開口 122内的副產 物反應並生成氣體，因此可在清洗製程中同時進行抽氣，以將 這些氣體生成物抽掉。 需要注意的是’由於氫氣之自由基(radicai)在高溫（如I% C以上）下容易與含矽之殘留物反應生成廢氣，而這些廢氣若 未在將導電金屬填入開口 122之前完全抽離，則後續進行熱製 ® 程後將會導致第一導電層114的電性受損。因此，本實施例是 將清洗製程的工作溫度控制在室溫至1〇〇。匚之間，且較佳的是 維持在室溫至60°c之間’例如是50°C，以減少氫氣之自由基 與含石夕之殘留物反應所生成的廢氣量。此處所謂之室溫是指在 不對工作環境進行降溫或加熱之情況下的溫度，一般通常為 25 C左右’但其並非本發明所欲限定之範圍。 圖2A至圖2D分別為本發明之一實施例中，以不同溫度 對晶圓上之内連線結構進行清洗製程後，晶圓允收測試(Wafer Acceptance Test, WAT)之密集介層插塞鏈(via Chain)示意圖， 201145452 且本實施例以斜線表示出晶圓210上的電性不良區。請參照圖 至圖2C，當清洗製程的溫度分別為310。〇、200〇C以及150 c時，後續在晶圓21 〇上會測得高比例的電性不良區。然而， 當清洗製程的溫度控制為5〇t時，後續在晶圓210上僅測得 少數的電性不良區’如圖2D所示。由此可知，在清洗圖1之 開口 122的製程中將溫度控制在i〇〇t：以下，可有效提高内連 線結構的製程良率。 請繼續參照圖1，除此之外，為避免因通入的氫氣量過 多，導致其與殘留在開口 122内之副產物反應生成過多廢氣而 未月bTG全抽離’在其他實施例中也可以減少乾式清洗製程中氫 氣的用量，進而減少氫氣與副產物反應生成的廢氣。舉例來 -兒，乾式清洗製程中可同時通入氫氣與惰性氣體，例如氦氣。 ，中，氣體G内之氫氣含量例如是20%。舉例來說，氫氣與 ，氣的較佳比例可為1 : 4，且氫氣的流量可以是2〇〇sccm，氦 氣的流量則可以是800sccm。 ’ 本發明在上述實施例中所揭露的製程適用於製作任何具 有超低介電材料層的内連線結構，為使熟f此技藝者更加瞭解 本發明，以下將舉雙鑲嵌結構的製程為例配合圖式來進一步說 明本發明’但其並非用以限定本發明。 圖3A至圖3B為本發明之一實施例中以先形成溝渠 (trench first)之方式製作雙鑲嵌結構之製程的剖面示意圖。請^ 考圖3A，首先提供基底310，其上形成有介電層312及第一 導電層314，其中第-導電層314是鑲嵌於介電層312内而 在第-導電層314上則形成有第—阻障層316，其例如是由氮 化矽(silicon nitride)所構成。接著，在第一阻障層316上依序 形成超低介電材料層320、糊終止層、硬罩幕層 201145452 mask，HM)340以及頂蓋層350,其中超低介電材料層32〇的材 質例如是AMAT的BlackDiamond II，但本發明不以此為限。 而且’超低介電材料層320的介電常數大約介於19至2.5之 間，較佳則為2.0。蝕刻終止層330的材質可以是氮氧化矽 (SiON) ’硬罩幕層340的材質可以是氮化鈦⑽anic血此， TiN)。而且，頂蓋層350可以是單層結構，也可以是複合層結 構，如氮氧化>5夕/氧化石夕。 然後，移除部分之頂蓋層350、硬罩幕層34〇、蝕刻終止 層330及其下方之部分超低介電材料層32〇，以於超低介電材 料層320中幵>成溝渠322。本實施例例如是利用微影姓刻的方 式移除部分的這些臈層，並透過钱刻參數的控制，將钱刻製程 終止於超低介電材料層320的某深度，進而形成溝渠322。在 形成溝渠322之後，接著再移除溝渠322内的部分超低介電材 料層320及對應之第一阻障層316，以形成介層洞324。在此， 介層洞324係與溝渠322構成暴露出第一導電層314的開口 321。 具體來說’形成介層洞324的方法是先在超低介電材料層 320上形成圖案化光阻層（圖未示），以暴露出溝渠322内的 4刀超低介電材料層320。接著再以此圖案化光阻層為罩幕， 對超低介電材料層320及對應之第一阻障層416進行蝕刻製程 以形成介層洞324。然後，再移除剩下的圖案化光阻層。 承上所述，由於在移除剩下的圖案化光阻層時，往往會在 開二321内殘留製程中所生成的副產物’因此接著必須進^乾 式清洗製程’以移除在#刻製程後仍殘留在溝渠似及介層洞 =4内的副產物。舉例來說，本實施例是在溫度介於室溫至議 之間的工作環境下軟氣體G來進行電漿清洗製程，且較 201145452 佳的工作溫度是介於室溫至60°C之間，例如50°C。而氣體G 可以包括氫氣。由於在室溫至100°C之間的溫度下進行電聚清 洗製程可減少氫氣之自由基與含矽之殘留物反應所生成的廢 氣量，因此本實施例除了可以有效清除溝渠322與介層洞324 内之副產物以外，更可以降低將溝渠322與介層洞324内之廢 氣完全抽淨的困難度。In addition to affecting the adhesion of the interface between the layers, the gas easily reacts with hydrogen ions to form by-products. At this time, an ultra-low dielectric material belonging to a porous material (p〇r〇us material) will easily adsorb these by-products, so that these by-products adhere to the sidewalls and the bottom of the via hole, resulting in a process yield of the dual damascene structure. decline. Therefore, how to remove the polymer produced by the ultra-low dielectric material layer in a more convenient and efficient manner, and the destruction of the dual damascene structure in the cleaning process towel is still an urgent problem to be researched and improved in the industry. SUMMARY OF THE INVENTION In view of the above, the object of the present invention is to provide a method for manufacturing an interconnect structure, which can be ordered before the *damage, and produces by-products to improve the process [f The invention proposes a method for manufacturing an interconnect structure in which a first conductive layer has been formed on the substrate. Next, a portion of the ultra-low dielectric material layer is removed at the base == to form a surface to illuminate the first-handed ride exposed by the opening. Its towel, the working temperature of this process is between room temperature and Qing. Between c. Dry heart first 201145452 In the present invention, the above m includes gas. In the present invention, in the above-mentioned gas, the hydrogen content of the gas is 4, and in one embodiment of the present invention, the gas further includes an inert gas such as IL. For example, in the embodiment, the ratio of hydrogen to helium in the gas described above is in the present invention. In the gas of the present invention, the flow rate of hydrogen gas is 200 sccm, and the flow rate of helium gas is 80 〇 sccm. The working temperature of the dry cleaning process of ======================================================================================================= Forming a first barrier layer overlying the first conductive layer, and further removing the corresponding portion of the first barrier layer when removing the dielectric material layer to form the opening to expose a portion of the first conductive layer. ▲$—the embodiment towel' forms a hard mask layer on the ultra-low dielectric material layer of the removed ultra-low dielectric material layer, and then removes the portion = more mask layer to expose the above-mentioned ultra low The layer of dielectric material is intended to form the opening. In the method of (4), the method of forming the upper σ includes removing the first portion (10) of the upper ultra-low dielectric material layer into a ditch. The second layer of the super-electric material layer is then removed from the second portion of the trench (10) to form a via hole to form the opening with the trench. In an embodiment of the invention, the second conductive layer is filled in the opening to electrically connect the second conductive layer to the first conductive layer. 201145452 In the embodiment of the present invention, before the filling of the second conductive layer, the second barrier layer is further formed to cover the sidewall of the opening. In the embodiment of the invention - the dielectric constant of the ultralow dielectric material layer; i is between 1.9 and 2.5. For example, the dielectric constant of the ultralow dielectric material layer is, for example, 2.0. . The invention adopts a dry cleaning process in an environment of room temperature to 100C in an ultra-low dielectric material to reduce the gas used in the cleaning process and the by-products remaining in the opening. The exhaust gas generated by the reaction enters Φ to prevent excessive exhaust gas from being completely removed from the opening and affecting the electrical properties of the subsequently formed interconnect structure. The above and other objects, features, and advantages of the present invention will be apparent from the description and appended claims [Embodiment] FIG. 1 is a cross-sectional view showing an internal wiring structure in a partial process in an embodiment of the present invention. Referring to FIG. 2, a substrate 110 is first provided, in which a dielectric layer 112 and a first conductive layer 114 have been formed on the substrate 110, and the first conductive layer 114 is, for example, embedded in the dielectric layer 112. Specifically, the material of the first conductive layer 114 is, for example, beryllium copper. An ultra-low dielectric material 120 is then formed on the substrate 11 () to cover the first conductive layer 114. In this embodiment, the material of the ultra-low dielectric material is, for example, AMAT's BlackDiam〇nd π, and the dielectric hang number is "between 1.9 and 2.5" and preferably 2.G. However, the present invention is not limited thereto. In addition, in this embodiment, before the formation of the ultra-low dielectric material layer 120, a first barrier layer 115 may be formed on the substrate 11G, which is used, for example, by nitrite to avoid the first The metal atoms of the conductive layer 114 diffuse into the ultra-low dielectric 120. The portion of the ultra-low dielectric material 12G and the corresponding first-resistance 201145452 barrier layer 115 are removed to form the exposed first conductive layer 114. In detail, the opening 122 is made, for example, by using a patterned photoresist layer (not shown) as a mask, and is formed by a residual method, and 'after removing the patterned photoresist layer, The by-product money generated in the process towel is prevented from remaining in the opening 122 to affect the yield of the subsequent process, and then the dry cleaning process is performed. In this embodiment, the plasma cleaning process is used to remove the residue in the opening σ 122. By-products, due to the high cleaning of the Aktivpre-dean (referred to as APC) process The efficiency, and the interconnect structure that is cleaned by this cleaning can have sufficient electron mobility reliability φ (eleCtr〇migrati〇nreliabiHty), so in this embodiment, for example, the opening 122 is cleaned by APC. In detail, this embodiment The gas cleaning process is performed by introducing a gas enthalpy, wherein the gas G includes, for example, hydrogen gas. Hydrogen radicals released by the hydrogen gas can react with by-products remaining in the opening 122 to generate a gas. Pumping can be performed simultaneously in the cleaning process to remove these gas products. It should be noted that 'the radicals of hydrogen are easily reacted with the residue containing ruthenium at high temperatures (eg, I% C or more). Exhaust gas is generated, and if the exhaust gas is not completely removed before the conductive metal is filled into the opening 122, subsequent electrical processing will cause electrical damage to the first conductive layer 114. Therefore, this embodiment will The working temperature of the cleaning process is controlled from room temperature to 1 Torr, and preferably between room temperature and 60 ° C 'for example, 50 ° C to reduce hydrogen free radicals and The amount of exhaust gas generated by the reaction of the residue. The term "room temperature" as used herein refers to a temperature which is not lowered or heated in the working environment, and is generally about 25 C', but it is not within the scope of the present invention. FIG. 2A to FIG. 2D respectively illustrate a dense dielectric plug of a Wafer Acceptance Test (WAT) after a cleaning process on an internal interconnect structure on a wafer at different temperatures according to an embodiment of the present invention. A schematic diagram of a via chain, 201145452, and this embodiment shows oblique regions of electrical defects on the wafer 210. Referring to Figures 2C, the temperature of the cleaning process is 310. When 〇, 200〇C, and 150c, a high proportion of electrically defective regions will be measured on the wafer 21 后续. However, when the temperature of the cleaning process is controlled to 5 〇t, only a small number of electrically defective regions are subsequently measured on the wafer 210 as shown in Fig. 2D. Therefore, it can be seen that in the process of cleaning the opening 122 of Fig. 1, the temperature is controlled to be below i〇〇t: the process yield of the interconnect structure can be effectively improved. Please continue to refer to FIG. 1 , in addition, in order to avoid excessive amount of hydrogen introduced, it reacts with by-products remaining in the opening 122 to generate excessive exhaust gas, and the full moon bTG is completely extracted' in other embodiments. It can reduce the amount of hydrogen in the dry cleaning process, and thus reduce the exhaust gas generated by the reaction between hydrogen and by-products. For example, in the dry cleaning process, hydrogen and an inert gas such as helium can be simultaneously introduced. In the middle, the hydrogen content in the gas G is, for example, 20%. For example, a preferred ratio of hydrogen to gas may be 1:4, and the flow rate of hydrogen may be 2 〇〇sccm, and the flow rate of helium may be 800 sccm. The process disclosed in the above embodiments of the present invention is suitable for fabricating any interconnect structure having an ultra-low dielectric material layer. To make the present invention more familiar to the present invention, the process of the dual damascene structure is as follows. The invention is further described with reference to the drawings, which are not intended to limit the invention. 3A-3B are schematic cross-sectional views showing a process of fabricating a dual damascene structure by first forming a trench first in an embodiment of the present invention. Referring to FIG. 3A, a substrate 310 is first provided, on which a dielectric layer 312 and a first conductive layer 314 are formed, wherein the first conductive layer 314 is embedded in the dielectric layer 312 and formed on the first conductive layer 314. There is a first barrier layer 316 which is composed, for example, of silicon nitride. Next, an ultra-low dielectric material layer 320, a paste stop layer, a hard mask layer 201145452 mask, HM) 340, and a cap layer 350 are formed on the first barrier layer 316, wherein the ultra-low dielectric material layer 32〇 The material is, for example, AMAT's BlackDiamond II, but the invention is not limited thereto. Moreover, the dielectric constant of the ultra low dielectric material layer 320 is between about 19 and 2.5, preferably 2.0. The material of the etch stop layer 330 may be bismuth oxynitride (SiON). The material of the hard mask layer 340 may be titanium nitride (10) anic blood, TiN). Further, the cap layer 350 may have a single layer structure or a composite layer structure such as oxynitridation > Then, a portion of the cap layer 350, the hard mask layer 34, the etch stop layer 330, and a portion of the ultra-low dielectric material layer 32A underneath are removed to form a layer in the ultra-low dielectric material layer 320. Ditch 322. In this embodiment, for example, the enamel layer is removed by using a lithography method, and the etch process is terminated by a certain depth of the ultra-low dielectric material layer 320 to form the trench 322. After the trenches 322 are formed, a portion of the ultra-low dielectric material layer 320 and the corresponding first barrier layer 316 in the trenches 322 are then removed to form vias 324. Here, the via 324 and the trench 322 constitute an opening 321 exposing the first conductive layer 314. Specifically, the method of forming the via 324 is to first form a patterned photoresist layer (not shown) on the ultra-low dielectric material layer 320 to expose the 4-pole ultra-low dielectric material layer 320 in the trench 322. . Then, the photoresist layer is patterned as a mask, and the ultra-low dielectric material layer 320 and the corresponding first barrier layer 416 are etched to form via holes 324. Then, the remaining patterned photoresist layer is removed. As described above, since the by-products generated in the residual process are often left in the opening 321 during the removal of the remaining patterned photoresist layer, it is then necessary to perform a dry cleaning process to remove the #刻刻After the process, the by-products remaining in the ditch and the mesopores = 4 remain. For example, in this embodiment, the soft gas G is used for the plasma cleaning process in a working environment with a temperature between room temperature and the temperature, and the working temperature is better than the temperature of 201145452 between room temperature and 60 ° C. , for example, 50 ° C. The gas G may include hydrogen. Since the electropolymerization cleaning process at a temperature between room temperature and 100 ° C can reduce the amount of exhaust gas generated by the reaction of the hydrogen radical and the ruthenium-containing residue, the embodiment can effectively remove the trench 322 and the interlayer. In addition to the by-products in the holes 324, the difficulty in completely purging the exhaust gas in the trenches 322 and the vias 324 can be reduced.
而且’在本實施例之氣體G中’氫氣所佔比例約為2〇% 至50%，而其餘部分則可以是情性氣體，如氦氣。具體來說， 本實施例所使用之氣體G中，氫氣與氦氣的比例可以是丨：2， 也可以是1 : 4。在氫氣與氦氣之比例為丨：4的實施例中，氣 氣的流量例如是200sccm，氦氣的流量則是800sccm。 由上述可知’本實施例除了透過降低乾式清洗製程中的工 作,度來避免氫氣與殘留在開口内的副產物反應生成過多的 廢氣外’ ^可藉喊少乾式清洗製程情使㈣氫氣量來進— 步減少廢氣的生成，以避免發生因廢氣抽離不全而在後續 中對所形成的雙鑲統構之紐造成不良的影響。 圖4為以前述製程形成開口後，以不同之乾式清洗製程另 ;開口内之殘留物後’在開口内以歐傑電子光譜儀(A喂 =errspeetn)sec)py’AEs)所測得之銅訊號的比較曲線圖。請Ρ =參照圖3A及圖4，撗軸座標上的m及Μ兩點分別代= 值二5作'皿度進行乾式清洗製程的内連線結構，縱軸座申 值則為在開口内所測得之鉬 平田’丄书 構是在3UTC的高溫卫作其中’E1所代表内連線矣Further, in the gas G of the present embodiment, the proportion of hydrogen is about 2% to 50%, and the remainder may be an inert gas such as helium. Specifically, in the gas G used in the embodiment, the ratio of hydrogen gas to helium gas may be 丨:2 or 1:4. In the embodiment where the ratio of hydrogen to helium is 丨:4, the flow rate of the gas is, for example, 200 sccm, and the flow rate of helium is 800 sccm. It can be seen from the above that the present embodiment can prevent the hydrogen from reacting with the by-products remaining in the opening to generate excessive exhaust gas by reducing the work in the dry cleaning process, which can be used to reduce the amount of hydrogen in the dry cleaning process. Further steps are taken to reduce the generation of exhaust gas to avoid adverse effects on the formed double-inlaid ridges in the subsequent stages due to exhaust gas detachment. Figure 4 shows the copper measured by the above-mentioned process after the opening is formed by a different dry cleaning process; the residue in the opening is 'in the opening by the Auger electron spectrometer (A feed = errspeetn) sec) py'AEs) A comparison chart of signals. Please refer to Fig. 3A and Fig. 4, the m and Μ on the 座 axis coordinate = = 2, respectively, for the inner connection structure of the dry cleaning process, and the value of the vertical axis seat is within the opening. The measured molybdenum Pingtian '丄书构 is a high temperature guard in 3UTC where the 'E1 represents the interconnected line矣
ApC清洗製程。相較 f 5GC的工作^下進仃上述々ApC cleaning process. Compared with the work of f 5GC
對應之銅。^ 對應之舰鮮均值大於E 由此可知，在5(rc的工作環境下進辛 201145452 APC，洗製⑽目較於在高溫31()。⑶卫作環境下進行紙清 洗製程，可較有效地清洗溝渠似與介層洞似内的殘留物二 ，避免第-導電層314被殘留物所覆蓋，進而可測得較多的銅 §fL "5虎。 請參照圖3B，於溝渠322以及介層洞324内填入第二導 電$ 360，以形成雙鑲嵌結構300。其中，第二導電層36〇的 材質例如是銅，而填入第二導電層36〇的詳細製程為此技術領 域者所熟知，此處不再贅述。 此外，本實施例在填入第二導電層36〇之前，係先形成一 層第二阻障層370覆蓋住溝渠322及介層洞324的側壁與底 部，以避免後續填入之第二導電層36〇中的金屬離子經由;冓渠 322及介層洞324的側壁擴散至超低介電材料層42〇内。其中， 在形成第二阻障層370的製程中，可藉由調整參數來決定第二 阻障層370在介層洞324底部的厚度，以降低後續填入之第二 導電層360與第一導電層314之間的阻抗。 本發明是在超低介電材料層中形成開口後，在介於室溫至 l〇〇°C之間的工作環境下進行乾式清洗製程，以減少清洗製程 中所使用的氣體與殘留在開口内的副產物反應生成的廢氣，進 而可避免廢氣過多而難以完全抽離。而且，除了控制工作溫度 外，本發明還可以減少乾式清洗製程中所使用的氫氣量，以達 相同之功效。 基於上述’本發明不但可有效地清洗殘留在開口内的副產 物，更可以避免清洗製程中所生成之廢氣殘留在開口内而對内 連線結構之電性造成不良的影響，進而在維持内連線結構之信 賴度(reliability)的同時’亦提高製程良率。 雖然本發明已以較佳實施例揭露如上，然其並非用以限定 201145452 本發明，任何熟習此技藝者， 、 内，當可作些許之更動與謂飾，因發明之積神和範圍 附之ΐ請專利所界定者轉。發仅保tf|!圍當視後 【圖式簡單說明】 剖面二為本發明之一實施例中内連線結構在部分製程中的 圖2A至圖2D分別為本發明之一 A 對晶圓上之内連線έ士爐、隹〜太 也丫彳中，以不同溫度 圖。 連線、，'°構進仃清洗製程後，晶圓的參數測試示意 他圖3Β為本發明之一實施例中以先形成溝渠之方 式製作雙·結構之製程的剖面示意圖。 圖4為以前述製程形成開口後，以*同之乾式清洗製程清 洗開口内之殘留物後’在開σ内所測得之鋼訊號的比較曲線 圖。 【主要元件符號說明】 300 :雙鑲嵌結構 H 310:基底 112、312 :介電層 114、 314 :第一導電層 115、 316 :第一阻障層 120 ' 320 :超低介電材料層 122、321 :開口 210 :晶圓 322 :溝渠 324 :介層洞 330 :餘刻終止層 12 201145452 340 :硬罩幕層 350 :頂蓋層 360 :第二導電層 370 :第二阻障層 G :氣體Corresponding copper. ^ Corresponding ship fresh average value is greater than E. It can be seen that in 5 (rc working environment, entering Xin 201145452 APC, washing (10) is better than high temperature 31 (). (3) paper cleaning process can be more effective The cleaning of the trench is similar to the residue in the via hole, avoiding the first conductive layer 314 being covered by the residue, and thus measuring more copper §fL "5 tiger. Please refer to FIG. 3B, in the trench 322 And the second hole $360 is filled in the via hole 324 to form the dual damascene structure 300. The material of the second conductive layer 36 is, for example, copper, and the detailed process of filling the second conductive layer 36 is the technology. It is well known in the art and will not be described here. In addition, before filling the second conductive layer 36, the first barrier layer 370 is formed to cover the sidewalls and bottoms of the trench 322 and the via 324. In order to prevent the metal ions in the second conductive layer 36〇 that are subsequently filled in, the sidewalls of the trench 322 and the via hole 324 are diffused into the ultra-low dielectric material layer 42〇, wherein the second barrier layer is formed. In the process of 370, the second barrier layer 370 can be determined in the via hole by adjusting the parameters. The thickness of the bottom portion of 324 is to reduce the impedance between the second conductive layer 360 and the first conductive layer 314 which are subsequently filled in. The present invention is formed in the ultra low dielectric material layer after opening at room temperature to l〇 The dry cleaning process is carried out in a working environment between 〇 ° C to reduce the exhaust gas generated by the reaction between the gas used in the cleaning process and the by-products remaining in the opening, thereby avoiding excessive exhaust gas and being difficult to completely withdraw. In addition to controlling the working temperature, the present invention can also reduce the amount of hydrogen used in the dry cleaning process to achieve the same effect. Based on the above, the present invention can not only effectively clean the by-products remaining in the opening, but also avoid the cleaning process. The generated exhaust gas remains in the opening and adversely affects the electrical properties of the interconnect structure, thereby improving the process yield while maintaining the reliability of the interconnect structure. Although the present invention has been The preferred embodiment is disclosed above, but it is not intended to limit the present invention to 201145452. Anyone skilled in the art may, within a certain time, make a few changes and Mingzhi Jishen and scope are attached to the patent to define the person to turn. Send only tf|! After the view of the [simplification of the diagram] Section 2 is an embodiment of the invention, the interconnect structure in part of the process 2A to 2D are respectively a different temperature diagram of the inner wiring gentleman furnace, the 隹~太也丫彳 on the wafer, the connection line, the '° structure 仃 cleaning process, The parameter test of the wafer is shown in FIG. 3 , which is a schematic cross-sectional view of a process for fabricating a double structure by forming a trench first in an embodiment of the present invention. FIG. 4 is a dry cleaning process after the opening is formed by the above process. A comparison curve of the steel signals measured within the opening σ after cleaning the residue in the opening. [Main Element Symbol Description] 300: Dual damascene structure H 310: Substrate 112, 312: Dielectric layer 114, 314: First conductive layer 115, 316: First barrier layer 120' 320: Ultra low dielectric material layer 122 321 : opening 210 : wafer 322 : trench 324 : via hole 330 : residual stop layer 12 201145452 340 : hard mask layer 350 : cap layer 360 : second conductive layer 370 : second barrier layer G : gas