201145239 々、發明說明： 【發明所屬之技術領域】 示系統，特別關於一種源 需要更小尺寸的源極驅動 本發明係關於一種影像顯 極驅動器。 【先前技術】 一個以上的源極驅動器可固定於 用以傳送資料信號至資料線以驅 在影像顯示系統中， 玻璃基板的像素陣列上， 動像素陣列。 為了降低成本並縮小尺寸 器。 【發明内容】 :發明揭露了一種具有小尺寸之源極驅動器的 不糸統。 根據本發明之一實施例，該源極驅動器包括第一數位 =類比轉換ϋ、第二數位至類比轉換器 '第—切換電路與 —切換電路。第—數位至類比轉換器用以將N位元之數 ，碼轉換成第―類比信號，其中N為―正整數。第二數位 號類：轉換器用以將κ位元之數位碼轉換成第二類比信 曷1、、κ為—正整數並且小於Ν。第一切換電路控制第 哭頁丁資料、第二顯示資料與第_與第二數位至類比轉換 二之間的輕接關係。第二切換電路控制第—與第二類比信 ,、及第運异放大器與第二運算放大器之間的連接關 201145239 係“中第-運异放大盗轉接至一像素陣列之第一 線，第二運算放大器搞接至像素陣列之第二資料線。" 元ίΐΐ的實施例中，第—與第二顯示資料皆具有心 二=露了第一與第二切換電路的控制方法。根 康本發月之一貫施例，控制機制包含至 =陣列之-第-列之-第-時間區間，第-二= 工制用以純弟―顯示資料之所有位元 比，，，第二顯示資料之,個最重要 lg cant blts)至第二數位至類比轉換器。第二切換電路被 第一類比信號至第-運算放大以及連接 運算放大器。於第-時間區間之後， 並且在知描像素陣列之第—列之―第二時間 =Γ:皮控制用以耦接第二顯示資料之所有位元至第： -類比二匕=器’並且第二切換電路被控制用以連接第 類比L唬至第二運算放大器。 在第一時間區間，在第—別 ❿ 辛直接被Μ 5甘 取連接至苐—資料線之像 妾被充電至其目標電壓，而在第-列且連接至第1 =之像素僅被預先充電至其目標電以 :間區間’在第-列且連接至第一資料線之二= 電’此時源極驅動5|鼓六脏 之像辛從1日=將在第一列且連接至第二資料線 象素‘電壓的中間值充電至其目標電壓。 【實施方式】 目標和優點能更明顯 為使本發明之製造、操作方法、 201145239 易懂’下文特舉幾個較佳實施例，並配合 細說明如下： 所附圖式 作詳 實施例： 第1圖係顯示影像顯示系統100,复包 -實施例所述之-源極驅動器 -像素陣列。閘極驅動n 1G4用以控制掃描像素陣列 106的程序。源極驅動器1〇2透過資料線Dli、 DL3...DL2M分別傳送資料信號叫如、〇_、201145239 々, DESCRIPTION OF THE INVENTION: FIELD OF THE INVENTION The present invention relates to an image display driver, and more particularly to a source that requires a smaller size source drive. [Prior Art] More than one source driver can be fixed to transmit a data signal to a data line to drive an array of pixels on a pixel array of a glass substrate in an image display system. In order to reduce costs and reduce the size of the device. SUMMARY OF THE INVENTION The invention discloses a system having a small-sized source driver. According to an embodiment of the invention, the source driver comprises a first digit = analog conversion ϋ, a second digit to analog converter 'the first switching circuit and the switching circuit. The first-to-digital to analog converter is used to convert the number of N-bits into a first analog signal, where N is a positive integer. Second digit class: The converter converts the digit code of the k-bit into a second analog signal 1, κ is a positive integer and less than Ν. The first switching circuit controls the light connection between the first page data, the second display data, and the _th and second digits to the analog conversion. The second switching circuit controls the first and second analog signals, and the connection between the second operational amplifier and the second operational amplifier 201145239 is the first line of the first-to-one pixel array. The second operational amplifier is connected to the second data line of the pixel array. In the embodiment of the invention, the first and second display materials have the second control method of the first and second switching circuits. Kang Ben's consistent application of the month, the control mechanism includes to - the array - the first column - the first time interval, the second - the second system = the pure brother - all the bit ratios of the displayed data,, the second display data a most important lg cant blts) to a second digit to analog converter. The second switching circuit is first analog signal to the first operational amplification and connected to the operational amplifier. After the first time interval, and in the knowledge of the pixel array The second time = Γ: the skin control is used to couple all the bits of the second display data to: - analogy = 器 ' and the second switching circuit is controlled to connect the analogy L to Second operational amplifier. At first The interval between the first and the other is directly connected to the 苐 - the image of the data line is charged to its target voltage, while the pixel in the first column and connected to the 1 = is only precharged to its The target power is: the interval 'in the first column and connected to the first data line two = electricity' at this time the source drive 5 | drum six dirty image Xin from 1 day = will be in the first column and connected to the second The intermediate value of the data line pixel 'voltage is charged to its target voltage. [Embodiment] The objects and advantages can be more apparent in order to make the manufacturing and operation method of the present invention, 201145239 easy to understand. The details are as follows: The following is a detailed description of the drawings: Fig. 1 shows an image display system 100, a source driver-pixel array described in the multi-package-embodiment, and a gate driver n 1G4 for controlling scanning pixels. The program of the array 106. The source driver 1〇2 transmits the data signals respectively via the data lines Dli, DL3, ..., DL2M, such as 〇, 〇,
Data3…Data2M(如第3圖所示）至像素陣列1〇6。在此實施 例中，源極驅動器102控制像素陣列106根據一列反轉技 術(row inversion technique)顯示影像，其中列反轉技術為在 同一列上的像素點由具有相同極性的電壓所控制，而在相 鄰之一列上的像素點則由具有相反極性的電壓所控制。 第2圖係顯示如上所述之電壓極性的概念。如圖所示， 由-貝料線DLI、DL2、DL3...DL2M所傳送的資料信號 Data卜Data2、Data3...Data2M的電壓可被允許分佈於供應 電壓VDD至接地電壓GND之一電壓範圍内。一共用電^ VCOM可介於供應電壓VDD與接地電壓GND之間。介於 共用電壓VCOM與供應電壓VDD之間的電壓可被視為正 極性（positive polarity，標示為+)電壓，而介於共用電壓 VCOM與接地電壓GND之間的電壓可被視為負極性 (negative polarity，標示為-)電壓。 第3圖係顯示根據本發明之一實施例所述之源極驅動 器102之方塊圖。源極驅動器1〇2包含複數通道302 1、 302一2...302_M。各通道為像素陣列1〇6的兩資料線接收兩 201145239 筆顯示資料（數位），並輸出兩筆資料信號（類比）β例如 筆顯示資料ΙΝ1與ΙΝ2被傳送至通道302 1，田 ’兩 ^ , — 用以被轉換 成兩筆負料信號Dat:al與Data2 ’以傳送至資料線、 DL2。同樣的，兩筆顯示資料IN3與IN4祜偟、、， 與 瓜得迗至通道Data3...Data2M (as shown in Figure 3) to pixel array 1〇6. In this embodiment, the source driver 102 controls the pixel array 106 to display images according to a column inversion technique, wherein the column inversion technique is such that pixels on the same column are controlled by voltages having the same polarity, and Pixels on one adjacent column are controlled by voltages of opposite polarity. Figure 2 shows the concept of voltage polarity as described above. As shown, the voltages of the data signals Data2, Data3, ..., Data2M transmitted by the -bee feed lines DLI, DL2, DL3, ... DL2M can be allowed to be distributed over one of the supply voltage VDD to the ground voltage GND. Within the scope. A common power ^ VCOM can be between the supply voltage VDD and the ground voltage GND. The voltage between the common voltage VCOM and the supply voltage VDD can be regarded as a positive polarity (labeled as +) voltage, and the voltage between the common voltage VCOM and the ground voltage GND can be regarded as a negative polarity ( Negative polarity, labeled as -) voltage. Figure 3 is a block diagram showing a source driver 102 in accordance with an embodiment of the present invention. The source driver 1 〇 2 includes a plurality of channels 302 1 , 302 - 2 ... 302_M. Each channel is the two data lines of the pixel array 1〇6, receiving two 201145239 pen display data (digits), and outputting two data signals (analog) β, for example, the pen display data ΙΝ1 and ΙΝ2 are transmitted to the channel 302 1, Tian 'two ^ , — used to be converted into two negative signals Dat:al and Data2 'to be transferred to the data line, DL2. Similarly, two pens display the information IN3 and IN4祜偟,,, and
302一2，用以被轉換成兩筆資料信號Data3與〇ata4 送至資料線DL3與DL4。至於源極驅動器ι〇2最 以傳 道302JVI，兩筆顯示資料IN(2M-1)與iN2M[被轉換成的通 資料信5虎Data(2M-1)與Data2M ’以傳送至資料線 與 DL2M。 ^ 第4圖係顯示根據本發明之一實施例所述之通道範 例。通道400包括四個數位至類比轉換器①igital_tQ_Anai%302-2 is used to be converted into two data signals Data3 and 〇ata4 and sent to data lines DL3 and DL4. As for the source driver ι〇2, the most popular channel is 302JVI, and the two fields display data IN (2M-1) and iN2M [converted into the information letter 5 Tiger Data (2M-1) and Data2M ' to transfer to the data line and DL2M . ^ Figure 4 shows a channel example in accordance with an embodiment of the present invention. Channel 400 includes four digit to analog converters 1igital_tQ_Anai%
Converters，DACs) 402_1、402_2、402—3 與 402 4、一第 一切換電路404與一第二切換電路406，並且可更包含第 一運算放大器0P.[與第二運异放大器〇P2、閃鎖器 408_1-408_4 與電壓位準移位器（ievei Shifter) 410—1-410—4。運算放大器0P1與〇p2可以是軌對執運算 放大盗（rail-to-rail operational amplifier)，並且在其它實 施例中，第一與第二運算放大器0P1與〇p2可配置於源 極驅動器102外。至於閂鎖器408—1-408—4與電壓位準移 位器410—1-410_4可配置於第一切換電路4〇4之後，並且位 於數位至類比轉換器402一 1-402—4之前，並且為選擇性的 裝置。 數位至類比轉換器402_1用以將一 n位元之數位碼轉 換成類比彳§號S1 ’其中N為一正整數。數位至類比轉換器 402—2用以將一 K位元之數位碼轉換成類比信號S2，其中 7 201145239 κ為一正整數並且小於N。數位至類比轉換器4〇2_3與數 位至類比轉換器402J具有相同的解析度，用以將:^位 元之數位碼轉換成類比信號S3。數位至類比轉換器4〇2 4 與數位至類比轉換器4〇2_2具有相同的解析度，用以將二 K位元之數位碼轉換成類比信號S4。數位至類比轉換器 402一1與402—2為正極性轉換器（因此標示為PDAC)，並且 所產生的類比信號81與82之電壓係分佈於共用電壓（如第 2圖所示之VCOM)與供應電壓（如第2圖所示之VDD)之間 的一第一電壓範圍。數位至類比轉換器4〇2一3與4〇2 4為 負極性轉換器（因此標示為NDAC)，並且所產生的類比'信號 S3與S4之電壓係分佈於共用電壓（如第2圖所示之vcom) 與接地電壓（如第2圖所示之GND)之間的一第二電壓範 圍。值得注意的是，數位至類比轉換器4〇2一2與4〇2一4被 特別設計為具有解析度低於數位至類比轉換器4〇2j與 4〇2_3(由於K<N)。因此，與傳統的源極驅動器相比，其中 數位至類比轉換器皆具有相同的解析度，源極驅動器】⑽ 可具有較小的尺寸。在一些實施例中，N可為64而κ可為 4 〇 在以下的討論中，為簡化描述，將省略閂鎖器 408J-408一4與電壓位準移位器41〇J_41〇—4的部分。第一 切換電路404可決定如何將第一顯示資料IN1與第二顯示 貧料IN2耦接至數位至類比轉換器4〇2j、4〇2_2、4〇2_3 與402_4之輸入端。第二切換電路4〇6則控制數位至類比 轉換器402_1、402—2、402一3與402_4之輸出與第一運算 放大器OP1以及第二運算放大器〇p2的輸入之間的連接關 201145239 係。第一與第二切換電路404與406由至少一控制信號cs 所控制。第5A至5D圖係顯示由第—與第二切換電路4〇4 與406所控制之不同的連接結果。 第5 A圖係顯示由第一與第二切換電路4〇4與4〇6所提 供之第一連接模式。如圖所示，第一切換電路404將第一 顯示資料之所有位元IN1[0:(N-1)]耦接至數位至類比轉換 器402—1’並且耦接第二顯示資料之κ個最重要位元（m〇st significant bitS)IN2[((N-K):(N-l))]至數位至類比轉換器 • 402一2。第二切換電路406連接類比信號S1至第一運算放 大器OP1，以及連接類比信號S2至第二運算放大器0P2。 第一資料信號Datal於第一運算放大器〇pl的輸出端被產 生，並且被傳送至像素陣列的第一資料線(如第丨圖所示之 DL1)。第二資料信號Data2於第二運算放大器〇p2的輸出 端被產生，並且被傳送至像素陣列的第二資料線(如第i圖 所示之DL2)。正極性電壓被供應至第一與第二資料線DLi 與DL2。在第一連接模式中，數位至類比轉換器4〇2—3與 • 402_4不起作用。 —。 第5B圖係顯示由第一與第二切換電路4〇4與4〇6所提 供之第二連接模式。如圖所示，第一切換電路4〇4耦接第 二顯示資料之所有位元以2[0:〇^1)]至數位至類比轉換器 402—1，並且第二切換電路406傳送類比信號S1至第二運 算放大器OP2用以產生第二資料信號Data2，使得一正極 性電壓可被提供至於如第丨圖所示之第二資料線DL2上。 在第二連接模式中，數位至類比轉換器4〇2_2、4〇2_3、4〇2 4 以及第一運算放大器0P1不起作用。 〜 201145239 第5C圖係顯示由第一與第二切換電路404與406所提 供之第三連接模式。如圖所示，第一切換電路404將第— 顯示資料之所有位元IN1[0:(N_1)]耦接至數位至類比轉換 器402_3’並且耦接第二顯示資料之κ個最重要位元（m〇st significant bits)IN2[((N-K):(N-l))]至數位至類比轉換器 402—4。第二切換電路406連接類比信號S3至第一運算放 大器OP1 ’用以產生第一資料信號Datal，並且連接類比信 號S4至第二運算放大器OP2，用以產生第二資料信號 Data2。負極性電壓被供應至第一與第二資料線DL1與 DL2(參考第1圖），其分別用以傳送資料信號Datal與 Data2。在第三連接模式中，數位至類比轉換器4〇2_1與 402_2不起作用。 第5D圖係顯示由第一與第二切換電路404與406所提 供之第四連接模式。如圖所示，第一切換電路404耦接第 二顯示資料之所有位元IN2[〇:(N-l)]至數位至類比轉換器 402_3，並且第二切換電路4〇6傳送類比信號S3至第二運 鼻放大裔OP2用以產生第二資料"is號Data2 ’使得·一負極 性電壓可被供應至如第！圖所米之第二資料線DL2上。在 第四連接模式中，數位至類比轉換器402_1、402_2、402__4 以及第一運算放大器〇ρι不起作用。 第6A圖係顯示用以控制通痘400之第一與第二切換電 路404與406之至少一控制信璩CS的來源。如圖所示， 影像顯示系統600包含通道4〇〇與控制電路602。控制電 路602根據水平同步信號τρι產生信號ΤΡΓ，以形成至少 一控制信號CS，伴隨著極性位元p〇L·。水平同步信號TP1 201145239 與極性位兀POL係由時序控制 域所公知)所提供。水平同步信號TP1用以區St術領 各列顯示㈣。極性位元pQ π ”像素陣列之 實施例中’控制電路602可内建於 面，在一些實施例中，控制電路的 ^中另一方 括通道4GG)，而非内建於時序 建1源極驅動器（包 電路。 ”、、’序控制裔與源極，驅動器外部之一 根據如第6Α圖所示之於告 第二切換電路406的機制，：弟::換電路_與 時水平同步信號了p 先纣确應用列反轉技術 步信號TP1的第一位70 P0L的功能。根據水平同 掃描像素陣列之可提供-時間區間Trowl用以 顯示出正極性電壓 1 I且由極性位兀POL的狀態可 正極性驅動。被施加於第1像素上，用以執行 第-列並且耗接!如=料，要被第-像素(位於 數位值，顯示資料 Θ所示之:貝料線DL1)顯示之第一 輕接至如第i _ 2包含要被第二像素(位於第-列並且 據水平同步信f :之貝料線D L 2) _示之第二數位值。根 T_2用以掃推像二衝’可提供-時間區間 P〇L的狀態可顯厂、 之第一列，並且由極性位元 上，用以執行負:負極性電壓必須被施加於第二列像素 第三像素（位於第。二’驅動。此時，1 員示資料則包含要被 DL1)顯示之第三〜列並且耦接至如第1 圖所示之資料、線 〜位值，顯示資料收包含要被第四像素 201145239 (位於第二列並且耦接至如第1圖所示之資料線DL2)顯示 之第四數位值。包含如第6A圖所示之極性位元POL與信 號ΤΡΓ的控制信號會對應地被應用於控制通道400的第一 切換電路404與第二切換電路406，並且上述之第一、第 二、第三與第四連接模式（如第5A-5D圖所示）會分別在四 個時間區間Tl-T4(如第6B圖所示）被產生。參考至第6B 圖中所示之資料信號Datal與Data2之波形上的說明文 字，其顯示出：在第一時間區間T1，資料信號Datal的内 容來自於數位至類比轉換器（N-to-1 PDAC) 402_1，而資料 信號Data2的内容來自於數位至類比轉換器（K-to-1 PDAC) 402_2，使得資料信號Datal的電壓位準被充電至第一數位 值（包含於顯示資料IN1)的目標電壓，而此時資料信號 Data2的電壓位準僅被預先充電至第二數位值（包含於顯示 資料IN2)之電壓位準的中間值；在第二時間區間T2，資料 信號Datal不會被改變，而此時資料信號Data2的内容來 自於數位至類比轉換器（N-to-1 PDAC) 402_1，以補償第二 數位值的不足；在第三時間區間T3，資料信號Datal的内 容來自於數位至類比轉換器（N-to-1 NDAC) 402_3，而資料 信號Data2的内容來自於數位至類比轉換器（K-to-1 NDAC) 402_4，使得資料信號Datal的電壓位準被充電至第三數位 值的目標電壓，而此時資料信號Data2的電壓位準僅被預 先充電至第四數位值之電壓位準的中間值；在第四時間區 間T4，資料信號Datal不會被改變，而此時資料信號Data2 的内容來自於數位至類比轉換器（N-to-1 NDAC) 402_3，以 補償第四數位值的不足。 12 201145239 第7A圖係顯示用以控制通道400之第一與第二切換電 路之至少一控制信號CS的另一來源。如圖所示，影像顯 示系統700包含通道400與控制電路702。控制電路702 根據極性位元POL產生信號POL’，以形成至少一控制信 號CS用以控制通道400之第一切換電路404與第二切換 電路406。在一些實施例中，控制電路702可内建於用以 提供水平同步信號TP1與極性位元POL之時序控制器中。 另一方面，在一些實施例中，控制電路702可内建於源極 φ 驅動器（包括通道400)，而非内建於時序控制器中。在另一 些實施例中，控制電路702可為時序控制器與源極驅動器 外部之一電路。值得注意的是，當控制電路702未被内建 於源極驅動器中時，源極驅動器可需要一額外腳位用以接 收信號POL’。 根據如第7A圖所示之控制信號POL’，第7B圖使用波 形圖顯示出控制通道400之第一切換電路404與第二切換 電路406的機制。如圖所示，通道400之第一切換電路404 • 與第二切換電路406係由控制信號POL’所控制，上述第 一、第二、第三與第四連接模式（如第5A-5D圖所示）會分 別在四個時間區間Tl-T4(如第7B圖所示）被產生，用以實 現上述列反轉技術。 總言之，在所述的預先充電程序中（由數位至類比轉換 器（K-to-1 PDAC) 402—2 與(K-to_l NDAC) 402_4 所提供）， 各通道可允許使用解析度較低的數位至類比轉換器。例 如，在傳統的列反轉技術中，為了達到流暢的顯示，服務 兩資料線之一通道通常需要至少四個高解析度的數位至類 13 201145239 比轉換器。然而，在通道400中，流暢的顯示仍然可以達 成，並且僅需要兩個高解析度的數位至類比轉換器，包含 數位至類比轉換器（N-to-1 PDAC) 402_1 與（N-to-1 NDAC)402-3，而其餘兩個數位至類比轉換器可藉由低解析 度之數位至類比轉換器（包含數位至類比轉換器（K-to-1 PDAC) 402_2 與(K-to-1 NDAC)402-4)來完成。因此可大幅 降低源極驅動器的電路尺寸與成本。 此外，由第一切換電路與第二切換電路所建立的連線 也可藉由軟體而非電子電路完成。控制顯示資料、數位至 類比轉換器與運算放大器之間的耦接關係的方法同樣包含 於本發明所涵蓋的範圍。 本發明雖以較佳實施例揭露如上，然其並非用以限定 本發明的範圍，任何熟習此項技藝者，在不脫離本發明之 精神和範圍内，當可做些許的更動與潤飾，因此本發明之 保護範圍當視後附之申請專利範圍所界定者為準。Converters, DACs) 402_1, 402_2, 402-3 and 402 4, a first switching circuit 404 and a second switching circuit 406, and may further include a first operational amplifier OP. [with a second operational amplifier 〇 P2, flash The lockers 408_1-408_4 and the voltage level shifter (ievei Shifter) 410-1-410-4. The operational amplifiers OP1 and 〇p2 may be rail-to-rail operational amplifiers, and in other embodiments, the first and second operational amplifiers OP1 and 〇p2 may be disposed outside of the source driver 102. . As for the latch 408-1 - 408 - 4 and the voltage level shifter 410 - 1-410_4, it can be disposed after the first switching circuit 4 〇 4 and before the digital to analog converter 402 - 1-402 - 4 And is an optional device. The digital to analog converter 402_1 is used to convert an n-bit digital code into an analogy § § S1 ' where N is a positive integer. The digital to analog converter 402-2 is used to convert a K-bit digital code into an analog signal S2, where 7 201145239 κ is a positive integer and less than N. The digital to analog converter 4〇2_3 has the same resolution as the digital to analog converter 402J for converting the digital code of the ^ bit into the analog signal S3. The digital to analog converter 4〇2 4 has the same resolution as the digital to analog converter 4〇2_2 for converting the binary code of the two K bits into the analog signal S4. The digital to analog converters 402-1 and 402-2 are positive polarity converters (hence labeled PDAC), and the resulting analog signals 81 and 82 are distributed across a common voltage (such as VCOM shown in FIG. 2). A first voltage range between the supply voltage (such as VDD shown in Figure 2). The digital to analog converters 4〇2-3 and 4〇24 are negative polarity converters (hence the designation NDAC), and the resulting analog 'signal S3 and S4 voltages are distributed across the common voltage (as shown in Figure 2). A second voltage range between the vcom) and the ground voltage (as shown in Figure 2). It is worth noting that the digital to analog converters 4〇2-2 and 4〇2~4 are specifically designed to have lower resolution than digital to analog converters 4〇2j and 4〇2_3 (due to K<N). Therefore, the digital to analog converter has the same resolution compared to the conventional source driver, and the source driver (10) can have a smaller size. In some embodiments, N may be 64 and κ may be 4 〇 In the following discussion, for simplicity of description, latch 408J-408-4 and voltage level shifter 41〇J_41〇-4 will be omitted. section. The first switching circuit 404 can determine how to couple the first display material IN1 and the second display lean material IN2 to the input terminals of the digital to analog converters 4〇2j, 4〇2_2, 4〇2_3 and 402_4. The second switching circuit 4〇6 controls the connection between the digital to analog converters 402_1, 402-2, 402-3 and 402_4 and the inputs of the first operational amplifier OP1 and the second operational amplifier 〇p2. The first and second switching circuits 404 and 406 are controlled by at least one control signal cs. The 5A to 5D drawings show different connection results controlled by the first and second switching circuits 4〇4 and 406. Fig. 5A shows the first connection mode provided by the first and second switching circuits 4〇4 and 4〇6. As shown, the first switching circuit 404 couples all the bits IN1[0:(N-1) of the first display material to the digits to the analog converter 402-1' and couples the κ of the second display data. The most significant bit (m〇st significant bitS) IN2[((NK):(Nl))] to digital to analog converter • 402-2. The second switching circuit 406 connects the analog signal S1 to the first operational amplifier OP1, and connects the analog signal S2 to the second operational amplifier OP2. The first data signal Data1 is generated at the output of the first operational amplifier 〇pl and is transmitted to the first data line of the pixel array (DL1 as shown in the figure). The second data signal Data2 is generated at the output of the second operational amplifier 〇p2 and is transmitted to the second data line of the pixel array (DL2 as shown in Fig. i). A positive polarity voltage is supplied to the first and second data lines DLi and DL2. In the first connected mode, the digital to analog converters 4〇2—3 and • 402_4 have no effect. —. Fig. 5B shows a second connection mode provided by the first and second switching circuits 4〇4 and 4〇6. As shown, the first switching circuit 4〇4 is coupled to all bits of the second display data to 2[0:〇1]] to the digital to analog converter 402-1, and the second switching circuit 406 transmits the analogy. The signal S1 to the second operational amplifier OP2 are used to generate the second data signal Data2 such that a positive polarity voltage can be supplied to the second data line DL2 as shown in FIG. In the second connection mode, the digital to analog converters 4〇2_2, 4〇2_3, 4〇2 4 and the first operational amplifier OP1 have no effect. ~ 201145239 The 5C diagram shows the third connection mode provided by the first and second switching circuits 404 and 406. As shown, the first switching circuit 404 couples all the bits IN1[0:(N_1)] of the first display data to the digital to analog converter 402_3' and couples the κ most significant bits of the second display data. M〇st significant bits IN2[((NK):(Nl))]) to digital to analog converter 402-4. The second switching circuit 406 is connected to the analog signal S3 to the first operational amplifier OP1' for generating the first data signal Data1, and is connected to the analog signal S4 to the second operational amplifier OP2 for generating the second data signal Data2. The negative polarity voltage is supplied to the first and second data lines DL1 and DL2 (refer to Fig. 1) for transmitting the data signals Data1 and Data2, respectively. In the third connection mode, the digital to analog converters 4〇2_1 and 402_2 have no effect. The 5D diagram shows the fourth connection mode provided by the first and second switching circuits 404 and 406. As shown, the first switching circuit 404 is coupled to all of the bits IN2[〇:(N1)] of the second display data to the digital to analog converter 402_3, and the second switching circuit 4〇6 transmits the analog signal S3 to The second Yun nose magnified OP2 is used to generate the second data "is number Data2 ' so that a negative voltage can be supplied to the first! Figure 2 is the second data line DL2. In the fourth connection mode, the digital to analog converters 402_1, 402_2, 402__4 and the first operational amplifier 〇ρι do not function. Figure 6A shows the source of at least one control signal CS used to control the first and second switching circuits 404 and 406 of the acne 400. As shown, image display system 600 includes a channel 4 and a control circuit 602. The control circuit 602 generates a signal 根据 based on the horizontal synchronizing signal τρι to form at least one control signal CS accompanied by a polarity bit p 〇 L·. The horizontal sync signal TP1 201145239 and the polarity bit 兀 POL are known from the timing control domain. The horizontal synchronizing signal TP1 is used to display the columns in the area St (4). In the embodiment of the polar bit pQ π ” pixel array, the 'control circuit 602 can be built into the surface. In some embodiments, the other side of the control circuit includes the channel 4GG) instead of the built-in timing source 1 source. The driver (package circuit.), the 'sequence control source and the source, one of the external ones of the driver according to the mechanism shown in the sixth diagram to the second switching circuit 406, the brother:: change the circuit _ with the horizontal synchronization signal First, the function of the first bit 70 P0L of the column inversion technique step signal TP1 is applied first. According to the horizontally-scanned pixel array, the -time interval Trowl is used to display the positive polarity voltage 1 I and the polarity bit 兀 POL The state can be driven by the positive polarity. It is applied to the first pixel to perform the first column and is consumed! If the material is to be the first pixel (in the digital value, the data is displayed as shown in the figure: the hopper line DL1) The first light of the display is connected to the second digit value as indicated by the second pixel (located in the first column and according to the horizontal synchronization signal f: the feed line DL 2). The root T_2 is used to Sweeping like two rushes can provide - the time interval P 〇 L state can be displayed in the first column, And by the polarity bit, used to perform negative: the negative polarity voltage must be applied to the third column of pixels, the third pixel (located at the second. 'Driver. At this time, the 1 member data contains the DL1 to be displayed) Three to column and coupled to the data, line ~ bit value as shown in Figure 1, the display data contains the fourth pixel 201145239 (located in the second column and coupled to the data line DL2 as shown in Figure 1 The fourth digit value of the display. The control signal including the polarity bit POL and the signal 所示 as shown in FIG. 6A is correspondingly applied to the first switching circuit 404 and the second switching circuit 406 of the control channel 400, and the above The first, second, third and fourth connection modes (as shown in Figures 5A-5D) are generated in four time intervals Tl-T4 (as shown in Figure 6B), respectively. Reference to Figure 6B The explanatory text on the waveforms of the data signals Data1 and Data2 shown in the figure shows that in the first time interval T1, the content of the data signal Data1 comes from the digital to analog converter (N-to-1 PDAC) 402_1, and The content of the data signal Data2 comes from the digital to analog converter (K-to-1 PDAC) 402_2, so that the voltage level of the data signal Data1 is charged to the target voltage of the first digit value (including the display data IN1), and at this time, the voltage level of the data signal Data2 is only precharged to the second digit value ( The intermediate value of the voltage level included in the display data IN2); in the second time interval T2, the data signal Data1 is not changed, and the content of the data signal Data2 is from the digital to analog converter (N-to-1) PDAC) 402_1 to compensate for the shortage of the second digit value; in the third time interval T3, the content of the data signal Data1 comes from the digit to analog converter (N-to-1 NDAC) 402_3, and the content of the data signal Data2 comes from The digital to analog converter (K-to-1 NDAC) 402_4 causes the voltage level of the data signal Data1 to be charged to the target voltage of the third digit value, and at this time, the voltage level of the data signal Data2 is only precharged to the first The intermediate value of the voltage level of the four-digit value; in the fourth time interval T4, the data signal Data1 is not changed, and the content of the data signal Data2 is from the digital to analog converter (N-to-1 NDAC) 402_3 , To compensate for the lack of the fourth digit value. 12 201145239 Figure 7A shows another source for controlling at least one control signal CS of the first and second switching circuits of channel 400. As shown, image display system 700 includes a channel 400 and a control circuit 702. The control circuit 702 generates a signal POL' based on the polarity bit POL to form at least one control signal CS for controlling the first switching circuit 404 and the second switching circuit 406 of the channel 400. In some embodiments, control circuit 702 can be built into a timing controller for providing horizontal sync signal TP1 and polarity bit POL. On the other hand, in some embodiments, control circuit 702 can be built into the source φ driver (including channel 400) rather than being built into the timing controller. In other embodiments, control circuit 702 can be one of a timing controller and a source external to the source driver. It should be noted that when the control circuit 702 is not built into the source driver, the source driver may require an additional pin to receive the signal POL'. According to the control signal POL' as shown in Fig. 7A, Fig. 7B shows the mechanism of the first switching circuit 404 and the second switching circuit 406 of the control channel 400 using a waveform diagram. As shown, the first switching circuit 404 of the channel 400 and the second switching circuit 406 are controlled by the control signal POL', the first, second, third and fourth connection modes (eg, 5A-5D) Shown) will be generated in four time intervals Tl-T4 (as shown in Figure 7B) to implement the above column inversion technique. In summary, in the pre-charge procedure described (provided by the digital-to-analog converter (K-to-1 PDAC) 402-2 and (K-to_l NDAC) 402_4), each channel allows the resolution to be used. Low digit to analog converter. For example, in the traditional column inversion technique, in order to achieve smooth display, one channel serving two data lines usually requires at least four high-resolution digits to class 13 201145239 ratio converter. However, in channel 400, a smooth display is still achievable, and only two high-resolution digital to analog converters are needed, including digital to analog converters (N-to-1 PDAC) 402_1 and (N-to- 1 NDAC) 402-3, while the remaining two digit-to-analog converters can be used with low-resolution digital to analog converters (including digital to analog converters (K-to-1 PDAC) 402_2 and (K-to- 1 NDAC) 402-4) to complete. Therefore, the circuit size and cost of the source driver can be greatly reduced. In addition, the connection established by the first switching circuit and the second switching circuit can also be completed by software instead of electronic circuit. The method of controlling the coupling relationship between the display data, the digital to analog converter and the operational amplifier is also included in the scope of the present invention. The present invention has been described above with reference to the preferred embodiments thereof, and is not intended to limit the scope of the present invention, and the invention may be modified and modified without departing from the spirit and scope of the invention. The scope of the invention is defined by the scope of the appended claims.
14 201145239 【圖式簡單說明】 第1圖係顯示根據本發明之一實施例所述之影像顯示 系統。 第2圖係顯示電壓極性的概念。 第3圖係顯示根據本發明之一實施例所述之源極驅動 器之方塊圖。 弟4圖係顯示根據本發明之一實施例所述之通道範例。 第5A至5D圖係顯示由第一與第二切換電路所控制之 %：印 AA :由 > 1、14 201145239 [Simple Description of the Drawings] Fig. 1 shows an image display system according to an embodiment of the present invention. Figure 2 shows the concept of voltage polarity. Figure 3 is a block diagram showing a source driver in accordance with an embodiment of the present invention. Figure 4 shows an example of a channel in accordance with an embodiment of the present invention. Figures 5A through 5D show % controlled by the first and second switching circuits: AA: by >
四種不同的連接模式 第6A圖係顯示用以控制通道侧之第一與第二切換^ 路之至少一控制信號CS的來源。 第6B圖係顯示當應用如第6a 控制通道400之第一盥第_ C， 第7A圖㈣田 刀換電路時的信號波形圖。 弟7A圖係顯不用以控制通道仰〇 路之至少-控制信號cs的另—來源。第二切換電 第7B圖係顯示當應用如第7aFour different connection modes Fig. 6A shows the source of at least one control signal CS for controlling the first and second switching paths on the channel side. Fig. 6B is a diagram showing signal waveforms when the first circuit of the 6th control channel 400 is applied, for example, the _C, 7A (4) field-changing circuit. The brother 7A shows that it is not necessary to control the channel at least - the other source of the control signal cs. The second switching power is shown in Figure 7B when the application is like 7a
控制通道400之第—盥筮_ + & 團所不之控制信號CS 乐興弟一切換電路 电塔時的信號波。 主 要元件符號說明】 :〇、_、鳩〜影像顯示系統； 〜源極驅動器； 104〜閘極驅動器； 】〇6〜像素陣列； 3〇2-卜地-2、302-Μ、_〜通道; 15 201145239 402_1、402_2、402 3、402—4、K-to-l NDAC、N-to-l NDAC、K-to-lPDAC、N-to-lPDAC〜數位至類比轉換器； 404〜第一切換電路； 406〜第二切換電路； 408_1、408_2、408—3、408_4〜閂鎖器； 410_1、410_2、410_3、410_4〜電壓位準移位器； 602、702〜控制電路； CS、SI、S2、S3、S4、TP卜 ΤΡΓ〜信號；The control channel 400 is the first - 盥筮 _ + & group does not control the signal CS Le Xingdi a switch circuit circuit tower signal wave. Main component symbol description]: 〇, _, 鸠 ~ image display system; ~ source driver; 104 ~ gate driver; 〇 〜 6 ~ pixel array; 3 〇 2- 卜 - 2, 302 - Μ, _ ~ channel ; 15 201145239 402_1, 402_2, 402 3, 402-4, K-to-l NDAC, N-to-l NDAC, K-to-lPDAC, N-to-lPDAC ~ digital to analog converter; 404 ~ first Switching circuit; 406~second switching circuit; 408_1, 408_2, 408-3, 408_4~latch; 410_1, 410_2, 410_3, 410_4~ voltage level shifter; 602, 702~ control circuit; CS, SI, S2, S3, S4, TP ΤΡΓ~ signal;
Datal、Data2、Data3、Data4、Data(2M-l)、Data2M〜 貧料信號， DU、DL2、DL3、DL2M〜資料線； GND、VCOM、VDD〜電壓； INI 、 IN1[0:(N-1)] 、 IN2 、 IN2[0:(N-1)]、 IN2[((N-K):(N_1))]、IN3、IN4、IN(2M-1)、IN2M〜顯示資 料； OP1、OP2〜運算放大器； POL、POL’〜極性位元； ΤΙ、T2、T3、T4、Trowl、Trow2〜時間區間。 16Datal, Data2, Data3, Data4, Data(2M-1), Data2M~ poor material signal, DU, DL2, DL3, DL2M~ data line; GND, VCOM, VDD~ voltage; INI, IN1[0:(N-1 )], IN2, IN2[0:(N-1)], IN2[((NK):(N_1))], IN3, IN4, IN(2M-1), IN2M~ display data; OP1, OP2~ Amplifier; POL, POL'~ polar bit; ΤΙ, T2, T3, T4, Trowl, Trow2~ time interval. 16