201145006 六、發明說明： 【發明所屬之技術領域】 本發明揭露一種半導體電路’特別是一種於功率區域 間之隔離的系統和方法。 【先前技術】201145006 VI. Description of the Invention: [Technical Field] The present invention discloses a semiconductor circuit', particularly a system and method for isolation between power regions. [Prior Art]
在可攜式電子設備如手機、MP3隨身聽和數位相機内’ 維持低功率的消耗變得愈來愈有挑戰性時，正由於這些設 備的功能性愈來愈高，這些設備的處理功率和速度的增 加，經常需要增加所對應之電路設備的數量，且增加電路 狄備彳呆作時的時脈頻率，增加電路消耗之總功率。 目前已有少數技術用來管理積體電路（ICs)的功率# 耗。根據積體電路的功率需求，多重供應電壓（MSV)已被拜 來驅動其不同的區域。例如，執行計算區域的積體電路， ^專用於輸人-輸出（I/Q)界面區域的積體電路，比較需要 == 應二壓Λ驅動。亦可㈣操作模式，使用議 == 操作時，可能比讀出操作時，需要在彰 應電壓下操作。同時，時脈開控（α)可用來使-布 ::信號失效，以使積體電路之未使用區域失效。, 而不I &相機Ba片组使數據壓縮電路的時脈信號失效， 的區域失吟。而奸士低了個負責影像壓縮之晶片紐 k輯轉換的消除，内部節點電容的充 電，亦可使得動態的功率消耗可 以降低。 201145006 〜目㈣小設備的幾何形狀和㉟加所對應的電路密度， 靜態 漏電流已成為功率消耗的—個更重要因素因 一個僅以時脈閘控關閉的電路或邏輯區塊，由於靜離 漏 電流之故，@更可能潛在消訪觀的功率。一個靜^漏 電流問題的解決方法是’使未使用之區塊的電源^庳失 效。關閉電路之電源供應的一個困難，是維持一個電ς供 應已失效的積體電路區域，與一個電源供應有效的積體電 路區域之間，於邊界上的界面邏輯。橋接此種邊界的邏輯 攀可能有-些困難，包括由於浮動節點之不確定的狀態、於 兩個功率區域之間，界面元件内的洩漏電流、和在失效區 塊内’缺乏邏輯狀態之保存。 故而，未來所需的是，於功率區域間的連結之 率系統和方法。 【發明内容】 在一個具體實施例中，揭露一種功率區域之隔離界 面。該隔離界面有一個具有一耦合至第一功率區域和一記 憶體元件之單一輸入的電位轉換器。該記憶體元件有一耦 合至一電位轉換器輸出的單一輸入，一耦合至第二功率區 域的輸出，和一持留有效輸入（h〇ld enable input)，其 中當持留有效輸入顯示時，記憶體元件呈持留（hold) 一 輸入狀態（input state)。 在另一個具體實施例中，揭露一半導體電路。該導體 電路有一第一個功率區域，一第二個功率區域，和一功率 201145006 區域界面。該功率區域界面有一個電位轉換器，包括一個 輕合至第一功率區域的輸入，和一具有耦合至一電位轉換 器輸出的一個輸入的栓鎖（latch)，一個耦合至第二功率 區域的輸出’和一個持留輸入（h〇id input) ° 在更進一步的具體實施例中，揭露一種在第一功率區 域與第二功率區域間耦合之界面進行操作的方法。該方法 包括將界面放入一個睡眠模式，且將界面轉移至該睡眠模 式之外。而將界面放入此種睡眠模式，包括顯示一耦合至 第二功率區域所輪出的栓鎖之持留信號（hold signal)， 且在顯示持留信號之後，顯示在第一功率區域與栓鎖間所 搞合之電位轉換器的失效信號。將界面轉移至此種睡眠模 式之外’包括除去失效信號，且在除去失效信號之後，除 去持留信號。 以上所述已相當廣泛地略述本發明的特徵。以下將描 述本發明之其他特徵，此將形成本發明之申請專利範圍的 主題。必須感謝的是，一般習知技術所揭 露的概念和特殊While it is becoming more and more challenging to maintain low power consumption in portable electronic devices such as cell phones, MP3 players and digital cameras, the power of these devices is increasing due to the increasing functionality of these devices. As the speed increases, it is often necessary to increase the number of corresponding circuit devices, and increase the clock frequency when the circuit is ready to be used, increasing the total power consumed by the circuit. There are a handful of techniques currently used to manage the power consumption of integrated circuits (ICs). Depending on the power requirements of the integrated circuit, multiple supply voltages (MSV) have been driven to drive their different regions. For example, the integrated circuit of the calculation area is executed, and the integrated circuit dedicated to the input-output (I/Q) interface area is required to be compared == should be driven by two voltages. It can also be used in (4) operating mode. When using the == operation, it may be required to operate at an appropriate voltage than when reading the operation. At the same time, the clock start (α) can be used to disable the -cloth :: signal to disable the unused area of the integrated circuit. , and the I & camera's Ba chipset disables the clock signal of the data compression circuit, and the area is lost. The traitor has lowered the elimination of the chip-to-chip conversion for image compression, and the charging of the internal node capacitors can also reduce the dynamic power consumption. 201145006 ~ (4) small device geometry and 35 plus corresponding circuit density, static leakage current has become a power consumption - a more important factor due to a circuit or logic block only closed by clock gating, due to static For leakage currents, @ is more likely to potentially consume the power of the view. The solution to a static leakage current problem is to disable the power supply of unused blocks. One difficulty in powering down the circuit is to maintain an interface circuit area where the power supply has failed, and an interface logic on the boundary between a power supply circuit area that is effective for power supply. The logic of bridging such boundaries may have some difficulties, including due to the uncertain state of the floating nodes, leakage currents between the two power regions, interface elements, and the lack of logic states in the failed blocks. . Therefore, what is needed in the future is the system and method of linking between power regions. SUMMARY OF THE INVENTION In one embodiment, an isolation interface for a power region is disclosed. The isolation interface has a potential converter having a single input coupled to the first power region and a memory component. The memory component has a single input coupled to a potential converter output, an output coupled to the second power region, and a hold valid input (h〇ld enable input), wherein the memory component is retained while the valid input display is held Hold an input state. In another embodiment, a semiconductor circuit is disclosed. The conductor circuit has a first power region, a second power region, and a power 201145006 region interface. The power zone interface has a potential converter including an input coupled to the first power region, and a latch having an input coupled to a potential converter output, a coupling to the second power region Output 'and one hold input'. In a still further embodiment, a method of operating at an interface coupled between a first power region and a second power region is disclosed. The method includes placing the interface into a sleep mode and transferring the interface out of the sleep mode. The interface is placed in the sleep mode, including displaying a hold signal coupled to the latch of the second power region, and after displaying the hold signal, displayed between the first power region and the latch The failure signal of the potential converter that is engaged. Transferring the interface out of this sleep mode' includes removing the fail signal and removing the hold signal after removing the fail signal. The features of the present invention have been described quite broadly above. Other features of the invention will be described hereinafter which will form the subject of the scope of the invention as claimed. I must be grateful for the concepts and specialities exposed by the general know-how.
的具體實施例，可能可作為—個修改或設計其它結構或程 序的基礎’藉以執行本發明之相同目的。亦需以一般習知 技術來實現，且其它未脫離本發明所揭示之精神和範圍的 等效建構’均應包含在下述之申請專利範圍内。故而，關 於本發明之優點與精神可以藉由以下發明詳述及所附圖式 得到進一步的瞭解。 【實施方式】 201145006 “以下。夢細时論具體實施例的製作和使用。豸而，必須 =本發明提供許多制發明的概念，可能被收錄至各種 Α的上、下文内。所討論之特殊具體實施例僅是製作和 <用本發明之特定方法的說明，但不可限定本發明的範圍。 本發明將以一個特定上、下文内的具體實施例進行說 明，即在一個積體電路上一個連結和隔離功率區域的界面 電路。本發明的具體實施例亦可用於其它使用多重電源供 應和/或多重供應區的電路和系統。 第1圖顯示-個功率區域界面電路1〇〇的先前技術。 界面電路100包括電位轉換器1〇4和隔離室刷。電位 =器1〇4將邏輯信號ΙΝ，由第一功率區域1〇2轉換成信號 、中參考第二功率區域1〇8。第一功率區域ι〇2内的邏 輯參考低電壓供應佩，而第二功率區域1〇8内的邏輯是 參考高電壓供應VDDH。 首先，當使用功率閘控（PG)技術來關閉功率區域1〇2 時，低電壓供應VDDL通常由第一功率區域所分開，係使 VDDL接地，或拆開或打開VDDL供應線的線路以達成^當 第-功率區域102失效時’功率區域1〇2内的内部節點可 獲得一個不確定的狀態。因此，隔離室1〇6會有一個有效 的（ENABLE)輸入防止電位轉換器1〇4在輸出z上以一個 不確定值傳過第二功率區域1〇8。 先前技術的功率區域界面1〇〇技術至少有兩個缺點。 首先’當第-功率區域102失效時，第一功率區域1〇2内 的内部狀態會喪失。其次，電位轉換器1〇4的輸出階段内， 201145006 至少會發生靜態洩漏。因即使當第一個功率區域丨〇2失效 時，而電壓供應VDDH會繼續施加到電位轉換器1〇4上，而 發生洩漏。靜態洩漏電流的發生，是由於VDDH施加到電位 轉換器104内部元件的結果。若電位轉換器1〇4内部的節 點是浮動的，則此種靜態洩漏亦可能嚴重地惡化。 第2圖顯示一個根據本發明具體實施例的功率區域隔 離界面系統2 0 0。該系統2 0 0具有功率區域隔離界面2丨4， 在低電壓區域202和高電壓區域204之間進行連結。在一 典型的具體實施例中，低電壓區域用於邏輯電路，且有一 個約0. 9V和約1. 2V之間的額定電源電壓。依照系統的其 餘部份，是否需要低電壓區域202内的電路，可以使低電 壓區域202生效或失效。另一方面，高電壓區域204有一 個約1.0V和約1.2V之間的額定電源電壓。在本發明的一 些具體實施例内，這些額定電源電壓的範圍是可以設定 的。:¾尚電壓區域204是一個I/O區塊，則高電壓區域2〇4 通常會維持有效，而低電壓區域202是失效的。需注意， 功率區域202和204分別指定為一低電壓區域和一高電壓 區域，只是一個舉例。在本發明之其它具體實施例中，區 域202和204可在相同的電源電壓下操作，或區域M2可 在比區域204較高的電源電壓下操作。 功率區域隔離界面214有電位轉換電路206和栓鎖 208。栓鎖208最好是根據已知之傳統電路設計技術所設計 之一個透明的栓鎖。在第2圖甲，具體實施例内，栓鎖2〇8 有輸入彳&號D、輸出信號Q和活躍之低栓鎖輸入latchB。 201145006 當輸入LATCHB變高時，在D的輸入被傳送到在Q的輸出。 然而，當輸入LATCHB變低時，栓鎖208維持在Q的輸出， 直到LATCHB再變高為止。在本發明之其它具體實施例中， 栓鎖2 0 8之輸入和輸出的極性可能不同。例如，當輸入 LATCHB高時，可能被設定到栓鎖上輸出，或信號D和Q可 能被設定為相當的低。此外，栓鎖208可被儲存狀態的其 它元件，如觸發器或其它記憶體元件來執行。 電位轉換器206被設定成轉換輸入信號1(參考 • VDDL)，和邏輯輸出信號Z(參考VDDH)。當EN1為低時，有 效的信號EN將電位轉換器206的輸出定成常數（邏輯的高 位）。當EN為高時，電位轉換器206變成透明（輸入I被傳 至輸出Z)。在本發明之其它具體實施例中，I、Z和EN的 極性可能與第2圖内顯示之具體實施例不同。 基於輸入SLEEPB，功率控制邏輯210產生有效的信號 EN1和EN2，其可控制功率區域隔離界面214的操作。當 SLEEPB變低時，功率區域隔離界面214儲存最後的狀態， * 並使電位轉換器206失效，最好是將輸出Zo變成參考值， 或如VDDL的供應電壓。或者，可假設Zo是一個高阻抗的 狀態。在本發明之較佳具體實施例中，信號Zo在使電位轉 換器206失效（和輸出定住）之前，會被栓鎖208鎖上。該 方法可根據信號1〇來儲存信號Zo之有效狀態，而低電壓 區域202可能是失效的。當栓鎖208已被鎖上時，電位轉 換器206可能是失效的和/或被鎖定住。或者，如有必要， Zo節點能浮動，而不會造成相當大的洩漏電流。 201145006 第3圖係根據一較佳具體實施例來顯示信號eNI、 SLEEPB和EN2之間的定時關係。當信號SLEEPB變低時， 信號EN2在延遲d2之後變低，且信號EN1在延遲dl之後 變低’其中dl比d2還長。藉由dl比d2還長，而在電位 轉換器206的輸出z〇變成無效之前，栓鎖208的值（第2 圖）會被維持。當EN1變低時，電位轉換器206(第2圖）變 成無效（即輸出定成一定的電壓），因此在Z〇的輸出狀態， 可能與電位轉換器206變成無效前的值不同。 信號VDDL—ACTIVE可指出，低電壓區域202是否成為 活躍的。在本發明之較佳具體實施例中，在栓鎖208的狀 態’經由信號EN2所維持後，至少低電壓區域202是失效 的。使用一個PM0S頂部開關（PM0S)打開電源網，或一個 NM0S底部開關打開接地網，使低電壓區域202失效，然而， 其它功率區域關閉技術亦可用於其它的具體實施例中。經 由、’隹持检鎖在關閉低電壓功率區域之前的狀態，可以可靠 地維持低電壓區域輸出1〇的狀態。在其它的具體實施例 中’可在相對於功率區域界面電路214之啟動的其它時 間’關閉低電壓區域202。 另一方面’當低電壓區域被通電時，信號SLEEpB會變 高，且信號EN1在SLEEPB變高之後的時間延 變高， 二使電位轉換謂通電。同樣地，信號1二 的征、屈 …、甲dl最好比d2有較長 的延遲。信號VDDL_ACTIVE最好右产吨 诱明★此 在^竣EN2，使栓鎖208 透月之月ij啟動低電壓區域202，以槪A + -免在拴鎖208的Qo輸 201145006 出上失靈。 第4圖根據在本發明之另一個較佳具體實施例來顯示 功率界面和隔離系統400。就像第2圖内的具體實施例， 系統400具有在低電壓區域401與高電壓區域204之間耦 合的電位轉換器206，和检鎖208的功率界面和隔離電路 214。在目前的具體實施例中，在低電壓區域4〇1内，pm〇s 電晶體ΜΡ0至MPn的電路與低電壓電源VDDL之間輕合。電 晶體ΜΡ0至MPn的栅門被耦合至活躍的高信號DISABLE， 經由逆變器422被耦合至VDDL_ACTIVE。在本發明的其它 具體實施例中，除了使用PMOS切換ΜΡ0至MPn之外，、^ 可使用其它的電路技術，如麵〇s電晶體。 ’' 功率控制邏輯420具有：在輸入信號乩阢卯與 406和408之間所耦合的延遲元件4〇2和延遲元件 延遲兀件402有-個dl❾時間延遲，而延遲元件* 一 個d2的時間延遲，其中dl的時間延遲最 f大。在本發明之較佳具體實謝，時間延遲:= 1至2個時脈週期之間，且時間延遲 遲/= 發明之其它具體二= = = =延遲。在本 好以-台有限狀態機器來產二時間=遲在: ^ 、體貫轭例中，可使用其它的延遲吝斗# V逆步的柄門延遲、逆變器鏈、延遲線等。 被耦合,I:t信號SLEEPB與多工機侧的選擇輪入間 5月的具體實施例中，功率控制邏輯 201145006 行第3圖的波形圖。或者，可使用其它功率控制邏輯的控 制，例如，可使用同步邏輯而不是非同步邏輯來產生ENl 和EN2信號，或其它習知的邏輯設計技術。 第5圖根據本發明之一個具體實施例來顯示電位轉換 器500。電位轉換器5〇〇具有一個在VDDH與G1節點間， 與在VDDL與G1節點間耦合的電位轉換器電路。節點G1經 由NMOS切換電晶體mn 1 〇，而與地面輕合。同樣的，輸出 節點z被耦合。當EN為高時，電晶體MN1〇將節點G1耦合 至地面，因此，可使電位轉換器的操作有效。然而，當EN 為低時，PM0S切換電晶體MP18 ’將輸出z耦合至VDDH， 並被打開，因此將輸出z拉高，且破保輸出Z獲得已知的 狀態，而使電位轉換器500失效。在本較佳的具體實施例 中，信號EN係參考VDDH。 電位轉換器500亦有一對由MP15和MP16製成之十字 形耦合的PMOS電晶體。MP15的汲極被耦合至NMOS，輸入 電晶體MN11 ’且MP16的汲極被耦合至NMOS電晶體MN13。 邏輯輸入信號I被耦合至輸入電晶體MN11的栅門，而一個 逆變版的邏輯輸入信號I，係透過一個由電晶體MN12和 MP20所參考組成之逆變器的VDDL，施加至電晶體MN13。 該逆變器可參考至低電壓VDDL。因此，如第5圖所示MP20 的源頭’被接到其沒極。而在MP15和MN11的汲·極，一個 由電晶體MN14和MP17所組成之逆變器，可輸出Z緩衝邏 輯信號。當MN10關閉時，在電位轉換器5〇〇之輸出階段内 的電晶體MN14，可獲得一個高阻抗的狀態，因此降低洩漏。 201145006 ==具體實施例中，可使用其它的習知電位轉 換電位電路來執行電位轉換器500。 ^上所述僅為本發明之較佳實施例而已 範圍;凡其它未脫離本發明= ，谢如述之申請 【圖式簡單說明】 為了對本發明及其優點有更完整的理解，可參考以下 的說明及所附的圖式，其中包括： 第1圖顯示習知技術之功率區域界面； 第2圖員示功率區域隔離界面電路之具體實施例圖； 第3圖‘，’、員示功率區域隔離界面電路之具體實施例的定 時圖； 第4圖顯示根據更進一步之具體實施例的功率區域隔 離界面電路圖；以及 第5圖顯不電位轉換器電路之具體實施例圖。 【主要元件符號說明】 100功率區域界面電路 102第一功率區域 104電位轉換器 106隔離室 108第二功率區域 201145006 200功率區域隔離界面系統 2 0 2低電壓區域 204尚電壓區域 206電位轉換電路 208栓鎖 210功率控制邏輯 214功率區域隔離界面 400隔離系統 # 401低電壓區域 402延遲元件 404延遲元件 406多工機 408多工機 420功率控制邏輯 422逆變器 500電位轉換器The specific embodiments of the invention may be implemented as a basis for modifying or designing other structures or procedures. It is also to be understood that the invention is to be construed as being limited by the scope of the invention. Therefore, the advantages and spirit of the present invention can be further understood from the following detailed description of the invention and the accompanying drawings. [Embodiment] 201145006 "The following is a brief description of the production and use of specific embodiments. However, the present invention provides many concepts of invention, and may be included in various sputums. The specific embodiments are merely illustrative of the invention and the specific method of the invention, but are not intended to limit the scope of the invention. The invention will be described in a specific embodiment, hereinafter, on an integrated circuit. An interface circuit that interconnects and isolates power regions. Embodiments of the invention may also be used in other circuits and systems that use multiple power supplies and/or multiple supply regions. Figure 1 shows a previous power region interface circuit 1 The interface circuit 100 includes a potential converter 1〇4 and an isolation chamber brush. The potential=device 1〇4 converts the logic signal from the first power region 1〇2 into a signal, and the reference second power region 1〇8. The logic in the first power region ι2 is referenced to the low voltage supply, and the logic in the second power region 〇8 is the reference high voltage supply VDDH. First, when the power gate is used When the control (PG) technique is used to turn off the power region 1〇2, the low voltage supply VDDL is usually separated by the first power region, grounding VDDL, or disassembling or opening the line of the VDDL supply line to achieve the first power region. When the 102 fails, the internal node in the power region 1〇2 can obtain an indeterminate state. Therefore, the isolation chamber 1〇6 has an effective (ENABLE) input to prevent the potential converter 1〇4 from being outputted on the output z. The uncertainty value passes through the second power region 1〇8. The prior art power region interface 1〇〇 technique has at least two disadvantages. First, when the first power region 102 fails, the interior of the first power region 1〇2 The state will be lost. Secondly, at the output stage of the potential converter 1〇4, at least a static leakage will occur at 201145006. Even when the first power region 丨〇2 fails, the voltage supply VDDH will continue to be applied to the potential converter 1 Leakage occurs on 〇 4. The occurrence of static leakage current is due to the application of VDDH to the internal components of the potential converter 104. If the node inside the potential converter 1〇4 is floating, this static leakage It is also possible to deteriorate severely. Figure 2 shows a power zone isolation interface system 2000 according to an embodiment of the invention. The system 2000 has a power zone isolation interface 2丨4, in the low voltage zone 202 and the high voltage zone. Between the 204, a low voltage region is used for the logic circuit, and has a rated power supply voltage between about 0.9 V and about 1.2 V. According to the rest of the system, The circuitry within the low voltage region 202 is required to enable or disable the low voltage region 202. On the other hand, the high voltage region 204 has a nominal supply voltage between about 1.0 V and about 1.2 V. Some implementations of the invention In the example, the range of these rated supply voltages can be set. The 3⁄4 voltage region 204 is an I/O block, and the high voltage region 2〇4 will generally remain active while the low voltage region 202 is disabled. It should be noted that the power regions 202 and 204 are designated as a low voltage region and a high voltage region, respectively, just to be an example. In other embodiments of the invention, regions 202 and 204 may operate at the same supply voltage, or region M2 may operate at a higher supply voltage than region 204. The power zone isolation interface 214 has a potential conversion circuit 206 and a latch 208. The latch 208 is preferably a transparent latch designed in accordance with known conventional circuit design techniques. In Figure 2, in the specific embodiment, the latch 2〇8 has an input 彳&#, an output signal Q, and an active low-lock input latchB. 201145006 When the input LATCHB goes high, the input at D is transferred to the output at Q. However, when input LATCHB goes low, latch 208 remains at the output of Q until LATCHB goes high again. In other embodiments of the invention, the polarity of the inputs and outputs of the latch 2 0 8 may be different. For example, when the input LATCHB is high, it may be set to the latch output, or the signals D and Q may be set to be quite low. In addition, latch 208 can be implemented by other components of the stored state, such as flip flops or other memory components. The potential converter 206 is set to convert the input signal 1 (reference • VDDL) and the logic output signal Z (reference VDDH). When EN1 is low, the active signal EN sets the output of the potential converter 206 to a constant (logic high). When EN is high, the potential converter 206 becomes transparent (input I is passed to output Z). In other embodiments of the invention, the polarities of I, Z and EN may differ from the specific embodiment shown in Figure 2. Based on the input SLEEPB, the power control logic 210 generates valid signals EN1 and EN2 that control the operation of the power zone isolation interface 214. When SLEEPB goes low, power zone isolation interface 214 stores the last state, * and disables potential converter 206, preferably by turning output Zo into a reference value, or a supply voltage such as VDDL. Alternatively, assume that Zo is a high impedance state. In a preferred embodiment of the invention, signal Zo is latched by latch 208 before failure of potential converter 206 (and output assertion). The method can store the active state of signal Zo based on signal 1 ,, while low voltage region 202 may be inactive. When the latch 208 has been locked, the potential converter 206 may be disabled and/or locked. Or, if necessary, the Zo node can float without causing considerable leakage current. 201145006 Figure 3 shows the timing relationship between signals eNI, SLEEPB and EN2 in accordance with a preferred embodiment. When the signal SLEEPB goes low, the signal EN2 goes low after the delay d2, and the signal EN1 goes low after the delay dl' where d1 is longer than d2. By the fact that dl is longer than d2, the value of latch 208 (Fig. 2) is maintained until the output z〇 of potentiometer 206 becomes inactive. When EN1 goes low, the potential converter 206 (Fig. 2) becomes inactive (i.e., the output is set to a constant voltage), so the output state at Z〇 may be different from the value before the potential converter 206 becomes inactive. Signal VDDL_ACTIVE can indicate whether low voltage region 202 is active. In a preferred embodiment of the invention, at least the low voltage region 202 is disabled after the state of the latch 208 is maintained via the signal EN2. The power grid is turned on using a PM0S top switch (PM0S), or an NMOS bottom switch opens the ground grid to disable the low voltage region 202. However, other power region turn-off techniques can be used in other embodiments. The state in which the low voltage region is output 1 可以 can be reliably maintained by the state of the 'locked lock' before the low voltage power region is turned off. In other embodiments, the low voltage region 202 can be turned off at other times relative to the activation of the power region interface circuit 214. On the other hand, when the low voltage region is energized, the signal SLEEpB goes high, and the signal EN1 has a high delay after SLEEPB goes high, and the potential transition is energized. Similarly, the sign of the signal 1 and the sign of the dl are preferably delayed by a longer delay than d2. The signal VDDL_ACTIVE is best to produce the right ton. ★ In EN2, let the latch 208 traverse the month of the moon ij to start the low voltage area 202, so that 槪A + - avoid the Qo loss of the 拴 208. Figure 4 shows a power interface and isolation system 400 in accordance with another preferred embodiment of the present invention. As with the specific embodiment of FIG. 2, system 400 has a potential converter 206 coupled between low voltage region 401 and high voltage region 204, and a power interface and isolation circuit 214 for lock 208. In the present embodiment, in the low voltage region 4〇1, the circuit of pm〇s transistors ΜΡ0 to MPn is lightly coupled with the low voltage power supply VDDL. The gates of transistors ΜΡ0 to MPn are coupled to the active high signal DISABLE, which is coupled to VDDL_ACTIVE via inverter 422. In other embodiments of the invention, in addition to using PMOS switching ΜΡ0 to MPn, other circuit techniques, such as a 〇s transistor, may be used. The power control logic 420 has a delay element 4〇2 coupled between the input signal 乩阢卯 and 406 and 408 and a delay element delay element 402 having a dl❾ time delay, and a delay element* a d2 time. Delay, where the time delay of dl is the most f. In the preferred embodiment of the invention, the time delay is: = between 1 and 2 clock cycles, and the time delay is delayed / = the other specific two of the invention = = = = delay. In the case of the finite state machine, the second time = late: ^, the body yoke example, other delay bucket #V reverse step handle delay, inverter chain, delay line, etc. can be used. In the specific embodiment, which is coupled, I:t signal SLEEPB and the selection round of the multiplexer side, power control logic 201145006 is the waveform diagram of Figure 3. Alternatively, control of other power control logic can be used, for example, synchronous logic rather than asynchronous logic can be used to generate ENl and EN2 signals, or other conventional logic design techniques. Figure 5 shows a potential converter 500 in accordance with an embodiment of the present invention. The potential converter 5A has a potential converter circuit coupled between the VDDH and G1 nodes and between the VDDL and G1 nodes. The node G1 switches the transistor mn 1 经 via the NMOS and is lightly coupled to the ground. Similarly, the output node z is coupled. When EN is high, the transistor MN1 耦合 couples the node G1 to the ground, so that the operation of the potential converter can be made effective. However, when EN is low, the PM0S switching transistor MP18' couples the output z to VDDH and is turned on, thus pulling the output z high, and the guaranteed output Z obtains a known state, causing the potential converter 500 to fail. . In the preferred embodiment, signal EN is referenced to VDDH. The potential converter 500 also has a pair of cross-coupled PMOS transistors made of MP15 and MP16. The drain of MP15 is coupled to the NMOS, input transistor MN11' and the drain of MP16 is coupled to NMOS transistor MN13. The logic input signal I is coupled to the gate of the input transistor MN11, and an inverted version of the logic input signal I is applied to the transistor MN13 through a VDDL of an inverter composed of transistors MN12 and MP20. . The inverter can be referenced to a low voltage VDDL. Therefore, as shown in Fig. 5, the source ' of the MP20 is connected to its pole. In the MP15 and MN11 poles, an inverter consisting of transistors MN14 and MP17 can output a Z-buffered logic signal. When the MN 10 is turned off, the transistor MN14 in the output stage of the potential converter 5 可获得 can obtain a high impedance state, thus reducing leakage. 201145006 == In a specific embodiment, the potential converter 500 can be implemented using other conventional potential conversion potential circuits. The above description is only for the preferred embodiment of the present invention; any other application without departing from the invention =, Xie Rutu [Simplified Description of the Drawings] For a more complete understanding of the present invention and its advantages, reference is made to the following description. And the accompanying drawings, including: Figure 1 shows a power zone interface of a conventional technique; Figure 2 shows a specific embodiment of a power zone isolation interface circuit; Figure 3, ', ', power zone isolation A timing diagram of a particular embodiment of the interface circuit; Figure 4 shows a power area isolation interface circuit diagram in accordance with a still further embodiment; and a fifth embodiment of a potential conversion converter circuit. [Main component symbol description] 100 power region interface circuit 102 first power region 104 potential converter 106 isolation chamber 108 second power region 201145006 200 power region isolation interface system 2 0 2 low voltage region 204 voltage region 206 potential conversion circuit 208 Latch lock 210 power control logic 214 power zone isolation interface 400 isolation system # 401 low voltage region 402 delay component 404 delay component 406 multiplexer 408 multiplexer 420 power control logic 422 inverter 500 potential converter