TW201142796A - Liquid crystal display - Google Patents

Abstract

A liquid crystal display includes a source driver for providing plural data signals, a gate driver for providing plural gate signals according to a high-level gate signal modulation voltage, a pixel array unit for illustrating images according to the data signals and the gate signals, and a gate pulse modulation unit. The gate driver is further utilized for performing a power-off residual image decay operation on the pixel array unit according to a reset signal. The gate pulse modulation unit is employed to provide the high-level gate signal modulation voltage for performing a waveform shaping operation on the gate signals. The waveform shaping operation has a voltage clamping function controlled by the reset signal. The voltage clamping function is disabled during a predetermined interval after powering the liquid crystal display.

Description

201142796 VI. Description of the Invention: [Technical Field] The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device which can avoid the occurrence of noise in the boot surface. [Prior Art] Lu Liquid Crystal Display (LCD) has the advantages of slimness, power saving and low radiation, so it has been widely used in computer screens, mobile phones, personal digital assistants (PDAs), flat-panel TVs. And other electronic products such as communication/entertainment equipment. The working principle of the liquid crystal display device is to change the arrangement state of the liquid crystal molecules in the liquid crystal layer by changing the voltage difference between the liquid crystal layers, thereby changing the light transmittance of the liquid crystal layer, and then matching the light source provided by the backlight module to display an image. The figure is a schematic view of a conventional liquid crystal display device. As shown in FIG. 1, the liquid crystal display device 1A includes a pixel array unit 1 having a plurality of halogen PXs, a source driver 1〇4, a gate driver, and a gate pulse modulation (GatePulseModulation). Unit (10). The source driver 1〇4 is used to provide a plurality of data signals to the pixel array unit. The inter-pole driver gamma is used to provide a complex gate signal to the pixel array unit 1 根据 according to the high-level gate signal modulation voltage VGHM and the low-level polarity signal reference voltage VGL, and the pixel array unit is Display images based on complex data signals and complex gate signals. The polarity driver H)6 can also perform the shutdown afterimage attenuation operation on the pixel array unit excitation according to the reset signal X0N. • The 12G side of the brewing pulse channel unit provides the word _ _ _ voltage 5 201142796 VGHM. The gate pulse modulation unit 120 includes an inverter 14A, a first transistor 13A, a second transistor 135, a resistor Rx, and a diode 125. Inverter 140, first electric

The crystal 130, the second transistor 135 and the resistor Rx are used to pull the high-level gate signal modulation voltage VGHM from the high-level gate signal reference voltage VGH according to the chamfer control signal VFLK, thereby performing the gate signal. The waveform chamfering operation, the diode 125 has a voltage clamping function for the waveform chamfering operation according to the clamping voltage Vdamp. In the operation of the liquid crystal display device ίο, the clamp voltage Vdamp can be quickly raised to the input voltage level and fed to the gate driver 106 via the diode 125 during a predetermined period of time after the power-on, but at this time, the low level The gate signal reference voltage VGL has not yet established a working level, so the gate driver 106 is unable to perform normal logic operation, thus generating a complex noise-like gate signal. Moreover, since the reset signal at this time can cause the driver to simultaneously output all the gate signals to the pixel array unit, that is, the plurality of types of noise generated by the driver 106 during the predetermined period of time after the power-on. The _ signal will be fed into the pixel array unit 1〇〇, which will cause the noise of the boot screen. In other words, the noise phenomenon is caused by the enable of the clamp during the predetermined time period. SUMMARY OF THE INVENTION According to the present invention, a liquid crystal display device capable of avoiding occurrence of noise in a boot surface includes a pixel array unit, a device, and a gate __(4). The book is her coffee and the gate is driven. Miscellaneous coffee __==== line image display rights and tenderness (four). 201142796

The column 7L is used to adjust the voltage according to the high-level gate signal to provide the complex signal required for the single-line image display operation of the pixel array. The open-pole pulse-modulation unit is electrically connected to the gate driver. The driver is used to provide the threshold voltage modulation voltage, and the gate pulse modulation unit has a voltage clamp controlled by the reset signal. In the operation of the liquid crystal display device, after the liquid crystal display device is turned on for a predetermined period of time, the reset signal is reset to the first array to disable the voltage clamping function, and after the financial period, the reset signal is switched to be different; - The second state of the state 'According to the enable voltage clamping function. According to an embodiment of the present invention, a liquid crystal display device capable of avoiding noise generated on a startup screen, including a source driver, a gate driver, a pixel array unit, and a gate pulse modulation unit. The source driver is used to provide a complex data signal. The gate driver is used to modulate the voltage according to the high level gate signal to provide a plurality of gate signals. The 昼素_ unit is electrically connected to the drive _ _ drive wire, which is used to give the seam according to the plural data. The pulse-change unit is electrically connected to the gate driver to provide a high-level gate signal modulation voltage, and the inter-pole pulse wave is controlled by the _ clamp. In the operation of the liquid crystal display device, during the predetermined time period after the liquid crystal display device is turned on, the selection signal is in the first state to disable the voltage clamping function, and after the predetermined time period, the selection signal is switched to the second state different from the second state. According to the voltage clamp function. [Embodiment] Hereinafter, the specific embodiment of the liquid crystal display device according to the present invention will be described in detail in conjunction with the drawings, but the actual compensation provided is not the scope covered by the present invention. 201142796 FIG. 2 is a schematic structural view of a first embodiment of a liquid crystal display device of the present invention. As shown in Fig. 2, the liquid crystal display device 2 includes a pixel array having a plurality of elements.

The wave shift is 7L 22G early. The source 羯n gang gamma provides a complex data signal to the pixel array early το 200. The gate driver 2〇6 is used to provide a plurality of inter-pole signals to the pixel array unit 200 according to the high-level gate signal modulation house VGHM and the low-level gate signal reference VLI, and the pixel array unit That is, the plurality of pixels are driven according to the complex data signal and the complex gate signal to display the image. The _ zone actuator can perform the shutdown afterimage attenuation operation on the pixel array unit 2 according to the reset signal ,. The operation related waveform of the reset signal 系 is a conventional technique and will not be described. The crystal 230 is a P-type thin film transistor or a p-type field effect transistor is an N-type thin film transistor or (4) a field effect transistor. Inverter wheel terminal 'the lover's end is used to receive the control signal vpLi ^ with the first end, the second end and the gate terminal, wherein the first end is used to: 参老雷厌'/mu. — 闸脉脉The Boju unit 22 is used to provide high-level gate signal modulation voltage. The gate pulse modulation unit 220 includes an inverter, a first transistor 230, an electrical body 235, a resistor Rx, a diode 225, and a selector. The first electric N-type field effect transistor. Inverted ϋ contains input and

201142796

Rx. The resistor Rx is electrically coupled to the second transistor 235. *Strong 4$· - oca - human pine if potential Vref = selection, 250 contains first input, second input and round-out - input to receive Ma Lai Vdamp, second input end threat (four) imtm: _225 [_ 225 includes positive > and negative peak thode), wherein the positive terminal is electrically connected to the selector (10) and is electrically connected to the second end of the first transistor 23A. Thin, negative inverter, first-electrode, second transistor attack and resistance ^ and combined into a waveform chamfering circuit, used to provide high-level inter-polar signal modulation voltage, according to the complex gate The signal performs waveform chamfering. In addition, the single characteristic of the diode milk enables the waveform chamfering operation performed by the waveform chamfering circuit to have a voltage home function. The second trap 250 is based on the reset signal to perform the selection operation, and accordingly The input terminal or the second input terminal is electrically connected to the positive terminal of the diode, thereby selecting the home voltage vcIamp or the reference potential Vref to be fed into the positive terminal of the diode milk. Therefore, the reset signal X0N is used to control the shutdown residual image attenuation operation, and is also used to control the selection and selection operation. This can simplify the peach (4) cost. When the county touches the VcIamp to feed the positive terminal of the diode 225, the diode 225 is activated according to the clamp voltage to perform the (quad) Wei on the high-order side. When the reference potential Vref is selected and fed to the positive terminal of the polar body 22s, the diode μ5 performs a voltage clamping function on the high-level gate signal modulation voltage VGHM according to the reference potential Vref^, due to the same-level closed-circuit signal. The range of the modulation voltage VGHM is between the high=gate signal reference voltage VGH and the reference potential Vref, so the diode can hardly reduce the reference potential Vref to perform the yaw clamp ship. That is to say, the selector 250 can perform the selection operation according to the reset signal history to enable/disable the voltage home function 201142796 month b. The still-bias gate signal reference voltage vgh can be connected to the capacitor via the first transistor 230

Cg performs a fast charging operation, which causes the two-level closed-circuit signal to be modulated, and vghm quickly rises to the still-biased gate signal reference voltage VGH. Alternatively, the reference potential can perform a discharge operation on the capacitor Cg via the second transistor 235 and the resistor Rx, thereby lowering the high-level gate signal modulation voltage VGHM, wherein the resistor is used to control the discharge rate. In the discharge operation of the capacitor cg, the selector 250 selects the clamp voltage Vdamp to be fed to the positive terminal of the diode 225 to enable the voltage clamping function, so when the high-level gate signal modulation voltage VGHM drops to the clamp voltage In Vclamp, the diode 225 is forward-driven, so that the Micro Motion (10) is turned off and the VGHM is read up to the clamp voltage Vclamp until the subsequent charge and discharge operation is performed. In the operation of the liquid crystal display device 20, the reset signal 重置ον is in the first state during the predetermined period of time after the power-on, so that the selector 25 is actuated. Selecting the reference potential doctor to remove the electric crane position Wei, (10) the Vdamp recorded in the silk county rises to the input voltage level 'but the clamp voltage Vdamp is not fed to the positive end of the diode milk, ie The high-level clamp Vdamp cannot be fed to the interpole driver 2G6 during the expected segment. Therefore, the gate driver 2G6 does not generate a complex type of noise gate signal. That is to say, even if the reset state (X(10) of the first state causes the gate driver to simultaneously output all the errors to the pixel array 200' startup screen, the noise phenomenon does not occur. After the predetermined time period, the reset 汛唬X:N is switched to a second state different from the first state, so that the selector 2 5 〇 selects the I# bit voltage Vd with the questionable level to read the voltage clamping function. . Fig. 3 is a schematic view showing the structure of a second embodiment (4) of the liquid crystal display device of the present invention. As shown in Fig. 3, the liquid crystal display device 3 () includes a pixel array unit, a source driver 10 201142796 204, a gate driver bird, a capacitor Cg, and a gate pulse modulation unit. The idle pulse wave modulation unit 32G is similar to the gate pulse wave modulation unit 22A shown in Fig. 2, and the main difference is that the diode 225 is replaced with the diode 325. The diode includes a positive and a negative terminal, wherein the positive terminal is electrically connected to the output terminal of the selector 250 and is connected to the second terminal of the second transistor 235. That is to say, the negative electrode & of the diode milk is electrically connected to the connection node of the second transistor 235 and the resistor. In the operation of the liquid crystal display device ^ when the discharge operation of the capacitor 执行 is performed, the selector 250 selects

The clamp voltage Vdamp is taken to the clamp ship, and when the second electric crystal 235 and 1 are connected, the junction is lowered to the voltage Vdamp.

The 235 is the pass-through, so that the high-level gate signal modulation voltage VQHM is generally kept in the wire (four) pressure Vdamp straight line operation. Except for the above operation of the diode 325, the rest of the operation of the liquid crystal display device 3 is the same as that of the liquid crystal display device 20, and will not be described again. * Fig. 4 is a schematic view showing the structure of a third embodiment of the liquid crystal display device of the present invention. As shown in Fig. 4, the liquid crystal display device 4 () includes a pixel array unit, a source driver gate driver 206, a capacitor Cg, and a gate pulse wave modulation unit side. The gate pulse modulation unit 42G is similar to the gate pulse modulation unit 22A shown in Fig. 2, with the difference that the selector is replaced with a selector. The selector includes a first electro-optical body 451 and a fourth electro-optical crystal 453', wherein the third transistor 451 is an n-type thin film electroporation or a ^^ type electro-effect transistor, and the fourth transistor 453 is P-type thin germanium transistor type 2 ^ effect transistor. The third transistor 451 includes a first end, a second end and an intermediate end, the first end is used to receive the clamping voltage, and the second end is electrically connected to the diode extreme end of the diode for receiving the reset signal XON. . The fourth transistor is configured to include a second terminal and a gate terminal of the 201142796, wherein the first end is electrically connected to the reference potential W, the second end is electrically connected to the positive terminal of the diode 225, and the gate terminal is used for receiving the reset. Signal coffee. When the reset signal XON is maintained in the first state, the fourth transistor is turned on and the third transistor is turned off, so that the reference potential Vref is selected to be fed to the positive terminal of the diode milk to remove the light ship. t reset minus () Ν _ in the second state, the three transistors 451 are turned on and the fourth transistor 453 is turned off, so that the clamp voltage Vdamp having a high level is selected to be fed to the positive terminal of the diode 225. Enable voltage home function. In addition to the above operations regarding the third transistor 451 and the fourth transistor loose, the lion's Wei Jingling device 2G of the liquid crystal display device 40 is described. Lu Figure 5 is a schematic view showing the structure of a fourth embodiment of the liquid crystal display device of the present invention. As shown in Fig. 5, the liquid crystal display split 5 〇 includes a pixel array unit, a source driver inter-pole driver 206, a capacitor eg, and a gate pulse modulation unit 52. The pulse path unit 520 is similar to the gate pulse modulation unit 第 shown in Fig. 3, the main difference being that the selector 25 is replaced with the selector 550. The selector 550 includes a first electric body 551 and a fourth transistor 553, wherein the third transistor 551 is an n-type thin film electric b body or an N-type field effect transistor, and the fourth transistor 553 is a p type. Thin film transistor Lu or p-type field effect transistor. The third transistor 551 includes a first end, a second end and a gate terminal, wherein the first end is used to receive the clamping voltage Vdamp, and the second end is electrically connected to the diode terminal to be used to receive the reset signal. Hey. The fourth transistor is cut to include a first-to-first and a gate terminal, wherein the first terminal is electrically connected to the reference potential Vref, and the second terminal is electrically connected to the positive terminal of the diode 325, and the gate terminal is configured to receive the reset signal. When the field 5 field XON is maintained in the first state, the fourth transistor 553 is turned on and the third electrode body 551 is turned off, and the reference potential Vref is selected to be fed to the anode of the diode 325. 12 201142796 Voltage clamping function. When the reset signal X0N is maintained in the second state, the first electrical aa body 551 is turned on and the fourth transistor 553 is turned on, and the clamp voltage Vdamp having the high level is selected to be fed to the positive terminal of the diode 325. The voltage clamping function is enabled. Except for the above operations regarding the third transistor 551 and the fourth transistor 553, the rest of the operation of the liquid crystal display device 50 is the same as that of the liquid crystal display device 3, and will not be described again. Figure 6 is a schematic view showing the structure of a fifth embodiment of the liquid crystal display device of the present invention. As shown in Fig. 6, the liquid crystal display device 6G includes a pixel array unit, a source driver 204, a gate driver 2〇6, a capacitor Cg, and an open-pole pulse modulation unit (10). The pulse wave modulation unit 620 is similar to the gate pulse modulation unit 22A shown in Fig. 2, and the main difference is that the selection H 25〇· is replaced by the selector (4). The selector (4) includes a first input terminal, a second input terminal and an output terminal, wherein the first input terminal is configured to receive the home position voltage Vdamp, the second input terminal is electrically connected to the reference potential system, and the output terminal is electrically connected to the second pole. The positive end of body 225. The selector (10) performs a selection operation according to the selection signal Ssel different from the reset signal ,. When the selection signal is kept in the first state, the H (four) f is selected to connect the second input end and the output end to select the reference potential (4). The positive terminal of the diode 225 is fed. When the selection signal (5) is maintained in the second state, the selector (4) is electrically connected to the first input terminal and the output terminal to feed the positive terminal of the diode 225 with the clamp voltage Vclamp. Therefore, in the operation of the liquid crystal display device 6, in addition to the power (four) bit work, the predetermined time period does not need to be equal to the reset signal, and the first state is maintained when the device is turned on. The predetermined period of clamping function to improve operational performance. In addition to the above operation regarding the selection signal _, the rest of the operation of the liquid crystal display device is the same as that of the liquid crystal display, and will not be described. The figure is a schematic structural view of a sixth embodiment of the liquid crystal display device of the present invention. For example, 201142796, the seventh liquid crystal display device 7A includes a pixel array unit 2204, a gate driver 2〇6, a snow wave generation-1 g, and a gate pulse dependence unit 720. The gate 72 is similar to the pole-wave modulation unit gamma shown in Fig. 3, and is replaced with a selector 75 at the gate 250. . The selector includes a fourth input terminal, a second input terminal and an output terminal, wherein the first input terminal is used to receive the local electrical connection to the parameter line ef, and the input terminal is connected to the second positive terminal. Selecting (4) 75G is different from the reset 峨X〇N selection. The positive terminal 820 of the polar body 325 selects the clamp voltage Vd or the reference potential re to enter the positive terminal of the polar body 325. Therefore, in the operation of the liquid crystal display device, the predetermined period of the bit function does not need to be equal to the period of resetting the signal-state, and the pre-emption period of the de-energizing voltage clamping function can be more flexibly adjusted. Operational performance. Except for the above-described operation for selecting the signal fine, the remaining operation of the liquid helium display device 70 is the same as that of the liquid crystal display device 3, and will not be described. /Day 8 FIG. 8 is a schematic structural view of a seventh embodiment of the liquid crystal display device of the present invention. As shown in Fig. 8, the liquid crystal display device 80 includes a pixel array unit, a source driver 〇4, a gate driver, a capacitor Cg, and a gate pulse modulation _82. The idle pulse wave modulation unit 820 is similar to the gate pulse modulation unit_ shown in Fig. 6, the main difference being that the selector 650 is replaced with the selector 85A. The selector (4) includes a third transistor 85i and a fourth transistor 853, wherein the third transistor 85 is an n-type thin film transistor or an N-type field effect transistor, and the fourth transistor 853 is a p-type thin film transistor or P-type field effect transistor. The third transistor 851 includes a first end, a second end and a gate: wherein the first end is used to receive the clamping voltage Vdamp, and the second end is electrically connected to the diode end 201142796. Receive the selection signal Ssd. The fourth transistor 853 includes a first end, a second end and an intermediate end, wherein the first end is electrically connected to the reference potential, the second end is electrically connected to the positive terminal of the diode 225, and the gate terminal is used for receiving the selection signal (5) . When the selection signal Ssel turns on the fourth transistor 853 and turns off the third transistor 851, the selector 850 selects the reference potential to be fed to the positive terminal of the diode milk to disable the voltage clamping function. When the selection signal Ssel turns on the third transistor 851 and turns off the fourth transistor 853, the selector 85 selects a clamping voltage with a high level to feed the positive terminal of the diode 225 to enable the voltage clamp. Bit function. Except for the above operations regarding the third transistor and the fourth transistor, the remaining operations of the liquid crystal display device 8 are applied to the liquid crystal display device 6, and will not be described again. ★ Fig. 9 is a schematic structural view showing an eighth embodiment of the liquid crystal display device of the present invention. As shown in Fig. 9, the liquid crystal display device 9 () includes a pixel array unit, a source driver 2〇4, a gate driver 2〇6, a capacitor Cg, and a gate pulse wave modulation unit 9. The open-pole pulse modulation unit 92 is similar to the gate pulse modulation unit 72〇, _ shown in Fig. 7, with the difference that the selector 750 is replaced with the selector 950. The selector 950 includes a third transistor 951 and a fourth transistor 953, wherein the third transistor 951 is an N-type thin film transistor or an N-type field effect transistor, and the fourth transistor 953 is a p-type field effect. The third tank 951, the first: the first: the first end is used to receive the clamping voltage Vclamp, the second end is electrically connected to the diode milk positive pole, the gate terminal is used to receive the selection signal (9), the fourth transistor (6) contains The first end, the second end and the gate terminal, wherein the first end is electrically connected to the reference potential vref, the second end is electrically connected to the positive terminal of the diode 32s, and the gate terminal is used for receiving the selection signal (4). * When the selection signal Ssel turns on the fourth transistor 953 and cuts off the third transistor %], select 15 201142796 = two test potentials μ are fed to the positive terminal of the diode 325 to disable the power = two... when selecting the signal Ssel When the third transistor 951 is turned on and cut off, the selector (4) selects the home voltage with a high level to be fed to (4) Jingwei Newwei. In addition to the operation of the above-mentioned three-crystal and fourth transistor 953, the liquid crystal The rest of the operation of the thin device 9G is the same as that of the liquid crystal display device, and will not be described again. In the operation of the liquid crystal display device of the present invention, the signal can be reset in the predetermined S-segment after the power-on. Select 峨 to stop the operation of the input voltage to disable the voltage clamp function' so the clamp voltage rises quickly to the input voltage level. The clamper with the input power is not able to feed into the predetermined time period. The gate driver 2 and the gate driver will not generate a plurality of types of noise gate signals. Therefore, even if the reset signal for attenuating the shutdown image remains in the predetermined time period, all the gate signals are simultaneously output to the gate device. Alien array unit, noise of the boot screen The present invention has not been described in the above embodiments, and is not intended to limit the present invention, and any one of ordinary skill in the art to which the present invention pertains, without departing from the scope of the present invention, The scope of protection of the present invention is defined by the scope of the appended claims. [Fig. 1 is a schematic diagram of a conventional liquid crystal display device. The figure is a schematic structural view of a first embodiment of a liquid crystal display device of the present invention. Fig. 3 is a schematic structural view of a second embodiment of a liquid crystal display device of the present invention. 16 201142796 FIG. 4 is a third embodiment of a liquid crystal display device of the present invention. Figure 5 is a schematic view showing the structure of a liquid crystal display device according to a fourth embodiment of the present invention. Figure 6 is a schematic view showing the structure of a liquid crystal display device according to a fifth embodiment of the present invention. FIG. 8 is a schematic structural view of a seventh embodiment of a liquid crystal display device of the present invention. FIG. 9 is a liquid crystal display device of the present invention. A schematic configuration of the eighth embodiment.

[Main component symbol description]

10, 20, 30, 40, 50, 60, 70, 80, 90 100, 200 104, 204 106, 206 120, 220, 320, 420, 520 '620'720 > 820 ' 920 125 > 225 ' 325 130 ' 230 135 , 235 140 , 240 250 , 450 , 550 , 650 , 750 , 850 , 950 liquid crystal display device pixel array unit source driver gate driver gate pulse wave modulation unit diode first transistor Two transistor inverter selector 45 Bu 55 851, 951 Third transistor 201142796 453, 553, 853, 953 Fourth transistor PX Alizarin Rx Resistance Ssel Select signal Vclamp Clamp voltage VFLK Chamfer control signal VGH high Level gate signal reference voltage VGHM High level gate signal modulation voltage VGL Low level gate signal reference voltage Vref Reference potential XON Reset signal 18

Claims (1)

201142796 VII. Patent application scope: A liquid crystal display device, comprising: image display operation; a pixel array unit for performing a source drive n, electrical connection _ 卩 卩 (4) column unit performs the image display operation "" The multiple data signals required for the continuous operation; A 駆 H H ( (4) 昼 _ unit, listen Inter-polar signal adjustment (four) pressure bribes _ prime _ unit implementation of the township image = the complex number of signals required for operation, and used to perform a single-it operation on the book array according to the reset signal - shutdown thief decay operation; and -, a gate a pulse modulation unit connected to the gate driver for providing the high level gate triggering unit, the gate pulse modulation unit having a voltage clamping function controlled by a reset signal; The reset signal is in a first state to disable the voltage clamping function during a predetermined period of time after the liquid crystal display device is turned on, and the reset signal is switched to be different from the first state after the predetermined period of time. The first state, according to which the voltage clamping function is enabled. The liquid crystal display device of claim 1, wherein the gate pulse modulation unit comprises: an inverter 'including an input end and an output end', wherein the wheel end is configured to receive a chamfer control a first transistor, a second terminal and a gate terminal, wherein the first terminal is configured to receive a high-level gate signal reference voltage. The gate terminal is electrically connected to the gate. An output end of the phase device, the second end is configured to output the high level gate signal modulation voltage; the second transistor 'including a first end, a second end and a gate end, wherein the first end is electrically Connected to the second end of the first transistor, the gate terminal is electrically connected to the output end of the inverter; the resistor is electrically connected between the second end of the second transistor and a reference potential; a positive terminal and a negative terminal, wherein the negative terminal is electrically connected to the second end of the second transistor or the second end of the first transistor; and the selector includes a first input end, a first a second input end and an output end, wherein the first input end is used Receiving a clamp voltage, the second input end is electrically connected to the reference potential, the output end is electrically connected to the positive terminal of the diode, and the selector selects the clamp voltage or the reference according to the reset signal a potential is fed from the output terminal to the positive terminal of the diode; wherein the inverter, the first transistor, the second transistor, and the resistor are used to control the signal and the high level gate according to the control signal The pole signal reference voltage is provided to provide the high level _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The liquid crystal display device according to claim 2, wherein the liquid crystal display device is turned on after the liquid crystal display device is turned on, and the liquid crystal display device according to claim 2, wherein the liquid crystal display device is turned on after the liquid crystal display device is turned on. The first state of the reset signal is used to cause the selector to select the reference potential to disable the voltage clamping function. 4. The liquid crystal display device of claim 2, wherein the second state of the reset signal is used by the selector to select the clamp voltage to enable the voltage clamping function after the predetermined period of time. 5. The liquid crystal display device of claim 2, wherein: the first electro-crystalline system is a P-type thin film transistor or a P-type field effect transistor; and the second electro-crystalline system is an N-type thin film electric Crystal or an N-type field effect transistor. 6. The liquid crystal display device of claim 2, wherein the selector comprises: a third transistor comprising a first end, a second end and a gate terminal, wherein the first end is configured to receive the pliers a second voltage electrically connected to the positive terminal of the diode, the gate terminal for receiving the reset signal; and a fourth transistor comprising a first terminal, a second terminal and a gate terminal The first end is electrically connected to the reference potential, and the second end is electrically connected to the positive terminal of the diode, and the gate terminal is configured to receive the reset signal. 7. The liquid crystal display device of claim 6, wherein: 21 201142796 the third electro-crystalline system is an N-type thin film transistor or an N-type field effect transistor, and the fourth electro-crystalline system is a P Type thin film transistor or a P type field effect transistor. 8. The liquid crystal display device of claim 6, wherein the first end of the fourth transistor is electrically connected to a ground potential. 9. The liquid crystal display device of claim 2, wherein the resistor is electrically connected between the second end of the second transistor and a ground potential. The liquid crystal display device of claim 2, further comprising: a capacitor electrically connected between the second end of the first transistor and the reference potential. U·=The liquid crystal display device of claim 1() is electrically connected between the second end of the first electric solar cell and the ground potential. 12· A liquid crystal display device comprising: · Lu-source driving H, providing a re-feeding signal; the inter-pole driving g, 帛 according to the - high-precision deceleration to provide a digital gate signal; The pixel array 70' is electrically connected to the source to drive the sufficient driver for electrically connecting to the gate driver according to the signal and the secret age-age image; and the gate pulse modulation unit. For providing the high 22 201142796 level gate signal modulation voltage, the gate pulse modulation unit has a voltage clamping function controlled by a selection signal; wherein one of the liquid crystal display devices is turned on During the time period, the selection signal is in a first state to disable the voltage clamping function, and after the predetermined time period, the selection signal is switched to be different from the second state of the first state, thereby enabling the voltage clamp Bit function. 13. The liquid crystal display device of claim 12, wherein the gate pulse modulation unit comprises: an inverter comprising an input end and an output end, wherein the input end is configured to receive a chamfer control a first transistor, a second terminal and a gate terminal, wherein the first terminal is configured to receive a high-level gate signal reference voltage, and the gate terminal is electrically connected to the reverse phase The second end is configured to output the high level gate signal modulation voltage; the second transistor includes a first end, a second end and a gate end, wherein the first end Electrically connected to the second end of the first transistor, the gate terminal is electrically connected to the output end of the inverter; a resistor electrically connected between the second end of the second transistor and a reference potential; a diode comprising a positive terminal and a negative terminal, wherein the negative terminal is electrically connected to the second end of the second transistor or the second end of the first transistor; and 23 201142796 a selector comprising a first input end, a second input end and an output end, wherein The first input end is configured to receive a clamp voltage, the second input end is electrically connected to the reference potential, the output end is electrically connected to the positive end of the diode, and the selector selects the clamp according to the selection signal The bit voltage or the reference potential is fed from the output terminal to the positive terminal of the diode; wherein the inverter, the first transistor, the second transistor and the resistor are used to control the signal according to the chamfer And the high-level gate signal is used to provide the high-level gate signal modulation voltage, and a waveform chamfering operation is performed on the gate signals, and the unidirectional transmission characteristic of the diode can be The waveform chamfering operation has the voltage clamping function, and the selector is configured to enable/disable the voltage clamping function according to the selection signal. 14. The liquid crystal display device of claim 13, wherein the first state of the selection signal is used by the selector to select the reference potential to disable the predetermined period of time after the liquid crystal display device is turned on. This voltage clamp function. 15. The liquid crystal display device of claim 13, wherein the second state of the selection signal is used by the selector to select the clamping voltage to enable the voltage clamping function after the predetermined period of time. 16. The liquid crystal display device of claim 13, wherein: 24 201142796 4 the first electro-crystalline system is a P-type thin film transistor or a P-type field effect transistor; and the second electro-crystalline system is a N A thin film transistor or an N-type field effect transistor. 17. The liquid crystal display device of claim 13, wherein the selector comprises: a third transistor comprising a first end, a second end and a gate terminal, wherein the first end is configured to receive the pliers a second voltage electrically connected to the positive terminal of the diode, the gate terminal for receiving the selection signal; and a fourth transistor comprising a first end, a second end and a gate terminal The first end is electrically connected to the reference potential, and the second end is electrically connected to the positive terminal of the diode, and the gate terminal is configured to receive the selection signal. 18. The liquid crystal display device of claim 17, wherein: the third electro-crystalline system is an N-type thin film transistor or an N-type field effect transistor; and • the fourth electro-crystalline system is a P-type film A transistor or a P-type field effect transistor. 19. The liquid crystal display device of claim 17, wherein the first end of the fourth transistor is electrically connected to a ground potential. 20. The liquid crystal display device of claim 13, wherein the resistor is electrically connected between the second end of the second transistor and a ground potential. The liquid crystal display device of claim 13, further comprising: a capacitor electrically connected between the second end of the first transistor and the reference potential. 22. The liquid crystal display device of claim 21, wherein the capacitor is electrically connected between the second end of the first transistor and a ground potential. ,figure. 26