TW201140819A - Diode memory - Google Patents

Abstract

A diode memory device has an intermediate structure between the two terminals, such as a p terminal and the n terminal.

Description

201140819 1 yyyjuji η VI. Description of the Invention: TECHNICAL FIELD The present invention relates to a diode memory device. [Prior Art] Ceria antifuse memory is often designed as a one-time program (OTP). In a memory array, an additional diode or transistor is required to access a particular recovery cell. Similarly, 'resistive random-access memory' in an array of memory usually requires an additional diode to select a transistor to access a particular memory cell, and the pair is not selected. ^ Emotional access. Although such an external access device is still necessary, J selects a specific memory cell from a cell array, but such an external access dreams the scalability of the memory device and increases Manufacturing Advantages 0 ' [Invention] One embodiment of the present invention is a diode memory device having an object structure between a P end point and an n end point. This intermediate is the middle finger node, and the two-pole system formed by this synchronization (in_situ) is absolute. This insulation device is blocked by the memory of the county's diodes, ', and taken. An example of this intermediate structure is ruthenium dioxide ((10), the name of the ruthenium punch through the gate oxide layer (for example)

Si02 shows excellent memory switching characteristics), electric Japanese and Japanese, this action 201140819 ( * 1 WOiJjr / \ · placed in the substrate is unipolar. Other intermediate structures include metal oxide materials, high dielectric Constant-high-k materials, tantalum nitride, and niobium oxynitride, all materials that change stoichiometry and resistive types, can be used to form resistive devices. Unlike anti-fuse memory, diode memory devices do not. An external insulator and an access device are required, such as an external diode or an external transistor. Therefore, the two-pole system is a 0T-1R device (no transistor, single resistor). Another embodiment of the present invention is a diode. An array of bulk memory devices, such as on an integrated circuit. Another embodiment of the invention is a method of operating the diode memory device, such as reading, setting, or resetting ( Another embodiment of the present invention is a method of operating an array of diode memory devices, such as writing a selected binary memory device or a plurality of selected binary memory devices. The address is followed by a read, set, or reset operation. Another embodiment of the invention is to fabricate an array of diode memory devices or two φ pole memory devices, such as in normal memory operation ( An initial breakdown operation is performed before resetting and setting operations. One aspect of the present technology is an integrated circuit device having a cross-point array and a control circuit. The array includes a plurality of bit lines and a plurality of word lines. The plurality of intersections of the bit lines and the word lines include a diode memory replacement device. The diode memory device includes a diode and a Memory element 0 3 201140819 The diode includes a first end point and a second end point, the first end point is electrically coupled to one of the bit lines, and the second end point is One of the word lines is electrically coupled. The memory element is located between the first end and the second end of the diode. The memory element is bidirectionally switchable to a first Between a memory state and a second memory state. The plurality of diodes of the diode memory device can reduce the current passing through the unselected intersections between the bit lines and the word lines. The control circuit is coupled with the intersection and the point array. Bias arrangement to the selected parent of one of the intersections of the bit lines and the word lines to bidirectionally switch the memory of the diode memory device at the selected intersection In one embodiment of the invention, the first end point is in a doped well region and the second end point is part of a word line. In one embodiment, the doped region has a first doping The impurity and a first concentration, and the two poles further comprise a -doped region, the doped region is located in the well region, and the first: holding the impurity state. The doped region is below the memory element and i has a concentration less than the first concentration. In one embodiment, the light channel junction is used to represent the high switching ratio of the diode (the implanted depth of the FF m ^ implanted depth and its doped ice operation). Channel blending operation (RESET water). W * degree is secreted on the surface of the ♦ surface (such as reading ang / wood) with a handful of resistance (undoped or very light-faced stone kiln initial melting area (in the present invention = miscellaneous) close to the switch Switching); then the oxygen atom is quickly formed in the ring layer and dispersed to the solvency t, and after cooling, forms a dioxin phase and is easily expanded in an embodiment _, and the component (4) includes gasification. 201140819

( » 1 WOUjr/\T In one embodiment, the memory element includes a first hafnium oxide layer, a tantalum nitride layer on the first hafnium oxide layer, and a second oxidation on the tantalum nitride layer The stone layer is, for example, an S〇n〇s device. In one embodiment, a polar body component includes a metal oxide, tantalum nitride, hafnium oxynitride, a programmable resistance material, and a dielectric constant greater than that of yttrium oxide. Any one of the dielectric constant materials. In one embodiment, the diode memory device further comprises at least one of: (i) an upper buffer layer between the first end point and the memory element; And φ (i 一下 a lower buffer layer between the second terminal and the memory element. In an embodiment the 'control circuit applies a first forward bias having a first set of electrical characteristics Arranging to the selected intersection to switch the memory element of the diode memory device at the selected intersection from the first memory state to the second memory state. And, the control circuit is configured to have a second group of electricity One of the second forward biases is arranged to the selected intersection At the fork, the memory element of the diode memory device at the selected intersection is switched from the second memory state to the first memory state. φ In one embodiment, the control circuit induces a dielectric collapse by induced dielectric collapse. Dielectric breakdown induced epitaxy switches the memory element of the diode memory device at the selected intersection from the first memory state to the second memory state. And the 'control circuit induces Joule heating. Switching the s-resonance element of the diode memory device at the selected parent fork from the second memory state to the first memory state. In an embodiment, the first memory state corresponds to having a first The diode current-voltage characteristic diode memory device' and the second memory state correspond to a diode memory 201140819 1 wuujrrv 1 11 device having a second diode current-voltage characteristic. The body current voltage characteristic and the second diode current voltage characteristic have different forward characteristics. For example, the ideality factor η varies, and the series resistance Rs is also variable. In one embodiment, the memory component is switchable between at least four memory states, the first memory state and the second memory state. One aspect of the present technology is to operate an integrated body. The method of the circuit includes the steps of: biasing the selected intersections at the intersections of the bit lines and the word lines to bidirectionally switch one of the diode memory devices at the selected intersection A memory device, wherein the diode memory device comprises a diode, the diode comprising a first end point, a second end point, and a memory element. The first end point system and the plurality of bit elements One bit line in the line is electrically coupled, and the second end point is electrically coupled to one of the plurality of word lines, and the memory element is located at the first end and the second end of the diode Between the points. By the diode of the diode memory device at the unselected intersection, the current at the intersection where the intersection of the bit line and the word line is selected is reduced. An embodiment further includes: prior to normal operation of the diode memory device, applying an initial bias to the diode memory device to change the memory component from an unused state to a memory state state. An embodiment further includes: before the normal operation of the diode memory device, applying an initial bias to the diode memory device, so that the memory component has a non-second 201140819, 1 pole current voltage One of the characteristics of the unused state changes to one of the memory states having a diode current-voltage characteristic. In one embodiment, the biasing arrangement comprises: applying a first forward bias having a first set of electrical properties to the selected intersection to be located at the selected intersection a memory element of the diode memory device is switched from a first memory state to a second memory state; and a second forward bias having a second set of electrical properties is applied to the intersection selected by φ The memory element of the diode memory device at the selected intersection has been switched from the second memory state to the first memory state. In one embodiment, the biasing arrangement comprises: inducing epitaxy by inducing a dielectric breakdown of the memory component to place a memory component of the diode memory device at the selected intersection Switching a first memory state to a second memory state, and by inducing a Joule heating effect of the memory component, to cause a memory component of the selected diode device to be removed from the second memory state Switch to the first memory state. In one embodiment, the first memory state corresponds to a diode memory device having a first diode current-voltage characteristic, and the second memory state corresponds to having a second diode current-voltage characteristic. A diode memory device in which the first diode current voltage characteristic and the second diode current voltage characteristic have different forward characteristics. In one embodiment, the biasing arrangement described herein switches the memory elements between memory states having different diode current and voltage characteristics. In one embodiment, the biasing arrangement switches the memory component 7 201140819 1 vvuij^r/\ between at least four memory states, and the technique of the present invention has a diode. One of the memory control circuits is an integrated circuit device. The diode memory device includes a first component. The diode includes a --end point and a "heart" and a memory element. ^ ^ ^ is a point and a second end point. The memory source is located between the first end of the diode and the first touch - 1 and the point. The diode element is switched bidirectionally between the -th-think state and the second memory state. In some embodiments, the first end point is located in a well region having a -th-concentration: first-doped state, wherein the doped region of the well region has the first doped state and has Small (four) - concentration - the second concentration. In other embodiments, the diode of the diode memory device is biased in response to a bias across a diode memory device corresponding to an unselected diode memory device, reducing current through the pole Body memory device. The control circuit is coupled to the diode memory device. The control circuit is biased to the diode memory device to bidirectionally switch the memory elements of the diode memory device. Other embodiments are disclosed herein. The terms set, reset, and crash here refer to the operations performed on the diopter of the diode and the state of the diode memory generated by the operation of the same title; these specifics in the text The use of the system is clear. [Embodiment] Fig. 1 is a diagram of a diode memory device having an intermediate oxide structure. This structure is similar to the general metal oxide half field effect transistor 8 201140819 (MOSFET), however the structure here has no source/drain junction. An ultra-thin thermal gate oxide layer with a thickness of 1.2 nm is placed between the N+ polysilicon gate and the P-substrate. A pulse is applied to the gate and the gate current is measured. After the formation of the pulse (1st SET operation) destroys the gate oxide layer, an N+/P_ junction is formed. A negative gate voltage (_VG) corresponds to a forward read and allows a large current for reading and programming. The doping of the N+ gate is approximately 8xl 〇 2 〇 cm-3. The P channel doping with a thickness of 1200A is approximately 7X1017 cnT3. Light doping close to the surface contributes to the φ reset/set operation. The memory of the memory component disposed inside the diode (in the case of the present invention, the cerium oxide is a storage node) has one or more advantages: the FEOL process does not require new materials and process steps; self-formed Self-formed selecting device; Ν+/Ρ·2-pole system is automatically formed after the gate oxide layer is cut off; the cost of the 4F2 0T1R ReRAM device is very low; and the same miniaturization capability as the CMOS process. Conversely, the memory element and the diode are arranged in series rather than being disposed. • Other memory inside the diode has one or more disadvantages that are similar to current rrAM' PCM devices. This is because in the limitation of switching materials (the material cannot be manufactured in FEOL or MEOL), the additional diode or transistor cannot be manufactured synchronously with the switching material; the process cost is greatly increased; and the process is more Complex. Figure 2 is a diagram showing the operation of a soft crash, a hard crash, a reset, and a setup operation on the diode memory device of Figure 1. For the fresh MOS diode, the negative Vg of the 1 ns pulse is gradually increased until a soft collapse (SBD) occurs at -6 V, followed by a hard collapse at 9 201140819 1 ννυυ^ΓΛ -9v (HBD) ). After the hard (four) collapse, the N+/p junction is formed. Interestingly, 'when Vg exceeds tearing, the idle current decreases' and the gate resistance increases ("REset" state). After the initial formation step, the resistance hysteresis is repeatable by alternately applying a _7V (SET operation) pulse and a _13V (RESET operation) pulse. Therefore, the MOS diode performs a memory switching feature. The memory system switches by changing the gate current and gate resistance, rather than by charge storage. The 3A-3D picture is the first! The I-V characteristic plot of the different states of the diode memory device of the figure. The ideal diode factor n is also extracted. Because it is an N-type gate, a negative gate voltage (_VG) corresponds to a forward read and allows a large current to be read and programmed. An initial MOS diode (Fig. 3B) has a negligible gate current ' and proves that the state at this time is similar to a resistor. After lst HBD or SET operation (formation) (3D), the forward current is increased when the reverse current is kept low, thus providing a large switching ratio of the PN diode (ON/OFF) Ratio ) ( > 8 levels). This large ratio can support "self-selected" diode operation without the need for additional means (e.g., a diode or transistor) in a cross-point memory array. Because the two-pole system is formed synchronously, there is no need to fabricate a separate isolation device, which is ideal for a low cost cross-point memory array. The RESET operation (Fig. 3C) greatly reduces the forward current, so this approach allows detection limits close to three levels. A pure PN diode (Fig. 3A) without an intermediate gate oxide layer is manufactured and massed 201140819

· I is used for comparison. Figure 3D indicates that the SET state read current is close to the PN diode and the extracted ideal factor (η) is also close to each other (~1.3 to 1.4). Both the RESET and SET states show the diode correction characteristics such that no separate access/insulation devices are required in the cross-point array of the diode memory device. An example of a crosspoint array is a type of NAND (NAND-like) array. Another example of a cross-point array is a two-dimensional array with X-Y addressed memory. The high-density memory includes a diode memory device having a 4F2 area of φ, wherein the F system is the smallest feature size. Another embodiment includes a multi-stack array of cross-point memories. Figure 4 is a periodic diagram of the diode memory device of Figure 1. This diode memory device can switch almost one hundred unipolar cycles. This memory cell is miniaturized to L = 0.13 um and W = 0.02 um. Figure 5 is a diagram of the read disturb immunity of the diode memory device of Figure 1. Figure 6 is a high temperature retention of the diode memory device of Figure 1. Figure 2 is stable after more than 1000 hours of 150 degree baking. Fig. 7 is a diagram showing transient states of different states of the diode memory device of Fig. 1 using pulse IV technique. Program the width using one of 100 ns. The RESET operating current is much larger than the SET operating current. The device size is L/W = 0.2 um/0.2 um. Figure 8 is an IV plot of a PN diode device (without an intermediate oxide layer). Different sizes of PN diodes (without intermediate oxide layer) have permanent damage (stUck open) after application of the 201140819 (stress) high voltage application, losing switching characteristics. Figure 9A is a photograph of a rigid collapsed diode memory device biased by a negative gate. This embodiment has an n+ polysilicon gate which exhibits a strong dust polarity dependence and which occurs at -Vg. The polysilicon from the N+ gate penetrates the thin tunnel oxide layer after the HBD operation. This phenomenon is known as "dielectric collapse induced epitaxy," (DBIE). In another embodiment having a p+ polysilicon gate and a η body, the HBD occurs with the application of +Vg. In the Schottky gate embodiment, the polarity depends on the Schottky barrier system tending to be similar to the polycrystalline dream gate or the n+ polysilicon gate. Among them, the Schottky barrier has a built-in voltage and The work function of the Schottky metal of the Schottky barrier and the Fermi level (which can be compared to the work function of the semiconductor, the Fermi level, the electron affinity, the conduction band, and the valence band) are determined. A photo of a diode memory device with a positive voltage applied to the gate. No HBD occurs. Figure 10A is a schematic diagram of the diode memory device after the reset operation. ~ The programming current of the RESET operation causes some Localized heating, which results in the separation of a thick SiO 2 layer and a bottom polysilicon layer. Figure 10B is a photo of the contact area of the diode memory device after the reset operation. TEM image after RESET operation Shows high programming current on the surface Severe damage. Part of the crystalline lanthanum near the surface is converted to 201140819 » 1 ννυι * and polycrystalline germanium. However, the contact zone is normal. Figure 10C is a photo of the contact area of the diode memory device after the setup operation. The SET operation initiates the ruthenium in the oxide layer. The 10D image is a photographic view of the contact area of the diode memory device after the set state 1 〇〇 period. The 11A-11F diagram shows the different states. The lower diode memory device diagram. # SBD operation creates a percolation path between the polysilicon gate and the substrate. A permeation path triggers a hard collapse, and then the current induces a DBIE. After the HBD, the (RESET operation) increases. The bias voltage induces Joule heating near the stone. The argon heat effect dominates the RESET operation. Finally, the region temperature is close to the enthalpy melting point (Tcd, 1685K). The oxygen ions from the nearby layer can easily drift to the melting enthalpy. And after the current is turned off and the temperature is cooled, SiO 2 is formed. Therefore, after the reset operation, Si 〇 2 and a part of polysilicon can be observed at the substrate. The oxide layer is very It is a leakage-rich oxide layer that makes the forward current of the RESET state extremely higher than the initial state. The SET operation is similar to the first (formation) hbd, and the SET operation has a lower Joule heating effect than the RESET operation. Lower temperatures require less current. In SET operation, helium atoms are pushed by high momentum electron flow, and then atoms are stacked to form a filament, similar to the electromigration effect (electr〇niigration) The DBIE dominates the SET operation. In this way the 'SET/RESET operation can be performed repeatedly, respectively, 13 201140819 to form a dream and sex. S·02 leads to § 己 体 — — — — — 记忆 记忆 记忆 记忆 记忆 t t t f f f f f f 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第 第The current figure 12 is a diagram showing the relationship between the dimensions of Figure 1. The 12Α and 12th drawings compare the operating voltage and the corresponding operation = motor. The shaking system is reduced to L = 〇 13um, w = 〇〇 2um, showing the south density storage capacity. The HBD and SET operating power (4) are not dependent on the device size. When the device size is reduced, the reset operating voltage and the RE S E T operating current are reduced. However, the current is not linearly reduced with the | area. Under the 20 nm node, the predicted RESET operating current is still in the mA range. Since the high power consumption of the smelting process limits the power micro-shock, a more efficient thermal insulation that reduces power will support further miniaturization. Figure 13 is a diagram showing different IV characteristics of a diode device of a second figure after continuous application of a voltage. Figure 13 shows the suitability of multiple time programmable applications that store multiple bits in a single diode memory device. The gate current associated with the gate oxide leakage current can be adjusted by different pulse widths/pulse voltages. The starting device is the initial device, which behaves like a resistor. The component is then gradually applied with voltage to a different current state. The observed gradual collapse of the gate oxide demonstrates the suitability of a multi-time program (MTP) or multi-level-cell (MLC) application to a single diode On the memory device 201140819 t · 1 ττ r\ * Store multiple bits. When the thin oxide layer m〇SFET is slightly reduced to 1 〇 nm, the diode memory device is shrunk to less than 10 nm. Because it is based on changing the interpole current and gate resistance instead of charge storage to store data to eliminate the L memory problem of storing a small number of electrons, the microscopic system can be improved. Figure 14 is an intermediate buffer layer _ oxidation Layer's buffer structure is one of the diode memory devices. • The same oxide structure consists of a metal oxide material 'high dielectric constant material, nitrided, and nitrous oxide, all of which change the stoichiometric and resistive type' can be used to form a resistive device. The different buffer structures are a type of semiconductor (semiconductorMike) layer between the oxide structure and the gate, or between the gate and the substrate, or between the oxide structure and the idle electrode and the gate and Between the substrates. The high melting point and the strong bond of the oxidized hair dominate the qing/set/r ur τ • operation' so the transient and pulse voltages are high. The 'xiao consumption' of the material rate other than Shi Xi/dioxotomy is retained by the self-selection (Self_Sdeeted) property. The buffer layer is, for example, an oxide, a phase change, and a semiconductor material. This buffer layer can be used as a correction characteristic for performing PN diodes. The buffer layer is also a metal, and the device performs a Schottky characteristic. r Limbs 叙 第 第 具有 中间 中间 叙 叙 叙 叙 叙 叙 叙 叙 叙 叙 叙 叙 叙 叙 叙 叙 叙 叙 叙 叙 叙 叙 叙 中间 中间15 201140819 L TV SJ LJJA. Γ\ , a lightly doped n_region is close to the surface in a n+ well region. The first oxide layer formed on the η region is a thickness of u Å, and is formed by in situ steam generation meth〇d. The tantalum nitride layer formed on the first oxide layer has a thickness of 2 Å. y The second oxide layer formed on the tantalum nitride layer is 28 angstroms thick and 2 is formed by a high temperature oxidation method. Different embodiments change different temperatures: thickness 'and material. The pulse width of each Vg pulse is i〇〇ns. Figure 19 is an IV characteristic diagram of the diode memory device of Figure 15. Figure 20 is a periodic diagram of the diode memory device of Figure 15. Each state is extracted at Vg = 2V. Figure 21 is a flow chart showing the operation of the diode memory device. Step 26G2 is performed on the -initial diode memory device. In the step genus, the sexual intercourse is performed on the diode memory device. In step ·, the = reset operation is performed on the diode memory device to place the diode memory device in the reset state. The foregoing, step-by-step and newly manufactured diode memory devices are associated with the preparation of the end user for general use. The next steps are related to the general operation of a diode memory device, e.g., by the end user. In step 2606, the two pole = memory device is in the - reset state. In the step leg, the χ_γ input address of a particular diode memory device in a cross-point array is performed on a diode memory device. In step 2610, the diode memory is placed in the second set state. Multiple diode memory devices can input the address at one time. In step 2614, a reset operation is performed on a diode memory device, for example, a χ-γ input address of a particular diode memory device in the array of intersections. Multiple diode memory devices can be input to the address at one time. Repeating step 2606, the diode memory device is attached to a reset bear. During normal operation, in the diode memory, in step 26〇8, in a reset state (step 2: = take a read operation on a diode memory device) For example, the diode memory device is selected by a Χ·γ input address of a particular diode 6 memory device in an array of cross-points. In step 2612, a set state is provided. In the middle (step 2610), a read operation is performed on the selected one of the diode memory devices. For example, the 'diopolar memory device is a specific diode in the array of one parent cross point. The χγ input address of the memory device is selected. φ Figure 22 is a block diagram of an integrated circuit with an array of diode memory devices, and the control logic is applied to the selected diode memory device. Operationally, for example, reading, setting, and resetting operations. Figure 22 illustrates an integrated circuit 2750 including a diode memory array 2700. The block selects one of the word line decoders 2701 and a plurality of The word line 2702 is coupled and electrically communicated 'and tied in two The bulk memory array 2700 is arranged along a column. A one-bit line decoder 2703 is coupled to a plurality of bit lines 2704 and electrically communicates. This bit line 2704 is in the middle of the diode memory array 2700. The arrangement is set to read 17 201140819 to fetch data and write data into the diode memory cells in the diode memory array 2700. The bus 2705 supplies the address to the word line decoder 27〇1 and the bit. A line decoder 2703. The sense amplifier and data input structures in block 2706 include current sources for reading, programming, and erasing modes, and the sense amplifiers and data input structures in block 2706 pass through the bus 2707 is coupled to bit line decoder 2703. The data is supplied by input/output port on integrated circuit 2750 through data input line 2711 to the data input structure in block 2706. The data is determined by block 2706. The sense amplifier is supplied to the input/output port ' on the integrated circuit 2750 through the data output line 2715 or to other data destinations on the inside or outside of the integrated circuit 2750. The reset, and read bias arrangement state machines are located in circuit 2709, which controls the bias arrangement supply voltage 2708. The bias arrangement bidirectionally switches the state of the memory elements of the diode memory device, such as at SET and RESET. Switching between the two. Figure 23 is a partial schematic diagram of an array of alternating and in-situ memory using the diode memory cells described herein. As shown in the schematic diagram of Figure 23, each memory of the array 1〇〇 The cell system is a diode memory device, which is represented by a diode path access device along a current path between a corresponding word line 11 〇 and a corresponding bit line 120 A resistive memory element (shown as a variable resistor in Figure 23) is connected in series. As described in more detail below, the diode memory device can be programmed into multiple states. The array includes a plurality of word lines 110 (and a plurality of bit lines 120 'word lines 11 〇 including word lines 110a, 110b, and u〇c, and the flat 201140819 extends in a first direction, the bit lines 120 includes bit lines 12〇a, 120b, and i2〇c that extend flatly in a first direction that is perpendicular to the first direction. The array 1〇〇 is referred to as an array of intersections because of the word lines and The bit lines 120 are crossed to each other, but do not actually intersect, and the diode cell lines are located at the intersections of the word line 11 〇 and the bit line 12 。. These memory cells representing the array 1 , are disposed at the intersections of the word line 11 〇 b and the bit line 120 b, and the diode memory cells 115 represent a diode 130 and a series disposed in series. The variable resistor 140. The diode memory cell 115 is electrically connected to the word line and the electrically coupled bit line 120b. Read or write (set/reset) the array 1 〇〇 diode memory cell 115 can be induced by applying an appropriate voltage pulse to the corresponding word line 丨1卟 and bit line 12〇b. Current is applied through the selected memory cell 115. The level and duration of the applied voltage are dependent on the operation, such as a read operation or a program operation (set/reset). The data values in 115 are used in a read (or sense) operation. The bias circuit is coupled to the corresponding word line u〇b and the bit line 120b' to apply a bias arrangement across the appropriate amplitude and duration. The "It is on the cell 115" to induce current flow without causing the memory cell 115 to undergo a state change. The current through the memory cell 115 depends on the resistance' value and the data value of the diode memory device 115. For example, the data value can be calculated using a sense amplifier (eg, a sense amplifier/data input structure) to compare the current on the bit line l2〇b with a suitable reference current and flow through the unselected two poles. The current of the body memory device is reduced or substantially eliminated by the diode in the one-pole memory device selected in 201140819. In the case of the diode device Data value In the programming operation, the 'bias circuit (for example, the bias supply voltage) is coupled to the corresponding word line 11Gb and the bit line, and (10) the bias is arranged across the appropriate amplitude and duration. The data is stored in the memory cell 115 by an induced-programmable change ("reset/reset". The bias arrangement includes a first bias arrangement that is sufficient to forward bias the diode 130 and change two The state of the polar memory device changes from a first programmable state to a second programmable state. The bias arrangement also includes a second bias arrangement that is sufficient to forward bias the diode memory device and will be second The programmable state changes to a first-programmable state. In an embodiment, the per-bias arrangement for unipolar operation of the memory element (10) may include - or a plurality of voltage pulses ' and the voltage level and pulse time may be determined empirically from the various embodiments. Illustrated examples of diode memory cells include phase change based memo material 'including chalcogenide-based materials and other materials chalcogen including oxygen (Ο), sulfur (s) Any one of the four elements of the code (^) and 碲(Te) is a part of the v] family in the periodic table. The chalcogen includes a compound having a polyelectropositive element, a ruthenium root, a chalcogen element. The chalcogenide alloy includes a composition having a crush 2 of other materials. The other material is, for example, a transition metal. A chalcogenant gold # contains one or more elements of the period IVA from the group IVA, such as (Ge) and tin (Sn). Usually, the chalcogenide alloy includes a composition, and the human product g 201140819 , · 1 wou ^ r / \f includes one or more records (Sb), gallium (Ga), marriage (In), and silver (Ag). Many phase change memory materials have been described in the technical literature, including

Ga/Sb, In/Sb, In/Se, Sb/Te, Ge/Te, Ge/Sb/Te, In/Sb/Te, Ga/Se/Te, Sn/Sb/Te, In/Sb/Ge, Ag/In/Sb/Te, Ge/Sn/Sb/Te,

Ge/Sb/Se/Te, and Te/Ge/Sb/S alloys. A loose range of 'alloy compositions' in the Ge/Sb/Te alloy series may be feasible. The composition may have characteristics such as TeaGebSbioo-u+y. One investigator has shown that the most useful alloy has one of the average concentrations of Te in the deposited material preferably φ less than 70% 'typically less than about 60% and usually less than about 23% to about 58%. Te, and the best is between 48% and 58% Te. The concentration of Ge is more than about 5%, and the range in the material ranges from about 8% to about 30% on average, and is generally maintained below 50%. Preferably, the concentration of Ge ranges from about 8% to about 40%. The main constituent element remaining in this composition is Sb. These percentages are the percentage of the atoms of the total ι00% atom of the constituent elements. (Ovshinsky 5,687,112 patent, c〇ls. 10-11.) Specific alloys evaluated by other researchers include Ge2sb2Te5, #GeSb2Te4, and GeSb4Te7. (Noboru Yamada, "Potential of Ge-Sb-Te Phase-Change Optical Disks for High-Data-Rate

Recording',, SPIEV. 3109, pp. 28-37 (1997).) More generally, a transition metal' is, for example, chromium (Cr), iron (Fe), nickel (Ni), niobium (Nb), Pd), platinum (pt), and mixtures or alloys thereof, can be combined with Ge/Sb/Te to form a phase change alloy having programmable resistance type characteristics. A particular example of a useful memory material can be found in 〇vshinsky '112 in columns 11-13, which is incorporated herein by reference. In some embodiments, the chalcogenide and other phase change materials are doped with the impurity 21 201140819 to modify the conductivity, phase transition temperature, melting point temperature, and other characteristics of the memory element using the doped chalcogenide. Representative impurities used to dope the chalcogen include nitrogen, helium, oxygen, cerium oxide, cerium nitride, copper, silver, gold, aluminum, aluminum oxide, lanthanum, oxidized knobs, tantalum nitride, titanium, and titanium oxide. . See U.S. Patent No. 6,800,504, and U.S. Patent Application Serial No. U.S. The phase change alloy system is switchable between a first structural state and a second structural state, wherein the first structural state material is an ordinary crystalline phase, and the second structural state material is active in a memory cell. A generally crystalline crystalline phase of the local sequence of the channel region. These alloys are at least bistable. The amorphous phase is used to refer to a disordered structure, which is more disorderly than a single crystal system. The amorphous phase has a known property, for example, a higher resistivity than a crystalline phase. Refers to a more ordered structure, which is more ordered than an amorphous structure, and the crystalline phase has a known property, for example, a lower resistivity than an amorphous phase. Typically, the phase change material is electrically switchable between different states spanning a local sequence spanning between a completely amorphous state and a fully crystalline state range. Other material properties that are affected by changes between the amorphous phase and the crystalline phase include atomic sequence, free electron cost, and activation energy. The material can be switched between different solid states or between two or more mixed solids, thus providing a gray scale between the fully amorphous and fully crystalline states. Therefore, the electrical properties in this material can vary. By applying an electronic pulse, the phase change alloy can be transformed from one phase to another. It has been observed that a shorter, higher amplitude pulse tends to change the phase change material to a generally amorphous state. A longer, lower amplitude pulse 22 201140819 [vvoujr/\ ' tends to change the phase change material into a one-by-one crystal form. The energy transfer in a shorter, more frequent amplitude pulse is sufficiently clastic to allow the crystal structure of the Moonch 1 and the summer to be short enough to prevent the atoms from being combined into crystals. The appropriate amount of variation for the pulse can be over-realized, ie, specifically, the specific phase-change alloy. In the paragraphs disclosed below, the phase change; # Μ 燹 枓 is called GST, and it can be understood that other types of phase change material g 4 叶 leaf J is used. One material that can be used for PCRAM described herein is Ge2Sb2Te5. Other programmable resistive memory materials can be used in the middle of the diode memory cell, (other embodiments of the structure include other materials that use different crystal phase changes to determine the resistance value, or use - an electronic pulse to change the resistive state Other materials include examples of materials used in resistive random access memory (PRAM), such as metal oxides, including tungsten oxide (\), oxidized recording (Qing), and oxidized sharp (Can 2) , copper oxide ((^〇2), oxidation group (Ta205), oxidation (Al2〇3), oxidation drill (c〇〇), iron oxide (Fe203), antimony oxide (Hf〇2), titanium oxide (Ti 〇2), barium titanate (SrTi03), barium strontium (srZr03), barium titanate ((BaSr) Ti〇3). Additional examples include magnetic memory random access memory (MRAM) Materials such as spin-torque-transfer (STT) MRAM 'for example, like c〇FeB, Fe, c〇, Ni, Gd,

At least one of Dy, CoFe, NiFe, MnAs, MnBi, MnSb, Cr02, Mn0Fe203, Fe0Fe205, Ni0Fe203, MgOFe2, EuO, and Y3Fe5012. For example, please refer to U.S. Patent Application Serial No. 2/7/176,251, entitled "Magnetic Memory Device and Method of Fabricating the Same", which is incorporated herein by reference. 23 201140819 x TV vr λ ri » <Additional examples include solid electrolytic materials or nano-ion memory for programmable-metallization-cell (PMC) memory, such as silver-doped yttrium sulfide electrolytes, and copper-doped yttrium Sulfide electrolytes. For example, see "A macro model of programmable metallization cell devices," by NE Gilbert et al., Solid-State Electronics 49 (2005) 1813-1819, which is incorporated herein by reference. An exemplary method is to use a PVD splash or magnetic splash method using a gas source such as argon, nitrogen, and/or helium at a pressure of 1 to 100 mTorr. This deposition is usually done at room temperature. A projection collimator of 1 to 5 aspect ratio can be used to improve the filling performance. To improve the filling performance, a DC bias of tens of volts to hundreds of volts Alternatively, a combination of DC bias and projection illuminator can be used simultaneously. An exemplary method of forming a chalcogenide material using chemical vapor deposition (CVD) is disclosed in US Patent Application No. 2006/0172067, entitled "Chemical Vapor Deposition of Chalcogenide Materials", incorporated herein by reference. Another exemplary method of forming a chalcogenide material using CVD is disclosed in "Highly Scalable" by Lee, et al. Phase Change Memory with CVD GeSbTe for Sub 50nm Generation", 2007 Symposium on VLSI Technology Digest of Technical Papers, pp· 102-103 o Perform a post-deposition annealing treatment in a vacuum or a nitrogen atmosphere to improve the crystallization of chalcogenide materials The annealing temperature is generally in the range of from 100 to 400 degrees, and the annealing time is less than 30 minutes. 201140819 » 1 woi^^r/\, in summary, although the invention has been disclosed in detail by preferred embodiments and examples As above, it is not intended to limit the invention. It will be apparent to those skilled in the art that the present invention can be modified and modified without departing from the spirit and scope of the invention. Therefore, the scope of the invention is defined by the scope of the appended claims. [Simple diagram of the diagram] Figure 1 shows a diode memory with an intermediate oxide structure.

Body device diagram. Figure 2 is a diagram showing the soft collapse, hard collapse, reset, and setup operation diagrams on the diode memory device of Figure 1. Fig. 3A-3D is a diagram showing the IV characteristics of the different states of the diode memory device of Fig. J. Figure 4 is a timing diagram of the diode memory device of the second diagram. Fig. 5 is a view showing the reading force diagram of the diode memory device of Fig. 1. Figure 6 is a diagram showing the high temperature preservation of the diode memory device of Fig. Fig. 7 is a diagram showing transient current diagrams of different states of the diode memory device of Fig. 1. Figure 8 is a graph showing the iv curve of the memoryless diode device. Fig. 9A is a photograph showing a photo of a diode collapsed δ reciprocal device after a hard breakdown by a negative gate. Figure 9 is a photograph of a diode memory device after a positive gate bias. 25 201140819 i. v\KJUji r\ t * Figure 10A shows a photo of the diode memory device after the reset operation. Fig. 10B is a photograph showing the contact area of the diode memory device after the reset operation. Fig. 10C is a photograph showing the contact area of the diode memory device after the setting operation. Fig. 10D is a photograph showing the contact area of the diode memory device after one cycle in the set state. Figure 11A-11F shows a diagram of a diode memory device in different states. Fig. 12A shows the relationship between the operating voltage versus the size of the diode memory device of Fig. 1. Fig. 12B is a diagram showing the relationship between the operating sulfur and the size of the operating diode device of the first diode. Figure 13 is a diagram showing the different timings of a diode memory device in a second figure after continuous voltage application, showing multiple time programmable for storing multiple bits in a single-diode memory device. Suitability of the application. Fig. 14 is a view showing a diode memory device having an intermediate buffer layer and an oxide layer buffer layer structure. Fig. 15 is a diagram showing a diode device having no - intermediate oxide layer, nitride layer, and oxide layer structure. Figure 6 (6) and (4) Figure 15 shows the hard-headed, reset' and setup operation diagrams on the diode memory device.

Fig. 19 is a view showing the IV characteristic of the diode memory device of Fig. 15. H 26 201140819 4 i · Fig. 20 is a timing chart of the diode memory device of Fig. 15. Figure 21 is a flow chart showing the operation of the diode memory device. Figure 22 is a block diagram of an integrated circuit having an array of diode memory devices, and control logic applied to the operation of the selected diode memory device, such as reading, setting, and Reset operation. Figure 23 is a partial schematic illustration of one of the cross-point memory arrays of the diode memory cells described herein. [Main component symbol description] ® 100 : array 110, 110a, 110b, 110c: word line 115: diode memory cell 120, 120a, 120b, 120c: bit line 130: diode 140: variable resistor 27

Claims (1)

201140819 1 woujr/\ · VII. Patent application scope: 1. An integrated circuit device comprising: a cross-point array comprising a plurality of bit lines and a plurality of word lines, the bits The plurality of intersections of the line and the word lines include a plurality of diode memory devices, the diode memory device comprising: a diode comprising a first end point and a second An end point, the first end point is electrically coupled to one of the bit lines, the second end point is electrically coupled to one of the word lines; and a memory a body element between the first end point and the second end point of the diode, the memory element being bidirectionally switchable between a first memory state and a second memory state, wherein the The diodes of the diode memory device reduce current through the unselected intersections of the bit lines and the intersections of the word lines; and a control circuit, the intersection Array coupling, the control circuit is biased (bias arrangement) Switching to the intersection of one of the bit lines and one of the intersections of the word lines, bidirectionally switching the memory element of the diode memory device at the selected intersection . 2. The integrated circuit device of claim 1, wherein the first end point is in a doped well region and the second end point is part of the word line. 3. The integrated circuit device according to claim 1, wherein the first end point is located in a well area, and the well area has a first concentration of 28 201140819. · i wou^rA4 first a doped state, and the second end point is a portion of the word line, and the diode memory device further includes: a doped region having the first doped state in the well region, the doping The miscellaneous region is located below the memory element and has a second concentration that is less than one of the first concentrations. 4. The integrated circuit device of claim 1, wherein the memory component comprises yttrium oxide. 5. The integrated circuit device of claim 1, wherein the memory element comprises a first ruthenium oxide layer, a tantalum nitride layer on the first ruthenium oxide layer, and One of the second oxidized dream layers on the tantalum nitride layer. 6. The integrated circuit device of claim 1, wherein the memory device comprises a metal oxide, a tantalum nitride, a bismuth oxynitride, a programmable resistive material, and a dielectric constant greater than Any one of the materials of the niobium oxide dielectric constant. 7. The integrated circuit device of claim 1, wherein the diode memory device further comprises at least one of: an upper buffer layer at the first end point and the memory component And a buffer layer located between the second end point and the memory element. 8. The integrated circuit device of claim 1, wherein the control circuit is configured to have a first forward bias of a first set of electrical characteristics to the selected intersection. And switching the memory element from the first memory state to the second memory state of the diode memory device at the selected intersection; and wherein the control circuit is configured to have a second set of electrical second bias biases is arranged to the selected intersection to select the memory component of the diode memory device at the selected intersection from the second memory state Switch to the first memory state. 9. The integrated circuit device of claim 1, wherein the control circuit is located at the selected intersection by inducing a dielectric breakdown induced epitaxy of the memory element. The memory element of the diode memory device is switched from the first memory state to the second memory state; and wherein the control circuit is located by inducing a Joule heating of the memory component The memory element of the diode memory device at the selected intersection switches from the second memory state to the first memory state. 10. The integrated circuit device of claim 1, wherein the first memory state corresponds to the diode memory device having a first diode current and voltage characteristic, and the second memory The state corresponds to the diode memory device having a second diode current-voltage characteristic, wherein the first diode current-voltage characteristic and the second diode current-voltage characteristic have different forward characteristics. 11. The integrated circuit device of claim 1, wherein the memory component is switchable between at least four memory states, the four memory states including the first memory state and the second memory state. 12. A method of operating an integrated circuit 'includes: applying a bias to a plurality of bit lines and a plurality of word lines. 201140819. i woi^jr/\* One of a plurality of intersections is selected Intersection, bidirectionally switching a plurality of memory states of a memory component of one of the diode memory devices at the selected intersection, wherein the diode memory device includes a diode, the diode a first end point and a second end point, and a memory element, the first end point is electrically coupled to one of the bit lines, the second end point and the One of the word lines is electrically coupled, the memory element being located between the first end of the diode and the second end point, and passing through the unselected intersections The current is reduced by the diode of the diode memory device at the intersection of the φ bit lines and the unselected intersections of the word lines. 13. The method of operating an integrated circuit of claim 12, comprising: applying an initial bias to the diode memory device prior to normal operation of the diode memory device, The memory component is changed from an unused state to one of the memory states. 14. The φ method of operating an integrated circuit as described in claim 12, comprising: arranging an initial bias to the diode memory device prior to normal operation of the diode memory device The memory element is changed from an unused state having a non-diode current-voltage characteristic to a memory state of the memory states having a diode current-voltage characteristic. 15. The method of operating an integrated circuit of claim 12, wherein the applying the biasing arrangement comprises: applying a first forward bias having a first set of electrical properties to the The selected intersection, the diode element at the selected intersection 31 201140819 l * · * * 1 The memory element of the memory device is switched from a first memory state to a second memory state; And arranging, by the second forward bias having a second set of electrical properties, the memory component of the selected two-pole memory device to be located at the selected intersection Switching from the second memory state to the first memory state. 16. The method of operating an integrated circuit of claim 12, wherein the biasing arrangement comprises: locating the diode memory at the selected intersection Setting the memory element to induce dielectric collapse induced epitaxy to switch the memory element from a first memory state to a second memory state; and by placing the diode at the selected intersection The memory element of the memory device induces a Joule heating effect to switch the memory element from the second memory state to the first memory state. The method of operating an integrated circuit according to claim 12, wherein a first memory state corresponds to the diode memory device having a first diode current and voltage characteristic, and a second memory The state corresponds to the diode memory device having a second diode current and voltage characteristic, wherein the first diode current voltage characteristic and the second diode current voltage characteristic have different forward characteristics. 18. The method of operating an integrated circuit according to claim 12, wherein the biasing arrangement switches the memory element between a plurality of memory states, wherein the memory states are different. The diode voltage characteristics of the diode. 19. The operating integrated circuit as described in item 12 of the application of the patent 32 201140819 . l w〇i〇jr/\ 1 method wherein the biasing arrangement switches the memory component in at least four memory states. 20. An integrated circuit device comprising: a diode memory device comprising: a diode comprising a first terminal and a second terminal; and a memory component located in the diode Between the first endpoint and the second endpoint, the memory component is bidirectionally switchable between a first memory state and a second memory state; wherein the first endpoint is located with a first One of the first doped states in a concentration has a first doped region in the well region and has a second concentration less than the first concentration; and a control circuit The control circuit is coupled to the diode memory device to bias the memory element of the diode memory device bidirectionally. 33