201140749 六、發明說明： 【發明所屬之技術領域】 本發明是有關於半導體裝置’且特別是有關於一種半導 體裝置的製造方法。 【先前技術】 現有的半導體加工设備中最基本的加工單位為整片晶 圓’而整片晶圓在加工後’不巧*避免地因加工製程的缺陷而有 部分區域發生f性或結财㈣攸。#這料良㈣晶圓總 面積面積的_過高時’若後續再以整片晶圓進行加工處理， 無異於浪費了加工設備的產能’進而增加製程成本，並 製程效率。 一 【發明内容】 本發明的目的就是在提供一種半導體裝置的製造戈 法，可降低製程成本及提高製程效率。 'BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and, more particularly, to a method of fabricating a semiconductor device. [Prior Art] The most basic processing unit in the existing semiconductor processing equipment is the whole wafer 'and the whole wafer is processed after the 'unfortunately* avoids some areas of f- or wealth due to defects in the processing process. (4) Hey. #本料良(4) When the total area of the wafer is too high, the subsequent processing of the entire wafer is equivalent to wasting the throughput of the processing equipment, thereby increasing the process cost and process efficiency. SUMMARY OF THE INVENTION An object of the present invention is to provide a method for fabricating a semiconductor device, which can reduce process cost and improve process efficiency. '
為達成上述目的，本發明提出一種半導體裝置的製幻 2百先，提供承載基底及多個晶圓切片。各晶圓切片具有主 ，表^與背面，其中主動表面與背面相對，且各晶圓切片⑽ 切於主動表面上。接著’在承載基底與晶置 =片=主動表面間形成輪層，以將晶圓切片黏著至承载基肩 。再於各晶圓切片中形成至少—個料通孔而與對應 電性連接。之後’令這些晶圓切片與承載基底分離二 在本發明的較佳實施例中，上述之黏著 於承载基底與_切狀間。 者胃健®案化分句 圓切片與承载 以或得多個晶 在本發明的較佳實施例中，在令上述這些晶 基底分離之後，更包括對各晶圓切片進行切^曰 粒(chip) 〇 在本發明的較佳實施例中，移除上述黏著層的方法包括紫 201140749 外光照射、熱炫、機械剝離或溶劑溶解。 在本發明的較佳實施例中，形成矽導通孔的方法是先在各 晶圓切片中形成至少—個貫孔，接著在晶圓切片的背面形成介 電層’以使介電層填人這些貫孔内。紐，移除位在貫孔内的 部分介電層’以暴露㈣應的連接塾。之後，在這些貫孔内填 入金屬層，以形成與連接墊電性連接的矽導通孔。一 、In order to achieve the above object, the present invention provides a phantom of a semiconductor device, providing a carrier substrate and a plurality of wafer slices. Each wafer slice has a main surface, a front surface and a back surface, wherein the active surface is opposite to the back surface, and each wafer slice (10) is cut on the active surface. A turn layer is then formed between the carrier substrate and the wafer = sheet = active surface to adhere the wafer slice to the carrier shoulder. Further, at least one material via hole is formed in each wafer slice to be electrically connected to the corresponding one. Thereafter, the wafer slices are separated from the carrier substrate. In a preferred embodiment of the invention, the above is adhered to the carrier substrate and the tangential region. In the preferred embodiment of the present invention, after the separation of the crystal substrates, the wafer slicing is further included. Chip) In a preferred embodiment of the invention, the method of removing the above-mentioned adhesive layer includes violet 201140749 external light irradiation, heat smog, mechanical peeling or solvent dissolution. In a preferred embodiment of the present invention, the method of forming the via holes is to form at least one via hole in each wafer slice, and then form a dielectric layer on the back side of the wafer slice to fill the dielectric layer. These are through the holes. New, removes a portion of the dielectric layer located within the via to expose the (four) interface. Thereafter, a metal layer is filled in the through holes to form a meandering via which is electrically connected to the connection pads. One ,
在本發明的較佳實施例中，提供上述晶圓切片的方法可以 是先提供具有至少―個可用區與至少—個不良區的晶圓，然後 沿可用區切割晶圓，以獲得上述晶圓切片。 在本發明的較佳實施例中，上述之承載基底為透明基底。 在本發明的較佳實施例中，其中在形成上述這些 之前，更包括薄化上述這些晶圓切片。 —、孔 。本發明之半導體裝㈣製造綠可先挑㈣各晶圓的可 用區並將其切割下來之後，再將這些晶圓切片黏著在符合機台 規格的承縣底上’以利於進行後續㈣導通孔製程。而且α 2這些晶圓切片是以具暫時性黏著力的黏著層黏著於承載 =士 ’因此可在將晶圓切片切割成晶粒之前先將晶圓切片盘 承載基底分離，以使承載基底具可重複_性。也就是說^ 良率高的部分進行後續製程節省成 ^為讓本發明之上述和其他目的、特徵和優點能更明顯易 懂，下文特舉較佳實施例，並配合所附圖式，作詳細說明如下。 【實施方式】 請參閱圖Μ至圖1Η，其繪示為本發明之—實施例的 體裝置在部分製程中的剖面示意圖。 請參關1Α，首先提供承縣底⑽及多個晶圓切片 4 m 201140749 120。承載基底110可以是透明的圓形基底，以符合現有機台， 但不以此為限。各晶圓切片120分別具有彼此相對的主動表面 122與背面124，且各晶圓切片120可包括至少一個連接墊 126，位於主動表面122上。具體來說，連接墊126是與形成 在晶圓切片120之主動表面122上的線路（圖未示）電性連接。 除此之外’晶圓切片120的主動表面122上已形成有至少一個 半導體元件128 ’其是透過線路與連接墊126而與外部電路電 性連接。在本實施例中，半導體元件128例如是微透鏡陣列 (micro lens array)及彩色遽光片（c〇i〇r filter)陣列，但本發明不 • 以此為限。 值得一提的是’這些晶圓切片120可以是來自同一片晶 圓，也可以是來自不同片晶圓。詳細來說，如圖2A所示，本 實施例係先提供具有已知的可用區1〇2與不良區1〇4的晶圓 忉〇，然後再如圖2B所示，沿可用區W2切割晶圓10〇，以獲 得晶圓切片120。換言之’晶圓切片12〇是透過切割下晶圓1〇〇 的可用區102而得。 請參閱圖1B，在承載基底110與晶圓切片120的主動表 鲁面122間形成黏著層13〇 ,以將晶圓切片12〇黏著至承载基底 上。在本實施例中，黏著層13〇可佈滿於晶圓切片12〇的 主動表面122與承載基底Π0之間。特別的是，黏著層13〇是 八有暫時性黏著力的黏著層，例如紫外膠、熱炫膠或者可以溶 劑將其溶解的可溶解膠，但本發明不以此為限。 7 (J請參閱圖1C，從這些晶圓切片120的背面124進行薄化 製程’以縮減晶圓切>1 12G的厚度。而本實施例之晶圓切片 120在薄化製程後的厚度約介於1〇〇〜2⑽微米之間但本發 明不以此為限，熟習此技藝者可自行依據實際需求而定。 201140749 請參閱圖ID至圖if’於各晶圓切片12〇中形成至少一個 石夕導通孔m而與連接塾126電性連接。詳細來說，形成 通孔127的方法係先在各晶圓切片12G中形成至少—個貫孔 127a’如圖1D所示，而形成貫孔12乃的方法可以是雷射穿孔 或深反應式離子蝕刻（deep reactive ion etching，DRIE)，但不以 此為限。 一 請再參閱圖1E，接著在晶圓切片12〇之背面124上形 介電層127b，並使其填入貫孔127a内。然後，移除位於貫孔 127a内以及連接墊126表面上之部分介電層127b，以暴露出 連接墊126。在本實施例中，介電層12几例如是二氧化矽， 但不以此為限。而移除位於部分介電層127b之方法可以是 用雷射或殊反應式離子餘刻，但不以此為限。 ^之後，請參照圖1F，在貫孔127a内填入金屬層127c，而 形成與對應之連接墊126電性連接的矽導通孔丨27。在此，金 屬層127c即是藉由介電層mb而與晶圓切片12〇電性絕緣， 以避免各矽導通孔127之間發生短路的問題。而且，各金屬層 =7c係自對應之貫孔127a延伸至該晶圓切片12〇的背面124。 •詳，來說，形成金屬層127C的方法是先在這些晶圓切片12〇 的背面124上形成一層金屬層129a，如圖3A所示，以填滿各 晶圓切片120的貫孔127a。然後，如圖3B所示，移除位於晶 圓切片120之背面124上的部分金屬層129a。舉例來說，、= 在晶圓切片120之背面124上的部分金屬層129a例如是透過 化學機械研磨（Chemical Mechanical Polishing，CMP)的方式而 移被除。 "" 後續，於晶圓切片120之背面124上形成圖斤所示之多 個金屬圖案129b，而分別與金屬層129a電性連接。也就是說， m 6 201140749 本實施例之金屬層127c是由金屬層129a與金屬圖案i29b所 構成’其辛金屬層129a與金屬圖案129b的材質不同，但本發 明不限於此。在其他實施例中，金屬層127c也可以是形成 在晶圓切片120之背面124上，並共形地填入貫孔127a内的 單一膜層，如圖4所示。在此，金屬層127(1可由高導電材料 例如銅、鋁或者其他高導電材料製成，但不以此為限。 在形成金屬層127c後，令晶圓切片12〇與承載基底il〇 分離，如圖1G所示。具體來說，本實施例例如是以紫外光照 射黏著層130、熱熔黏著層13〇、利用機械力將晶圓切片12〇 ♦自承載基底110上剝離或以溶劑溶解黏著層13〇等方式來分離 晶圓=片12:與承載基底11G，但本發明不以此為限。 需要注意的是，雖然本實施例是將黏著層130佈滿於承載 基底110與晶圓切片12〇之間，但在其他實施例中，如圖$所 示，黏著層130還可呈圖案化地分佈於承載基底11〇與晶圓切 片120之間，而不與晶圓切片12〇之主動表面122上的元件接 觸，以避免在移除黏著層130時損壞這些半導體元件128。 、請參閱圖1H’本實施例在將晶圓切片12〇與承載基底11〇 •分離之後，更接著對各晶圓切片進行切割，以獲得多個晶 粒200供後續封裝製程使用。舉例來說，這些晶粒2⑽可以是 CMOS〜像感測器、微機電系統晶粒、高頻半導體元件或是其 他無須彼此堆叠封裝的半導體晶粒，但本發明不以此為限。 曰綜上所述’本發明之半導體裝置的製造方法可先挑選出各 =圓的可用區並將其切割下來之後，再將這些晶圓切片黏著在 符合機台規，的承載基底上，以進行後續製程。也就是說，本 心明可^·對單片晶圓中良率高的部分進行後續製程，以節省成 本並提高總製程良率。 201140749 而且，這些晶圓切片可以藉由具暫時性黏著力的黏著層黏 者於承載基底上’並且在將晶圓切片切割成晶粒之前，先將晶 圓切片與承載基底分離。如此一來，承載基底即可重藉倍用， 以進一步降低製程成本。 雖然本發明已以較佳實施例揭露如上，然其並非用以限定 本發任何m技藝者，在*脫離本發明之精神和範 内’ 些許之更動與卿，因^ 附之申請專利範圍所界定者為準。德 ⑽圍田視後 【圖式簡單說明】In a preferred embodiment of the present invention, the method for providing the wafer slicing may be to first provide a wafer having at least one available region and at least one defective region, and then cutting the wafer along the available region to obtain the wafer. slice. In a preferred embodiment of the invention, the carrier substrate is a transparent substrate. In a preferred embodiment of the invention, wherein the wafer slices are further thinned prior to forming the above. —, hole. The semiconductor device of the present invention (4) can be used to manufacture the green (4) available regions of each wafer and then cut them, and then paste the wafer slices on the bottom of the Chengxian County that meets the specifications of the machine to facilitate subsequent (four) vias. Process. Moreover, the α 2 wafer slices are adhered to the carrier by a temporary adhesive layer, so that the wafer slice carrier substrate can be separated before the wafer is sliced into crystal grains, so that the carrier substrate is provided. Repeatable _ sex. In other words, the above-mentioned and other objects, features and advantages of the present invention will become more apparent and obvious. The following detailed description of the preferred embodiments and the accompanying drawings The details are as follows. [Embodiment] Referring to the drawings to Fig. 1A, there is shown a cross-sectional view of a body device according to an embodiment of the present invention in a partial process. Please refer to 1Α, first provide Chengxian bottom (10) and multiple wafer slices 4 m 201140749 120. The carrier substrate 110 may be a transparent circular substrate to conform to the existing machine, but is not limited thereto. Each wafer slice 120 has an active surface 122 and a back surface 124 opposite each other, and each wafer slice 120 can include at least one connection pad 126 on the active surface 122. In particular, the connection pads 126 are electrically coupled to circuitry (not shown) formed on the active surface 122 of the wafer slice 120. In addition to this, at least one semiconductor element 128' has been formed on the active surface 122 of the wafer slice 120, which is electrically connected to the external circuit through the wiring and the connection pad 126. In the present embodiment, the semiconductor element 128 is, for example, a micro lens array and a color filter array, but the invention is not limited thereto. It is worth mentioning that these wafer slices 120 may be from the same wafer or from different wafers. In detail, as shown in FIG. 2A, the present embodiment first provides a wafer cassette having a known usable area 1〇2 and a defective area 1〇4, and then cut along the usable area W2 as shown in FIG. 2B. The wafer is 10 Å to obtain a wafer slice 120. In other words, the wafer slice 12 is obtained by cutting the available area 102 of the lower wafer 1 . Referring to FIG. 1B, an adhesive layer 13A is formed between the carrier substrate 110 and the active surface 122 of the wafer slice 120 to adhere the wafer slice 12 to the carrier substrate. In this embodiment, the adhesive layer 13 can be filled between the active surface 122 of the wafer slice 12A and the carrier substrate Π0. In particular, the adhesive layer 13 is an adhesive layer having a temporary adhesive force, such as an ultraviolet glue, a hot glue or a dissolvable glue which can be dissolved by a solvent, but the invention is not limited thereto. 7 (J. See FIG. 1C, the thinning process is performed from the back surface 124 of the wafer slice 120 to reduce the thickness of the wafer cut > 1 12 G.) The thickness of the wafer slice 120 of this embodiment after the thinning process It is between about 1 〇〇 and 2 (10) micrometers, but the invention is not limited thereto, and those skilled in the art can determine according to actual needs. 201140749 Please refer to the figure ID to figure if' in each wafer slice 12〇 The at least one conductive via hole m is electrically connected to the connection port 126. In detail, the method of forming the via hole 127 is to form at least one through hole 127a' in each wafer slice 12G as shown in FIG. 1D. The method of forming the through holes 12 may be laser perforation or deep reactive ion etching (DRIE), but not limited thereto. Please refer to FIG. 1E again, and then on the back of the wafer slice 12〇 The upper dielectric layer 127b is shaped and filled into the through hole 127a. Then, a portion of the dielectric layer 127b located in the through hole 127a and on the surface of the connection pad 126 is removed to expose the connection pad 126. In this embodiment For example, the dielectric layer 12 is, for example, cerium oxide, but is not limited thereto. The method of removing the portion of the dielectric layer 127b may be a laser or a special reactive ion remnant, but not limited thereto. After that, referring to FIG. 1F, the metal layer 127c is filled in the through hole 127a. The via hole 丨 27 is electrically connected to the corresponding connection pad 126. Here, the metal layer 127c is electrically insulated from the wafer slice 12 by the dielectric layer mb to avoid the respective via holes 127. A problem of short circuit occurs between them. Moreover, each metal layer = 7c extends from the corresponding through hole 127a to the back surface 124 of the wafer slice 12A. • Specifically, the method of forming the metal layer 127C is first in the crystal A metal layer 129a is formed on the back surface 124 of the 12-turn circular slice, as shown in FIG. 3A, to fill the through hole 127a of each wafer slice 120. Then, as shown in FIG. 3B, the back surface of the wafer slice 120 is removed. A portion of the metal layer 129a on the portion 124 of the wafer slice 120. For example, the portion of the metal layer 129a on the back surface 124 of the wafer slice 120 is removed by, for example, chemical mechanical polishing (CMP). " Subsequent, forming a map on the back side 124 of the wafer slice 120 The plurality of metal patterns 129b shown in the figure are electrically connected to the metal layer 129a. That is, m 6 201140749 The metal layer 127c of the present embodiment is composed of a metal layer 129a and a metal pattern i29b. 129a is different from the material of the metal pattern 129b, but the invention is not limited thereto. In other embodiments, the metal layer 127c may also be formed on the back surface 124 of the wafer slice 120 and conformally filled into the through hole 127a. A single film layer, as shown in Figure 4. Here, the metal layer 127 (1 may be made of a highly conductive material such as copper, aluminum or other highly conductive material, but not limited thereto. After the metal layer 127c is formed, the wafer slice 12〇 is separated from the carrier substrate il〇 Specifically, in this embodiment, for example, the adhesive layer 130, the hot-melt adhesive layer 13A are irradiated with ultraviolet light, and the wafer slice 12 ♦ is peeled off from the carrier substrate 110 by mechanical force or by solvent. Dissolving the adhesive layer 13 or the like to separate the wafer = sheet 12: and the carrier substrate 11G, but the invention is not limited thereto. It should be noted that although the embodiment is to fill the adhesive layer 130 with the carrier substrate 110 and The wafer slices are between 12 turns, but in other embodiments, as shown in FIG. $, the adhesive layer 130 may also be patterned to be distributed between the carrier substrate 11 and the wafer slice 120 without wafer slicing. The elements on the active surface 122 are contacted to avoid damaging the semiconductor elements 128 when the adhesive layer 130 is removed. Referring to FIG. 1H', the present embodiment separates the wafer slice 12〇 from the carrier substrate 11 And then cutting each wafer slice, A plurality of dies 200 are obtained for use in subsequent packaging processes. For example, the dies 2 (10) may be CMOS~image sensors, MEMS die, high frequency semiconductor components, or other semiconductor dies that do not need to be stacked on each other. However, the present invention is not limited thereto. In summary, the manufacturing method of the semiconductor device of the present invention can first select the available areas of each circle and cut them, and then stick the wafer slices in accordance with the method. The machine is on the load-bearing substrate for subsequent processing. That is to say, Benxin Ming can make subsequent processes for the high-yield part of the single wafer to save cost and improve the total process yield. Moreover, the wafer slices can be adhered to the carrier substrate by an adhesive layer having a temporary adhesion, and the wafer slice is separated from the carrier substrate before the wafer slice is cut into the die. The carrier substrate can be reused to further reduce the process cost. Although the present invention has been disclosed in the preferred embodiment as above, it is not intended to limit any of the present techniques. The spirit and scope of the present invention may be subject to the definition of patent application scope. (10) After the field is considered as a short description of the drawings
对八^二至圖出繪示為本發明之—實施例中半導體裝置在 口 P为製程中的剖面示意圖。 夕古2B繪示為本發明之一實施例中提供晶圓切片 之方法的不意圖。 全屬，二ΐ圖3B綠示為本發明之一實施例中在貫孔中形成 金屬層的流程剖面圖。 剖面^音圖騎發明之—實施例巾半導體裝置在部分製程中的The figure is a cross-sectional view of the semiconductor device in the process of the present invention in the process of the present invention.夕古2B illustrates the notion of a method of providing wafer dicing in one embodiment of the present invention. Figure 3B is a cross-sectional view showing the flow of a metal layer formed in a through hole in an embodiment of the present invention. Profile ^ sound map riding invention - the embodiment of the semiconductor device in part of the process
圖5繪示為本發明 中的剖面示意圖。 之一實施例中半導體裝置在部分製程 【主要元件符號說明】 100 ·晶圓 102 :可用區 104 :不良區 110 ·承載基底 120 .晶圓切片 122 :主動表面 201140749 124 :背面 126 :連接墊 127 :矽導通孔 127a :貫孔 127b :介電層 127c、129a :金屬層 12% :金屬圖案 128 :半導體元件 130 :黏著層 200 ·晶粒Figure 5 is a schematic cross-sectional view showing the present invention. In one embodiment, the semiconductor device is in part process [main component symbol description] 100. Wafer 102: usable area 104: defective area 110 · carrier substrate 120. wafer slice 122: active surface 201140749 124: back surface 126: connection pad 127 : 矽 via hole 127a : through hole 127b : dielectric layer 127c, 129a : metal layer 12% : metal pattern 128 : semiconductor element 130 : adhesive layer 200 · grain