201138306 六、發明說明： 【發明所屬之技術領域】 本發明是有關於-種緩衝電路，特別是指一種緩衝電 路及包含該緩衝電路的資料驅動器。 【先前技術】 由於源極隨輕器（_rce foll。wer)具有源極之於間極的 電壓增益近似於i的特性，且具有高輸入電阻、低輸出電 卩的特f生所以常被用來當作緩衝電路，以隔離前後級電 路的負載效應，並使閘極電壓完整地傳遞到源極端來做為 緩衝電路的輸出電壓。 但實際上，源極電壓除了受控於資料電壓外，還受押 於源極隨麵器的電晶體臨界電壓。不幸地，非晶棟㈣ 成的電晶體在經過長時間操作後，其臨界電壓會產生變異 ，並且〇4個變異量會因資料電壓不同而改變。 因此’產學界紛紛提出多種方法，試圖降低臨界電壓 對輸出電壓的影響。例如：透過增加緩衝電路的元件個數 來改善’但過多的元件會造成操作不穩定，致使輸出電壓 難以維持定值。 【發明内容】 因此，本發明之目的，即在提供一種緩衝電路，以少 數控制信號’即能補償源極隨耦器的電晶體臨界電壓變異 對緩衝電路輸出電壓的影響。 而本發明之另一目的，即在提供一種資料驅動器，能 將一資料電壓完整地傳遞給後級電路。 201138306 於是，本發明緩衝電路，適用於耗接一負載電容，包 括：一開關，接收-資料電壓，並根據一掃描信號切換地 輪出該資料電壓；及-補償電路’具有一驅動電晶體，該 補償電路根據-第一控制信號和—第二控制信號來產生一 相當於該㈣電晶體臨界電壓的壓降；該負載電容會根據 -亥第一控制#號、該資料電壓與該壓降進行充電，而改變 自身跨壓，且當该負載電容的跨壓相當於該資料電壓時， 該負載電容便停止充電。 而本發明資料驅動器，適用於耦接一負載電容，包含 .一暫存電路，用以接收一輸入電M，並根據該輸入電壓 送出一貝料電壓；及一緩衝電路，電連接該暫存電路且包 括：一_，接收該資料電壓，並根據一掃描信號切換地 輸出該資料電壓；及一補償電路，具有一驅動電晶體，該 補償電路根據一第一控制信號和一第二控制信號來產生一 相當於該驅動電晶體臨界電壓的壓降；該負載電容會根據 该第二控制信號、該資料電壓與該壓降進行充電而改變 自身跨壓，且當該負載電容的跨壓相當於該資料電壓時， 該負載電容便停止充電。 【實施方式】 有關本發明之前述及其他技術内容、特點與功效，在 以下配合參考圖式之一個較佳實施例的詳細說明中，將可 清楚的呈現。 參閱圖1，本發明資料驅動器10〇之較佳實施例適用於 接收一輸入電壓並據以送出一驅動電壓ν〇υτ給—像素電路 201138306 200。資料驅翻# -緩衝電路丨 電連接的一暫存電路101及 G2°當該暫存電路1G1根據該輸人 緩衝電路1〇2會起緩衝作用根據該資料電壓 電壓V〇UT來提供給—像素電路200，而降低暫 子電路101與像素電路2〇〇間的負載效應。 - 1具有 路102包括一開關1及一補償電路2。該開關 1具有-開關電晶體η’該補償電路 賴91' 钴 ^ 至置电曰目 —重置電晶體22、一驅動電晶體23，以 合電容24。卷帝曰碰” 祸 母—電晶體11、21〜23具有一第一端、一第二 端和一控制端。詳細連接情形可參考圖卜並說明如下。 該：合電容24的一端(下稱八點越第一重置電晶體 的第-端，且耗接驅動電晶體23的控制端。該轉合電容 24的另一端(下稱Β點)耦接開關電晶體u的第二端且耦 =二重置電晶體22的第一端。並且’驅動電晶體^的 第-端會和該第二重置電晶體22的第二端耗接在—起形成 一個送出該驅動電壓V〇uj輸出端，且這個輸出端會電連 接到像素電路200的一負載電容2〇1。 此外，開關電晶體11的第一端和第一重置電晶體21的 第一端分別接收該資料電壓。開關電晶體u的控制端接收 —掃描信號SCAN，該二個重置電晶體21、22的抑制端八 別接收-第一控制信號CTRL1。並且，做為_源：隨柄： 之主要晶體的驅動電晶體23會接收_第二控制信號CM〗 〇 當開關電晶體1!根據該掃描信號SCAN切換地輸出該 6 201138306 資料電壓，該眘4aL + ^ 傳遞到驅動電晶：由開關電晶體11和搞合電容24 23藉由复笛-山3的控制端（即閘極），提供驅動電晶體 。 端（即源極）對該負載電容201進行充電的參考 本實施例中 重置階段 這些信號的時序如圖2所示。 仗岈間t0〜tl的重置階段 〜z且丨白十又，貝科m壓=〇乂（伏特），201138306 VI. Description of the Invention: [Technical Field] The present invention relates to a buffer circuit, and more particularly to a buffer circuit and a data driver including the same. [Prior Art] Since the source follower (_rce foll.wer) has a source-to-interpole voltage gain similar to i, and has a high input resistance and low output power, it is often used. It is used as a buffer circuit to isolate the load effect of the front and rear stage circuits and to pass the gate voltage completely to the source terminal as the output voltage of the buffer circuit. However, in fact, in addition to being controlled by the data voltage, the source voltage is also subjected to the transistor threshold voltage of the source follower. Unfortunately, the amorphous voltage (4) of the transistor after a long period of operation, its threshold voltage will be mutated, and the four variations will vary due to the data voltage. Therefore, the industry has come up with a variety of methods to try to reduce the impact of the threshold voltage on the output voltage. For example, it is improved by increasing the number of components of the snubber circuit. However, excessive components cause unstable operation, making it difficult to maintain a constant output voltage. SUMMARY OF THE INVENTION Accordingly, it is an object of the present invention to provide a snubber circuit that compensates for the effect of the threshold voltage variation of the source follower on the output voltage of the snubber circuit with a small number of control signals. Another object of the present invention is to provide a data driver that can completely transfer a data voltage to a subsequent stage circuit. 201138306 Thus, the snubber circuit of the present invention is adapted to consume a load capacitor, comprising: a switch, receiving-data voltage, and switching the data voltage according to a scan signal; and the compensation circuit has a driving transistor. The compensation circuit generates a voltage drop corresponding to the critical voltage of the (IV) transistor according to the first control signal and the second control signal; the load capacitance is based on the -1 first control #, the data voltage and the voltage drop Charging is performed to change its own voltage across the load, and when the voltage across the load capacitor is equivalent to the data voltage, the load capacitor stops charging. The data driver of the present invention is adapted to be coupled to a load capacitor, comprising: a temporary storage circuit for receiving an input power M, and sending a billet voltage according to the input voltage; and a buffer circuit electrically connecting the temporary storage The circuit further includes: a_ receiving the data voltage, and switching the data voltage according to a scan signal; and a compensation circuit having a driving transistor, wherein the compensation circuit is based on a first control signal and a second control signal Generating a voltage drop corresponding to the threshold voltage of the driving transistor; the load capacitance is charged according to the second control signal, the data voltage and the voltage drop to change its own voltage across the load, and when the load capacitance is equivalent to the voltage across the load At the voltage of the data, the load capacitor stops charging. The above and other technical contents, features, and advantages of the present invention will be apparent from the following detailed description of the preferred embodiments. Referring to Figure 1, a preferred embodiment of the data driver 10 of the present invention is adapted to receive an input voltage and thereby send a drive voltage ν 〇υ τ to the pixel circuit 201138306 200. Data flooding # - snubber circuit 一 electrically connected to a temporary storage circuit 101 and G2 ° when the temporary storage circuit 1G1 according to the input snubber circuit 1 〇 2 will be buffered according to the data voltage voltage V 〇 UT to provide - The pixel circuit 200 reduces the load effect between the temporary sub-circuit 101 and the pixel circuit 2〇〇. - 1 has a circuit 102 comprising a switch 1 and a compensation circuit 2. The switch 1 has a -switching transistor η' which is coupled to the capacitor 24 by a resetting transistor 22, a reset transistor 22, and a reset transistor.卷 曰 ” ” 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电 电The eighth end of the first reset transistor is called the eighth end, and the control end of the driving transistor 23 is consumed. The other end of the switching capacitor 24 (hereinafter referred to as the defect) is coupled to the second end of the switching transistor u. And coupling = two to reset the first end of the transistor 22. And the first end of the 'driving transistor ^ and the second end of the second reset transistor 22 are connected to form a driving voltage V The output terminal of the 〇uj is electrically connected to a load capacitor 2〇1 of the pixel circuit 200. Further, the first end of the switching transistor 11 and the first end of the first reset transistor 21 respectively receive the data Voltage. The control terminal of the switching transistor u receives the scan signal SCAN, and the suppression terminals of the two reset transistors 21, 22 receive the first control signal CTRL1. Also, as the source: the handle: the main The crystal drive transistor 23 will receive the _second control signal CM〗 开关 When switching the transistor 1! According to the scan No. SCAN switches the output of the 6 201138306 data voltage, which is passed to the driving transistor: by the switching transistor 11 and the engaging capacitor 24 23 by the control end of the whistle-mountain 3 (ie the gate) Driving the transistor. The terminal (ie, the source) charges the load capacitor 201. The timing of these signals in the reset phase in this embodiment is as shown in FIG. 2. The reset phase of the t0~tl is zz and 丨White ten, Beike m pressure = 〇乂 (volts),
=信號CTRL2與掃描信號SCAN為低電位， 二 制信號CTRL!是高電位_ 控 此時：如圖3所示’第一重置電晶體21的第一、二蠕 通’使得A點呈現如資料電壓般的0V。而第二重置電晶 〇驅動電晶體23也導通，使得耦合電容Μ根據低電 位的第—控制信號CTRL2進行放電而降低耦合電容Μ 壓，以讓B點降為〇v。 補償階段 • 回復參閱圖2，在時間U〜t2的補償階段，資料電壓維 持〇v(伏特）’掃描信號SCAN維持低電位，控制信銳 CTRL1、CTRL2均為高電位。 此時，如圖4所示，該第一重置電晶體21仍導通，a .點保持ον。且第二重置電晶體22與驅動電晶體23也導通 ，使得耦合電容24根據高電位的第二控制信號CTRL2進行 充電而加大耦合電容24的跨壓，直到B點電壓=(_1)χ「驅 動電晶體23之臨界電壓VTH」。 資料電壓輪出階段 201138306 回復參閱圖2,在時間t2~t3的資料電壓輸出階段，第 二控制信號CTRL2維持高電位，資料電壓幅值增為Vdata ’知描信號SCAN改為高電位，第一控制信號cTRu改為 低電位。 ^時’如圖5所示，該兩個重置電晶體21、22的第一 、一端都不導通。但開關電晶體11的第-、第二端導通而 讓、=電壓=VDATA ’加上麵合電容24的麵合效應，A點電 壓遂增為vDATA+vTH，使得驅動電晶體23導通。 之後，負載電容201根據高電位的第二控制信號 CTRL2進行充電，也根據耦合電容24的跨壓進行充電，來 提升負載電容201的跨壓(即一驅動電Μ ν〇υτ)。此時，驅 動電晶體23產生的的驅動電流Idrwe大小如下： I drive 二 K(yGS _vTHf =K((VDATA + ^ΤΗ - y〇UT ) - VTH f ⑴ 其中，VGS代表驅動電晶體23控制端之於第二端的電 壓，κ代表驅動電晶體23的元件轉導參數（deWce trans_ conductance parameter) ° 直到驅動電壓V0UT的大小提升到Vdata，驅動電流 Idrive降為〇 ’驅動電晶體23轉為不導通，負載電容2〇1便 停止充電動作形成穩定狀態。且在下一次重置階段之前， 負載電容201都會維持住這個驅動電壓v〇ut=Vdata。 回復參閱圖1，總結來說，在補償階段時，補償電路2 會讓耦合電容24產生電壓大小=「驅動電晶體23之臨界電 壓」的壓降’即A、B點的電壓差。之後，在資料電壓輸出 201138306 階段時’補償電路2再利用這個壓降來補償，使得負載電 容2〇1《電停止後，驅動„ v晰僅會反應資料電壓 Vdata的值。 因此’緩衝電路102送出的驅動電壓V0UT僅相關於收 到的資料電壓’即使驅動電晶體23因長期使用而造成臨界 電壓VTH發生變異，也不會影響驅動電壓ν〇叮值。此外， 本實施例使用的信號時序相對簡I，足以讓電路完全地充= signal CTRL2 and scan signal SCAN are low, binary signal CTRL! is high potential _ control at this time: as shown in Figure 3 'first reset transistor 21 first, second creep" makes point A appear as The data voltage is 0V. The second reset transistor driver transistor 23 is also turned on, so that the coupling capacitor 放电 discharges according to the low-level first control signal CTRL2 to lower the coupling capacitor voltage to lower the point B to 〇v. Compensation phase • Referring back to Figure 2, during the compensation phase of time U~t2, the data voltage is maintained at 〇v (volts). The scan signal SCAN is kept low, and the control signals CTRL1 and CTRL2 are both high. At this time, as shown in FIG. 4, the first reset transistor 21 is still turned on, and the point remains ον. And the second reset transistor 22 and the driving transistor 23 are also turned on, so that the coupling capacitor 24 is charged according to the high potential second control signal CTRL2 to increase the voltage across the coupling capacitor 24 until the voltage at point B = (_1) χ "The threshold voltage VTH of the driving transistor 23". Data voltage rotation stage 201138306 Reply to Figure 2, in the data voltage output stage of time t2~t3, the second control signal CTRL2 maintains a high potential, and the data voltage amplitude is increased to Vdata 'Knowledge signal SCAN is changed to high potential, first The control signal cTRu is changed to a low potential. As shown in Fig. 5, the first and one ends of the two reset transistors 21, 22 are not turned on. However, the first and second ends of the switching transistor 11 are turned on, and = voltage = VDATA' plus the surface sealing effect of the upper combining capacitor 24, and the voltage at point A is increased to vDATA + vTH, so that the driving transistor 23 is turned on. Thereafter, the load capacitor 201 is charged according to the second control signal CTRL2 of the high potential, and is also charged according to the voltage across the coupling capacitor 24 to increase the voltage across the load capacitor 201 (i.e., a driving voltage ν ντ). At this time, the driving current Idrwe generated by the driving transistor 23 is as follows: I drive 2 K (yGS _vTHf = K((VDATA + ^ΤΗ - y〇UT ) - VTH f (1) where VGS represents the control terminal of the driving transistor 23 For the voltage at the second terminal, κ represents the component transduction parameter of the driving transistor 23 (deWce trans_ conductance parameter) ° until the magnitude of the driving voltage VOUT is increased to Vdata, and the driving current Idrive is reduced to 〇' the driving transistor 23 is turned non-conductive. The load capacitor 2〇1 stops the charging action and forms a steady state. Before the next reset phase, the load capacitor 201 maintains the driving voltage v〇ut=Vdata. The reply is shown in Figure 1, in summary, during the compensation phase. The compensation circuit 2 causes the coupling capacitor 24 to generate a voltage drop = "the voltage drop of the threshold voltage of the driving transistor 23", that is, the voltage difference between points A and B. Then, at the stage of the data voltage output 201138306, the compensation circuit 2 is reused. This voltage drop is compensated so that the load capacitance is 2〇1. After the power is stopped, the drive „v is only reflected by the value of the data voltage Vdata. Therefore, the drive voltage V0 sent by the buffer circuit 102 The UT is only related to the received data voltage 'even if the threshold voltage VTH is mutated due to long-term use of the driving transistor 23, and the driving voltage ν〇叮 value is not affected. Moreover, the signal timing used in this embodiment is relatively simple, Enough to make the circuit fully charged
電或放電，使得資料電壓能完整地傳至像⑽的負 載電容201。 以下更提出-些模擬數據和實驗數據來佐證。 模擬數據 參閲圖6的H-SPICE模擬結果，其說明了縱使驅動電 晶體23之臨界電壓Vth發生變異，驅動電壓v謝都會相等 於資料電壓。而且’不管臨界電壓變異值為〇v、'v、 2V或3V(伏特），都能滿足這個相等關係。 圖7的H_SPICE模擬結果更繪出了 1料電壓減去驅 動電壓VOUT的結果，相對於資料電壓的關係圖。從圖中， 可以觀察到與純…2V < 3V的臨界電壓變異值心相 比，資料電壓與驅動電壓Vgut的差異全都限縮在㈣内。 實驗數據 參閱圖8,其是利用非晶相銦鎵鋅氧化物(aiGz〇, A·—1" InGaZn〇)透明電晶體的實驗模擬結果。很明顯 地’驅動電壓V〇UT幾近於資料電壓，所以可以推論本實施 例能夠適用於a-IGZO製程。 201138306 參閱圖9,與-習知源極隨輕器相比，在同樣具有臨界 電壓變異值IdV的情況下，以實線繪製的本實施例驅動 電Μ νουτ幾近於資料電壓，但是以虛線㈣的習知源極隨 ㈣”比資㈣壓少了 2V左右，造成資料電麼 不能完整地傳遞到像素電路200。 參閱圖10值得注意的是，在另一實施例中該開關 電晶體11所接收的資料電壓也可以改為總是高電位的 v嶋，且較佳地’在這種情況下，該第一重置電晶體21會 收到一個低電位的參考電壓。 麵 且值得注意的是，前述該等電晶體11、21〜23均為以 非晶石夕（a-Si)製程製得的N型電晶體，存在著載子移動率低 的先天缺,fi 以本例以少數條控制信號來決定晶體操作 時序’可有效彌補此一缺點。但實際應用不應以非晶石夕製 程的晶體為限。並且，本例的緩衝料1〇2是可獨立出於 該資料驅動器100。 綜上所述，本實施例緩衝電路102在補償階段先利用 控制k號CTRL1、CTRL2來產生-個電壓大小=「驅動電_ 晶體23之臨界電壓」的壓降，再於資料電壓輸出階段藉助 k個壓降提升驅動電晶H 23之控制端電座’使達充電穩定 狀態的驅動電壓v0UT=vDATA，而不受臨界電壓VrrH影響， 因此 > 料電壓能穩定且完整地送到像素電路2〇〇，故確實能 達成本發明之目的。 惟以上所述者，僅為本發明之較佳實施例而已，當不 能以此限定本發明實施之範圍，即大凡依本發明申請專利 10 201138306 範圍及發明說明内容所作之簡單的等效變化與修飾，皆仍 屬本發明專利涵蓋之範圍内。 【圖式簡單說明】 圖1是一電路圖’說明本發明資料驅動器之較佳實施 例； 圖2是一時序圖’說明本實施例緩衝電路所接收信號 的時序； 圖3是一示意圖，說明緩衝電路於重置階段的等效電 路； 圖4是一示意圖’說明緩衝電路於補償階段的等效電 路； 圖5是一不意圖，說明緩衝電路於資料電壓輸出階段 的等效電路； 圖6是一模擬示意圖，說明H spiCE的模擬結果展現 出縱使臨界電壓發生變異’驅動電壓仍相等於資料電壓； 圖7是一模擬示意圖，說明H_spiCE的模擬結果展現 出資料電壓與驅動電壓間僅存在些微差異； 圖8是-模擬示意圖，說明以a_IGZ〇電晶體來模擬， 驅動電壓幾近於資料電壓； 圖9是一模擬示意圖，說明相較於習知源極隨搞器， 本實施例的驅動電壓幾近於資料電壓；及 圖10是一電路圖，說明本發明資料驅動器之另一較佳 實施例。 201138306 【主要元件符號說明】 100… •…資料驅動器 11 .… ••…開關電晶體 101… •…暫存電路 2 .....補償電路 102… •…緩衝電路 21 •… •…第一重置電晶體 200… …·像素電路 22… •…第二重置電晶體 201… •…負載電容 23 .•… •…驅動電晶體 1…… •…開關 24··· ••…耦合電容Electric or discharge, so that the data voltage can be completely transmitted to the load capacitance 201 like (10). The following is a summary of some simulation data and experimental data to support. Analog Data Referring to the H-SPICE simulation result of Fig. 6, it is shown that even if the threshold voltage Vth of the driving transistor 23 is varied, the driving voltage v will be equal to the data voltage. Moreover, this equality relationship can be satisfied regardless of the threshold voltage variation value 〇v, 'v, 2V or 3V (volts). The H_SPICE simulation result in Fig. 7 further plots the result of the 1 material voltage minus the driving voltage VOUT, relative to the data voltage. From the figure, it can be observed that the difference between the data voltage and the driving voltage Vgut is limited to (4) compared with the threshold of the pure voltage of 2V < 3V. Experimental Data Referring to Fig. 8, an experimental simulation result using an amorphous phase indium gallium zinc oxide (aiGz〇, A·-1" InGaZn〇) transparent transistor is used. It is obvious that the driving voltage V〇UT is close to the data voltage, so it can be inferred that the present embodiment can be applied to the a-IGZO process. 201138306 Referring to FIG. 9, compared with the conventional source with the light device, in the case of the same threshold voltage variation value IdV, the driving power of the present embodiment drawn by the solid line is almost close to the data voltage, but with the dotted line (four) The conventional source is reduced by about 2V with the (four)" ratio (four) voltage, so that the data is not completely transmitted to the pixel circuit 200. Referring to Fig. 10, it is noted that in another embodiment, the data received by the switch transistor 11 is received. The voltage can also be changed to always high potential v嶋, and preferably 'in this case, the first reset transistor 21 will receive a low potential reference voltage. It is worth noting that the foregoing The transistors 11, 21 to 23 are all N-type transistors produced by an amorphous (a-Si) process, and there is a congenital lack of carrier mobility, and in this case, a few control signals are used. To determine the crystal operation timing 'can effectively make up for this shortcoming. However, the practical application should not be limited to the crystal of the amorphous Aussie process. Moreover, the buffer material 1〇2 of this example can be independently driven by the data driver 100. As described above, the present embodiment buffers electricity In the compensation phase, the control k-number CTRL1 and CTRL2 are used to generate a voltage drop of "voltage value = "the threshold voltage of the driving power _ crystal 23", and then the driving voltage crystal H 23 is boosted by the k voltage drop in the data voltage output stage. The control terminal electric seat 'actuates the driving voltage v0UT=vDATA in the charging stable state without being affected by the threshold voltage VrrH, so the material voltage can be stably and completely sent to the pixel circuit 2〇〇, so the present invention can be achieved. The purpose. However, the above is only a preferred embodiment of the present invention, and the scope of the present invention is not limited thereto, that is, the simple equivalent change of the scope of the invention and the description of the invention is as follows. Modifications are still within the scope of the invention. BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram illustrating a preferred embodiment of a data driver of the present invention; FIG. 2 is a timing diagram illustrating the timing of signals received by the buffer circuit of the present embodiment; FIG. 3 is a schematic diagram illustrating buffering The equivalent circuit of the circuit in the reset phase; FIG. 4 is a schematic diagram illustrating the equivalent circuit of the buffer circuit in the compensation phase; FIG. 5 is a schematic diagram illustrating the equivalent circuit of the buffer circuit in the data voltage output stage; A simulation diagram shows that the simulation results of H spiCE show that even if the threshold voltage mutates, the driving voltage is still equal to the data voltage. Figure 7 is a schematic diagram showing that the simulation results of H_spiCE show only slight differences between the data voltage and the driving voltage. Fig. 8 is a schematic diagram showing the simulation of the a_IGZ〇 transistor, the driving voltage is almost close to the data voltage; Fig. 9 is a schematic diagram showing that the driving voltage of the embodiment is close to that of the conventional source finder. The data voltage; and FIG. 10 is a circuit diagram illustrating another preferred embodiment of the data driver of the present invention. 201138306 [Description of main component symbols] 100... •...data driver 11 .... ••...switching transistor 101... •...temporary circuit 2 .....compensating circuit 102...•...buffering circuit 21 •... •...first Reset transistor 200...Pixel circuit 22...•...Second reset transistor 201...•...Load capacitor 23 .•... •...Drive transistor 1... •...Switch 24··· ••...Coupling capacitor
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