TW201137975A - Silicon carbide semiconductor device and its manufacturing method - Google Patents

Abstract

The present invention provides a silicon carbide semiconductor device having an ohmic electrode that can achieve improved adhesion to a wiring line by suppressing deposition of carbon without forming a Schottky contact, and also provides its manufacturing method. When an ohmic electrode is formed for a SiC semiconductor device, a first metal layer (12) that is formed of a first metal element is formed on one main surface of an SiC layer (11). Meanwhile, a Si layer (13) that is formed of Si is formed on a surface of the first metal layer, wherein the surface is on the reverse side of the surface facing the SiC layer (11). A laminated structure (10A) formed by the aforementioned process is subjected to a heat treatment. Consequently, there can be obtained a silicon carbide semiconductor device which includes an ohmic electrode that has good adhesion to a wiring line, while being suppressed in deposition of carbon atoms on the surface layer of the electrode and formation of a Schottky contact between Si and SiC.

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a niobium carbide semiconductor device and a method of manufacturing the same, and more particularly to a niobium carbide semiconductor capable of improving adhesion between an electrode and a wiring. Device and method of manufacturing the same. [Prior Art] A tantalum carbide (Sic) which is one of wide-bandgap semiconductors has been attracting attention as a material for realizing a high-frequency power element or a heat-resistant/radiation-resistant element. Since the tantalum carbide can form an oxide film (si〇2) by the same method as the bismuth (si), the carbonization semiconductor device, for example, M〇SFET (Metal 〇xide_ Semiconductor Field_Effect Transist〇r, metal oxide semiconductor field Research on electro-optical crystals has become increasingly popular. In addition, compared with Si, the SiC band gap (prohibited bandwidth) is wider, and the dielectric breakdown electric field strength is large. Therefore, for example, a semiconductor device using Sic is used as a semiconductor device having excellent switching characteristics and a large voltage compared with a semiconductor device using Si. In general, a SiC semiconductor device is provided with a wiring for easily taking out an electrical signal from an electrode formed on a substrate. It is not limited to the sic semiconductor device, and the Si semiconductor device can be smoothly exchanged with the external electric signal via the wiring. Fig. 35 is a schematic cross-sectional view showing the state of electrodes and wirings of a general SiC semiconductor device. As shown in FIG. 35, in the SiC semiconductor device 99A in which the electrode 98 is disposed on one main surface of the SiC semiconductor substrate 99, there is a case where carbon is deposited on one main surface of the electrode 98 which is not opposed to the SiC semiconductor substrate 99. 97. Here, the electrode 98 is an ohmic electrode which is in contact with the SiC semiconductor substrate 99 in 147784.doc 201137975. Further, the term "main surface" as used herein refers to a surface having the largest area among the planes forming the surface. After the carbon 97(c) is precipitated, when the wiring 96 disposed on one main surface of the electrode 98 which is not opposed to the Sic semiconductor substrate 99 is formed, the wiring 96 cannot be directly connected to the electrode 98 in the region where the carbon 97 is interposed. contact. Therefore, the carbon 97 deteriorates the adhesion of the electrode (10) to the wiring %. Therefore, it is a cause of an unfavorable situation in which the wiring 96 is peeled off from the electrode 98, and it is possible to affect the durability or electrical characteristics of the Sic semiconductor device 99. In order to solve the above problems, for example, a structure in which an alloy layer of Νι and Si is formed on the SiC substrate 95 is considered in the publication of Japanese Laid-Open Patent Publication No. Hei 7-99169 (hereinafter referred to as "Patent Document 1"). Fig. 36 is a schematic cross-sectional view showing a structure in which an alloy layer of Ni and Si is formed on a sic semiconductor layer. The electronic component 95A shown in Fig. 36 is subjected to heat treatment after forming the Ni si alloy layer 94 on the Sic substrate %, whereby the Ni_Si alloy layer % has a function as an ohmic electrode, which is disclosed in the patent document. Further, in the work of the patent literature, there is also a case where a layered structure in which a Si layer is formed on a SiC substrate 95 and a state layer is formed on the Si layer is subjected to heat treatment to form an ohmic electrode. The carbon 97 shown is formed by reacting a metal constituting the electrode 98 with SiC of the sic semiconductor substrate 99 by heat treatment at the time of forming the electrode 98, whereby c (carbon) is generated as a residue from sic Precipitated on the surface of the electrode 98. Therefore, in order to constitute an ohmic contact, Patent Document 1 discloses that on the surface of the vehicle of the Sic semiconductor substrate 99, an alloy layer 94 which is an alloy of metal (Ni) and Si is formed, thereby forming a picture 147784. .doc 201137975 shows the electronic component 95A. Patent Document 1 also discloses the following:

An Si layer is formed on the main surface of the SiC semiconductor substrate 99, and a tantalum layer is laminated on the Si layer, followed by heat treatment, whereby an electronic component 95A as shown in FIG. 36 is formed, and SiC and metal are eutectic (alloyed). The reaction temperature of Si and metal is lower than that of the metal. When the SiC and the metal are subjected to a cerium formation reaction, it is necessary to cut off the "S:" bond, and in contrast, when the Si and the metal undergo a bismuthation reaction, it is not necessary to cut the above-mentioned bond. The energy necessary for the hydration reaction is small, and accordingly the reaction temperature becomes low. Therefore, 'in the middle of raising the temperature for the purpose of heat treatment, on the upper side of the structure (the upper surface side of the SiC substrate 95 in Fig. 36) si and Ni The reaction is carried out. After Si and Nl are reacted to complete the hydration, the Si chemistry of the reaction between Si and Ni is inhibited, so that the reaction between SiC and (6) can be suppressed to produce C °. Therefore, C is not substantially It is the uppermost part of the structure (the uppermost layer of the Ni_Si alloy layer in Fig. 36). Therefore, it is considered that C does not substantially precipitate on the surface of the ohmic electrode. PRIOR ART DOCUMENT Patent Document Patent Document 1: Japanese Patent Laid-Open No. Hei 7-99169 The problem to be solved by the invention However, as disclosed in Patent Document i, when a Ni-Si alloy layer 94 (an alloy layer containing Si) or a layer is formed on the siC substrate 95, the siC semiconductor layer and There 147784.doc 201137975

The layer of Si will be in direct contact. In this case, the inventors found that the following problems exist. The following is explained. In general, Si operates as a Schottky electrode with respect to the SiC system. Therefore, after the Si layer or the alloy layer containing Si is directly contacted with the Sic layer, there is a possibility that Si does not remain alloyed as it is, but remains in contact with SiC. In this case, since this portion functions as a Schottky electrode, it is considered to have an influence on the electrical characteristics of the tantalum carbide semiconductor device. ', / For example, if Si forms an alloy (deuteride) with Ni which forms an alloy layer or Ni which exists in a Ni layer on a layer, it is possible that the Schottky electrode is not formed by 〇 and It has a function as a good ohmic electrode as disclosed in Patent Document i. However, for example, when the amount of 8 相对 is excessive with respect to the amount of Ni which may occur 2, or when there is a localized region having a high concentration of si due to uneven process conditions, unreacted Si will precipitate. In the structure disclosed in Patent Document 1, it is possible that the precipitated si is in direct contact with Sic to form a Schottky contact as described above. The present invention has been made in view of the above problems, and an object thereof is to provide a tantalum carbide semiconductor device having an ohmic electrode which can improve wiring adhesion by suppressing precipitation of carbon without causing Schottky contact, and a method of manufacturing the same. Means for Solving the Problem A method of manufacturing a niobium carbide semiconductor device of the present invention is a method of manufacturing a niobium carbide semiconductor device having an ohmic electrode. The manufacturing method includes the steps of: forming a SiC layer comprising tantalum carbide; forming a layer of a second metal 147784.doc -6 · 201137975 comprising a second metal element and containing no carbon atoms on one major surface of the Sic layer; Forming a Si layer containing germanium (Si) and not containing carbon atoms on a surface of the first metal layer opposite to the surface opposite to the sic layer; and forming an ohmic electrode to the Sic layer, the above-mentioned The metal layer and the Si layer are heat treated. According to the above method, after the second metal layer is formed between the sic layer and the Si layer, the Schottky contact can be suppressed by direct contact of the unreacted Si with the Sic layer. In the crucible, the metal constituting the P metal element is preferably one. The reason is that, as described in detail below, for example, if the second metal layer is composed of two kinds of metals, it is difficult to form a reaction state in accordance with the target in the heat treatment step, that is, the first condition, Si and one of the two metals. A binary reaction occurs, and after that, Si reacts with two metals in a ternary reaction. Further, after the first metal layer is formed between the SiC layer and the Si layer, a heat treatment step is performed, whereby when the temperature is raised in the step of performing the heat treatment, first, the first metal layer is preferentially reacted with the Si layer to be alloyed. The bismuth compound is caused by the reaction temperature of Si and the metal layer being lower than the reaction temperature of the sic and the metal layer as described above. After the cerium metal element forming the second metal layer in the reaction is completely consumed, SiC and the first The reaction of the metal layer is hindered. Further, even when the metal element of the first metal layer remains after the reaction with the layer (1), the upper portion of the first metal layer (the surface layer opposite to the SiC layer) is formed. a layer in which Si of the Si layer is alloyed with a metal atom of the metal layer (after mashing). Therefore, it is possible to suppress precipitation of C as a residue generated by the reaction between the SiC layer and the first metal layer (by the second metal layer) The surface of the ohmic electrode formed by the reaction with the layer (the surface of the layer after the Si of the Si layer is alloyed with the metal atom of the metal layer (after mashing)). Therefore, it can be suppressed by 147784.doc 2011379 75. The wiring adhesion is deteriorated by the precipitation of c on the surface layer of the ohmic electrode to which the wiring is connected. Further, the second metal layer (or the Si layer) which is "having no carbon atoms" is a private quality. The metal layer or the 81 layer which does not contain a carbon atom or has a carbon atom concentration of 1% or less in terms of the number of atoms. Further, the method for producing a niobium carbide semiconductor device of the present invention further preferably includes the following steps. Before the step of performing the heat treatment, a second metal layer containing a second metal element and containing no carbon atoms is formed on the surface of the Si layer opposite to the surface opposite to the surface of the i-th metal layer. Therefore, depending on the conditions of the step of performing the heat treatment, a layer remaining on the layer including the metal constituting the second metal layer may be formed on the surface of the formed ohmic electrode (the surface opposite to the surface facing the SiC layer). Alternatively, a layer containing a metal constituting the second metal layer may be formed at a high concentration. Therefore, after the wiring is connected to the surface of the ohmic electrode, the ohmic electrode is formed with respect to the complete cerium. Compared with the case where the surface layer is connected to the wiring, the wiring can be more closely adhered to the ohmic electrode. The adhesion of the wiring can be improved in a stepwise manner. Here, the surface layer is, for example, a self-ohmic electrode. It is preferable that the surface (the surface opposite to the surface facing the SiC layer) is within 1 nm, and the region does not contain carbon atoms. Further, if the second metal layer is present, the Sic and the i-th can be reduced. The carbon (C) generated by the reaction of the metal layer may be deposited on the surface layer of the second metal layer. Further, the method for manufacturing the niobium carbide semiconductor device of the present invention has a niobium 147784.doc 201137975 electrode of a niobium carbide semiconductor device. a manufacturing method comprising the steps of: forming a SiC layer comprising tantalum carbide; forming a first metal layer containing a first metal element and not containing a carbon atom on one main surface of the SiC layer; Forming a Si metal layer containing germanium (Si) and the above-mentioned one i-th metal element and containing no carbon atoms on a surface of the metal layer opposite to the surface opposite to the SiC layer; and forming an ohmic layer , The above SiC layer, said first metal layer, and said metal layer is heat-treated 8 Shu. According to the above method, after the first metal layer is formed between the SiC layer and the Si metal layer, the unreacted Si contained in the Si metal layer can be prevented from directly contacting the SiC layer to form a Schottky contact. Further, after the first metal layer is formed between the SiC layer and the Si metal layer, a heat treatment step is performed, whereby the first metal layer is first and the Si contained in the Si metal layer is preferentially heated during the heat treatment step. The reaction is carried out to carry out alloying (deuteration). After the first metal element forming the first metal layer in the reaction is completely consumed, the reaction between S i C and the first metal layer is inhibited. Further, even when the metal element of the first metal layer remains after reacting with the Si of the Si metal layer, the Si portion of the Si metal layer is formed on the upper portion of the first metal layer (the surface layer on the Si metal layer side). A layer that is alloyed with a metal atom of the metal layer (after mashing). Therefore, it is possible to suppress the phenomenon that C, which is a residue generated by the reaction between the SiC layer and the first metal layer, is deposited on the surface of the electrode (the ohmic electrode formed by the reaction between the first metal layer and the Si metal layer). Therefore, it is possible to suppress the deterioration of the wiring adhesion due to the precipitation of carbon (C) on the surface layer of the ohmic electrode to which the wiring is connected. Preferably, the method for producing a tantalum carbide semiconductor device of the present invention further comprises the following steps: in the case of forming a Si metal layer as described above, and also before the step of performing the heat treatment, in the above metal layer On the surface opposite to the surface facing the first metal layer, a second metal layer containing a second metal element and containing no carbon atoms is formed. Thereby, a layer remaining on the layer including the metal constituting the second metal layer can be formed on the surface of the formed ohmic electrode (the surface opposite to the surface opposite to the SiC layer) according to the conditions of the step of performing the heat treatment Alternatively, a layer containing a metal constituting the second metal layer in a high concentration may be formed. Therefore, after the wiring is connected to the surface of the ohmic electrode, the wiring can be more closely adhered to the ohmic electrode than when the wiring is connected to the surface layer of the completely erbium-doped ohmic electrode. That is, the adhesion of the wiring can be further improved. In the method for producing a tantalum carbide semiconductor device according to the present invention, in the step of performing heat treatment, an alloy containing a metal element of lanthanum and cerium (Si) may be formed on one main surface of the SiC layer and contains carbon atoms. A carbon-containing telluride layer. Here, the SiC of the SiC layer is also in contact with the first metal layer, so that it reacts with the first metal layer by increasing the temperature of the heat treatment to cause deuteration. Thus, the reaction between SiC and the first metal layer is achieved. On the telluride layer, it is in a state containing C derived from SiC. As a result, a carbon-containing telluride layer containing carbon atoms is formed. However, if the C produced by the above hydration is not present on the surface layer of the laminate structure (here, the outermost surface of the formed ohmic electrode), the wiring is not connected to the surface layer of the ohmic electrode. There will be obstacles. Therefore, on one main surface of the SiC layer, a carbon-containing telluride layer containing a metal of 147784.doc •10·201137975 element and Si and containing carbon atoms may be formed. In order to form a good ohmic contact, the first metal element is preferably selected from the group consisting of nickel (Ni), titanium (Ti), aluminum (A1), platinum (Pt), tungsten (W), and palladium (Pd). An element of a group. Further, the second metal element is preferably one selected from the group consisting of titanium (Ti), aluminum (A1), and chromium (Cr). By making the second metal element an element as described above, it is possible to surely improve the adhesion between the ohmic electrode and the wiring. The tantalum carbide semiconductor device of the present invention can be manufactured by using the above-described method for producing a tantalum carbide semiconductor device of the present invention, comprising: a SiC layer containing tantalum carbide; and a telluride layer disposed on one main surface of the Sic layer The upper layer contains an alloy of a cerium metal element and cerium (si), and the surface layer on the opposite side to the surface opposite to the SiC layer does not contain carbon atoms. Further, the SiC layer is in ohmic contact with the above-mentioned layer. Thereby, the surface layer of the telluride layer which becomes the ohmic electrode does not contain carbon atoms, so that when the wiring is connected to the surface of the germanide layer, the vaporized layer (ohmic electrode) due to the presence of the carbon atom can be prevented. ) The adhesion to the wiring deteriorates.

The area within 10 nm from the surface of the layer.

The carbon telluride layer is disposed on the SiC layer - and the vaporized layer containing no carbon atoms. On one of the major surfaces of the layer, it contains a 147784.doc • 11 · 201137975 alloy of the first metal element and bismuth (Si) and contains carbon atoms. The layer of the lithium-free layer containing no carbon atoms is disposed on the main surface of the carbon-containing s-slung layer opposite to the surface opposite to the Sic layer, and comprises a bismuth metal element and an alloy thereof. The surface layer on the opposite side of the surface opposite to the carbon-containing telluride layer does not contain carbon atoms. The SiC layer is in ohmic contact with the carbon-containing telluride layer. Thereby, it is connected to the carbon-containing telluride layer as the ohmic electrode. Since the surface layer of the telluride layer containing a carbon atom does not contain a carbon atom, when the wiring is connected to the surface of the vaporized layer, the adhesion of the vaporized layer to the wiring due to the presence of carbon atoms can be prevented from deteriorating. The tantalum carbide semiconductor device may further include an upper germanide layer formed on the surface layer of the germanide layer, including an alloy of the second metal element and Si, and opposite to the surface opposite to the germanide layer The surface layer does not contain carbon atoms. In this case, the second metal element can be selected independently of the second metal element constituting the telluride layer, so that the wiring is connected to the upper germanide layer. In the case of the surface structure, the degree of freedom in selecting a metal element capable of improving the adhesion to the wiring as the second metal element can be increased. In the silicon carbide semiconductor device of the present invention, the first metal element is preferable. It is one element selected from the group consisting of nickel, titanium, aluminum, platinum, tungsten, and palladium. In this case, good ohmic contact between the SiC layer and the telluride layer can be achieved. Preferably, it is one element selected from the group consisting of titanium, aluminum, and chromium. By making the second metal element an element as described above, it is possible to surely improve the adhesion of the upper vapor layer (ohmic electrode) to the wiring. 147784.doc • 12-201137975 The effect of the invention is that the Schottky-based semiconductor device does not generate Schottky contact, and according to the present invention, the deposition of carbon can be provided to improve the manufacture of wiring. [Embodiment] [Embodiment] The embodiments of the present invention will be described with reference to the embodiments of the present invention, and the same reference numerals will be used to refer to the figures in the embodiments. (Embodiment 1) FIG. 1 is a schematic cross-sectional view showing a laminated structure of an ohmic electrode in which a tantalum carbide semiconductor device according to an embodiment of the present invention is not formed, and FIG. 2 shows an embodiment of the present invention. A flow chart of the formation sequence of the tantalum carbide semiconductor device of the first embodiment is shown in Fig. 1. The laminated structure 10A shown in Fig. 1 is a laminated structure for forming the tantalum carbide semiconductor device according to the first embodiment of the present invention before heat treatment. As shown in the laminated structure 10A of the first embodiment, in order to form the ohmic electrode of the tantalum carbide semiconductor device according to the first embodiment of the present invention, first, a SiC layer 11 containing tantalum carbide is formed on one main surface of the Sic substrate 1A. Then, in the siC layer 11 On one main surface, a first metal layer 12 including a first metal element is formed, and on the surface opposite to the surface of the first metal layer opposite to the SiC layer 11 (upper side in FIG. 1), A Si layer 13 containing Si is formed. According to this configuration, when the laminated structure 10 A is heat-treated, the first metal element constituting the first metal layer 12 is preferentially reacted with Si of the Si layer 13 having a reaction temperature lower than that of Si of the SiC layer 11 to be alloyed. (矽 147784.doc • 13-201137975). Therefore, by the heat treatment, "the layer 13 reacts with the second metal layer 12 to be deuterated. Further, as the heat treatment temperature rises, after the heating temperature reaches the reaction temperature of the Si of the first metal layer 12 and the SiC layer 11, The first metal element reacts with Si of the SiC layer 11 to start bismuthation. At this time, since Si of SiC reacts with the first metal element, the remaining carbon (c) is retained as a residue. When the surface layer of the laminated structure 1A (the uppermost one in FIG. 1) is precipitated, the material constituting the wiring and the surface layer of the laminated structure are densely connected when the wiring is connected to the surface layer of the laminated structure 丨〇A. The property is deteriorated, causing a phenomenon such as peeling of the wiring, etc. However, before the generated c is chromatographed on the surface of the laminated structure 10A, the reaction of Si of the Si layer 13 which has just started the reaction with the first metal element is caused. After the entire third metal element is consumed, the first metal element that reacts with the SiC of the SiC layer 11 does not exist. Therefore, it is possible to suppress the reaction between SiC and the first metal element, thereby suppressing the influence of the wiring adhesion. Production Further, in the upper layer region of the first metal layer 丨2 in the laminated structure 10A (the region close to the Si layer 13), the bismuth layer is first formed in order to at least first mash the layer with the layer 13. The telluride layer formed by the reaction of the ith metal element of the i-th metal layer 丨2 with the SiC of the SiC layer 11 reaches the upper end portion of the first metal layer 12 of the build-up structure 10A. Therefore, As a result of the reaction of a part of SiC with the first metal layer 12, even if it stays inside the laminated structure 10A, the possibility that the c reaches the surface layer of the laminated structure 1a is also low. The first metal layer 12 is interposed between the SiC layer 11 and the Si layer 13 to suppress precipitation of the surface layer c of the buildup structure 10A. 147784.doc 201137975 Further, as described above, 'Si is relative to the SiC system as Schottky. Therefore, it is not preferable to make the Si layer or the alloy layer containing Si directly contact the layer of siC. However, if the first metal layer 12' is disposed between the SiC layer 11 and the Si layer 13 as in the laminated structure 10A, The SiC of the SiC layer 11 is inhibited from being in direct contact with the Si of the Si layer 13 to form a Schottky That is, as described above, for the SiC layer 11 and the Si layer 13 which are in direct contact, the first metal element of the first metal layer 12 preferentially reacts with the Si of the 8 丨 layer 3 having a lower reaction temperature to be alloyed. After the Si layer 13 reaches the SiC layer 11 beyond the region of the first metal layer 12 in the laminated structure 10A before the heat treatment, if the reaction between the Si layer 13 and the first metal layer 12 is completed, The fact that all of them have been etched into the 'thirsty' does not contribute to the direct contact between the Si of the Sihua compound and the SiC of the SiC layer 11 to form a Schottky contact. According to the above, the possibility of forming the Schottky contact can be reduced by interposing the first metal layer 12. In the case where the first metal element constituting the first metal layer 12 is arranged in a two-element, for example, a reaction in which the reaction with Si is caused by the heat treatment is a three-element reaction. For example, when heating is performed in a state in which the three elements of the metal A, the metal B, and the Si are contained, when the reaction temperature of the metal A and the metal B is close to the reaction temperature of the metal B and Si, the metal A, the metal B, and The ternary reaction of Si. Further, in the initial state, for example, Si is only in direct contact with metal A, resulting in that metal B and Si are not in direct contact. Therefore, in the initial state, the binary reaction of metal A and Si is carried out, but as the reaction progresses, the morphological change of the reaction is considered to be a ternary reaction of metal A, metal B, and Si. For such a reaction, for example, using a pre-measurement reaction such as a label, it is difficult to form a target that meets the target 147784.doc -15·201137975. It is preferable that the metal constituting the first metal element of the first metal layer 12 is one of the above. Specifically, 'it is preferably one element selected from the group consisting of nickel, titanium, aluminum, turned, tungsten, and palladium. Thereby, a good ohmic electrode can be formed by heat-treating the laminated structure 1A according to the correlation of the work functions of SiC and Si. Here, a method of manufacturing the carbonized carbide semiconductor device according to the first embodiment of the present invention will be described with reference to Fig. 2 . First, a step (sl〇) of preparing a substrate is carried out. Specifically, a substrate on which a tantalum carbide semiconductor device is formed, that is, a SiC substrate 10 shown in Fig. 1 is prepared. For example, an n-type SiC wafer can be used as the sic substrate 1 〇, and can also be used as a p-type SiC wafer. Next, the step of forming a SiC layer (S2〇) is carried out. Specifically, the SiC layer 11 containing tantalum carbide is formed on one main surface of the siC substrate 10 as in the SiC layer 11 in the laminated structure 10A of Fig. i. The step of forming the SiC layer (S20) is, for example, to make the directions of the crystal faces for forming the main surface of the laminated structure 10A uniform by epitaxial growth to ensure good electrical characteristics of the formed semiconductor device, and to fill

The thickness of the SiC substrate 10 is performed. An n-type epitaxial layer may be formed depending on the substrate to be used or the use of the formed semiconductor device, and a p-type epitaxial layer may be formed. In order to form the epitaxial layer, it is preferred to use a vapor phase epitaxial growth method, that is, for example, a mixture containing 5 Å which constitutes SiC and (a material gas which is cerane (SiHj or propylene (C^8)) The gas phase growth is carried out by using an impurity source having an n-type or p-type semiconductor property, that is, Α1 or phosphorus, etc. Further, as a shape 147784.doc -16·201137975 into a P-type epitaxial layer a p-type impurity, methyl aluminum (TMA), for example, using a nitrogen (N 2 ) gas. The source ' can be used, for example, to form an n-type epitaxial layer-fired (Β2Η6) or three n-type impurity source, which can then be implemented The step of forming the first metal layer is specifically a step of forming a metal layer 12 containing a first metal element and containing no carbon atoms on a main surface of the training layer 11 shown in FIG. The first metal layer 12 is used to form an ohmic electrode after heat treatment. Here, if the ith metal layer 12 contains carbonogen +, then in the subsequent heat treatment step, it may be shown in FIG. The surface of the laminated structure is chromatographed to emit carbon atoms. gu匕' is preferably not contained in the P metal layer 12. The term "a carbon atom alone" means, for example, that the amount of carbon atoms is 1% in terms of the number of atoms. Further, the i-th metal layer 12 is preferably, for example, by a lining or vacuum shovel, ion beam evaporation. Or a read method is formed. As described above, the metal element constituting the first metal layer 12 is preferably one element selected from the group consisting of titanium, quartz, tungsten, and palladium. The step (S40) of the Si layer is specifically shown in the figure, and is formed on the surface of the first metal layer 12 opposite to the surface of the ("layer" opposite to the surface, and contains Si and does not contain The step of "layer 13 of carbon atoms. The 8: layer 13 is used to form an ohmic electrode when heat treatment is subsequently performed." The formation of the layer 13 is preferably carried out, for example, by a sputtering method or the like. Step (S5). Specifically, in order to form the ohmic electrode, the entire laminated structure 10A including the first metal layer 12 and the Si layer 13 shown in the figure is heat-treated to form a laminate. The step of alloying the first metal layer 12 of the structure 10A with the layer 13. 147 784.doc -17·201137975 For example, when heat treatment is performed on the laminated structure i 〇A of FIG. 1 to form an ohmic electrode, as an environment for performing heat treatment, it is preferable to use an environment such as argon (Ar), and An environment of an inert gas such as nitrogen may be used. Further, the temperature for heat treatment is preferably 8 〇〇 < t or more and iioo ° c or less, more preferably 900 〇 c or more and l 〇 5 〇 ec In the following, it is preferable to perform heating for 30 seconds or more and 5 minutes or less. After the heat treatment, the first layer of the first metal element constituting the first metal layer 12 is mashed (alloyed). Along with this alloying, this portion forms an ohmic contact with the sic layer ’ to form an ohmic electrode. Fig. 3 is a schematic cross-sectional view showing a laminated structure of an ohmic electrode which is an embodiment of the present invention after heat treatment. Further, Fig. 4 is a schematic cross-sectional view showing a laminated structure of another embodiment of the ohmic electrode which is an embodiment of the present invention after the heat treatment. The ohmic electrode 丨丨a shown in Fig. 3 and the ohmic electrode 1 2 a shown in Fig. 4 are all shown in the step (s5〇) of heat-treating the laminated structure 10A shown in Fig. 1. For example, the ohmic electrode 11A shown in FIG. 3 includes a carbon-containing telluride layer 41 disposed on a main surface including a tantalum carbide 31 (on one surface of the layer u), containing an alloy of a first metal element and Si, and containing a carbon atom; and a telluride layer 42 disposed on a main surface of the carbon-containing vapor-deposited layer 41 opposite to the surface opposite to the sic layer 11, comprising an alloy of a third metal element and si, and The surface layer on the opposite side of the surface of the carbon-containing telluride layer 41 does not contain carbon atoms. Further, "(the layer u is in ohmic contact with the carbon-containing telluride layer 41, and further, the surface layer here is as above For example, the uppermost layer of the ohmic electrode 丨丨a shown in FIG. 3, that is, the vaporized layer 42 147784.doc -18-201137975 is opposite to the surface opposite to the carbon-containing telluride layer 41 (FIG. 3). Further, for example, the ohmic electrode 12A shown in FIG. 4 includes a vaporized layer 42 which is disposed on one main surface of the SiC substrate 10 and contains carbon fossils. On one major surface of the SiC layer 11, a third metal element is contained The surface layer opposite to the surface of the alloy SiC layer and the SiC layer 11 does not contain carbon atoms. Moreover, the SiC layer 11 is in ohmic contact with the vaporized layer 42. The laminated structure shown in Fig. 1 After the heat treatment of 10A, the first metal element constituting the first metal layer 12 firstly undergoes a "reaction with the 8" layer 13 to be deuterated. The reason is that, compared with SiC, the second metal element is more compatible with Si. The reaction in which the bismuth is formed at a lower temperature. Since the first metal layer 12 and the Si layer 13 do not contain carbon atoms, the alloy formed by the reaction, that is, the vaporized layer 42 is not formed. The carbon atom is contained. However, as the heating temperature of the heat treatment rises, the heating temperature reaches a temperature at which the first metal element and the Si of the SiC are homogenized. Therefore, the Si of the i-th metal layer 12 and the Si layer 13 are caused. The SiC layer 11 and the Si of the SiC layer 11 are decidized. The bismuth compound layer 42 containing no carbon atoms is formed by crystallization of Si with the Si layer 13, and is formed by crystallization of Si with the SiC layer 11. Carbon containing carbon atoms remaining in the process The telluride layer 41. The hydrazine formation continues until all of the first metal elements are deuterated. Then, after the first metal element has been completely deuterated and the reaction is completed, the ohmic electrode 11A as shown in FIG. On one main surface of the layer 11, a carbon-containing vaporized layer 41 formed by mash-forming Si of the SiC layer 11 and the first metal element is formed, and the carbon-containing telluride layer 4 is opposed to the Sic layer. Table 147784.doc • 19-201137975 The surface is on the opposite side (the upper side of Fig. 3), and a vaporized layer 42 formed by mashing the 8 丨 layer 13 and the first metal element is formed. Wherein, for example, when the heating temperature of the heat treatment reaches a temperature at which the metal element and the Si of the SiC are deuterated, when the second metal element has been mashed with the Si of the Si layer 13, as shown in FIG. In the same manner as the ohmic electrode 12A, on the surface of the SiC layer 11 opposite to the surface on which the SiC substrate 1 is opposed (the upper side in FIG. 4), the formation of 81 layers 1; 3 of 81 and the first metal element is performed. The vaporized layer 42 formed of the chemical conversion does not contain carbon atoms. Even if the ohmic electrode having any of the configurations of FIG. 3 and FIG. 4 is formed, the carbon-containing telluride layer 4 and the carbon atoms of the sic layer do not reach the ohmic electrode. The surface layer of 12A is the surface layer of the telluride layer 42. Therefore, when the ohmic electrode manufacturing method of the present invention is used, carbon atoms are not deposited on the surface layer of the surface layer of the formed ohmic electrodes 11A and 12A, i.e., the lithium layer 42. Thereby, the adhesion of the wiring connected to the surface layer of the telluride layer 42 can be made good. After the I-made electrode, the step of forming the wiring portion is finally performed (S60). Specifically, it is formed on the surface layer of the ohmic electrode, that is, on the surface layer of the bismuth layer 42 of the ohmic electrodes 11A, 12A of FIGS. 3 and 4, which is formed to be used for taking out FIG. 3 and FIG. The step of the metal layer (pad) of the wiring of the electrical signal shown. The wiring portion can be formed, for example, by vacuum deposition, ion beam evaporation, 贱 key or the like. As described above, in the surface layer of the telluride layer 42 of the ohmic electrodes 11A and 12A in Figs. 3 and 4, carbon atoms or precipitated carbon 97 are not present (see Fig. 35). Therefore, the adhesion of the wiring portion connected to the surface layer of the telluride layer 42 can be made good. [Embodiment 2] Fig. 5 is a schematic cross-sectional view showing a laminated structure of an ohmic electrode for forming a carbonized carbide semiconductor device according to Embodiment 2 of the present invention. Fig. 6 is a flow chart showing the procedure for forming a tantalum carbide semiconductor device according to Embodiment 2 of the present invention. Here, the laminated structure 10B shown in Fig. 5 shows a laminated structure before heat treatment for forming the tantalum carbide semiconductor device according to the second embodiment of the present invention. As shown in the laminated structure 1 〇B of FIG. 5, the laminated structure prepared to form the ohmic electrode of the stone reversal semiconductor device according to the second embodiment of the present invention includes the laminated structure 丨〇A according to the first embodiment of the present invention (see Figure 丨) the same form. However, in the laminated structure 10B, on the surface opposite to the surface opposite to the first metal layer 12 of the Si layer 13 (the upper side in FIG. 5), a carbon containing a second metal element is formed and contains no carbon. The second metal layer 14 of the atom. Only at the point described, the laminated structure 10B is different from the laminated structure i〇A. The formation of the wiring portion after the heat treatment step is performed on the surface layer of the ohmic electrode. For example, in the ohmic electrodes 11A and 12 of the first embodiment of the present invention, the surface layer of the surface layer-based telluride layer 42 of the wiring portion is formed. However, in the second embodiment of the present invention, the second metal layer 形成 is formed on the uppermost layer of the laminated structure 1B. Therefore, the surface layer of the formed ohmic electrode also becomes the second metal layer 14 depending on the state after the heat treatment. Therefore, when the wiring portion is formed with respect to the second metal layer 14, the affinity between the metal element forming the wiring portion and the surface layer of the ohmic electrode is better than the If shape in which the wiring 4 is formed with respect to the vaporized layer. The adhesion between the wiring portion and the ohmic electrode can be improved. 147784.doc 201137975 The method for manufacturing the silicon carbide semiconductor device according to the second embodiment of the present invention is as shown in the flowchart of FIG. 6. The silicon carbide semiconductor device according to the second embodiment of the present invention is shown. The manufacturing method is basically the same as the method of manufacturing the carbonized carbide semiconductor device according to the first embodiment of the present invention. However, as shown in @6, the method of manufacturing the carbon-cut semiconductor device according to the second embodiment of the present invention further includes the step (S45) of "forming the layer uu of FIG. 5 in the step of forming the layer (S4〇). A second metal layer containing a second metal element and containing no carbon atoms is formed on the surface opposite to the surface on the opposite side of the first metal layer 12 before the step (S5〇) of the hot spot s. When the second metal layer 14 contains a carbon atom, the carbon atom is diffused in the subsequent step of heat treatment, whereby the layer shown by the circle 5 and the surface layer of the mouth structure 10B contain carbon atoms. Therefore, it is preferred that the second metal layer 14 does not contain carbon atoms. The term "carbonogen-free" as used herein means that the amount of carbon atoms is, for example, 1% or less in terms of the number of atoms. Further, the second metal layer 14 is also preferably formed, for example, by sputtering, vacuum deposition, ion beam evaporation or electroplating, similarly to the first metal layer 12. As described above, the halogen constituting the second metal layer is preferably one selected from the group consisting of nickel, titanium, melamine, crane, and handle. The second metal layer 14 is also preferably composed of a metal element as well as the second metal layer 12. Further, the second metal element constituting the second metal layer 14 is preferably one element selected from the group consisting of titanium, aluminum, and chromium. Thus, according to the correlation between the work functions of SiC and si, The laminated structure 10B can form a good ohmic electrode when heat-treated. The flowchart of FIG. 6 differs from the flowchart of FIG. 2 only in the above points. 147784.doc •22· 201137975 That is, the step (S10) of FIG. 6 is the same step as the step (S 10) of FIG. 2 . Hereinafter, the steps (S20), (S30), (S40), (S50), and (S60) of Fig. 6 are also the same steps as the steps of Fig. 2 . Here, the obtained structure of the laminated structure 1b after the step of heat treatment (S50) is different from the embodiment of the present invention. Fig. 7 is a schematic cross-sectional view showing a laminated structure of an ohmic electrode according to a second embodiment of the present invention after heat treatment. Further, Fig. 8 is a schematic cross-sectional view showing a laminated structure of another embodiment of the ohmic electrode which is the second embodiment of the present invention after the heat treatment. Fig. $ is a schematic cross-sectional view showing a laminated structure of still another embodiment of the ohmic electrode according to the second embodiment of the present invention after the heat treatment. The ohmic electrode iiB shown in Fig. 7, the ohmic electrode 12B shown in Fig. 8, and the ohmic electrode 13B shown in Fig. 9 each show a state in which the step (S50) of heat-treating the laminated structure 10A shown in Fig. 1 is performed. For example, when Si of the Si layer 13 shown in FIG. 5 is firstly cleaved with the second metal element of the first metal layer 12 and the second metal element of the second metal layer 14, Si is mixed. The first metal element and the second metal element are the three element germanide layer 43. However, for example, before all of the first metal elements are reacted with the layer 13 to be etched, if the first metal element and the 8 丨 (the layer bismuth is formed together), it is formed as shown in FIG. The ohmic electrode 丨丨b is disposed on a surface of the SiC layer 11 opposite to the surface opposite to the surface of the SiC substrate 1 (on the upper side in FIG. 7), and is provided with an alloy containing the first metal element and Si and contains carbon atoms. The carbon-containing telluride layer 41 is provided on the main surface opposite to the surface of the carbon-containing telluride layer 41 opposed to the Sic layer 11 and is provided with an alloy containing a first metal element, a second metal element, and Si. The surface layer on the opposite side to the surface of the carbonaceous-ceramic layer 41 to 147784.doc -23- 201137975 is a vaporized layer 43 containing no carbon atoms. Among them, for example, the heating temperature of the heat treatment is attained to make the metal Before the temperature of the element and the S!C Si is mashed, when the third metal element has been

When the Si of the Si layer 13 is decidualized, as in the ohmic electrode 12B shown in FIG. 8, on the surface of the SiC layer 11 opposite to the surface opposite to the SiC substrate 10 (the upper side of FIG. 8), A vaporized layer 43 containing no carbon atoms formed by mash formation of Si, a second metal element, and a second metal element of the Si layer 13 is formed. Further, for example, when the thickness of the Si layer is more than a certain degree, for example, twice the total thickness of the first metal layer 12 and the second metal layer 14 shown in FIG. 5 depending on the type of the metal, it may cause " The layer 13 "reacts with the second metal element and the second metal element independently of the cerium formation. Furthermore, the term "thickness" as used herein refers to the distance between the opposing major surfaces. For example, for the Si layer of the Si layer 13, below the layered structure ι〇Β (the lower side of Figure 5), with the first! The metal element and the second metal element are mixed by the three elements to form a Sihua compound. Above the layered structure 10B (on the upper side of FIG. 5), since the 81 layer 13 is thick, there are cases where the first metal element is not Arrived, and only the second metal element and the Si of the Si layer 13 are deuterated. As a result, as shown in FIG. 9, there is also a case where the ohmic electrode 13B including the upper germanide layer 44 is formed, and the upper germanide layer 44 contains a second metal element and an alloy thereof, and is in the form of a telluride. The surface layer on the opposite side of the layer 43 opposite thereto does not contain carbon atoms. Further, although not shown, an ohmic electrode having a structure in which a telluride layer containing an alloy of a first metal element and Si and an alloy containing a second metal element and an alloy of Si may be formed. The composition of the laminated layer 147784.doc -24- 201137975. Since the ohmic electrode having such a composition is deuterated by a metal element and the two elements of Si, it is easier to predict the reaction by using a label or the like than in the case of forming the vaporized layer 43 by mixing three elements. . Further, in the second embodiment of the present invention, since the second metal layer 丨4 is included in the laminated structure 1B, the distance (thickness) from the SiC layer 丨丨 to the surface layer of the uppermost layer of the laminated structure is larger than the implementation of the present invention. The situation is ambiguous. Therefore, it is less likely that the C of the siC layer 11 reaches the surface layer. Further, for example, when the reaction temperature of the second metal element and Si is greatly increased as compared with the reaction temperature of the second metal element and si, or when the thickness of the second metal layer is extremely thick, the second metal is also considered. The elements are not all

Si is catalyzed by the reaction. At this time, for example, the surface layer of each of the ohmic electrodes shown in FIGS. 7 to 9 (the uppermost layer of the telluride layer in FIGS. 7 and 8 and the uppermost layer of the upper lithi layer in FIG. 9) remains on the second layer. Metal layer 14 (not shown). In this case, the wiring portion is formed in contact with the surface layer of the second metal layer 14 with respect to the ohmic electrode. Therefore, it is possible to maintain good adhesion compared to the case where the wiring layer is formed on the surface layer of the coating layer. Embodiment 2 of the present invention is only the above-described points and embodiments of the present invention. In the second embodiment of the present invention, the configuration, the condition, the sequence, the effect, and the like, which are not described above, are all based on the embodiment of the present invention. 1. One (Embodiment 3) FIG. 10 is a representation to form the present invention. (C) A carbon-cut tantalum of 147784.doc 201137975 A schematic cross-sectional view of a laminated structure of an ohmic electrode of the device. Here, the laminated structure 1 〇c shown in Fig. 0 represents a tantalum carbide used to form the third embodiment of the present invention. The laminated structure of the semiconductor device before the heat treatment is performed. The laminated structure prepared to form the ohmic electrode of the carbonized carbide semiconductor device according to the third embodiment of the present invention is provided in the first embodiment of the present invention. The laminated structure 10 Α (refer to FIG. i) has the same form. However, in the laminated structure 10C, instead of the 8 丨 layer i 3 of the laminated structure, the formation of si and a first metal element is not performed. The Si metal layer 15 having carbon atoms. The layered structure i 〇c is different from the layer structure 丨〇A only in the above-described point. The order of formation of the tantalum carbide semiconductor device according to the third embodiment of the present invention is as shown in FIG. The order of formation of the carbonized carbide semiconductor device according to the first embodiment of the present invention is as follows. However, as described above, the Si metal layer 15 is formed in place of the Si layer 13 of the buildup structure 10A in the buildup structure 1〇c. Therefore, Fig. 2 The step of forming the Si layer in the step (S40) is a step of forming the Si metal layer (S4〇>. Thus, the Si metal layer 15' contains the first metal in the initial state in which the Si-containing layer is subjected to heat treatment. In the element, since the S element is present in a position closer to the first metal element, when the heat treatment is performed, Si and the first metal element can be more rapidly formed. Therefore, the first metal element can be suppressed. It is possible to suppress the precipitation of C of the sic layer 11 by the Si of the SiC layer 11. Further, as the second metal element constituting the Si metal layer 15, nickel, titanium, Ming, Ming, and One of the group consisting of tungsten and Syria However, in the same manner as the second metal element shown in the second embodiment, one element selected from the group consisting of titanium, aluminum, and chromium may be used as the element 147784.doc -26-201137975. (4) The state 3 differs from the first embodiment of the present invention only in the points described above. That is, in the third embodiment of the present invention, the configuration, the condition, the procedure, the effect, and the like which are not described above are all the embodiments of the present invention. (Embodiment 4) FIG. 11 is a schematic cross-sectional view showing a laminated structure of an ohmic electrode in which a tantalum carbide semiconductor device according to Embodiment 4 of the present invention is not formed. Here, the laminated structure 10 D is not shown. The laminated structure before heat treatment for forming the tantalum carbide semiconductor device according to the fourth embodiment of the present invention. As shown in the laminated structure 10D of Fig. 11, the laminated structure prepared to form the ohmic electrode of the tantalum carbide semiconductor device according to the fourth embodiment of the present invention is the same as the laminated structure 丨0B (see Fig. 本) of the second embodiment of the present invention. form. However, in the laminated structure 10D, the Si layer 13' of the laminated structure 丨0B is formed in the same manner as the laminated structure i〇c of the third embodiment of the present invention, and the Si metal layer 15 containing a first metal element and containing no carbon atoms is formed. . In other words, the method further includes the step of forming a second metal element and not containing a carbon atom on the surface of the Si metal layer 15 opposite to the surface opposite to the first metal layer 12 in the laminated structure 10D. The second metal layer 14 is formed. Thus, the second metal layer 14 can also be formed on the main surface of the Si metal layer 15. The laminated structure 10D is different from the laminated structure 10B only in the points described above. The order of formation of the tantalum carbide semiconductor device according to the fourth embodiment of the present invention is based on the order of formation of the tantalum carbide semiconductor device according to the second embodiment of the present invention shown in Fig. 6. However, as described above, in the laminated structure 1A, the Si metal layer 15 is formed instead of the Si layer I3 of the structure 147784.doc • 27·201137975 structure 10B. Therefore, the step (S40) of forming the Si layer of Fig. 6 becomes the step (s4) of forming the Si metal layer. As described above, even when the second metal layer 14 is formed on the main surface of the Si metal layer I5, the layer containing "the third layer is contained in the initial state before the heat treatment as in the case of the Si metal layer 15," Since the Si element is present in a position closer to the first metal element, Si can be cyanated more rapidly with the first metal element during the heat treatment. Embodiment 4 of the present invention is only at the above points. In the fourth embodiment of the present invention, the configuration, the condition, the procedure, the effect, and the like which are not described above are all based on the second embodiment of the present invention. Embodiment 1 FIG. 12 to FIG. A schematic cross-sectional view showing a state in which each step is performed when a pn diode is formed in the second embodiment of the present invention. More specifically, Fig. a shows that the step of Fig. 6 is performed in order to form a pn diode (sl〇 Fig. 13 is a schematic cross-sectional view showing a state in which the step (S20) of Fig. 6 is performed in order to form a ruthenium diode. Fig. 4(4) shows a state in which ion implantation is performed in order to form a diode. Rough Fig. 16 is a schematic cross-sectional view showing a state in which a field oxide film is formed in order to form a pn diode. Fig. 16 is a schematic cross-sectional view showing a state in which the step (sc) of Fig. 6 is performed in order to form a pn diode. Fig. 17 is a schematic cross-sectional view showing a state in which the step (S50) of Fig. 6 is performed in order to form a Pn diode. Fig. _ shows a schematic diagram of a state in which the step (S6〇) of Fig. 6 is performed in order to form a Pn diode. Fig. B is a schematic cross-sectional view of a completed pn diode. Referring to _~19, 147784.doc • 28-201137975, a manufacturing method of the pn diode of the present invention is applied. As shown in the step (s10) of preparing the substrate of Fig. 6, for example, an n-type SiC substrate 20 is prepared. Secondly, a step (S20) of forming a Sic layer as shown in Fig. 6 is formed on one main surface of the SiC substrate 20. - The type of insect crystal layer is referred to as Fig. 7 (7). Further, on the surface opposite to the surface of the n-type layer 21 and the surface of the substrate j, a 磊-type epitaxial layer 22 is formed (refer to Fig. 13). The laminated structure of the η· type epitaxial layer 21 and the 〆 type epitaxial layer 22 as shown in FIG. 13 is mixed with the η· type epitaxial layer 21 The concentration is lel6 em·3, the film thickness is 10 μηι, the impurity concentration of the p-type epitaxial layer 22 is 2 ei7 cm_3, and the film thickness is 〇8 μιη. Then, as shown in FIG. 14, the p+ type epitaxial layer 22 is Internally implanting A] ions, thereby forming a Α1 ion implantation region 23. The step of forming the A1 ion implantation region 23 can make the formed ohmic electrode have good electrical contact with the substrate, so that the impurity concentration is higher than that of the p+ type epitaxial layer. The impurity concentration of the layer 22 is higher than the region of about 2 to 3 positions. Here, the dose of the ion implanted A1 ion is le5 cm 2 . Further, as shown in FIG. 14 , the depth of the helium ion implantation is preferably It is shallower than the thickness of the P+ type epitaxial layer 22. In order to form the Ai ion implantation region 23 as shown in FIG. 14, first, an oxidation having a certain thickness is formed on the main surface of the /-type epitaxial layer 22 opposite to the n-type epitaxial layer 21 by, for example, thermal oxidation. A ruthenium film (Si 〇 2 film) ^ Then, a resist of a certain thickness is applied onto the SiO 2 film. In this state, the resist is patterned by, for example, photolithography. Next, the above-described resist formed with a pattern is used as a mask, and the si〇2 film is partially removed (patterned) by etching, for example, by RIE etching. As a result, an 8 丨〇 2 film having an opening portion in which the erbium 147784.doc -29-201137975 sub-injection region 23 is exposed can be obtained. Then, after the resist is removed, the opening of the Si〇2 film is performed on the main surface side of the Ρ+-type epitaxial layer 22 opposite to the η·-type epitaxial layer 21, and then the erbium ion implantation is performed, and then the removal is performed. ο ing the film, thereby forming an A1 ion implantation region 23 showing the aspect shown in Fig. 14. In the A1 ion implantation region 23, the impurity concentration is higher than that of the P+ type epitaxial layer 22, and the electrical resistance is small. The ohmic electrode formed later can be electrically contacted with the substrate. Here, 'in order to activate the impurity of the A1 ion implantation region 23, 17 〇 (: 30 minutes of activation annealing (heat treatment) is performed. Thereafter, As shown in FIG. 15, on the main surface of the P+ type epitaxial layer 22 and the A1 ion implantation region 23 (on the upper side of FIG. 15), field oxidation including Si〇2 is formed by thermal oxidation in, for example, a wet environment. The film 24 (thickness 50 nm) is formed by protecting the p + -type epitaxial layer 22 and the main surface of the A1 ion implantation region 23. The human-film is formed by field oxidization using, for example, photolithography. a mask having an opening pattern on the film 24, which is removed by etching using the mask or the like The field oxide film 24 formed on the main surface of the A1 ion implantation region 23 and the p+ type epitaxial layer 22 is not opposed. Thereby, the main surface of the A1 ion implantation region 23 which is opposite to the p+ type crystal layer 22 is exposed. Then, in this state, as a step (S30) of forming the first metal layer shown in Fig. 6, a Ti film 25 having a thickness of, for example, 1 nm is formed on the gossip ion implantation region 23 as shown in Fig. 16. Instead of Ti (titanium), for example, A1 (aluminum) or Ni (nickel), Pt (platinum), W (tungsten), Pd (palladium), or the like may be used. Then, as a step of forming a Si layer as shown in FIG. (S40), for example, a Si layer 27 having a thickness of 50 nm is formed on the main surface of the Ti film 25 as shown in Fig. 16. 147784.doc -30·201137975 Next, as a step of forming a second metal layer as shown in Fig. 6 ( S45), for example, a film 5 〇nmiTi film 25 is formed on the main surface of the Si layer 27 as shown in Fig. 16. Alternatively, Ti (titanium) may be used instead of Ti (titanium), for example, A1 (Cr) or Cr (Chromium). In the sea state, as a heat treatment step (S5〇) shown in Fig. 6, the entire system shown in Fig. 16 was heat-treated for 2 minutes. As a result, Ti which is the Ti film 25 of the first metal layer, and the ruthenium of the Ti film 25 which is the second metal layer and the Ti thin film 25 which is the second metal layer are formed into a bismuth telluride layer. The electrode 5 is an ohmic electrode, which can be formed by a tantalum film 25 as a first metal layer, a region of the layer 27 for mash-forming, and a butadiene film as a second metal layer. The form formed by laminating the regions formed by the bismuthization of Si in the layer may be the ruthenium film 25 as the i-th metal layer, the § 1 of the layer 27, and the second metal layer. The Ti film 25 is a layered telluride layer in which the three elements are mixed and deuterated. Alternatively, a Ti film 25 which is not etched into the surface layer of the electrode 51 and the A1 ion implantation region 23 may be left. Then, on the surface layer of the electrode 51 as the ohmic electrode by the step of forming the wiring portion (S6〇), as shown in FIG. 18, for example, a film 5 having a thickness of 5 Å and a film 26 having a thickness of 3 nm 2 A1 are formed as wirings (pads). ). According to the above procedure, one ohmic electrode of the Pn diode is completed, but in order to function as an actual pn diode, two ohmic electrodes (two poles) are necessary. Therefore, as shown in FIG. 19, for example, an ohmic electrode (electrode η) is formed also on the main surface (back surface) of the sic substrate 2 and the n-type epitaxial layer 21 which are not opposed to each other, whereby The ρη diode is 1〇〇. The ρη diode 1〇〇 contains eight in existence! An ohmic electrode with a good wiring that inhibits the formation of a Schottky electrode from Si and Sic by suppressing the carbon atom from the surface of the electrode 147784.doc •31 · 201137975. Furthermore, the ohmic electrode (electrode 51), the Ti film 25, and the A1 film 26 on the back surface of the Sic substrate 20 are substantially the same as the electrode 5 i, the Ti film 25, and the A1 film 26 on the p + type epitaxial layer 22. The manufacturing method is the same. Further, the ohmic electrode formed on the main surface of the SiC substrate 20 and the n-type epitaxial layer 21 which are not opposed to each other is formed in the same manner as in the second embodiment of the present invention, as shown in FIG. Means formed. At this time, as shown in Fig. 19, in order to make the SiC substrate 20 be in good electrical contact with the formed ohmic electrode, it is not necessary to perform ion implantation for doping impurities with a high concentration. The reason for this is that the Sic substrate 2 〇 generally contains impurities at a high concentration, so that the contact resistance is smaller than that of the P + -type epitaxial layer 22, and good electrical contact can be obtained in this state. Further, the method for forming the second embodiment of the present invention is exemplified as the method of forming the ohmic electrode of the above-described pn diode 1 ,. However, the present invention is not limited thereto, and other embodiments of the present invention may be implemented, for example. An ohmic electrode is formed by the formation of the forms ^, 3, and 4. When any of the embodiments is used, the electrodes 51 of Figs. 17 to 19 can be formed by one or two layers of a telluride layer formed by mashing Si with one or two metal elements. (Embodiment 2) FIG. 20 to FIG. 26 are schematic cross-sectional views showing a state in which each step is performed when a JFET (Red Surface Field-Connected Field Effect Transistor) according to Embodiment 2 of the present invention is used. . More specifically, FIG. 2B shows a schematic cross-section of 147784.doc • 32-201137975 in which the steps of FIG. 6 are performed in order to form a RESURF·JFET. FIG. 21 is a diagram showing execution for forming a RESURF-JFET. Fig. 22 is a schematic cross-sectional view showing a state in which ion implantation is performed to form a RESURF-JFET. Fig. 23 is a view showing a state in which a field oxide film is formed in order to form a RESURF-JFET. Fig. 24 is a schematic cross-sectional view showing a state in which the step (S45) of Fig. 6 is performed in order to form a RESURF-JFET, and Fig. 25 is a view showing a state in which the step (S50) of Fig. 6 is performed in order to form a RESURF-JFET. Fig. 26 is a schematic cross-sectional view showing a state in which the RESURF-JFET which has been completed after the step (S60) of Fig. 6 is formed in order to form a RESURF-JFET. With reference to Fig. 20 to Fig. 26, the use of the present invention will be described. First, as shown in Fig. 20, as shown in Fig. 20, a step (S10) of preparing a substrate in Fig. 6 is prepared, for example, an η-type SiC substrate 20 is prepared. Next, a step of forming a SiC layer as Fig. 6 is provided. (S20), in SiC A p + -type epitaxial layer 22 is formed on one main surface of the board 20 (refer to FIG. 21). Further, on the surface of the p + type epitaxial layer 22 opposite to the surface opposite to the SiC substrate 20, n + type epitaxial is formed. Layer 32 (see Fig. 21). On the surface of the n + -type epitaxial layer 32 opposite to the surface opposite to the p + -type epitaxial layer 22, a P + -type epitaxial layer 22 is further formed (see Fig. 21). The laminated structure of the p+ type epitaxial layer 22, the n+ type epitaxial layer 32, and the p+ type epitaxial layer 22 as shown in FIG. 21 is formed, and the p+ type epitaxial layer 22 opposite to the SiC substrate 2 is formed. The impurity concentration is 2el7 cm_3, and the film thickness is 10 μηη n + type worm layer 32 has an impurity concentration of 2el7 cm·3 and a film thickness of 0.4 μm. The uppermost p+ type epitaxial layer 22 has an impurity concentration of 2el7 cnT3, film. The thickness is 0.2 μm. Then, as shown in FIG. 22, p ions and A1 ions are implanted into the innermost layer of the p + type epitaxial layer 22 and the n + type bar 147784.doc -33 - 201137975 crystal layer 32. The source region 33, the gate region 34, and the drain region 35 are formed. The steps of forming the source region 33 and the drain region 35 are for electrically connecting the formed ohmic electrode to the substrate. Preferably, the impurity concentration is higher than the impurity concentration of the n+ type epitaxial layer 32 by a region of about 2 to about 3. Further, the step of forming the gate region 34 is to increase the gate of the transistor formed by the control. The electrical property of the electrode of the electrode is a step of forming a region in which the impurity concentration is higher than the impurity concentration of the P + -type epitaxial layer 22 and the n + -type epitaxial layer 32 by about 1 to 3 bits. Here, in order to form the source region 33 and the drain region 35, p (phosphorus) ions are mainly implanted in a dose of 6 el 4 cm by ion implantation, and in order to form the gate region 34, Ai ions are made at 8 el 4 cm · 2 The dose is injected. Further, in order to homogenize the electric field intensity distribution as the region between the source region 33 and the drain region 35 of the resurf_JFET to have a function of suppressing electric field concentration, as shown in Fig. 22, the source region 33 is preferable. The depth of the gate region 34 and the drain region 35 is deeper than the thickness of the p+ type epitaxial layer 22 of the uppermost layer, and is shallower than the total thickness of the p+ epitaxial layer and the epitaxial layer 32. In order to form the source region 33, the gate region 34, and the j: and the polar region 35 shown in Fig. 22, it is preferable to use, for example, the same as the case of forming the μ ion implantation region 23 as shown in Fig. 14 described above. Photolithography and ion implantation. Here, in order to activate the impurities in the source region 33, the gate region 34, and the drain region 35, activation annealing (heat treatment) was performed at 1700 ° C for 30 minutes. Thereafter, 'as shown in FIG. 23' on the main surface of the p+ type epitaxial layer 22 and the source region 33, the idle region 34, and the drain region 35 (on the upper side of FIG. 23), for example, in a wet environment Thermal oxidation to form a 100 nm field oxide containing Si 〇 2 147784.doc -34·201137975 Membrane 24. The field oxide film is formed to protect the principal surfaces of the p + -type epitaxial layer 22, the source region 33, the gate region 34, and the drain region 35. For example, a mask having an opening pattern formed on the field oxide film 24 is formed using photolithography. # The p+ type epitaxial layer is removed from the source region 33, the gate region 34, and the drain region 35 by using the mask material. The field oxide film 24 formed on the surface of the main surface is not opposed. Thus, the source region 33, the gate region 34, and the drain region 35 are combined with the 磊-type epitaxial layer. The surface of the main surface is not facing. Then, in this state, as a step (S30) of forming the second metal layer shown in Fig. 6, as shown in Fig. 24, for example, a thickness of 5 Å is formed on the source region 33, the gate region 34, and the drain region 35. % of nm2Ni film. Further, in place of Ni (nickel), for example, Ai (aluminum) or (titanium), Pt (platinum), w (tungsten), Pd (palladium) or the like may be used. Next, as the step (S40) of forming the Si layer shown in Fig. 6, as shown in Fig. 24, a Si layer 27 of, for example, a thickness of 1 〇〇 nm is formed on the main surface of the Ni thin film 36. Next, as a step (S45) of forming the second metal layer shown in Fig. 6, as shown in Fig. 24, a Ni film 36 having a thickness of, for example, 20 nm is formed on the main surface of the Si layer 27. Further, instead of seeing (nickel), for example, Ti (titanium) or A1 (inger), Cr (chromium) or the like may be used. In this state, as a heat treatment step (S5〇) shown in FIG. 6, the entire system shown in FIG. 24 is heat-treated at 1 Torr for 2 minutes. Thus, Ni as the first metal layer. The Ni of the thin film 36, the Si of the Si layer 27, and the Ni of the Ni thin film 36 as the second metal layer are germanium-formed to form an electrode 52 as a telluride layer as shown in Fig. 25. The electrode 52 is an ohmic electrode. 52 can be formed by the film 36 as the i-th metal layer and the region after the layer 27 is deuterated, and the Ni film as the second metal layer is published as 147784.doc •35·201137975 layer 27 Si The electrode 52 may be formed by laminating the region formed by the bismuthization, and the electrode 52 may be an n 丨 film % as the first metal layer, Si of the Si layer 27, and a Ni film 36 as the second metal layer. The three elements are mixed and eutecticized into a single layer of germanide layer. Alternatively, the surface of the electrode 52, which is not opposite the source region 33, may also have a Ni film 36 that has not been deuterated. The electric power as the ohmic electrode by the step of forming the wiring portion (S60) On the surface layer of 52, for example, a thin film 25 of a thickness of 5 〇 nm 2 and a thin film 26 of a thickness of 3 nm are formed as wirings (pads) as shown in Fig. 26. The RESURF-JFET 200 shown in Fig. 26 formed in accordance with the above sequence includes An ohmic electrode (electrode 52) of a wiring having good adhesion, which can suppress carbon atoms from being crystallized on the surface of the electrode 52 or suppress formation of a Schottky electrode from 8 Å and Sic. Further, Embodiment 2 of the present invention has been exemplified. The method of forming the ohmic electrode of the RESURF-JFET 200 described above is not limited thereto, and as another embodiment of the present invention, for example, the formation methods of the first, third, and fourth embodiments may be used to form ohmic. When any of the embodiments is used, the electrodes 52 of FIGS. 25 to 26 can be formed by a bismuth layer or a two-layer bismuth layer formed by mashing Si with one or two metal elements. 27 to 34 are schematic cross-sectional views showing a state in which each step is performed when a lateral MOSFET is formed in the third embodiment of the present invention. More specifically, Fig. 27 shows that Fig. 6 is performed in order to form a horizontal type m〇sfet. Step (sio) Fig. 28 is a schematic cross-sectional view showing a state in which the step (S20) of Fig. 6 is performed to form a lateral type 147784.doc • 36·201137975 MOSFET. Fig. 29 shows an ion for forming a horizontal MOSFET. Fig. 30 is a schematic cross-sectional view showing a state in which a field oxide film is formed in order to form a lateral MOSFET. Fig. 31 shows a state in which the step (S45) of Fig. 6 is performed in order to form a lateral MOSFET. A schematic cross-sectional view. Fig. 32 is a schematic cross-sectional view showing a state in which the step (S50) of Fig. 6 is performed in order to form a lateral MOSFET. Fig. 33 is a schematic cross-sectional view showing a state in which a gate electrode is formed in order to form a lateral m〇SFET. Fig. 34 is a schematic cross-sectional view showing the state of the horizontal MOSFET which has been completed after the step (S60) of Fig. 6 is performed to form a horizontal MOSFET. A method of manufacturing a horizontal MOSFET according to a third embodiment of the present invention will be described with reference to Figs. 27 to 34. First, as shown in FIG. 27, as the step (s10) of preparing the substrate of FIG. 6, for example, an n-type SiC substrate 20 is prepared. Next, as a step of forming a siC layer (S20), a p-type epitaxial layer 31 is formed on one main surface of the SiC substrate 20. Thereby, the p-type epitaxial layer 31 as shown in FIG. 28 can be formed. Further, the P type worm layer 31 has an impurity concentration of le6 cm·3 and a film thickness of 1 〇 μιη. Then, as shown in Fig. 29, a p-ion is implanted into the p-type epitaxial layer 31 to form a source region 33 and a drain region 35 of a conductivity type. The steps of forming the source region 33 and the drain region 35 are performed in order to improve the electrical contact between the formed ohmic electrode and the substrate, and to improve the electrical characteristics of the gate electrode of the channel formed by the controlled transistor. The impurity concentration is higher than the impurity concentration of the ruthenium-type worm layer 31 by a region of about 2 to 3 positions. Here, in order to form the source region 33 and the drain region 35, for example, cerium (phosphorus) ions are implanted at a dose of 5e 14 cm·2 by ion implantation. Further, 147784.doc • 37- 201137975 is shown in Fig. 29. It is preferable that the depths of the source region 33 and the drain region 35 are shallower than the thickness of the P' type epitaxial layer 31. In order to form the source region 33 and the drain region 35 shown in Fig. 29, it is preferable to use photolithography and ion implantation in the same manner as the above-described A1 ion implantation region 23 shown in Fig. 14. Here, in order to activate the impurities of the source region 33 and the drain region 35, for example, after activation annealing (heat treatment) at 1750 ° C for 30 minutes, as shown in FIG. 3A, the P-type crystal layer 31 and the source are shown. On the main surface of the polar region 33 and the drain region 35 (upper side of FIG. 30), a 50 nm field oxide film 24 containing Si〇2 is formed by thermal oxidation in, for example, a wet environment. The field oxide film 24 functions as a gate insulating film and is formed to protect the main surfaces of the P-type crystal layer 31, the source region 33, and the drain region 35. For example, a mask having an opening pattern formed on the field oxide film 24 is formed using photolithography. A portion of the field oxide film 24 formed on the main surface of the source region 33 and the drain region 35 which is not opposed to the p-type epitaxial layer 3 is removed by etching using the mask or the like. Thereby, the source region 33 and the drain region 35 are partially exposed to one of the main surfaces on which the p-type epitaxial layer 31 is not opposed. Then, in this state, as the step (S30) of forming the second metal layer shown in FIG. 6, the region of the source region 33 and the drain region 35 on which the field oxide film 24 has been removed is formed as shown in FIG. For example, a thickness of 5 〇nmiNi film%. Further, in place of Ni, it is also possible to use, for example, A! (Ming) or Ding (Titanium), Pt (Start), W (Tungsten), Pd (Ji), and the like. Next, as a step of forming a layer as shown in Fig. 6 (S40), as shown in Fig. 31, a Si layer 27 of 147784.doc - 38 - 201137975, for example, a thickness H) of the leg is formed on the main surface of the Ni film. Next, as a step of forming the second metal layer shown in Fig. 6, as shown in Fig. 31, a W film 37 having a thickness of, for example, 20 nm is formed on the main surface of Fig. 27. Further, for example, Ti (titanium) or Al (aluminum), Cr (chromium) or the like may be used. In this state, as a step (S50) of performing heat treatment as shown in Fig. 6, the entire system shown in Fig. 31 is subjected to heat treatment for 2 minutes, for example, at 1 〇〇〇 c > c. As a result, the first metal layer is formed into a tantalum film 36, and the layer "and" and the W film 37 as the second metal layer are mashed to form a telluride layer as shown in FIG. An electrode 53. The electrode is an ohmic electrode which can be formed by a germanium film 36 as a first metal layer and a germanium layer formed by the layer 27, and a w film 37 and a layer as a second metal layer. The Si of 27 is formed by laminating the regions formed by the Sihua compoundization. Further, the electrode 53 may be a film 36 as the ith metal layer.

The Si' of the Si layer 27 and the thin film 37 which is the second metal layer are mixed and eutecticized to form a single telluride layer. Alternatively, in the surface layer of the electrode 53 which is not opposed to the source region 33, for example, the W film 37 which is not cleaved may remain. Next, after forming a resist mask by, for example, photolithography, an A丨 film as a conductor film is formed by vacuum evaporation, ion beam plating or deplating, and should be the gate of the conductor film. A portion other than the portion of the electrode is removed (peeled) together with the resist mask, whereby an A1 film 26 as a gate electrode is formed on the field oxide film as shown in Fig. 33, where the thickness of the A1 film 26 is At 200 nm, the A film 26 is formed across the source region 33 and the drain region 35 (on the channel region). 147784.doc -39- 201137975 Then, by the step of forming the wiring portion (S60), a W film 37 having a thickness of 5 〇 (10) and a thickness of 3 are formed as shown in FIG. 34 on the surface layer of the electrode 53 as the ohmic electrode. The Ai film 26 of nm is used as a wiring (pad). Further, the film 26 and the film 26 are formed similarly on the film 26 as the gate electrode. The horizontal mosfet 300 packaged according to the above-described sequence is formed, and the wiring having good adhesion is good. An ohmic electrode capable of suppressing carbon atoms from being crystallized on the surface of the electrode 53 or suppressing the formation of a Schottky electrode from 81 and 81. Further, the formation method of the second embodiment of the present invention has been exemplified as described above. Although the method of forming the ohmic electrode of the horizontal MOSFET 300 is not limited to this, as another embodiment of the present invention, for example, the ohmic electrode may be formed by the formation methods of the first, third, and fourth embodiments. The electrodes 53 of FIGS. 32 to 34 can be formed by mashing one or two layers of Si and one or two metal elements. Further, it is not limited to a type MOSFET, for example, a vertical MOSFET. Embodiments of the present invention may be used in a carbon carbide-based semiconductor device having an ohmic electrode such as a MESFET or an IGBT. It is to be understood that the embodiments of the present disclosure and all embodiments are illustrative and not limiting. The scope of the present invention is disclosed by the scope of the claims and not the foregoing description, which is intended to include all modifications within the meaning and scope of the claims. Industrial Applicability The present invention A carbon carbide which forms an ohmic electrode which is improved in adhesion to wiring by suppressing the release of shouting. 147784.doc 201137975 The technology of the semiconductor device is particularly excellent. [Simplified description of the drawing] FIG. A schematic cross-sectional view showing a laminated structure of an ohmic electrode of a carbonized carbide semiconductor device according to an embodiment of the present invention. Fig. 2 is a flow chart showing a procedure for forming a carbonized carbide semiconductor device according to Embodiment 1 of the present invention. A schematic cross-sectional view of a laminated structure of an ohmic electrode as an embodiment of the present invention after heat treatment. Fig. 4 is a schematic cross-sectional view showing a laminated structure of another embodiment of an ohmic electrode which is an embodiment of the present invention after heat treatment. Fig. 5 is a schematic cross-sectional view showing a laminated structure of an ohmic electrode for forming a carbonized carbide semiconductor device according to a second embodiment of the present invention. Fig. 6 is a flow chart showing the procedure for forming a carbonized carbide semiconductor device according to Embodiment 2 of the present invention. Fig. 7 is a schematic cross-sectional view showing a laminated structure of an ohmic electrode of the embodiment of the present invention after heat treatment. Fig. 8 is a schematic cross-sectional view showing a laminated structure of another embodiment of the ohmic electrode according to the embodiment of the present invention after heat treatment. Fig. 9 is a schematic cross-sectional view showing a laminated structure of still another embodiment of the ohmic electrode according to the second embodiment of the present invention after the heat treatment. Fig. 10 is a schematic cross-sectional view showing a laminated structure of an ohmic electrode for forming a tantalum carbide semiconductor device according to a third embodiment of the present invention. Fig. 11 is a schematic cross-sectional view showing a laminated structure of an ohmic electrode for forming a tantalum carbide semiconductor according to a fourth embodiment of the present invention. 147784.doc 41 201137975 Fig. 12 is a schematic cross-sectional view showing a state in which the pn diode is formed and the step (s1) of Fig. 6 is performed. Fig. 13 is a schematic cross-sectional view showing a state in which the step (S2) of Fig. 6 is performed in order to form a pn diode. Fig. 14 is a schematic cross-sectional view showing a state in which ion implantation is not performed to form a ρη diode. Fig. 7 is a schematic cross-sectional view showing a state in which a field oxide film is formed in order to form a ρη diode. A schematic cross-sectional view showing a state in which the step (S45) of Fig. 6 is performed in order to form a ρη diode.广 I 17 李霸', a schematic cross-sectional view showing a state in which the step (S50) of Fig. 6 is performed in order to form a ρη diode. Fig. 1 is a schematic cross-sectional view showing a state in which the step (S60) of Fig. 6 is performed in order to form a Pn diode. Figure 19 is a schematic cross-sectional view of a completed pn diode. Fig. 2 is a schematic cross-sectional view showing a state in which the step (S 10) of Fig. 6 is performed in order to form a RESURF-JFET. Fig. 21 is a schematic cross-sectional view showing a state in which the soap-& garment is not subjected to the step (S20) of Fig. 6 in order to form a RESURF-JFET. Fig. 22 is a schematic cross-sectional view showing a state in which ion implantation is performed in order to form an rESURF_JFET. Fig. 23 is a schematic cross-sectional view showing a state in which a field oxide film is formed in order to form $resurf_jfet. Fig. 24 is a schematic cross-sectional view showing a state in which steps 147784.doc • 42-201137975 (S45) of Fig. 6 are executed in order to form rESURF_jFEt. Fig. 25 is a schematic cross-sectional view showing a state in which the step (S50) of Fig. 6 is performed in order to form a RESURF-JFET. Fig. 26 is a schematic cross-sectional view showing the state of the RESURF-JFET which has been completed after the step (S60) of Fig. 6 is performed to form the RESURF-JFET. Fig. 27 is a schematic cross-sectional view showing a state in which the step (S 10) of Fig. 6 is performed in order to form a lateral MOSFET. Fig. 28 is a schematic cross-sectional view showing a state in which the step (S20) of Fig. 6 is performed to form a lateral MOSFET. Fig. 29 is a schematic cross-sectional view showing a state in which ion implantation is performed to form a lateral MOSFET. Fig. 30 is a schematic cross-sectional view showing a state in which a field oxide film is formed in order to form a lateral MOSFET. Fig. 3 is a schematic cross-sectional view showing a state in which the step (S45) of Fig. 6 is performed in order to form a lateral MOSFET. Fig. 32 is a schematic cross-sectional view showing a state in which the step (S50) of Fig. 6 is performed in order to form a lateral MOSFET. Fig. 33 is a schematic cross-sectional view showing a state in which a gate electrode is formed to form a lateral MOSFET. Fig. 34 is a schematic cross-sectional view showing the state of the horizontal MOSFET which has been completed after the step (S60) of Fig. 6 is performed to form a lateral MOSFET. Fig. 35 is a schematic cross-sectional view showing the state of electrodes and wirings of a general SiC semiconductor device. Figure 36 shows the formation of an alloy layer of Ni and Si on the SiC semiconductor layer 147784.doc -43 -

A schematic cross-sectional view of the structure of 201137975. [Description of main component symbols] 10, 20 '95 10A, 10B, 10C, 10D 11 11A, 11B, 12A, 12B, 13B 12 13, 27 14 15 21 22 23 24 25 26 31 32 33 34 35 36 37

SiC substrate laminated structure SiC layer ohmic electrode first metal layer Si layer second metal layer Si metal layer η-type worm layer Ρ + type stray layer Α 1 ion implantation region field oxide film Ti film A1 film p-type worm layer n+ type remote crystal layer source region gate region> and polar region Ni film W film 147784.doc -44- 201137975

41 carbon-containing telluride layer 42 ' 43 lithium layer 44 upper lithium layer 51, 52, 53 , 98 electrode 94 Ni-Si alloy layer 95A electronic component 96 wiring 97 carbon 99 SiC semiconductor substrate 99A Sic semiconductor device 100 pn Diode 200 RESURF-JFET 300 Horizontal MOSFET 147784.doc -45-

Claims (1)

201137975 VII. Patent application scope: 1. A method for manufacturing a tantalum carbide semiconductor device, the tantalum carbide semiconductor device having an ohmic electrode, the manufacturing method comprising: step (S20) 'forming a Sic layer (11) comprising tantalum carbide; (S30) forming a first metal layer (12) containing a first metal element and containing no carbon atoms on one main surface of the siC layer (11); and step (S4〇) 'to the first metal layer (12) forming a Si layer (13, 15, 27) containing germanium and containing no carbon atoms on the surface opposite to the surface opposite to the (2) layer (11); and the step (S5 0), The sic layer (u), the first metal layer (I2), and the Si layer (13) are heat-treated to form an ohmic electrode. 2. The method for manufacturing a silicon carbide semiconductor device according to claim 1, further The method includes the following steps: Step (S45): forming a surface on the surface opposite to the surface of the Si layer (13) opposite to the second metal layer (12) before the step of performing the heat treatment (S5〇) The second metal element does not contain the carbon atom The metal layer (14). The method for producing a silicon carbide semiconductor device according to claim 2, wherein the second metal element (M) is one element selected from the group consisting of titanium, aluminum, and chromium. The method of manufacturing a tantalum carbide semiconductor device according to claim 1, wherein in the step (S5) of performing the heat treatment, a first metal element and a tantalum are formed on one main surface of the Sic layer (u). 147784.doc 201137975 An alloy comprising a carbon atom-containing carbide layer (41). The method of manufacturing a silicon carbide semiconductor device according to claim 1, wherein the first metal element is selected from the group consisting of nickel, titanium, aluminum, An element of a group consisting of platinum, tungsten, and palladium. 6. A method of manufacturing a tantalum carbide semiconductor device having an ohmic electrode. The manufacturing method includes the following steps: Step (S20), forming a layer of carbonaceous stone ye (11); on a main surface of the SiC layer (11), forming a first metal layer (12) containing an ith metal element and containing no carbon atoms; Forming a Si metal layer (15) comprising germanium and one of the first metal elements and not containing carbon atoms on the surface of the layer (12) opposite to the surface opposite to the SiC layer (u); and forming an ohmic layer The electrode is heat-treated to the Sic layer (11), the second metal layer (12), and the Si metal layer (15). The method for manufacturing a silicon carbide semiconductor device according to claim 6, further comprising the following Step: before the step of performing the heat treatment, forming a second metal element and not containing carbon on the surface of the metal layer (15) opposite to the surface opposite to the first metal layer (12) The second gold of the atom (14). The method of producing a silicon carbide semiconductor device according to claim 7, wherein the second metal element is one selected from the group consisting of titanium, aluminum, and chromium. 9. The method of manufacturing a silicon carbide semiconductor device according to claim 6, wherein in the step of heat treatment of the above 147784.doc 201137975, forming a first metal element and a first metal element on one main surface of the SiC layer (11) A stone-like alloy layer containing carbon atoms. 10. The method of manufacturing a niobium carbide semiconductor device according to claim 6, wherein the first metal element is one selected from the group consisting of ruthenium, titanium, samarium, tungsten, and the like. A silicon carbide semiconductor device comprising: a SiC layer (11) comprising tantalum carbide; and a vaporized layer (41, 43) disposed on one major surface of the SiC layer (11), comprising a first An alloy of a metal element and ruthenium, and a surface layer on the opposite side of the surface opposite to the SiC layer (11) does not contain carbon atoms; and the SiC layer (11) and the vaporization layer (41, 43) are Ohmic contact. 12. The tantalum carbide semiconductor device of claim 11, further comprising an upper layer (44) formed on a surface layer of the germanide layer (41, 43), comprising a second metal element and germanium The alloy layer does not contain carbon atoms on the surface layer opposite to the surface opposite to the above-described telluride layer (41, 43). 13. The silicon carbide semiconductor device according to claim 12, wherein the second metal element is one selected from the group consisting of titanium, aluminum, and chromium. 14. The tantalum carbide semiconductor device of claim 11, wherein the second metal element is selected from the group consisting of nickel, titanium, aluminum, platinum, tungsten, and palladium. 147784.doc 201137975 15. A silicon carbide semiconductor device comprising: a SiC layer (11) comprising tantalum carbide; a carbon-containing germanide layer (41) disposed on a major surface of the SiC layer (11) An alloy comprising a first metal element and ruthenium and comprising a carbon atom; and a ruthenide layer (43) disposed on the opposite side of the surface of the carbon-containing ruthenide layer (41) opposite to the SiC layer a surface layer comprising the first metal element and the bismuth alloy, and the surface layer opposite to the surface opposite to the carbon-containing hydrazine layer (41) does not contain carbon atoms; and the SiC layer (11) and The carbon-containing telluride layer (41) is subjected to ohmic contact. 16. The silicon carbide semiconductor device of claim 15, further comprising an upper layer (44) formed on the surface layer of the vapor layer (43), comprising a second metal element and an alloy of tantalum The surface layer on the opposite side to the surface opposite to the above-mentioned fragment (43) does not contain carbon atoms. 17. The silicon carbide semiconductor device according to claim 16, wherein the second metal element is one selected from the group consisting of titanium, aluminum, and chromium. 18. The carbonized carbide semiconductor device according to claim 15, wherein the first metal element is one element selected from the group consisting of nickel, titanium, aluminum, platinum, tungsten, and palladium. 147784.doc